pixels

Abstract

A pixel according to some embodiments includes a light source unit; a first transistor coupled between a first power supply and a first node and configured to control a drive current applied to the light source unit; a first bias transistor coupled between a first bias power supply and a gate electrode of the first transistor; and a second bias transistor coupled between a second bias power supply and a second node electrically coupled with an anode of the light source unit, wherein the first bias transistor and the second bias transistor are configured to be turned on during a first period before a data voltage is applied in a frame, and wherein the second bias transistor is configured to be turned on at least once during a second period after the data voltage is applied in the frame.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0106397, filed on August 24, 2020, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] This disclosure relates to pixels, display devices, and methods for driving display devices. Background Technology

[0004] With increasing interest in information display and the growing demand for portable information media, display devices have become widely needed and commercialized. Summary of the Invention

[0005] The technical problem addressed in this paper is to provide a display device that can improve afterimages.

[0006] A pixel according to some embodiments of the present disclosure may include: a light source unit; a first transistor connected between a first power supply and a first node and configured to control a drive current applied to the light source unit; a first bias transistor connected between the first bias power supply and the gate electrode of the first transistor; and a second bias transistor connected between a second bias power supply and a second node, the second node being electrically connected to the anode of the light source unit, wherein the first bias transistor and the second bias transistor are configured to be turned on during a first time period in a frame before the application of a data voltage, and wherein the second bias transistor is configured to be turned on at least once in a frame during a second time period after the application of a data voltage.

[0007] The voltage level of the first bias power supply can be lower than the voltage level of the second bias power supply.

[0008] The pixel may also include a third bias transistor connected between the first node and the second node.

[0009] The third bias transistor can be configured to be turned off in a second time period within a frame.

[0010] The pixel may also include: a second transistor connected between the gate electrode of the first transistor and a data line for applying a data voltage; and a third transistor connected between the first node and a sensing line for receiving an initialization power supply voltage.

[0011] The second and third transistors can be configured to conduct simultaneously between the first and second time periods.

[0012] The pixel may also include a storage capacitor connected between the first node and the gate electrode of the first transistor and configured to store a data voltage.

[0013] The light source unit may include at least one light-emitting element configured to emit light by driving current.

[0014] The first transistor can be configured to receive drive current from a first power supply, wherein the light source unit is configured to provide the drive current from the first transistor to a second power supply, the second power supply being set to a voltage value lower than that of the first power supply.

[0015] The first bias power supply can be the second power supply, wherein the second bias power supply can be the initialization power supply.

[0016] A display device according to some embodiments of the present disclosure may include: a plurality of pixels; and a power driver providing a first bias power supply and a second bias power supply to the plurality of pixels, wherein each of the plurality of pixels includes: a light source unit; a first transistor connected between the first power supply and a first node for controlling a drive current applied to the light source unit; a first bias transistor connected between the first bias power supply and the gate electrode of the first transistor; and a second bias transistor connected between the second bias power supply and a second node electrically connected to the anode of the light source unit, wherein the first bias transistor and the second bias transistor are configured to be turned on during a first time period in a frame before a data voltage is applied, and wherein the second bias transistor is configured to be turned on at least once in a frame during a second time period after the data voltage is applied.

[0017] The voltage level of the first bias power supply can be lower than the voltage level of the second bias power supply.

[0018] The pixel may also include a third bias transistor connected between the first and second nodes and configured to cut off during a second time period within a frame.

[0019] Each of the plurality of pixels may further include: a second transistor connected between the gate electrode of the first transistor and a data line for applying a data voltage; and a third transistor connected between the first node and a sensing line for receiving a voltage for initialization power.

[0020] The second and third transistors can be configured to conduct simultaneously between the first and second time periods.

[0021] The first transistor can be configured to receive drive current from a first power supply, wherein the light source unit is configured to provide the drive current from the first transistor to a second power supply, the second power supply being set to a voltage value lower than that of the first power supply.

[0022] The first bias power supply can be the second power supply, wherein the second bias power supply can be the initialization power supply.

[0023] A method for driving a display device according to some embodiments of the present disclosure may include: providing a first bias voltage to the gate electrode of a first transistor during a first time period in a frame, and providing a second bias voltage to the anode of a light source unit; providing a data voltage to a storage capacitor connected to the gate electrode of the first transistor after the first time period; and providing a second bias voltage to the anode of the light source unit during a second time period in a frame after the data voltage is provided.

[0024] The first bias voltage can have a level lower than the second bias voltage.

[0025] The second time segment can occur multiple times within a single frame. Attached Figure Description

[0026] The accompanying drawings are included to provide a further understanding of the claimed embodiments. The drawings are incorporated in and form a part of this specification, and together with the description, they serve to illustrate aspects of the claimed embodiments.

[0027] Figure 1 This is a schematic block diagram illustrating a display device according to some embodiments.

[0028] Figure 2 This is a circuit diagram showing a pixel of a display device according to some embodiments.

[0029] Figure 3 It is shown Figure 2 The timing diagram shows an example of the operation of one pixel.

[0030] Figure 4A It is a graph used to illustrate the characteristic changes of the first transistor in a display device according to a comparative example, in which a residual image may appear.

[0031] Figure 4B It is a graph used to illustrate the changes in the characteristics of a light-emitting element in a display device according to a comparative example, in which a residual image may appear.

[0032] Figure 5 It is a graph used to illustrate the effect of improving afterimage in a display device according to some embodiments.

[0033] Figure 6 This is a schematic block diagram illustrating a display device according to some embodiments.

[0034] Figure 7 This is a circuit diagram showing a pixel of a display device according to some embodiments.

[0035] Figure 8 It is shown Figure 7 The timing diagram shows an example of the operation of a single pixel. Detailed Implementation

[0036] Some aspects of this disclosure and methods of implementing these aspects can be more readily understood by referring to the detailed description and accompanying drawings of the embodiments. However, the described embodiments may be implemented in a variety of different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete and will fully convey the aspects of this disclosure to those skilled in the art. Therefore, processes, elements, and techniques that are unnecessary for those skilled in the art may not be described in order to fully understand the aspects of this disclosure.

[0037] Unless otherwise stated, the same reference numerals, characters, or combinations thereof denote the same elements in the drawings and written description, and therefore will not be described again. Furthermore, portions unrelated to the description of the embodiments may not be shown for clarity.

[0038] In the detailed description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of the various embodiments. However, it will be apparent that various embodiments may be implemented without utilizing these specific details or using one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various embodiments.

[0039] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the spirit and scope of this disclosure, the first element, first component, first region, first layer, or first part described below may be referred to as a second element, second component, second region, second layer, or second part.

[0040] It will be understood that when a component, layer, region, or part is referred to as being "formed on," "on," "connected to," or "linked to" another component, layer, region, or part, it can be directly formed on, directly on, directly connected to, or directly linked to another component, layer, region, or part; or it can be indirectly formed on, indirectly on, indirectly connected to, or indirectly linked to another component, layer, region, or part, such that one or more intervening components, layers, regions, or parts may exist. For example, when a layer, region, or part is referred to as being "electrically connected" or "electrically linked" to another layer, region, or part, it can be directly electrically connected or directly electrically linked to another layer, region, and / or part, or an intervening layer, region, or part may exist. However, "direct connection / direct link" means that one component is directly connected to or directly linked to another component without any intermediate components. Similarly, other expressions describing relationships between components (such as "between," "directly between," or "adjacent to" or "directly adjacent to") can be interpreted similarly. Additionally, it will be understood that when an element or layer is referred to as "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can be one or more intervening elements or layers.

[0041] For the purposes of this disclosure, when a statement such as “at least one of…” follows a list of elements, it modifies the entire list of elements, rather than a single element in the list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z (such as XYZ, XYY, YZ, and ZZ), or any variation thereof. Similarly, a statement such as “at least one of A and B” can include A, B, or A and B. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, a statement such as “A and / or B” can include A, B, or A and B.

[0042] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that, when used in this specification, the terms “comprises,” “comprising,” “have,” “having,” “includes,” and “including” indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0043] As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as approximations rather than terms of degree and are intended to account for inherent biases in measured or calculated values ​​that will be recognized by one of ordinary skill in the art. “About” or “approximately” as used herein includes the value and the average of the value within an acceptable range of deviations determined by one of ordinary skill in the art, considering the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value. Furthermore, the word “may” is used in describing embodiments of this disclosure to mean “one or more embodiments of this disclosure.”

[0044] When one or more implementations can be carried out differently, a particular process sequence can be performed differently than the described sequence. For example, two consecutively described processes can be performed substantially simultaneously, or in the reverse order of their description.

[0045] The electronic or electrical devices and / or any other related devices or components according to the embodiments of this disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of these devices can be formed on a single integrated circuit (IC) chip or on separate IC chips. Additionally, various components of these devices can be implemented on a flexible printed circuit film, a tape-on-a-package (TCP), a printed circuit board (PCB), or formed on a substrate.

[0046] Furthermore, the various components of these devices can be processes or threads that run on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components for performing the various functions described herein. The computer program instructions are stored in memory implemented in the computing device using standard storage devices, such as random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media, such as CD-ROMs, flash drives, etc. Additionally, those skilled in the art will recognize that, without departing from the spirit and scope of the embodiments of this disclosure, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices.

[0047] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in common dictionaries, shall be interpreted as having the same meaning as they have in the context of the relevant technology and / or this specification, and shall not be interpreted as having an idealized or overly formal meaning unless expressly so defined herein.

[0048] In the following description, a display device according to an embodiment of the present disclosure will be described with reference to the accompanying drawings in relation to embodiments of the present disclosure.

[0049] Figure 1 This is a schematic block diagram illustrating a display device according to some embodiments.

[0050] Reference Figure 1 According to some embodiments, the display device 1000 may include a display unit 100, a scan driver 200, a bias driver 300, a data driver 400, a sensing unit 500, a timing controller 600, and a power supply unit 700.

[0051] The display unit 100 may include a plurality of pixels PX and can display images. The display unit 100 may include a plurality of data lines DL1, ..., and DLn, a plurality of sensing lines SL1, ..., and SLn, a plurality of scan lines SC1, ..., and SCn, a plurality of sensing control lines SS1, ..., and SSn, and a plurality of bias control lines BL11, ..., BL1n, BL21, ..., BL2n, BL31, ..., and BL3n. The plurality of pixels PX are positioned to be respectively connected to the plurality of data lines DL1, ..., and DLn, the plurality of sensing lines SL1, ..., and SLn, the plurality of scan lines SC1, ..., and SCn, the plurality of sensing control lines SS1, ..., and SSn, and the plurality of bias control lines BL11, ..., BL1n, BL21, ..., BL2n, BL31, ..., and BL3n. For example, when pixel PX is located in the i-th row and j-th column of display unit 100, pixel PX can be connected to the j-th data line DLj, the j-th sensing line SLj, the i-th scan line SCi, the i-th sensing control line SSi, and the i-th bias control lines BL1i, BL2i, and BL3i. Each pixel PX can receive voltages from the power supply unit 700, including the first power supply VDD, the second power supply VSS, the initialization power supply Vint, the first bias power supply BV1, and the second bias power supply BV2.

[0052] Here, the first power supply VDD, the second power supply VSS, the first bias power supply BV1, and the second bias power supply BV2 can be supplied to the pixel PX through separate power lines, and the initialization power supply Vint can be supplied to the pixel PX through sensing lines SL1, ..., and SLn. However, this disclosure is not limited thereto.

[0053] The scan driver 200 can receive a scan control signal SCS from the timing controller 600. The scan driver 200 can sequentially provide scan signals to scan lines SC1, ..., SCn in response to the scan control signal SCS. Furthermore, the scan driver 200 can receive a sensing line control signal SSS from the timing controller 600. The scan driver 200 can sequentially provide sensing control signals to sensing control lines SS1, ..., SSn in response to the sensing line control signal SSS.

[0054] As some implementation methods, in Figure 1 In this embodiment, the scan driver 200 can be connected to multiple scan lines SC1, ..., and SCn and multiple sensing control lines SS1, ..., and SSn to provide scan signals and sensing control signals, but this disclosure is not limited thereto. According to some embodiments, the multiple sensing control lines SS1, ..., and SSn can be connected to a single driver, and the single driver can provide sensing control signals to the sensing control lines SS1, ..., and SSn.

[0055] The bias driver 300 can receive a bias drive control signal BCS from the timing controller 600. The bias driver 300 can sequentially provide bias control signals to a plurality of bias control lines BL11, ..., BL1n, BL21, ..., BL2n, BL31, ..., and BL3n in response to the bias drive control signal BCS. In some embodiments, the plurality of bias control lines BL11, ..., BL1n, BL21, ..., BL2n, BL31, ..., and BL3n may include a first bias control line BL1, a second bias control line BL2, and a third bias control line BL3. Therefore, the bias driver 300 can provide a first bias control signal to the first bias control line BL1, a second bias control signal to the second bias control line BL2, and a third bias control signal to the third bias control line BL3.

[0056] exist Figure 1 In this diagram, bias control lines BL1, BL2, and BL3 are shown connected to a single bias driver 300, but this disclosure is not limited thereto. According to some embodiments, each of the bias control lines BL1, BL2, and BL3 may be connected to a different bias driver.

[0057] The data driver 400 can receive a data control signal DCS from the timing controller 600. In response to the data control signal DCS, the data driver 400 can convert the image data RGB into an analog data signal (or data voltage) and sequentially provide data signals to the data lines DL1, ..., and DLn.

[0058] The sensing unit 500 can receive a sensing drive control signal SDS from the timing controller 600. In response to the sensing drive control signal SDS, the sensing unit 500 can provide an initialization power supply Vint to the sensing lines SL1, ..., SLn. Furthermore, the sensing unit 500 can receive a sensing signal corresponding to the degradation information of pixel PX from pixel PX. For example... Figure 1 As shown, the sensing unit 500 is illustrated as being configured separately from the data driver 400, but this disclosure is not limited thereto. According to some embodiments, the sensing unit 500 may be included within the data driver 400.

[0059] The timing controller 600 can receive input control signals and input image signals from an image source such as an external graphics device. The timing controller 600 can generate image data RGB suitable for the operating conditions of the display unit 100 based on the input image signals, and can provide the image data RGB to the data driver 400. The timing controller 600 can generate a scan control signal SCS for controlling the driving timing of the scan driver 200, and can generate a sensing line control signal SSS based on the input control signals, and can provide the scan control signal SCS and the sensing line control signal SSS to the scan driver 200. Furthermore, the timing controller 600 can generate a bias drive control signal BCS for controlling the driving timing of the bias driver 300, a data control signal DCS for controlling the driving timing of the data driver 400, and a sensing drive control signal SDS for controlling the driving timing of the sensing unit 500 based on the input control signals, and can provide the bias drive control signal BCS, the data control signal DCS, and the sensing drive control signal SDS to the bias driver 300, the data driver 400, and the sensing unit 500, respectively.

[0060] The power supply unit 700 can supply the voltages of the first power supply VDD, the second power supply VSS, the initialization power supply Vint, the first bias power supply BV1, and the second bias power supply BV2 to the pixel PX. The first power supply VDD can be a voltage with a high level, which is supplied to the light-emitting element LD included in the pixel PX. Figure 2 The anode (shown in the diagram) and the second power supply VSS can be a voltage with a low level, which is supplied to the light-emitting element LD (illuminant) included in the pixel PX. Figure 2 The cathode is shown in the diagram. The first power supply VDD and the second power supply VSS can be driving voltage sources for emitting light from the pixel PX. The initialization power supply Vint can be a power supply used to initialize (or reset) the pixel PX, and can be a voltage with a level different from that of the second power supply VSS. The first bias power supply BV1 can be the first transistor T1 (shown in the diagram) supplied to the pixel PX. Figure 2 The voltage source is shown in the diagram, and the second bias power supply BV2 can be a voltage source supplied to the anode of the light-emitting element LD. In some embodiments, the voltage provided by the first bias power supply BV1 can be lower than the voltage provided by the second bias power supply BV2.

[0061] exist Figure 1 In this embodiment, the timing controller 600, sensing unit 500, data driver 400, and power supply unit 700 are shown in a separate configuration, but this disclosure is not limited thereto. At least two of the timing controller 600, sensing unit 500, data driver 400, and power supply unit 700 may be implemented as a single chip.

[0062] In the following text, reference will be made to Figure 2 Describes pixels according to some implementation methods.

[0063] Figure 2 This is a circuit diagram showing a pixel of a display device according to some embodiments.

[0064] Reference Figure 2 According to some embodiments, a pixel PX may include a pixel circuit PXC and a light source unit LSU for generating light with a brightness corresponding to a data signal.

[0065] The pixel circuit PXC may include a first transistor T1, a second transistor T2, a third transistor T3, a storage capacitor Cst, and bias transistors BT1, BT2, and BT3. The bias transistors BT1, BT2, and BT3 may include the first bias transistor BT1, the second bias transistor BT2, and the third bias transistor BT3.

[0066] The first transistor T1 can be a drive transistor for controlling the drive current applied to the light source unit LSU, and can be connected between the first power supply VDD and the first node b. For example, the first electrode of the first transistor T1 can be connected to the first power supply VDD, the second electrode of the first transistor T1 can be connected to the first node b, and the gate electrode of the first transistor T1 can be connected to the third node a. The first transistor T1 can control the drive current applied from the first power supply VDD through the first node b to the light source unit LSU according to the voltage difference between the first node b and the third node a. In some embodiments, the first electrode of the first transistor T1 can be the drain electrode, and the second electrode of the first transistor T1 can be the source electrode, but this disclosure is not limited thereto. According to some embodiments, the first electrode can be the drain electrode, and the second electrode can be the source electrode.

[0067] The second transistor T2 can be a switching transistor that selects and activates pixel PX in response to a scan signal, and can be connected between data line DL and third node a. For example, the first electrode of the second transistor T2 can be connected to data line DL, the second electrode of the second transistor T2 can be connected to third node a, and the gate electrode of the second transistor T2 can be connected to scan line SC. When a scan signal with a gate on-state voltage (e.g., a high-level voltage) is provided from scan line SC, the second transistor T2 can be turned on to electrically connect data line DL and third node a. Here, third node a can be a point connecting the second electrode of the second transistor T2 and the gate electrode of the first transistor T1, and the second transistor T2 can transmit the data voltage to the gate electrode of the first transistor T1.

[0068] The third transistor T3 can be a sensing transistor used for external compensation of pixel PX, and can be connected between sensing line SL and first node b. For example, the first electrode of the third transistor T3 can be connected to sensing line SL, the second electrode of the third transistor T3 can be connected to first node b, and the gate electrode of the third transistor T3 can be connected to sensing control line SS. When a sensing control signal with a gate on-state voltage (e.g., a high-level voltage) is provided from sensing control line SS, the third transistor T3 can be turned on to electrically connect sensing line SL and first node b.

[0069] According to some implementations, the display device can be driven by dividing the operation of the display device into display periods and sensing periods.

[0070] The sensing period can be a period of time used to extract characteristics of each pixel PX (e.g., the threshold voltage of the first transistor T1).

[0071] During the sensing period, the third transistor T3 can obtain a sensing signal through the sensing line SL by connecting the first transistor T1 to the sensing line SL, and can use the sensing signal to detect the characteristics of each pixel PX (including the threshold voltage of the first transistor T1). The image data can be transformed using information related to the characteristics of each pixel PX, thereby compensating for characteristic deviations between pixels PX.

[0072] Additionally, the third transistor T3 can be an initialization transistor capable of initializing the first node b. When the third transistor T3 is turned on by a sensing control signal during the sensing and / or display period, the voltage of the initialization power supply Vint can be transferred to the first node b. Therefore, the other electrode of the storage capacitor Cst connected to the first node b can be initialized.

[0073] According to some implementations, the sensing line SL can be omitted, and the first electrode of the third transistor T3 can be connected to the data line DL. Additionally, when the sensing control line SS is omitted, the gate electrode of the third transistor T3 can be connected to the scan line SC.

[0074] Simultaneously, various methods can be used to extract information related to the characteristics of pixel PX during the sensing period. In some implementations, pixel PX can be driven by various driving methods during the sensing period.

[0075] Additionally, the display period can be the period during which an image (e.g., a predetermined image) is displayed by pixels PX in response to a data signal. See below for further details. Figure 3 Describes the process of driving pixel PX during the display period.

[0076] One electrode of the storage capacitor Cst can be connected to the third node a, and the other electrode of the storage capacitor Cst can be connected to the first node b. The storage capacitor Cst can be charged with the data voltage corresponding to the data signal provided to the third node a during each frame period. Therefore, the storage capacitor Cst can store the voltage of the gate electrode of the first transistor T1 (i.e., the data voltage).

[0077] The first bias transistor BT1 can be a transistor used to apply a bias voltage to the first transistor T1, and can be connected between the first bias power supply BV1 and the third node a. For example, the first electrode of the first bias transistor BT1 can be connected to the first bias power supply BV1, the second electrode of the first bias transistor BT1 can be connected to the third node a, and the gate electrode of the first bias transistor BT1 can be connected to the first bias control line BL1. When a first bias control signal with a gate on-state voltage (e.g., a high-level voltage) is provided from the first bias control line BL1, the first bias transistor BT1 can be turned on to connect the first bias power supply BV1 and the third node a. Therefore, the voltage of the first bias power supply BV1 can be applied to the gate electrode of the first transistor T1. Here, the voltage applied from the first bias power supply BV1 can be referred to as the first bias voltage.

[0078] The second bias transistor BT2 can be a transistor used to apply a bias voltage to the light source unit LSU, and can be connected between the second bias power supply BV2 and the second node c. For example, the first electrode of the second bias transistor BT2 can be connected to the second bias power supply BV2, the second electrode of the second bias transistor BT2 can be connected to the second node c, and the gate electrode of the second bias transistor BT2 can be connected to the second bias control line BL2. When a second bias control signal with a gate on-state voltage (e.g., a high-level voltage) is provided from the second bias control line BL2, the second bias transistor BT2 can be turned on to connect the second bias power supply BV2 and the second node c. Therefore, the voltage of the second bias power supply BV2 can be applied to the second node c. The second node c can be the point where the light source unit LSU and the pixel circuit PXC are connected, and the voltage of the second bias power supply BV2 can be provided to one electrode of the light source unit LSU. Here, the voltage applied from the second bias power supply BV2 can be referred to as the second bias voltage.

[0079] The third bias transistor BT3 can be a transistor used to adjust the bias application timing (or emittance timing) and can be connected between the first node b and the second node c. For example, the first electrode of the third bias transistor BT3 can be connected to the first node b, the second electrode of the third bias transistor BT3 can be connected to the second node c, and the gate electrode of the third bias transistor BT3 can be connected to the third bias control line BL3. When a third bias control signal with a gate on-state voltage (e.g., a high-level voltage) is provided from the third bias control line BL3, the third bias transistor BT3 can be turned on to connect the first node b and the second node c. That is, the third bias transistor BT3 can electrically connect the first transistor T1 and the light source unit LSU. Therefore, the voltage of the first node b can be applied to the second node c.

[0080] In some embodiments, each of the first transistor T1, the second transistor T2, the third transistor T3, and the bias transistors BT1, BT2, and BT3 may comprise silicon semiconductor and may be an N-type transistor. However, this disclosure is not limited thereto. According to some embodiments, at least one of the first transistor T1, the second transistor T2, the third transistor T3, and the bias transistors BT1, BT2, and BT3 may comprise oxide semiconductor, or may be changed to a P-type transistor.

[0081] The light source unit LSU may include at least one light-emitting element LD connected between a first power supply VDD and a second power supply VSS.

[0082] In some embodiments, the light-emitting element (LD) can be a micro-light-emitting element with dimensions ranging from nanometers to micrometers. These micro-light-emitting elements can include materials with inorganic crystal structures, and materials with inorganic crystal structures can emit light. However, this is just an example, and at least one of the light-emitting elements (LD) can be an organic light-emitting element.

[0083] The light source unit (LSU) may include a first electrode ELT1 (also called a first pixel electrode or first alignment electrode) connected to a first power supply VDD via a pixel circuit PXC, a second electrode ELT2 (also called a second pixel electrode or second alignment electrode) connected to a second power supply VSS, and a plurality of light-emitting elements (LDs) connected in parallel in the same direction between the first electrode ELT1 and the second electrode ELT2. In some embodiments, the first electrode ELT1 may be an anode, and the second electrode ELT2 may be a cathode.

[0084] According to some implementations, the first power supply VDD and the second power supply VSS can have different potentials, causing the light-emitting element LD to emit light. As an example, the first power supply VDD can be set to a high potential power supply, and the second power supply VSS can be set to a low potential power supply. In this case, the potential difference between the first power supply VDD and the second power supply VSS can be set to be greater than or equal to the threshold voltage of the light-emitting element LD during the emission period of the pixel PX.

[0085] Each of the light-emitting elements (LDs) can emit light with a brightness corresponding to the drive current supplied through the corresponding pixel circuit (PXC). For example, during each frame period, the pixel circuit (PXC) can supply a drive current to the light source unit (LSU) corresponding to the grayscale value to be rendered in the corresponding frame. The drive current supplied to the light source unit (LSU) can be shunt and can flow to the light-emitting elements (LDs) connected in the forward direction. Therefore, when each light-emitting element (LD) emits light with a brightness corresponding to the current flowing through it, the light source unit (LSU) can emit light with a brightness corresponding to the drive current.

[0086] The light-emitting elements (LDs) can be connected in parallel in the forward direction between the first electrode ELT1 and the second electrode ELT2. Each LD connected in the forward direction between the first power supply VDD and the second power supply VSS can constitute an effective light source, and these effective light sources can constitute the light source unit (LSU) of the pixel PX.

[0087] In some embodiments, in addition to the light-emitting elements LD that constitute each effective light source, the light source unit LSU may also include at least one ineffective light source. For example, at least one reverse light-emitting element LDrv may also be connected between the first electrode ELT1 and the second electrode ELT2.

[0088] Each reverse-emitting element (LDrv) can be connected in parallel with the light-emitting element (LD) constituting the effective light source between the first electrode ELT1 and the second electrode ELT2, and can be connected between the first electrode ELT1 and the second electrode ELT2 in the opposite direction to the light-emitting element LD. Even when a driving voltage (e.g., a predetermined driving voltage and / or a forward driving voltage) is applied between the first electrode ELT1 and the second electrode ELT2, the reverse-emitting element (LDrv) can remain in a disabled state. Therefore, the reverse-emitting element (LDrv) can remain substantially non-emitting.

[0089] According to some embodiments, a light source unit (LSU) may include at least two light-emitting elements (LDs) connected in series with each other. In some embodiments, the light source unit (LSU) may include multiple light-emitting elements (LDs) connected in series in the forward direction between a first power supply (VDD) and a second power supply (VSS), and the multiple light-emitting elements (LDs) may constitute each effective light source.

[0090] In the following text, reference will be made to Figure 3 Describes the operation of pixels according to some implementation methods.

[0091] Figure 3 It is shown Figure 2 The timing diagram shows an example of the operation of one pixel. Figure 3 A frame showing the time is displayed.

[0092] Reference Figure 3 First, the first bias control signal and the second bias control signal can be provided to the first bias control line BL1 and the second bias control line BL2 respectively, so that the first bias transistor BT1 and the second bias transistor BT2 can be turned on.

[0093] That is, the first bias transistor BT1 and the second bias transistor BT2 can be turned on between the first time point t1 and the second time point t2. The time period between the first time point t1 and the second time point t2 can be referred to as the first time period P1 in a frame. Before and after the first time period P1, the third bias transistor BT3 can be turned on continuously because the third bias transistor BT3 is provided with a third bias control signal.

[0094] During the first time period P1, since the first bias transistor BT1 is turned on, the voltage of the first bias power supply BV1 can be applied to the third node a. That is, the first bias voltage level V1 can be applied to the gate electrode of the first transistor T1. In some embodiments, the first bias voltage level V1 can be set to various voltages so that the third node a can be initialized. For example, the first bias voltage level V1 can be set to about -1V, but this disclosure is not limited thereto.

[0095] Furthermore, during the first time period P1, the voltage of the second bias power supply BV2 can be applied to the second node c because the second bias transistor BT2 is turned on. Additionally, the second bias voltage can also be applied to the first node b because the third transistor T3 is turned on. According to some embodiments, the second bias voltage level V2 can be higher than the first bias voltage level V1 and can have various values. For example, the second bias voltage level V2 can be set to approximately 0V, but this disclosure is not limited thereto.

[0096] The first time period P1 can be the time period during which a bias voltage (e.g., a corresponding bias voltage) is applied to each node connected to the first transistor T1 and the light source unit LSU.

[0097] After the second time point t2, the first bias transistor BT1 and the second bias transistor BT2 can be turned off, but the first bias voltage level V1 applied to the third node a and the second bias voltage level V2 applied to the first node b and the second node c can be maintained.

[0098] At the third time point t3, the scan signal and the sensing control signal can be provided to the scan line SC and the sensing control line SS respectively, so that the second transistor T2 and the third transistor T3 can be turned on.

[0099] With the second transistor T2 turned on, the data voltage DATA can be applied to the third node a. That is, the data voltage DATA can be applied to the gate electrode of the first transistor T1, and the data voltage DATA can be stored in the gate electrode via an electrode of the storage capacitor Cst connected to the gate electrode of the first transistor T1. Specifically, the data voltage DATA can be applied after the first time period P1, during which the voltage of the first bias power supply BV1 is applied to the first transistor T1, and the voltage of the second bias power supply BV2 is applied to the light source unit LSU.

[0100] Because the third transistor T3 is turned on, the initialization voltage level V3 of the initialization power supply Vint can be applied to the first node b. Since the third bias transistor BT3 is also turned on even after the third time point t3, the initialization voltage level V3 applied to the first node b can also be applied to the second node c. Because the first node b is connected to the other electrode of the storage capacitor Cst, the initialization voltage level V3 can be stored in the first node b. Furthermore, the initialization voltage level V3 of the initialization power supply Vint can be set to approximately equal to or higher than the second bias voltage level V2 of the second bias power supply BV2.

[0101] After the third time point t3, the voltage corresponding to the difference between the data voltage DATA and the initialization voltage level V3 can be stored in the storage capacitor Cst. Here, since the initialization voltage level V3 is fixed as a constant voltage, the voltage stored in the storage capacitor Cst can be determined by the data voltage DATA.

[0102] After the voltage corresponding to the difference between the data voltage DATA and the initialization voltage level V3 is stored in the storage capacitor Cst, the first transistor T1 can supply a current corresponding to the voltage stored in the storage capacitor Cst through the first node b, the third bias transistor BT3, and the second node c. The light source unit LSU can then generate light (e.g., light with a predetermined brightness) in response to the amount of current supplied from the first transistor T1.

[0103] Between the fourth time point t4 and the fifth time point t5, the second bias control signal can be provided to the second bias control line BL2, and the third bias control signal can be not provided to the third bias control line BL3.

[0104] When the second bias control signal is provided to the second bias control line BL2, the second bias transistor BT2 can be turned on. When the third bias control signal is stopped from being provided to the third bias control line BL3, the third bias transistor BT3 can be turned off. Therefore, the first node b and the second node c can be electrically disconnected.

[0105] When the second bias transistor BT2 is turned on, a second bias voltage level V2 can be applied to the second node c. When the second bias voltage level V2 is applied to the second node c, the light-emitting element LD included in the light source unit LSU can be initialized to the applied bias state. In this case, the light-emitting element LD can be in a non-emitting state.

[0106] The time interval between the fourth time point t4 and the fifth time point t5 can be referred to as the second time interval P2 in a frame. That is, the second time interval P2 can be the period during which only the second bias power supply BV2 is supplied to the light source unit LSU after the data voltage DATA is applied to the pixel PX.

[0107] After the fifth time point t5, since the third bias transistor BT3 is turned on again, the second node c can be connected to the first node b, and the voltage of the second node c can be transferred to the first node b. In this case, the light source unit LSU can generate light (e.g., light with a predetermined brightness) in response to the amount of current supplied from the first transistor T1.

[0108] At the same time, although Figure 3 A frame may include a second time period P2 once, but this disclosure is not limited thereto. For example, a frame may include more than one second time period P2 for providing a second bias voltage level V2 to the light source unit LSU.

[0109] During the second time period P2, because the third bias transistor BT3 is turned off, a bias voltage can be provided to supplement the characteristics of the light source unit LSU, regardless of the driving of the first transistor T1 and the data voltage DATA stored in the storage capacitor Cst.

[0110] Because the third bias transistor BT3 connected to the second node c is turned off during the second time period P2, the light-emitting element LD of the light source unit LSU does not need to be supplied with drive current and can not emit light. That is, the second time period P2 can be referred to as the non-emission period.

[0111] Therefore, according to some embodiments, the display device can apply a bias voltage to the driving transistor and / or the light-emitting element during a frame. Thus, when a ghost image appears due to variations in the characteristics of the driving transistor and / or the light-emitting element, the recovery time of the ghost image can be reduced.

[0112] In the following text, reference will be made to Figure 4A , Figure 4B and Figure 5 This describes the characteristics of a display device according to a comparative example and the characteristics of a display device according to some embodiments.

[0113] Figure 4A It is a graph used to illustrate the characteristic changes of the first transistor in a display device according to a comparative example, in which a residual image may appear. Figure 4B It is a graph used to illustrate the changes in the characteristics of the light-emitting element in a display device according to a comparative example, in which a residual image may appear. Figure 5 This is a graph illustrating the effect of improving afterimage in a display device according to some embodiments. In the following text, reference will be made to the description above. Figure 2 The circuit diagram is provided for description.

[0114] Reference Figure 4A In a display device according to a comparative example, the gate-source voltage Vgs of the first transistor T1 before and after white stress is applied to the display device is shown.

[0115] The first transistor T1 can be connected between the first power supply VDD and the light source unit LSU, and can provide drive current to the light source unit LSU, enabling the light source unit LSU to emit light. The gate-source voltage Vgs of the first transistor T1 can be determined by the data voltage applied through the second transistor T2. Furthermore, the first transistor T1 can provide drive current to the light source unit LSU according to its gate-source voltage Vgs.

[0116] However, when the threshold voltage of the first transistor T1 changes, the driving current supplied to the light source unit LSU may gradually increase even when the same data voltage is applied. As the driving current increases, the brightness of the light emitted from the light-emitting element LD of the light source unit LSU increases, so even if the image of a frame changes, an afterimage may be retained.

[0117] like Figure 4A As shown, the case of providing a data voltage corresponding to white during an exemplary frame period will be described as an example. Here, when 48 gray levels are implemented before and after the exemplary frame, it can be seen that the drive current Id is set differently according to the same gate-source voltage Vgs. As described above, in the display device according to the comparative example, problems such as increased brightness of light emitted from the light-emitting element and afterimage generation may occur due to changes in the characteristics of the first transistor T1. In some embodiments, to solve this problem, a first bias voltage for controlling the gate-source voltage Vgs of the first transistor T1 can be applied.

[0118] When a first bias voltage is applied to the gate electrode of the first transistor T1, the first transistor T1 can be initialized to the characteristics corresponding to the first bias voltage, regardless of the data voltage provided in the previous frame period.

[0119] Reference Figure 4B In the display device according to the comparative example, as the gate-source voltage Vgs of the first transistor T1 increases, the drive current I can increase. Furthermore, as the drive current applied to the anode of the light-emitting element increases, the current flowing through the light-emitting element can also increase. Therefore, because the brightness of the light emitted from the light-emitting element increases, even if the image of a frame is changed, afterimages may be retained. As described above, in the display device according to the comparative example, due to the change in the characteristics of the light-emitting element, problems such as increased brightness of the light emitted from the light-emitting element and afterimage generation may occur.

[0120] Therefore, in order to solve this problem, in some implementations, a second bias voltage can be applied to control the voltage applied to the anode of the light-emitting element.

[0121] Reference Figure 5 In a display device according to some embodiments, the change in brightness over time can be confirmed.

[0122] To check the degree of image restoration of the display panel, in a display device that emits light (e.g., emits light with a predetermined brightness) according to some embodiments, stress is applied with black and / or white to darken or brighten the brightness of the display device. The lines shown, thicker than the trend lines, represent the brightness of the display device when black and / or white stress is applied.

[0123] At approximately 600 seconds, black stress is applied to the display device. At approximately 1200 seconds, black stress is applied to the display device again after white stress. In this case, a tendency is observed for the display device to recover display (e.g., display a predetermined brightness), and at approximately 600 seconds, it can be seen that the display device can recover quickly after black stress (e.g., return to the predetermined brightness). The fact that recovery (e.g., return to the predetermined brightness) takes a short time after stress application can mean that transient afterimages can be rapidly improved.

[0124] Therefore, in some embodiments, by applying a first bias voltage and a second bias voltage to the display device to apply black stress, the residual image can be quickly recovered even if the characteristics of the first transistor and the light-emitting element change. In some embodiments, to apply black stress, a first bias voltage and a second bias voltage having a low level can be applied.

[0125] That is, in a display device according to some embodiments, a bias voltage with a low level can be applied to the driving transistor and / or the light-emitting element (LD) during a frame. Therefore, when a ghost image occurs due to changes in the characteristics of the driving transistor and / or the light-emitting element (LD), the recovery time of the ghost image can be reduced.

[0126] In the following text, reference will be made to Figures 6 to 8 A display device and a method for driving the display device are described according to some embodiments.

[0127] Figure 6 This is a schematic block diagram illustrating a display device according to some embodiments. Figure 7 This is a circuit diagram illustrating a pixel of a display device according to some embodiments, and Figure 8 It is shown Figure 7 The timing diagram shows an example of the operation of a single pixel.

[0128] Figure 6 The block diagram is similar to Figure 1 The block diagram, Figure 7 The circuit diagram is similar to Figure 2 The circuit diagram, and Figure 8 The timing diagram is similar to Figure 3 The timing diagram. In the following text, the sequence will be omitted. Figures 1 to 3 The descriptions overlap, and the main focus will be on the differences.

[0129] First, refer to Figure 6 According to some embodiments, the display device 1000 may include a display unit 100, a scan driver 200, a bias driver 300, a data driver 400, a sensing unit 500, a timing controller 600, and a power supply unit 700'.

[0130] The display unit 100 may include a plurality of pixels PX and display an image. The display unit 100 may include a plurality of data lines DL1, ..., and DLn; a ​​plurality of sensing lines SL1, ..., and SLn; a ​​plurality of scan lines SC1, ..., and SCn; a plurality of sensing control lines SS1, ..., and SSn; and a plurality of bias control lines BL11, ..., BL1n, BL21, ..., BL2n, BL31, ..., BL3n. The plurality of pixels PX are positioned to be respectively connected to the plurality of data lines DL1, ..., and DLn; the plurality of sensing lines SL1, ..., and SLn; the plurality of scan lines SC1, ..., and SCn; the plurality of sensing control lines SS1, ..., and SSn; and the plurality of bias control lines BL11, ..., BL1n, BL21, ..., BL2n, BL31, ..., and BL3n. Each pixel PX may receive a first power supply VDD, a second power supply VSS, and an initialization power supply Vint voltage from the power supply unit 700'.

[0131] The power supply unit 700' can provide the voltages of the first power supply VDD, the second power supply VSS, and the initialization power supply Vint to the pixel PX.

[0132] Reference Figure 7 A pixel PX may include a pixel circuit PXC and a light source unit LSU for generating light with a brightness corresponding to the data signal.

[0133] The pixel circuit PXC may include a first transistor T1, a second transistor T2, a third transistor T3, a storage capacitor Cst, and bias transistors BT1, BT2, and BT3. The bias transistors BT1, BT2, and BT3 may include the first bias transistor BT1, the second bias transistor BT2, and the third bias transistor BT3.

[0134] The first bias transistor BT1 can be connected between the second power supply VSS and the third node a. For example, the first electrode of the first bias transistor BT1 can be connected to the second power supply VSS, the second electrode of the first bias transistor BT1 can be connected to the third node a, and the gate electrode of the first bias transistor BT1 can be connected to the first bias control line BL1. When the first bias transistor BT1 is turned on, the voltage of the second power supply VSS can be applied to the third node a.

[0135] The second bias transistor BT2 can be connected between the initialization power supply Vint and the second node c. For example, the first electrode of the second bias transistor BT2 can be connected to the initialization power supply Vint, the second electrode of the second bias transistor BT2 can be connected to the second node c, and the gate electrode of the second bias transistor BT2 can be connected to the second bias control line BL2. When the second bias transistor BT2 is turned on, the voltage of the initialization power supply Vint can be applied to the second node c. In some embodiments, the voltage of the second power supply VSS can be set to be lower than the voltage of the initialization power supply Vint.

[0136] Reference Figure 8 To describe the driver Figure 7 The method for pixel PX. A first bias control signal and a second bias control signal can be provided to the first bias control line BL1 and the second bias control line BL2 respectively between a first time point t1 and a second time point t2, so that the first bias transistor BT1 and the second bias transistor BT2 can be turned on. On the other hand, since the third bias transistor BT3 is not provided with a separate bias control signal, the third bias transistor BT3 can be turned off.

[0137] During the first time period P1, because the first bias transistor BT1 is turned on, the voltage of the second power supply VSS can be applied to the third node a. That is, the voltage level V4 of the second power supply VSS can be applied to the gate electrode of the first transistor T1. Furthermore, during the first time period P1, because the second bias transistor BT2 is turned on, the initialization voltage level V3 can be applied to the second node c. Additionally, the initialization voltage level V3 can be set to a level higher than the voltage level V4 of the second power supply VSS. Because the first transistor T1 can be turned on during the first time period P1, a high-level voltage can be provided to the first node b by applying current according to the first power supply VDD.

[0138] At the third time point t3, the scan signal and the sensing control signal can be provided to the scan line SC and the sensing control line SS, respectively, so that the second transistor T2 and the third transistor T3 can be turned on. Because the second transistor T2 is turned on, the data voltage DATA can be applied to the third node a, and because the third transistor T3 is turned on, the initialization voltage level V3 can be applied to the first node b. In some embodiments, because the initialization voltage level V3 is set to a level lower than the first power supply VDD, the voltage level of the first node b can be reduced at the third time point t3.

[0139] After the third time point t3, the voltage corresponding to the difference between the data voltage DATA and the initialization voltage level V3 can be stored in the storage capacitor Cst. Here, since the initialization voltage level V3 is fixed as a constant voltage, the voltage stored in the storage capacitor Cst can be determined by the data voltage DATA.

[0140] After the voltage corresponding to the difference between the data voltage DATA and the initialization voltage level V3 is stored in the storage capacitor Cst, the first transistor T1 can supply a current corresponding to the voltage stored in the storage capacitor Cst through the first node b, the third bias transistor BT3, and the second node c. The light source unit LSU can then generate light (e.g., light with a predetermined brightness) in response to the amount of current supplied from the first transistor T1.

[0141] Between the fourth time point t4 and the fifth time point t5, a second bias control signal can be provided to the second bias control line BL2, and the provision of a third bias control signal to the third bias control line BL3 can be stopped.

[0142] When the second bias control signal is provided to the second bias control line BL2, the second bias transistor BT2 can be turned on. When the third bias control signal is stopped from being provided to the third bias control line BL3, the third bias transistor BT3 can be turned off. Therefore, the first node b and the second node c can be electrically disconnected.

[0143] When the second bias transistor BT2 is turned on, the initialization voltage level V3 can be applied to the second node c. When the initialization voltage level V3 is applied to the second node c, the light-emitting element LD included in the light source unit LSU can be initialized to the applied bias state. In this case, the light-emitting element LD can be in a non-emitting state.

[0144] After the fifth time point t5, since the third bias transistor BT3 is turned on again, the second node c can be connected to the first node b, and the voltage of the second node c can be transferred to the first node b. In this case, the light source unit LSU can generate light (e.g., light with a predetermined brightness) in response to the amount of current supplied from the first transistor T1.

[0145] At the same time, although Figure 8 The second time period P2 may be included once during a frame, but this disclosure is not limited thereto. For example, a second time period P2 for providing an initial voltage level V3 to the light source unit LSU may be included more than once during a frame.

[0146] During the second time period P2, because the third bias transistor BT3 is turned off, an initialization voltage can be provided to supplement the characteristics of the light source unit LSU, regardless of the driving of the first transistor T1 and the data voltage DATA stored in the storage capacitor Cst.

[0147] Because the third bias transistor BT3 connected to the second node c is turned off during the second time period P2, the light-emitting element LD of the light source unit LSU does not need to be supplied with drive current and can not emit light. That is, the second time period P2 can be referred to as the non-emission period.

[0148] Therefore, according to some embodiments, the display device can apply a bias voltage to the driving transistor and / or the light-emitting element during a frame. Thus, when a ghost image appears due to variations in the characteristics of the driving transistor and / or the light-emitting element, the recovery time of the ghost image can be reduced.

[0149] According to these embodiments, by applying a bias voltage to the driving transistor and / or the light-emitting element during the first and second time periods of a frame, the residual image that may occur due to changes in the characteristics of the driving transistor and / or the light-emitting element can be improved.

[0150] The effects of this disclosure are not limited to those described above, and many more effects are included in this specification.

[0151] As described above, the best and / or suitable embodiments of this disclosure have been disclosed through detailed description and accompanying drawings. However, those skilled in the art or of ordinary skill will understand that various modifications and alterations are possible without departing from the spirit and scope of the disclosure as set forth in the appended claims.

[0152] Therefore, the technical scope of this disclosure is not limited to the detailed description in the specification, but should be determined by the claims and their functional equivalents that will be included therein.

Claims

1. Pixel, including: Light source unit; A first transistor is connected between a first power supply and a first node and is configured to control the drive current applied to the light source unit; A first bias transistor is connected between a first bias power supply and the gate electrode of the first transistor. A second bias transistor is connected between a second bias power supply and a second node, the second node being electrically connected to the anode of the light source unit. The second transistor is connected between the gate electrode of the first transistor and the data line for applying the data voltage. Wherein, the first bias transistor and the second bias transistor are configured to be turned on during a first time period in a frame before the data voltage is applied, and The second bias transistor is configured to turn on at least once during a second time period after the data voltage is applied in the frame, and the first bias transistor is configured to turn off during the second time period. Wherein, the voltage level of the first bias power supply is lower than the voltage level of the second bias power supply.

2. The pixel of claim 1 further includes a third bias transistor connected between the first node and the second node.

3. The pixel according to claim 2, wherein, The third bias transistor is configured to be turned off during the second time period in the frame.

4. The pixel according to claim 1, further comprising: The third transistor is connected between the first node and the sensing line used to receive the voltage of the initialization power supply.

5. The pixel according to claim 4, wherein, The second transistor and the third transistor are configured to be turned on simultaneously between the first time period and the second time period.

6. The pixel of claim 5 further includes a storage capacitor connected between the first node and the gate electrode of the first transistor, and configured to store the data voltage.

7. The pixel according to claim 4, wherein, The light source unit includes at least one light-emitting element configured to emit light through the driving current.

8. The pixel according to claim 7, wherein, The first transistor is configured to receive the drive current from the first power supply, and The light source unit is configured to supply the driving current provided by the first transistor to a second power supply, the second power supply being set to a voltage value lower than that of the first power supply.

9. The pixel according to claim 8, wherein, The first bias power supply is the second power supply, and wherein the second bias power supply is the initialization power supply.

10. The pixel according to claim 1, wherein, The second bias transistor is directly connected to the second node.

Images