A semiconductor device and a manufacturing method thereof

Abstract

Embodiments of the present application provide a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a transistor array. The manufacturing method comprises: providing a wafer; forming an isolation layer and a first mask layer on the wafer, the isolation layer having through holes arranged in an array; epitaxially forming a columnar conductive channel in the through holes; removing the first mask layer to expose the sidewall of the columnar conductive channel of the transistor array, the extending direction of the columnar conductive channel being perpendicular to the surface of the wafer; forming a gate layer around the columnar conductive channel on the sidewall of each columnar conductive channel of the transistor array; and forming a source and a drain of a transistor at the two ends of the extending direction of each columnar conductive channel of the transistor array, respectively. In the manufacturing method of the semiconductor device provided by the embodiments of the present application, the source and the drain of the transistor array can be located on different surfaces of the wafer, which can greatly reduce the area of the transistor array.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] Transistors are widely used in electronic devices as switching devices or driving devices. For example, transistors can be used in Dynamic Random Access Memory (DRAM) to control the capacitance in each memory cell.

[0003] In related technologies, transistors mainly include planar transistors and buried-channel transistors. However, regardless of whether it is a planar transistor or a buried-channel transistor, its source (S) and drain (D) are located on opposite sides of the gate (G). In this structure, the source and drain occupy different positions, resulting in a larger transistor area. Furthermore, in memory devices, the source and drain of the transistor are connected to different structures after formation. When the source and drain are located on opposite sides of the gate, it easily leads to complex internal circuit wiring and increased manufacturing difficulty. Summary of the Invention

[0004] In view of this, the present application provides a semiconductor device and a method for manufacturing the same to solve at least one technical problem existing in the prior art.

[0005] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0006] In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor device, the semiconductor device comprising a transistor array; the manufacturing method comprising:

[0007] A wafer is provided, on which an isolation layer and a first mask layer having vias arranged in an array are formed;

[0008] A columnar conductive channel is formed inside and outside the through hole;

[0009] Remove the first mask layer to expose the sidewalls of the columnar conductive channel of the transistor array, the columnar conductive channel extending perpendicularly to the wafer surface;

[0010] A gate layer is formed around each columnar conductive channel in the transistor array on the sidewall.

[0011] The source and drain of a transistor are formed at both ends of the extension direction of each columnar conductive channel in the transistor array.

[0012] In some embodiments of this application, the gate layer includes a gate oxide layer and a gate electrode; the formation of a gate layer surrounding the pillar-shaped conductive channels on the sidewalls of each pillar-shaped conductive channel in the transistor array includes:

[0013] A gate oxide layer is formed around each columnar conductive channel in the transistor array on the sidewall of each columnar conductive channel.

[0014] The gate electrode is formed around each of the gate oxide layers on the sidewalls of the gate oxide layer.

[0015] In some embodiments of this application, forming the gate oxide layer surrounding the pillar-shaped conductive channel on the sidewall of the pillar-shaped conductive channel of the transistor array includes:

[0016] The sidewalls of each pillar-shaped conductive channel of the transistor array are oxidized to form the gate oxide layer surrounding the pillar-shaped conductive channel.

[0017] In some embodiments of this application, forming the gate electrode surrounding each of the gate oxide layers on the sidewalls of the gate oxide layers includes:

[0018] Conductive material is deposited in the grid-like first groove formed by removing the first mask layer to form the gate electrode surrounding each of the gate oxide layers; wherein the upper surface of the gate electrode is lower than the upper surface of the columnar conductive channel.

[0019] In some embodiments of this application, the manufacturing method further includes:

[0020] A second mask layer is formed on the gate electrode and the columnar conductive channel;

[0021] Along the extension direction of the columnar conductive channel, starting from the second mask layer, the second mask layer, the gate electrode, and the isolation layer are etched sequentially to form a second groove; wherein the second groove is located between adjacent columnar conductive channels;

[0022] Insulating material is deposited in the second groove to form an isolation structure.

[0023] In some embodiments of this application, the manufacturing method further includes forming an air gap within the isolation structure.

[0024] In some embodiments of this application, the columnar conductive channels are arranged in an array, and the extension direction of the second groove is parallel to the column direction of the columnar conductive channels; the gate electrodes of the transistors located in the same column are interconnected, and the interconnected gate electrodes are word lines of the transistors in the same column.

[0025] In some embodiments of this application, the manufacturing method further includes, prior to forming the source and the drain:

[0026] The second mask layer is thinned until the end of the columnar conductive channel away from the wafer is exposed.

[0027] The wafer is thinned from the back side until the end of the columnar conductive channel near the wafer is exposed.

[0028] In some embodiments of this application, the step of forming the source and drain of a transistor at both ends of the extending direction of each pillar conductive channel in the transistor array includes:

[0029] At the end of the columnar conductive channel away from the wafer, ion implantation is performed on each columnar conductive channel to form the source or drain of each transistor in the transistor array;

[0030] Ion implantation is performed on each of the columnar conductive channels near the wafer to form the drain or source of each transistor in the transistor array.

[0031] In some embodiments of this application, the manufacturing method further includes:

[0032] A bit line is formed, which is connected to the source or drain of each transistor in the transistor array;

[0033] A storage capacitor is formed, one end of which is connected to the drain or source of each transistor in the transistor array, and the other end of which is grounded. The storage capacitor is used to store data written to the semiconductor device.

[0034] In some embodiments of this application, the storage capacitors are arranged in an array; the angle between the column direction and the row direction of the storage capacitors is 90 degrees.

[0035] In some embodiments of this application, the storage capacitors are arranged in an array; the angle between the column direction and the row direction of the storage capacitors is 120 degrees.

[0036] Secondly, embodiments of this application provide a semiconductor device, the semiconductor device comprising:

[0037] A transistor array having columnar conductive channels; wherein the columnar conductive channels of the transistor array are arranged in an array, and the extending direction of the columnar conductive channels is perpendicular to the plane formed by the column direction and the row direction of the columnar conductive channels.

[0038] The sidewalls of each columnar conductive channel in the transistor array have a gate layer surrounding the columnar conductive channel; wherein the gate layer includes a gate oxide layer and a gate electrode.

[0039] The columnar conductive channel of the transistor array has a source and a drain at each end of its extension direction.

[0040] An isolation structure is located between adjacent columnar conductive channels and is parallel to the gate electrode.

[0041] In some embodiments of this application, the isolation structure includes an insulating material layer and an air gap formed in the insulating material layer.

[0042] In some embodiments of this application, the extension direction of the isolation structure is parallel to the column direction of the columnar conductive channel; the gate electrodes of the transistors located in the same column are interconnected, and the interconnected gate electrodes are word lines of the transistors in the same column.

[0043] In some embodiments of this application, the semiconductor device further includes:

[0044] Bit lines are connected to the source or drain of each transistor in the transistor array;

[0045] A storage capacitor, one end of which is connected to the drain or source of each transistor in the transistor array, and the other end of which is grounded, is used to store data written to the semiconductor device.

[0046] In some embodiments of this application, the storage capacitors are arranged in an array; the angle between the column direction and the row direction of the storage capacitors is 90 degrees.

[0047] In some embodiments of this application, the storage capacitors are arranged in an array; the angle between the column direction and the row direction of the storage capacitors is 120 degrees.

[0048] This application provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a transistor array. The manufacturing method includes: providing a wafer; forming an isolation layer and a first mask layer on the wafer having vias arranged in an array; epitaxially forming columnar conductive channels inside and outside the vias; removing the first mask layer to expose the sidewalls of the columnar conductive channels of the transistor array, wherein the extending direction of the columnar conductive channels is perpendicular to the wafer surface; forming a gate layer surrounding the columnar conductive channels on the sidewalls of each columnar conductive channel of the transistor array; and forming a source and a drain of a transistor at opposite ends of the extending direction of each columnar conductive channel of the transistor array. In the semiconductor device manufacturing method provided in this application, the source and drain of the formed transistor array are located at opposite ends along the extending direction of the columnar conductive channels, which is perpendicular to the wafer surface, and the gate is formed around the columnar conductive channels. Thus, the source and drain of the transistors can be located on different sides of the wafer, greatly reducing the area of ​​the transistor array. Attached Figure Description

[0049] Figure 1A This is a schematic diagram of the structure of a planar transistor in related technologies;

[0050] Figure 1B This is a schematic diagram of the structure of a buried-channel transistor in related technologies;

[0051] Figure 1C This is a schematic diagram of the structure of a DRAM memory cell formed using planar transistors in related technologies;

[0052] Figure 1D This is a schematic diagram of the structure of a DRAM memory cell formed using buried channel transistors in related technologies.

[0053] Figure 1E This is a circuit diagram of a single memory cell in related technologies;

[0054] Figure 1F This is a circuit diagram of a memory cell array in related technologies;

[0055] Figure 2A , Figure 2B , Figure 2C and Figure 2D This is a schematic diagram of the DRAM array layout in related technologies;

[0056] Figure 3A A cross-sectional view of through holes arranged in an array, provided for an embodiment of this application;

[0057] Figure 3B A top view of through holes arranged in an array, provided for an embodiment of this application;

[0058] Figure 4A A cross-sectional view of the formation of a columnar conductive channel provided in an embodiment of this application;

[0059] Figure 4B A top view of the formation of a columnar conductive channel provided in an embodiment of this application;

[0060] Figure 5A This is a cross-sectional view provided in an embodiment of this application after removing the first mask layer;

[0061] Figure 5B This is a top view of an embodiment of the present application after removing the first mask layer;

[0062] Figure 6A A cross-sectional view of the formation of the second mask layer provided in an embodiment of this application;

[0063] Figure 6B For along Figure 6A Top view along the AA' direction;

[0064] Figure 7A A cross-sectional view of the formation of the second groove provided in an embodiment of this application;

[0065] Figure 7B For along Figure 7A Top view in the direction of BB';

[0066] Figure 8 Top view of four optional structures of the columnar conductive channel provided in the embodiments of this application;

[0067] Figure 9 A cross-sectional view of an isolation structure with an air gap provided for an embodiment of this application;

[0068] Figure 10 This is a cross-sectional view of a thinned wafer provided in an embodiment of this application;

[0069] Figure 11 This is a schematic diagram of an optional structure of a semiconductor device provided in an embodiment of this application;

[0070] Figure 12 A schematic diagram of an optional three-dimensional structure of a semiconductor device provided in an embodiment of this application;

[0071] Figure 13A and Figure 13B This application provides an optional arrangement of capacitors in a semiconductor device according to embodiments of the present application.

[0072] Figure 14A , Figure 14B and Figure 14C This is a schematic diagram of an optional structure of a storage capacitor in a semiconductor device provided in an embodiment of this application;

[0073] Figure 15 This is an optional process diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of this application.

[0074] The diagram includes: 101 - Source; 102, 302 - Bit lines; 103 - Drain; 104, 304, 404 - Storage capacitors; 105 - Word line; 106 - Transistor; 107 - Active region; 108, 308 - Bit line contacts; 109, 309 - Storage node contacts; 200 - Wafer; 200-1 - Wafer front side; 200-2 - Wafer back side; 201 - Isolation layer; 202 - First mask layer; 203 - Through-hole; 204, 204-1, 204-2, 204-3, 204-4 - columnar conductive channels; 205, 205-1, 205-2, 205-3, 205-4 - gate oxide layer; 206 - first groove; 207 - gate electrode; 208 - second mask layer; 209 - second groove; 210 - isolation structure; 211 - air gap; 501 - upper electrode plate; 502 - dielectric layer; 503 - lower electrode plate. Detailed Implementation

[0075] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0076] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0077] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0078] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0079] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0080] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0081] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0082] In related technologies, the transistors of mainstream memory include planar transistors and buried channel array transistors (BCAT). However, regardless of whether it is a planar transistor or a buried channel array transistor, the source and drain are located on the horizontal sides of the gate in terms of their structure. Figure 1A This is a schematic diagram of the structure of a planar transistor in related technologies. Figure 1B This is a schematic diagram of the structure of a buried-channel transistor in related technologies, such as... Figure 1A and 1B As shown, in the related technology, the source S and drain D of the transistor are located on opposite sides of the gate G. In this structure, the source and drain occupy different positions, resulting in a larger area for both planar transistors and buried channel transistors.

[0083] Furthermore, since transistors can be fabricated on silicon substrates, they can be used in various types of memory, such as DRAM, ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase-change random access memory (PCRAM), resistive random access memory (RRAM), and nano random access memory (NRAM). Typically, DRAM consists of multiple memory cells, each primarily composed of a transistor and a capacitor controlled by the transistor; that is, DRAM is a 1-transistor-1-capacitor (1T1C) memory cell.

[0084] Figure 1C This is a schematic diagram of the structure of a DRAM memory cell formed using planar transistors in related technologies. Figure 1D This is a schematic diagram of the structure of a DRAM memory cell formed using buried channel transistors in related technologies, such as... Figure 1C and Figure 1DAs shown, the source 101 of the transistor in the DRAM memory cell is electrically connected to the bit line 102, and the drain 103 is electrically connected to the storage capacitor 104. For chips formed using BCAT, chip-on-board (COB) packaging is typically used to form the memory. Since the source and drain of planar transistors and buried channel transistors are located on opposite sides of the gate, the bit lines and capacitors in the DRAM memory cell are also located on the same side of the gate. Furthermore, subsequent processes require the connection between the bit lines (BL), transistors, and capacitors, as well as the connection between the word lines (WL) and transistors. This results in complex circuit routing and a high manufacturing difficulty in the DRAM memory's storage array area.

[0085] Figure 1E This is a circuit diagram of a single memory cell in related technologies. Figure 1F This is a circuit diagram of a memory cell array in related technologies. For example... Figure 1E As shown, in a single memory cell, transistor 106 includes a gate, a source, and a drain. The gate of the transistor forms a word line 105, and the source (or drain) of the transistor is connected to a bit line 102. One end of the storage capacitor 104 is connected to the drain (or source) of the transistor, and the other end of the storage capacitor 104 is grounded. The storage capacitor is used to store data written into the memory cell. Figure 1F As shown, in a memory cell array, memory cells are arranged in an array, and each memory cell includes a transistor. In a DRAM memory array, a data bit is stored in the cell at the intersection of the column address and the row address. The row address strobe (RAS) is used to identify the row address, and the column address strobe (CAS) is used to identify the column address.

[0086] Figure 2A , Figure 2B , Figure 2C and Figure 2D This is a schematic diagram of the DRAM array layout in related technologies, such as... Figure 2A , Figure 2B , Figure 2C and Figure 2D As shown, the DRAM array layout includes parallel word lines 105 extending along a first direction, and the DRAM array layout also includes parallel bit lines 102 extending along a second direction, wherein the first direction and the second direction are not parallel. Figure 2C The word line 105 and bit line 102 shown extend in a perpendicular direction.

[0087] Continue to refer to Figure 2A , Figure 2B , Figure 2C and Figure 2D The DRAM array layout also includes active regions 107 arranged in parallel and extending along a third direction, with the angle between the extension direction of the active regions 107 and the extension direction of the bit lines 102 being 18° to 25°. Figure 2D Each transistor shown has an active region 107 that intersects with two word lines and one bit line. Both ends of the active region 107 are memory node contacts 109, and the middle of the active region 107 is a bit line contact 108. The two ends of the active region define the contact positions between the active region and the memory capacitors, i.e., the memory node cluster (SNC), while the middle of the active region defines the contact position between the active region and the bit line, i.e., the bit line contact (BLC). A single bit line can be used to individually read and erase two adjacent capacitors by switching the two word lines.

[0088] Therefore, for DRAM memory arrays in related technologies, when the feature size of the process is F, the minimum size of the memory cell in the memory array is 6F. 2 This means that the area occupied by a single storage unit is relatively large.

[0089] Based on the aforementioned problems in related technologies, this application provides a semiconductor device and its manufacturing method, which can provide a semiconductor device with a transistor structure of smaller area. Furthermore, the semiconductor device provided by this application can simplify the internal circuit layout of the semiconductor device and reduce the process difficulty of manufacturing the semiconductor device.

[0090] refer to Figure 15 , Figure 15 This is a schematic diagram of an optional process for manufacturing a semiconductor device according to an embodiment of this application. Figure 15 As shown, this application provides a method for manufacturing a semiconductor device, the semiconductor device including a transistor array; the method for manufacturing the semiconductor device includes the following steps:

[0091] Step S1501: Provide a wafer and form an isolation layer and a first mask layer on the wafer having vias arranged in an array;

[0092] Step S1502: Form columnar conductive channels inside and outside the through hole;

[0093] Step S1503: Remove the first mask layer to expose the sidewalls of the columnar conductive channel of the transistor array, wherein the extending direction of the columnar conductive channel is perpendicular to the wafer surface.

[0094] Step S1504: Form a gate layer surrounding the columnar conductive channel on the sidewall of each columnar conductive channel in the transistor array.

[0095] Step S1505: The source and drain of the transistor are formed at both ends of the extension direction of each columnar conductive channel in the transistor array.

[0096] The manufacturing method of the semiconductor device provided in the embodiments of this application will be described in further detail below.

[0097] refer to Figure 3A and Figure 3B , Figure 3A This is a cross-sectional view of through holes arranged in an array, provided in an embodiment of this application. Figure 3B This is a top view of an embodiment of the present application showing an array of through-holes. Figure 3A and Figure 3B As shown, a wafer 200 is provided, and an isolation layer 201 and a first mask layer 202 having arrayed vias 203 are formed on the wafer 200.

[0098] In this embodiment, the wafer is a single-crystal silicon material used to fabricate semiconductor devices. It is a silicon wafer formed by grinding, polishing, and slicing cylindrical single-crystal silicon. This embodiment does not impose any special limitations on the shape or size of the wafer. Figure 3B The image shown is only a partial view of the wafer and does not constitute a limitation on the scope of wafer protection in this application.

[0099] It should be noted that a wafer has two opposing surfaces; one surface is called the front side of the wafer, and the other surface is called the back side. For example... Figure 3A As shown, wafer 200 includes a front side 200-1 and a back side 200-2.

[0100] In some embodiments of this application, the vias arranged in an array can be formed by the following steps: forming an isolation layer and a first mask layer sequentially on a wafer, patterning the first mask layer, and then etching the isolation layer using the patterned first mask layer to form vias arranged in an array.

[0101] In this embodiment, the material of the isolation layer may include, but is not limited to, silicon nitride, silicon oxynitride, silicon carbide, silicon dioxide, or other insulating materials. The material of the first mask layer may include, but is not limited to, silicon nitride or silicon dioxide. The material of the isolation layer may be the same as or different from the material of the first mask layer. In this embodiment, the material of the isolation layer is silicon dioxide, and the material of the first mask layer is silicon nitride.

[0102] Here, the thickness direction of the wafer is defined as the Z-direction. Intersecting X and Y directions are defined on the top or bottom surface of the wafer perpendicular to the Z-direction. Based on the X and Y directions, the top or bottom surface of the wafer perpendicular to the Z-direction can be determined. For example, the X and Y directions are mutually perpendicular, thus the X, Y, and Z directions are mutually perpendicular to each other. In the embodiments of this application, vias, columnar conductive channels, and transistors are all arranged in an array, with the X-direction defined as the row direction and the Y-direction defined as the column direction. It should be noted that in the array arrangement, the row direction can be perpendicular to the column direction or have a certain angle between them.

[0103] Here, a dry etching process can be used to etch the isolation layer, such as plasma etching or reactive ion etching. It is worth noting that in this embodiment, the isolation layer is etched along the thickness direction of the wafer, i.e., the Z-direction; that is, the etching process does not etch the wafer itself. This embodiment does not impose any special limitations on the etching process.

[0104] refer to Figure 4A and Figure 4B , Figure 4A This is a cross-sectional view of the columnar conductive channel provided in an embodiment of this application. Figure 4B This is a top view of the formation of a columnar conductive channel provided for an embodiment of this application. (See attached image.) Figure 4A and Figure 4B As shown, columnar conductive channels 204 are formed on the inner and outer sides of the vias. The vias are arranged in an array on the wafer surface, and the columnar conductive channels 204 are also arranged in an array on the wafer surface.

[0105] It should be noted that many transistors are formed on a single wafer; therefore, multiple pillar-shaped conductive channels exist within a single wafer. In this embodiment, for ease of explanation, only a limited number of pillar-shaped conductive channels are shown as an example. For example, Figure 4B Only four columnar conductive channels arranged in an array are shown.

[0106] Specifically, epitaxial growth includes homoepitaxial growth and heteroepitaxial growth. For example, when the wafer is made of silicon, epitaxial growth of silicon material on a silicon substrate is homoepitaxial growth. In the embodiments of this application, silicon material can be epitaxially grown inside and outside vias to form an epitaxial layer, which subsequently serves as a pillar-shaped conductive channel.

[0107] refer to Figure 5A and Figure 5B , Figure 5A This is a cross-sectional view provided in an embodiment of this application after removing the first mask layer. Figure 5B This is a top view of an embodiment of this application after removing the first mask layer. Figure 5A and Figure 5BAs shown, the first mask layer is removed to expose the sidewalls of the columnar conductive channel 204 of the transistor array, the extension direction of the columnar conductive channel 204 being perpendicular to the surface of the wafer 200; and after removing the first mask layer, a grid-like first groove 206 is formed.

[0108] The transistors involved in the embodiments of this application may include field-effect transistors or other transistors with conductive channels. In the embodiments of this application, the columnar conductive channel is used to transfer or stop the transfer of charge under the action of an external electric field, thereby turning the transistor on or off.

[0109] In this embodiment, an array of columnar conductive channels is formed on the wafer surface, and the extension direction of each columnar conductive channel is perpendicular to the wafer surface, that is, the columnar conductive channel extends along the Z direction. Here, the extension direction of the columnar conductive channel is the direction of the current when the transistor is turned on.

[0110] In some embodiments of this application, the gate layer includes a gate oxide layer and a gate electrode; the formation of a gate layer surrounding the pillar-shaped conductive channels on the sidewalls of each pillar-shaped conductive channel in the transistor array includes:

[0111] A gate oxide layer is formed around each columnar conductive channel in the transistor array on the sidewall of each columnar conductive channel.

[0112] The gate electrode is formed around each of the gate oxide layers on the sidewalls of the gate oxide layer.

[0113] refer to Figure 6A and Figure 6B , Figure 6A This is a cross-sectional view of the formation of the second mask layer provided in an embodiment of this application. Figure 6B For along Figure 6A A top view along the AA' direction. (Example) Figure 6A and Figure 6B As shown, a gate oxide layer 205 is formed around the sidewall of each columnar conductive channel 204 in the transistor array, and a gate electrode 207 is formed around each gate oxide layer 205 on the sidewall of the gate oxide layer 205.

[0114] In some embodiments of this application, forming the gate oxide layer surrounding the pillar-shaped conductive channel on the sidewall of the pillar-shaped conductive channel of the transistor array includes:

[0115] The sidewalls of each pillar-shaped conductive channel of the transistor array are oxidized to form the gate oxide layer surrounding the pillar-shaped conductive channel.

[0116] Still referencing Figure 6AThe exposed sidewalls of the columnar conductive channel 204 can be oxidized in situ by heating or pressurizing. This allows the silicon on the sidewalls of the columnar conductive channel 204 to chemically react with a gas containing oxidizing substances at high temperatures, thereby generating a dense silicon dioxide film on the silicon surface to form the gate oxide layer 205 surrounding the columnar conductive channel 204. In other words, the gate oxide layer 205 completely covers the sidewalls of the columnar conductive channel 204. Here, the gate oxide layer is an insulating material, such as silicon dioxide, and it is located between the columnar conductive channel and the gate electrode for electrical isolation, preventing direct contact between the gate electrode and the columnar conductive channel that could cause charge leakage.

[0117] In some embodiments of this application, forming the gate electrode surrounding each of the gate oxide layers on the sidewalls of the gate oxide layers includes:

[0118] Conductive material is deposited in the grid-like first groove formed by removing the first mask layer to form the gate electrode surrounding each of the gate oxide layers; wherein the upper surface of the gate electrode is lower than the upper surface of the columnar conductive channel.

[0119] Still referencing Figure 6A Conductive material is deposited in the grid-like first groove, i.e., conductive material is deposited on the isolation layer 201 to form a gate electrode 207 surrounding each gate oxide layer 205, wherein the upper surface of the gate electrode 207 is lower than the upper surface of the columnar conductive channel. That is, after the gate electrode 207 is formed, a portion of the sidewalls of the gate oxide layer 205 near its top is still exposed.

[0120] Here, conductive material can be deposited in the first groove formed by removing the first mask layer through chemical vapor deposition (PVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) processes to form a gate electrode surrounding each gate oxide layer.

[0121] The conductive material may include, but is not limited to, titanium nitride, tungsten, or combinations thereof. In this embodiment, the deposited conductive material is tungsten. A tungsten thin film is formed by covering the sidewalls of the gate oxide layer with tungsten atoms using a low-pressure gas or plasma process, thereby forming the gate electrode. Since the formed gate electrode surrounds the columnar conductive channel, the width of the conductive channel can be increased, providing a larger channel current.

[0122] In some embodiments of this application, the manufacturing method further includes:

[0123] A second mask layer is formed on the gate electrode and the columnar conductive channel;

[0124] Along the extension direction of the columnar conductive channel, starting from the second mask layer, the second mask layer, the gate electrode, and the isolation layer are etched sequentially to form a second groove; wherein the second groove is located between adjacent columnar conductive channels;

[0125] Insulating material is deposited in the second groove to form an isolation structure.

[0126] like Figure 6A and Figure 6B As shown, a second mask layer 208 is formed on the gate electrode 207 and the columnar conductive channel 204.

[0127] It should be noted that during the actual deposition process of the second mask layer, the second mask layer will cover the surface of the gate electrode, the gate oxide layer and the columnar conductive channel. Usually after the deposition is completed, chemical mechanical polishing (CMP) is used to polish away the excess material of the second mask layer, so that the surface of the second mask layer is planarized.

[0128] The material of the second mask layer may include, but is not limited to, silicon nitride, silicon oxynitride, silicon carbide, silicon dioxide, or other insulating materials. The material of the second mask layer may be the same as or different from the material of the first mask layer. In this embodiment, both the first and second mask layers are made of silicon nitride.

[0129] refer to Figure 7A and Figure 7B , Figure 7A This is a cross-sectional view of the formation of the second groove provided in an embodiment of this application. Figure 7B For along Figure 7A A top view in the 'B' direction. (e.g., a top view in the 'B' direction) Figure 7A and Figure 7B As shown, along the extension direction of the columnar conductive channel 204, i.e. the Z direction, the second mask layer 208, the gate electrode 207 and the isolation layer 201 are etched sequentially with the second mask layer 208 as the etching starting point to form the second groove 209, wherein the second groove 209 is located between adjacent columnar conductive channels 204.

[0130] Here, a dry etching process can be used to etch the wafer, such as plasma etching or reactive ion etching. It is worth noting that in this embodiment, the second mask layer, the gate electrode, and the isolation layer are etched sequentially along the thickness direction of the wafer, with etching stopping at the isolation layer; that is, the etching process does not penetrate the isolation layer.

[0131] In some embodiments of this application, the columnar conductive channels are arranged in an array, and the extension direction of the second groove is parallel to the column direction of the columnar conductive channels; the gate electrodes of the transistors located in the same column are interconnected, and the interconnected gate electrodes are word lines of the transistors in the same column.

[0132] Still referencing Figure 7A Along the Z direction, the second groove 209 penetrates the gate electrode 207. Figure 7B In the top view shown, the extension direction of the second groove 209 is always perpendicular to the thickness direction of the wafer; in other words, the extension direction of the second groove 209 is perpendicular to the extension direction of the columnar conductive channel 204. Figure 7B The extension direction of the second groove 209 shown can be parallel to the Y direction, that is, the extension direction of the second groove 209 is parallel to the column direction of the columnar conductive channels 204. Gate electrodes extending in the same column direction are electrically connected to external circuits via external wiring to form word lines. The word lines can provide word line voltages, and these word line voltages control the conduction or cutoff of each transistor.

[0133] For example, the gate electrodes of columnar conductive channels located in the same column can be connected as a straight line as a word line and spaced apart in the row direction, that is, the gate electrodes of columnar conductive channels located in the same row are separated from each other.

[0134] Since the gate electrodes formed are interconnected in the same column direction to form word lines, word line routing in semiconductor devices can be facilitated and control performance can be optimized.

[0135] refer to Figure 8 , Figure 8 Top view of four optional structures of the columnar conductive channel provided in the embodiments of this application. Figure 8 (a) shows that the columnar conductive channel 204-1 is circular, and the gate oxide layer 205-1 surrounding its sidewalls is also circular; Figure 8 (b) The columnar conductive channel 204-2 shown is rectangular, and the gate oxide layer 205-2 surrounding its sidewalls is also rectangular; Figure 8 (c) shows that the columnar conductive channel 204-3 is trapezoidal, and the gate oxide layer 205-3 surrounding its sidewalls is also trapezoidal; Figure 8 (d) shows that the columnar conductive channel 204-4 is rhomboid, and the gate oxide layer 205-4 surrounding its sidewalls is also rhomboid. This application does not impose any special limitation on the shape of the columnar conductive channel in the top view; the columnar conductive channel can also be pentagonal, hexagonal, or other shapes in the top view.

[0136] refer to Figure 9 , Figure 9A cross-sectional view of an isolation structure with an air gap provided for an embodiment of this application. (See attached image.) Figure 9 As shown, insulating material can be deposited in the second groove to form an isolation structure 210. Further as... Figure 9 As shown, an air gap 211 can also be formed within the isolation structure 210.

[0137] By forming a second groove between adjacent columnar conductive channels and filling the second groove with insulating material, thus forming an isolation structure, direct contact between different word lines can be avoided, thereby achieving electrical isolation. Furthermore, an air gap is formed within the isolation structure to obtain a lower dielectric constant, thereby reducing parasitic capacitance.

[0138] Still referencing Figure 9 Along the Z-direction, the isolation structure 210 penetrates the gate electrode 207. As mentioned earlier, the extension direction of the second groove is always perpendicular to the thickness direction of the wafer; in other words, the extension direction of the second groove is perpendicular to the extension direction of the columnar conductive channel. Therefore, the extension direction of the isolation structure formed after filling the second groove is also perpendicular to the extension direction of the columnar conductive channel. Here, the extension direction of the isolation structure can be parallel to the Y-direction, that is, the extension direction of the isolation structure is parallel to the column direction of the columnar conductive channel arrangement.

[0139] In some embodiments of this application, the insulating material forming the isolation structure may include, but is not limited to, silicon dioxide, silicon nitride, silicon oxynitride, or silicon carbide.

[0140] In some embodiments of this application, the manufacturing method further includes, prior to forming the source and the drain:

[0141] The second mask layer is thinned until the end of the columnar conductive channel away from the wafer is exposed.

[0142] The wafer is thinned from the back side until the end of the columnar conductive channel near the wafer is exposed.

[0143] refer to Figure 10 , Figure 10 This is a cross-sectional view of a thinned wafer provided in an embodiment of this application. Figure 10 As shown, in the extension direction, i.e., the Z direction, the columnar conductive channel 204 has an end away from the wafer and an end close to the wafer. The second mask layer is thinned until the end of the columnar conductive channel away from the wafer is exposed; and the wafer is thinned from the back side of the wafer until the end of the columnar conductive channel close to the wafer is exposed.

[0144] Here, the methods for thinning wafers can include physical or chemical methods, such as physical thinning by grinding, or thinning by etching the wafer with corrosive liquids or gases.

[0145] Before thinning, a bonding process can be performed on the wafer, that is, a second wafer is bonded to the wafer to be thinned, which provides support and can prevent damage to the wafer to be thinned during the thinning process.

[0146] In some embodiments of this application, the step of forming the source and drain of a transistor at both ends of the extending direction of each pillar conductive channel in the transistor array includes:

[0147] At the end of the columnar conductive channel away from the wafer, ion implantation is performed on each columnar conductive channel to form the source or drain of each transistor in the transistor array;

[0148] Ion implantation is performed on each of the columnar conductive channels near the wafer to form the drain or source of each transistor in the transistor array.

[0149] In the transistor array, the sources of each transistor are arranged in an array, that is, the sources of each transistor are arranged at intervals in the row and column directions; the drains of each transistor are arranged in an array, that is, the drains of each transistor are arranged at intervals in the row and column directions.

[0150] Here, ion implantation (IMP) is used to implant particles to be doped onto the bottom of the wafer using an ion beam. Through a series of physicochemical interactions, the doped particles gradually lose energy and remain in the columnar conductive channels, thus forming the source or drain of the transistor array. The source or drain is electrically isolated from the gate electrode by the aforementioned gate oxide layer, effectively protecting the gate electrode material.

[0151] By forming source or drain electrodes located in the extension direction of each columnar conductive channel, the sources of each transistor are located in the same plane, and the drains of each transistor are located in the same plane. This simplifies the design of the internal circuit layout of semiconductor devices and reduces the manufacturing process difficulty of semiconductor devices.

[0152] It should be noted that, in the embodiments of this application, since the source or drain of each transistor is located on the same plane, they can be uniformly formed by a single ion implantation, thereby simplifying the manufacturing process and improving efficiency.

[0153] In some embodiments of this application, the manufacturing method further includes:

[0154] A bit line is formed, which is connected to the source or drain of each transistor in the transistor array;

[0155] A storage capacitor is formed, one end of which is connected to the drain or source of each transistor in the transistor array, and the other end of which is grounded. The storage capacitor is used to store data written to the semiconductor device.

[0156] refer to Figure 11 and Figure 12 , Figure 11 This is a schematic diagram of an optional structure of a semiconductor device provided in an embodiment of this application. Figure 12 This is a schematic diagram of an optional three-dimensional structure of a semiconductor device provided in an embodiment of this application. For example... Figure 11 and Figure 12 As shown, a bit line 302 is formed, which is connected to the source or drain of the transistor through a bit line contact 308; a storage capacitor 304 is formed, one end of which is connected to the drain or source of the transistor through a storage node contact 309, while the other end of the storage capacitor 304 is grounded.

[0157] In the semiconductor device manufacturing method provided in this application embodiment, the source and drain of the formed transistor array are located at opposite ends along the extension direction of the pillar-shaped conductive channel, which is perpendicular to the wafer surface, thus forming a vertical channel array transistor (VCAT). The gate is formed around the pillar-shaped conductive channel. In this way, the source and drain of the transistor can be located on different sides of the wafer, and the bit line and storage capacitor can be located on opposite sides of the conductive channel, greatly reducing the area of ​​the transistor array. The semiconductor device manufacturing method provided in this application embodiment ultimately obtains a semiconductor device with a minimum memory cell size of 4F. 2 .

[0158] refer to Figure 13A and Figure 13B , Figure 13A and Figure 13B This provides an optional arrangement of capacitors in the semiconductor device provided in the embodiments of this application. For example... Figure 13A As shown, the storage capacitors 404 are arranged in an array, and the angle between the column direction and the row direction of the storage capacitors is 90 degrees. Figure 13A The storage capacitors 404 shown are arranged in a square, that is, multiple adjacent storage capacitors are arranged in a square, with a storage capacitor located at each of the top corners of the square. Figure 13BAs shown, the storage capacitors 404 are arranged in an array; the angle between the column direction and the row direction of the storage capacitors is 120 degrees. The storage capacitors 404 are arranged in a hexagonal pattern, that is, multiple adjacent storage capacitors are arranged in a regular hexagon, with a storage capacitor at each vertex of the regular hexagon and a storage capacitor at the center of the regular hexagon.

[0159] Figure 13A This illustrates the case where the row and column directions of the storage capacitors are perpendicular to each other. Figure 13B This illustrates the case where the row and column directions of the storage capacitors form a 120-degree angle. It should be noted that in this embodiment, the columnar conductive channels are also arranged in an array, with the X direction defined as the row direction and the Y direction as the column direction. Here, the row direction of the storage capacitors and the row direction of the columnar conductive channels are the same; the column direction of the storage capacitors and the column direction of the columnar conductive channels are also the same. However, for the array distribution of the columnar conductive channels, this application only illustrates the case where the row and column directions of the columnar conductive channels are perpendicular to each other.

[0160] Furthermore, the arrangement of storage capacitors is not limited to... Figure 13A and Figure 13B As shown, the center of the storage capacitor and the center of the active area are of the same size in both the horizontal and vertical directions, although their centers may deviate to some extent. The storage capacitors, arranged vertically along the word lines, are shifted left and right in the upper and lower rows respectively. In the top view, the image of the storage capacitors can be stretched into an ellipse along a direction not parallel to the word lines. Figure 13B The storage capacitor shown is elliptical. In the semiconductor device manufacturing method provided in this application embodiment, the active region is directly exposed on the surface, and the connection between the storage capacitor and the active region does not need to pass through bit lines, which can simplify the internal circuit layout of the semiconductor device and reduce the process difficulty of semiconductor device manufacturing.

[0161] refer to Figure 14A , Figure 14B and Figure 14C , Figure 14A , Figure 14B and Figure 14C This is a schematic diagram illustrating an optional structure of a capacitor in a semiconductor device provided in an embodiment of this application. For example... Figure 14A , Figure 14B and Figure 14C As shown, Figure 14A The cup-shaped storage capacitor shown is... Figure 14B The cylindrical storage capacitor shown, and Figure 14CThe illustrated pillar-shaped storage capacitors all include an upper electrode plate 501, a lower electrode plate 503, and a dielectric layer 502 located between the upper and lower electrode plates. In the semiconductor device manufacturing method provided in this application embodiment, no special limitation is made on the type of storage capacitor; all three types of storage capacitors mentioned above can be used in the semiconductor device manufacturing method provided in this application embodiment.

[0162] This application also provides a semiconductor device, such as... Figure 9 As shown, the semiconductor device includes:

[0163] A transistor array having columnar conductive channels 204; wherein the columnar conductive channels 204 of the transistor array are arranged in an array, and the extending direction of the columnar conductive channels 204 is perpendicular to the plane formed by the column direction and the row direction of the columnar conductive channels.

[0164] The sidewalls of each columnar conductive channel 204 of the transistor array have a gate layer surrounding the columnar conductive channel 204; wherein the gate layer includes a gate oxide layer 205 and a gate electrode 207.

[0165] The columnar conductive channel 204 of the transistor array has a source and a drain at both ends of the extending direction, respectively.

[0166] Isolation structure 210; Isolation structure 210 is located between adjacent columnar conductive channels and is parallel to gate electrode 207.

[0167] Here, an isolation structure is located between adjacent columnar conductive channels to achieve electrical isolation between the gate electrodes of adjacent columnar conductive channels. More specifically, the gate electrodes of columnar conductive channels located in the same row are separated from each other by the isolation structure; the gate electrodes of columnar conductive channels located in the same column are interconnected to form word lines.

[0168] In some embodiments of this application, the isolation structure includes an insulating material layer and an air gap formed in the insulating material layer.

[0169] It should be noted that an air gap can also be set inside the isolation structure to reduce parasitic capacitance through air isolation, thereby enhancing the isolation effect.

[0170] In some embodiments of this application, the extension direction of the isolation structure is parallel to the column direction of the columnar conductive channel; the gate electrodes of the transistors located in the same column are interconnected, and the interconnected gate electrodes are word lines of the transistors in the same column.

[0171] In some embodiments of this application, the semiconductor device further includes:

[0172] Bit lines are connected to the source or drain of each transistor in the transistor array;

[0173] A storage capacitor, one end of which is connected to the drain or source of each transistor in the transistor array, and the other end of which is grounded, is used to store data written to the semiconductor device.

[0174] In some embodiments of this application, the storage capacitors are arranged in an array; the angle between the column direction and the row direction of the storage capacitors is 90 degrees.

[0175] In some embodiments of this application, the storage capacitors are arranged in an array; the angle between the column direction and the row direction of the storage capacitors is 120 degrees.

[0176] This application provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a transistor array. The manufacturing method includes: providing a wafer; forming an isolation layer and a first mask layer on the wafer having vias arranged in an array; epitaxially forming columnar conductive channels inside and outside the vias; removing the first mask layer to expose the sidewalls of the columnar conductive channels of the transistor array, wherein the extending direction of the columnar conductive channels is perpendicular to the wafer surface; forming a gate layer surrounding the columnar conductive channels on the sidewalls of each columnar conductive channel of the transistor array; and forming a source and a drain of a transistor at opposite ends of the extending direction of each columnar conductive channel of the transistor array. In the semiconductor device manufacturing method provided in this application, the source and drain of the formed transistor array are located at opposite ends along the extending direction of the columnar conductive channels, which is perpendicular to the wafer surface, and the gate is formed around the columnar conductive channels. Thus, the source and drain of the transistors can be located on different sides of the wafer, greatly reducing the area of ​​the transistor array.

[0177] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0178] The above description is only a preferred embodiment of this application and does not limit the patent scope of this application. All equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The semiconductor device includes a transistor array; The manufacturing method includes: A wafer is provided, on which an isolation layer and a first mask layer are formed having an array of vias; the wafer includes a front side and a back side disposed opposite to each other, the front side being in contact with the isolation layer; A columnar conductive channel is formed inside and outside the through hole; Remove the first mask layer to expose the sidewalls of the columnar conductive channel of the transistor array, the columnar conductive channel extending perpendicularly to the wafer surface; A gate layer is formed around the columnar conductive channel on the sidewall of each columnar conductive channel in the transistor array. The gate layer includes a gate oxide layer and a gate electrode. The gate oxide layer is located between the columnar conductive channel and the gate electrode. A second mask layer is formed on the gate electrode and the columnar conductive channel; along the extension direction of the columnar conductive channel, with the second mask layer as the etching starting point, the second mask layer, the gate electrode and the isolation layer are etched sequentially to form a second groove located between adjacent columnar conductive channels, and an insulating material is deposited in the second groove to form an isolation structure; The second mask layer is thinned from the front side of the wafer until the end of the columnar conductive channel away from the wafer is exposed; ion implantation is performed on each columnar conductive channel at the end away from the wafer to form the source or drain of each transistor in the transistor array; a storage capacitor is formed on the front side of the wafer, and the storage capacitor is connected to the source or drain of each transistor in the transistor array. The wafer is thinned from the back side until one end of the columnar conductive channel near the wafer is exposed; ion implantation is performed on each columnar conductive channel at the end near the wafer to form the drain or source of each transistor in the transistor array; bit lines are formed on the back side of the wafer and connected to the drain or source of each transistor in the transistor array.

2. The manufacturing method as described in claim 1, characterized in that, The formation of a gate layer surrounding the pillar-shaped conductive channels on the sidewalls of each pillar-shaped conductive channel in the transistor array includes: A gate oxide layer is formed around each columnar conductive channel in the transistor array on the sidewall of each columnar conductive channel. The gate electrode is formed around each of the gate oxide layers on the sidewalls of the gate oxide layer.

3. The manufacturing method as described in claim 2, characterized in that, The gate oxide layer formed around the pillar-shaped conductive channel on the sidewall of the transistor array includes: The sidewalls of each pillar-shaped conductive channel of the transistor array are oxidized to form the gate oxide layer surrounding the pillar-shaped conductive channel.

4. The manufacturing method as described in claim 2, characterized in that, The gate electrode, which surrounds each of the gate oxide layers, is formed on the sidewalls of the gate oxide layers, including: Conductive material is deposited in the grid-like first groove formed by removing the first mask layer to form the gate electrode surrounding each of the gate oxide layers; wherein the upper surface of the gate electrode is lower than the upper surface of the columnar conductive channel.

5. The manufacturing method as described in claim 1, characterized in that, The manufacturing method further includes forming an air gap within the isolation structure.

6. The manufacturing method as described in claim 1, characterized in that, The columnar conductive channels are arranged in an array, and the extension direction of the second groove is parallel to the column direction of the columnar conductive channels; the gate electrodes of the transistors located in the same column are interconnected, and the interconnected gate electrodes are word lines of the transistors in the same column.

7. The manufacturing method as described in claim 1, characterized in that, The manufacturing method further includes: A bit line is formed, which is connected to the source or drain of each transistor in the transistor array; A storage capacitor is formed, one end of which is connected to the drain or source of each transistor in the transistor array, and the other end of which is grounded. The storage capacitor is used to store data written to the semiconductor device.

8. The manufacturing method as described in claim 7, characterized in that, The storage capacitors are arranged in an array; the angle between the column direction and the row direction of the storage capacitors is 90 degrees.

9. The manufacturing method as described in claim 7, characterized in that, The storage capacitors are arranged in an array; the angle between the column direction and the row direction of the storage capacitors is 120 degrees.

10. A semiconductor device, characterized in that, The semiconductor device is manufactured by the manufacturing method according to any one of claims 1 to 9; the semiconductor device comprises: A transistor array having columnar conductive channels; wherein the columnar conductive channels of the transistor array are arranged in an array, and the extending direction of the columnar conductive channels is perpendicular to the plane formed by the column direction and the row direction of the columnar conductive channels. The sidewalls of each columnar conductive channel of the transistor array have a gate layer surrounding the columnar conductive channel; wherein the gate layer includes a gate oxide layer and a gate electrode, and the gate oxide layer is located between the columnar conductive channel and the gate electrode; The columnar conductive channel of the transistor array has a source and a drain at each end of its extension direction. An isolation structure; the isolation structure is located between adjacent columnar conductive channels and is parallel to the gate electrode; Bit lines are connected to the source or drain of each transistor in the transistor array; A storage capacitor, wherein the storage capacitor is connected to the drain or source of each transistor in the transistor array; An isolation layer is located between adjacent pillar-shaped conductive channels, between the gate layer and the bit line, and between the isolation structure and the bit line; The second mask layer is located between the columnar conductive channels and between the gate layer and the storage capacitor.

11. The semiconductor device as claimed in claim 10, characterized in that, The isolation structure includes an insulating material layer and an air gap formed in the insulating material layer.

12. The semiconductor device as claimed in claim 10 or 11, characterized in that, The extension direction of the isolation structure is parallel to the column direction of the columnar conductive channel; the gate electrodes of the transistors located in the same column are interconnected, and the interconnected gate electrodes are word lines of the transistors in the same column.

13. The semiconductor device as claimed in claim 10 or 11, characterized in that, One end of the storage capacitor is connected to the drain or source of each transistor in the transistor array, and the other end of the storage capacitor is grounded. The storage capacitor is used to store data written to the semiconductor device.

14. The semiconductor device as claimed in claim 13, characterized in that, The storage capacitors are arranged in an array; the angle between the column direction and the row direction of the storage capacitors is 90 degrees.

15. The semiconductor device as claimed in claim 13, characterized in that, The storage capacitors are arranged in an array; the angle between the column direction and the row direction of the storage capacitors is 120 degrees.

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