Method for manufacturing semiconductor device, semiconductor device, and memory

Abstract

The application discloses a semiconductor device manufacturing method, a semiconductor device and a memory. The method comprises the following steps: providing a substrate and a stack layer on the substrate, wherein the stack layer has a step structure; forming a virtual channel structure which penetrates through the step structure and extends into the substrate; and forming a medium layer which covers the step structure and the virtual channel structure. The application can improve the performance of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device, a semiconductor device, and a memory. Background Technology

[0002] In semiconductor devices, stacked layers have a stepped structure. Current technology involves covering the stepped structure with a dielectric layer and then forming a dummy channel hole (DCH) that penetrates both the dielectric layer and the stepped structure through a single etching process. This results in a relatively deep DCH. Due to limitations in the etching process, the top and bottom dimensions of a deep DCH differ significantly; that is, the bottom dimension is smaller, and the top dimension is larger. The smaller bottom dimension of the DCH can easily lead to bending of the word line (WL) corresponding to the bottom of the DCH. Conversely, the larger top dimension can reduce the connection window of the contact structure (CT) on the stepped structure, thus affecting the performance of the semiconductor device. Summary of the Invention

[0003] This invention provides a method for manufacturing a semiconductor device, a semiconductor device, and a memory, which can improve the performance of the semiconductor device.

[0004] This invention provides a method for fabricating a semiconductor device, comprising:

[0005] A substrate and a stack layer located on the substrate are provided, the stack layer having a stepped structure;

[0006] A virtual channel structure is formed that penetrates the stepped structure and extends into the substrate;

[0007] A medium layer is formed covering the stepped structure and the virtual channel structure.

[0008] More preferably, the step of forming a virtual channel structure that penetrates the stepped structure and extends into the substrate includes:

[0009] A first mask layer is formed on the stepped structure, the first mask layer having a first opening;

[0010] A virtual channel hole is formed through the first opening, penetrating the stepped structure and extending into the substrate;

[0011] The virtual channel structure is formed within the virtual channel hole.

[0012] More preferably, the step of forming the first mask layer on the stepped structure includes:

[0013] An initial mask layer is formed on the stepped structure, the initial mask layer comprising a first region and a second region;

[0014] The initial mask layer is processed to make the etching rate of the first region greater than that of the second region;

[0015] The initial mask layer is etched to form the first opening in the first region of the initial mask layer, thereby obtaining the first mask layer.

[0016] More preferably, the initial mask layer is an amorphous layer;

[0017] The step of processing the initial mask layer includes:

[0018] The amorphous layer is irradiated with a laser to crystallize the first or second region of the amorphous layer.

[0019] More preferably, the step of forming the virtual channel structure within the virtual channel hole includes:

[0020] An insulating layer is filled into the virtual channel hole and the first opening to form the virtual channel structure.

[0021] More preferably, after the step of forming the virtual channel structure within the virtual channel hole, the method further includes:

[0022] Remove the first mask layer.

[0023] More preferably, prior to the step of forming the initial mask layer on the stepped structure, the method further includes:

[0024] A second mask layer is formed on the surface of the stepped structure, the initial mask layer is located on the second mask layer, and the etching rate of the second mask layer is less than the etching rate of the initial mask layer;

[0025] The step of etching the initial mask layer to form the first opening in the first region of the initial mask layer includes:

[0026] The initial mask layer and the second mask layer are etched to form the first opening in the first region of the initial mask layer, and to form a second opening in the second mask layer corresponding to the first opening.

[0027] More preferably, the step of forming the virtual channel structure within the virtual channel hole includes:

[0028] An insulating layer is filled into the virtual channel hole, the first opening, and the second opening to form the virtual channel structure.

[0029] More preferably, the step structure includes multiple steps, and each step corresponds to at least one of the virtual channel structures;

[0030] Prior to the step of forming the dielectric layer covering the stepped structure and the virtual channel structure, the method further includes:

[0031] The top of the virtual channel structure is etched so that the height of the upper surface of the etched virtual channel structure is lower than the height of the upper surface of the corresponding step.

[0032] Accordingly, the present invention also provides a semiconductor device, comprising:

[0033] Base;

[0034] A stacked layer located on the substrate, the stacked layer having a stepped structure;

[0035] A virtual channel structure that penetrates the stepped structure and extends into the substrate; and,

[0036] A dielectric layer covering the stepped structure and the virtual channel structure.

[0037] More preferably, the semiconductor device further includes:

[0038] The first mask layer is located on the stepped structure, and the virtual channel structure also penetrates the first mask layer.

[0039] More preferably, the semiconductor device further includes:

[0040] A second mask layer is located between the stepped structure and the first mask layer, and the virtual channel structure also penetrates the second mask layer.

[0041] More preferably, the stack layer further includes a core area located outside the stepped structure;

[0042] The first mask layer is also located on the core region.

[0043] More preferably, the step structure includes multiple steps, and each step corresponds to at least one of the virtual channel structures;

[0044] The height of the upper surface of the virtual channel structure is lower than the height of the upper surface of the corresponding step.

[0045] This invention also provides a memory, including a memory array structure and a peripheral structure connected to the memory array structure;

[0046] The memory array structure includes the aforementioned semiconductor devices.

[0047] The beneficial effects of this invention are as follows: By providing a substrate and a stacked layer on the substrate, the stacked layer having a stepped structure, forming a virtual channel structure that penetrates the stepped structure and extends into the substrate, and then forming a dielectric layer covering the stepped structure and the virtual channel structure, the virtual channel structure is located only in the stepped structure and the substrate below the dielectric layer, reducing the depth of the virtual channel structure, thereby reducing the difference between the top and bottom dimensions of the virtual channel structure, i.e., reducing the top dimension of the virtual channel structure and increasing the bottom dimension. The increased bottom dimension of the virtual channel structure can improve the word line bending problem corresponding to the bottom of the virtual channel structure, and the decreased top dimension of the virtual channel structure can increase the connection window of the contact structure, improve the performance of the semiconductor device, and thus improve the performance of the memory. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments or prior art, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 A schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0050] Figure 2a A top view of a stacked layer in a semiconductor device provided in an embodiment of the present invention;

[0051] Figure 2b Another top view of the stacked layer in a semiconductor device provided in an embodiment of the present invention;

[0052] Figures 3a to 3k A schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0053] Figures 4a to 4i Another structural schematic diagram of a method for fabricating a semiconductor device provided in an embodiment of the present invention;

[0054] Figure 5 This is a schematic diagram showing the connection between the memory channel structure and the common source structure in a semiconductor device provided in an embodiment of the present invention.

[0055] Figure 6 This is another schematic diagram showing the connection between the memory channel structure and the common source structure in a semiconductor device provided in an embodiment of the present invention.

[0056] Figure 7 This is yet another schematic diagram showing the connection between the memory channel structure and the common source structure in a semiconductor device provided by an embodiment of the present invention.

[0057] Figure 8 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0058] Figure 9 Another schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0059] Figure 10 This is yet another structural schematic diagram of a semiconductor device provided in an embodiment of the present invention;

[0060] Figure 11 This is yet another structural schematic diagram of a semiconductor device provided in an embodiment of the present invention;

[0061] Figure 12 This is a schematic diagram of a memory provided in an embodiment of the present invention. Detailed Implementation

[0062] The specific structural and functional details disclosed herein are merely representative and are intended to describe exemplary embodiments of the invention. However, the invention can be embodied in many alternative forms and should not be construed as being limited solely to the embodiments set forth herein.

[0063] In the description of this invention, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more. Additionally, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion.

[0064] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0065] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms “a” and “an” as used herein are also intended to include the plural. It should also be understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated features, integers, steps, operations, units, and / or components, without excluding the presence or addition of one or more other features, integers, steps, operations, units, components, and / or combinations thereof.

[0066] See Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device provided in an embodiment of the present invention.

[0067] like Figure 1 As shown, the method for fabricating a semiconductor device provided in this embodiment of the invention includes steps 101 to 103, as detailed below:

[0068] Step 101: Provide a substrate and a stack layer on the substrate, the stack layer having a stepped structure.

[0069] In this embodiment of the invention, the substrate can be a silicon substrate, or a substrate comprising semiconductors of other elements or compound semiconductors. The substrate may also include a sacrificial layer and a stacked structure on the sacrificial layer. The stacked structure may include vertically alternating interlayer insulating layers and semiconductor layers. Both the sacrificial layer and the semiconductor layer may be polycrystalline silicon, etc. The substrate may also include other film layers, which are not specifically limited here.

[0070] The stacked layer may include a stacked structure and a capping layer on the stacked structure. The stacked structure includes multiple vertically alternating interlayer sacrificial layers and interlayer insulating layers, where vertical refers to the direction perpendicular to the upper surface of the substrate. There is no limitation on the number of stacked interlayer sacrificial layers and interlayer insulating layers, such as 48 layers, 64 layers, 128 layers, etc. Interlayer sacrificial layers include, but are not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride; interlayer insulating layers include, but are not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride; and capping layers include, but are not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

[0071] The stack layer can include a core region (SS) and a step region (Core). For example... Figure 2a As shown, the step regions SS can be located on opposite sides of the core region, meaning there can be two step regions SS, with one step region SS connected to each opposite side of the core region. For example... Figure 2bAs shown, the core region can also be located on opposite sides of the step region SS, meaning there can be two core regions, with one core region connected to each opposite side of the step region SS. The core region SS and the step region core can also have other positional relationships, which are not specifically limited here.

[0072] The core area of ​​the stack layer has a vertically extending memory channel structure that runs through the stack structure and extends into the substrate. The cover layer is located on the stack structure and covers the memory channel structure. The step area SS of the stack layer has a step structure.

[0073] like Figure 3a As shown, a substrate 1 is provided, and a stacked structure 21 is formed on the substrate 1. The stacked structure 21 includes a plurality of longitudinally alternating interlayer insulating layers 211 and interlayer sacrificial layers 212.

[0074] Then, as Figure 3b As shown, a memory channel structure 3 is formed longitudinally through the core region of the stacked structure 21 and extends into the substrate 1. The memory channel structure 3 includes a channel layer 31 and a memory dielectric layer 32 disposed around the channel layer 31. The memory dielectric layer 32 includes a tunnel layer (not shown) disposed around the periphery of the channel layer 31, a charge storage layer (not shown) disposed around the periphery of the tunnel layer, and a charge blocking layer (not shown) disposed around the periphery of the charge storage layer. The channel layer 31 can be polysilicon, etc.; the tunnel layer can be an oxide such as silicon oxide, silicon nitride, or silicon oxynitride; the charge storage layer can be an insulating layer containing quantum dots or nanocrystals or compounds containing nitrogen and silicon; and the charge blocking layer can be an oxide such as silicon oxide. The memory string channel structure 3 also includes an isolation layer 33 surrounded by the channel layer 31, which can be an oxide such as silicon oxide.

[0075] Then, as Figure 3c As shown, a cover layer 22 covering the storage channel structure 3 is formed on the stacked structure 21, and the stacked structure 21 and the cover layer 22 constitute the stack layer 2. A step structure 23 is formed in the step region SS of the stack layer 2. The step structure 23 includes multiple steps, and each step may correspond to an interlayer sacrificial layer 212 and an interlayer insulating layer 211 located on the interlayer sacrificial layer 212.

[0076] Step 102: Form a virtual channel structure that runs through the stepped structure and extends into the substrate.

[0077] In this embodiment of the invention, after forming a step structure 23 in the step region SS of the stack layer 2, a virtual channel hole is first formed that extends longitudinally through the step structure 23 and into the substrate 1, and then a virtual channel structure is formed in the virtual channel hole. In this embodiment, the virtual channel hole is formed only in the step structure 23 and the substrate 1 to reduce the depth of the virtual channel hole, thereby reducing the difference between the top and bottom dimensions of the virtual channel hole, that is, reducing the top dimension of the virtual channel hole and increasing the bottom dimension, thereby reducing the top dimension of the virtual channel structure and increasing the bottom dimension.

[0078] In the first embodiment, the formation of the virtual channel structure that penetrates the stepped structure and extends into the substrate in step 102 includes:

[0079] A first mask layer is formed on the stepped structure, the first mask layer having a first opening;

[0080] A virtual channel hole is formed through the first opening, penetrating the stepped structure and extending into the substrate;

[0081] The virtual channel structure is formed within the virtual channel hole.

[0082] The first mask layer extends along the upper surface of the stack layer 2, meaning it is formed on the step structure 23 of the stack layer 2, and can also be formed on the core region of the stack layer 2. The first opening in the first mask layer corresponds to the step structure 23. The first mask layer can be fabricated by etching the initial mask layer.

[0083] Specifically, the step of forming the first mask layer on the stepped structure includes:

[0084] An initial mask layer is formed on the stepped structure, the initial mask layer comprising a first region and a second region;

[0085] The initial mask layer is processed to make the etching rate of the first region greater than that of the second region;

[0086] The initial mask layer is etched to form the first opening in the first region of the initial mask layer, thereby obtaining the first mask layer.

[0087] like Figure 3d As shown, an initial mask layer 40 is formed on the step structure 23 and the core area of ​​stack layer 2. The initial mask layer 40 may include multiple spaced first regions, each corresponding to a position in the step structure 23 where a virtual channel structure needs to be set, and each first region corresponds to a position of a virtual channel structure. The other regions in the initial mask layer 40 besides the first regions are second regions, which correspond to positions in the step structure 23 where no virtual channel structure needs to be set.

[0088] By processing the initial mask layer 40, the etching rates of the first and second regions of the initial mask layer 40 can be differentiated, with the etching rate of the first region being greater than that of the second region. All regions of the initial mask layer 40 are etched simultaneously. Because the etching rate of the first region is faster than that of the second region, when the first region is completely removed, the second region still has a residual film layer, thus forming a first opening in the first region, resulting in a first mask layer 4 with the first opening. The initial mask layer 40 can be an amorphous layer, such as amorphous poly.

[0089] Specifically, when the initial mask layer 40 is an amorphous layer, the step of processing the initial mask layer includes:

[0090] The amorphous layer is irradiated with a laser to crystallize the first or second region of the amorphous layer.

[0091] like Figure 3e As shown, an irradiation pattern is pre-set in the machine tool. The initial mask layer 40 is irradiated with a laser through this pattern. Since the initial mask layer 40 is an amorphous layer, a specific area of ​​the initial mask layer 40 can crystallize after laser irradiation, forming a crystalline layer. The other areas of the initial mask layer 40 (excluding the specific area) remain amorphous layers. The specific area can be either the first region 41 or the second region 42. There is an etching difference between the crystalline and amorphous layers, resulting in an etching difference between the first region 41 and the second region 42. It should be noted that if the etching rate of the crystalline layer is greater than that of the amorphous layer, then the first region 41 is a crystalline layer and the second region 42 is an amorphous layer; conversely, if the etching rate of the amorphous layer is greater than that of the crystalline layer, then the first region 41 is an amorphous layer and the second region 42 is a crystalline layer.

[0092] Then, as Figure 3f As shown, the first region 41 and the second region 42 of the initial mask layer 40 are etched simultaneously. Since the etching rate of the first region 41 is greater than that of the second region 42, when all the film in the first region 41 is etched, there is still a film remaining in the second region 42, thus forming a first opening 43 in the first region 41, resulting in the first mask layer 4. Since there can be multiple first regions 41, there can also be multiple first openings 43, and each first region 41 corresponds to one first opening 43.

[0093] like Figure 3gAs shown, a virtual channel hole 5 is formed through the first opening 43 of the first mask layer 4, penetrating the stepped structure 23 and extending into the substrate 1. Since there can be multiple first openings 43, there can also be multiple virtual channel holes 5, with each first opening 43 corresponding to one virtual channel hole 5. Each step of the stepped structure 23 can correspond to at least one virtual channel hole 5.

[0094] Then, a virtual channel structure is formed in the virtual channel hole 5. Specifically, the step of forming the virtual channel structure in the virtual channel hole includes:

[0095] An insulating layer is filled into the virtual channel hole and the first opening to form the virtual channel structure.

[0096] like Figure 3h As shown, an insulating layer 6 is formed on the first mask layer 4, and the insulating layer 6 fills the first opening 43 and the virtual channel hole 5. Then, as... Figure 3i As shown, the insulating layer 6 on the first mask layer 4 is removed, leaving only the insulating layer 6 in the first opening 43 and the virtual channel hole 5. The insulating layer 6 in the first opening 43 and the virtual channel hole 5 constitute the virtual channel structure 51, which penetrates the step structure 23 and extends into the substrate 1. Each step of the step structure 23 corresponds to at least one virtual channel structure 51.

[0097] Step 103: Form a medium layer covering the stepped structure and the virtual channel structure.

[0098] After forming the virtual channel structure 51, the first mask layer 4 can be retained. At this time, the virtual channel structure 51 penetrates the first mask layer 4 and the step structure 23 and extends into the substrate 1. Then, a dielectric layer 7 is formed covering the first mask layer 4 and the virtual channel structure 51. The dielectric layer 7 fills the area above the step structure 23, making the upper surface of the dielectric layer 7 corresponding to the step region SS flush with the upper surface of the dielectric layer 7 corresponding to the core region Core. Figure 8 As shown.

[0099] After forming the virtual channel structure 51, the first mask layer 4 can also be removed, such as... Figure 3j As shown, at this point, the upper surface of the virtual channel structure 51 is slightly higher than the upper surface of its corresponding step. Then, as... Figure 3k As shown, a dielectric layer 7 is formed on the stack layer 2, covering the step structure 23 and the virtual channel structure 51. The dielectric layer 7 fills the area above the step structure 23, so that the upper surface of the dielectric layer 7 corresponding to the step region SS is flush with the upper surface of the dielectric layer 7 corresponding to the core region Core.

[0100] It should be noted that after removing the first mask layer 4 and before covering the dielectric layer 7, the top of the virtual channel structure 51 can be etched to make the upper surface of the etched virtual channel structure 51 flush with the upper surface of its corresponding step, or to make the height of the upper surface of the etched virtual channel structure 51 slightly lower than the height of the upper surface of its corresponding step. For example, the upper surface of the etched virtual channel structure 51 is flush with the upper surface of the interlayer sacrificial layer 212 in its corresponding step. Then, a dielectric layer 7 covering the step structure 23 and the virtual channel structure 51 is formed on the stack layer 2.

[0101] The dielectric layer 7 can be formed through two processes. First, a first dielectric layer (not shown in the figure) can be applied to the upper surface of the stepped structure 23, the virtual channel structure 51, and the core region. The thickness of the first dielectric layer can be very thin. Then, a second dielectric layer (not shown in the figure) is applied on top of the first dielectric layer. The second dielectric layer quickly fills the area above the stepped structure 23, making its upper surface flush. The first and second dielectric layers together constitute the dielectric layer 7.

[0102] In the second embodiment, after providing a substrate and a stack layer (the stack layer has a stepped structure) located on the substrate, a second mask layer is first formed on the surface of the stepped structure, and then a first mask layer is formed on the second mask layer, that is, the first mask layer is located on the second mask layer.

[0103] like Figure 4a As shown, stack layer 2 includes a stacking structure 21 and a cover layer 22. The stacking structure 21 includes an interlayer insulating layer 211 and an interlayer sacrificial layer 212 arranged vertically. The core region of stack layer 2 includes a storage channel structure 3 that extends vertically through the stacking structure 21 and into the substrate 1. The cover layer 22 is located on the stacking structure 21 and covers the storage channel structure 3. The storage channel structure 3 includes an isolation layer 33, a channel layer 31 disposed around the isolation layer 33, and a storage medium layer 32 disposed around the channel layer 31. The step region SS of stack layer 2 has a step structure 23.

[0104] A second mask layer 8 is formed on the step structure 23 of the stack layer 2. The second mask layer 8 can also be formed on the core region of the stack layer 2, that is, the second mask layer 8 extends along the upper surface of the stack layer 2. Then, an initial mask layer 40 is formed on the second mask layer 8, and the initial mask layer 40 extends along the upper surface of the second mask layer 8. The etching rate of the second mask layer 8 is less than the etching rate of the initial mask layer 40.

[0105] like Figure 4bAs shown, the initial mask layer 40 is processed such that the etching rate of the first region 41 of the initial mask layer 40 is greater than the etching rate of the second region 42 of the first mask layer 4. The initial mask layer 40 can be the initial mask layer 40 in the first embodiment described above, and the processing method of the initial mask layer 40 can be the same as that of the initial mask layer 40 in the first embodiment described above, which will not be described in detail here.

[0106] Then, as Figure 4c As shown, the initial mask layer 40 and the second mask layer 8 are etched to form a first opening 43 in the first region 41 of the initial mask layer 40, thereby obtaining the first mask layer 4, and a second opening 81 is formed in the second mask layer 8 corresponding to the first opening 43.

[0107] Since the first region 41 and the second region 42 of the initial mask layer 40 are etched simultaneously, and the etching rate of the first region 41 is greater than that of the second region 42, when all the film layer in the first region 41 is etched, there is still a film layer remaining in the second region 42. At this time, a first opening 43 is formed in the first region 41. The second mask layer 8 corresponding to the first opening 43 and the second region 42 are then etched. Preferably, after the second mask layer 8 corresponding to the first opening 43 is completely removed, there is still a film layer remaining in the second region 42. At this time, a second opening 81 is formed in the second mask layer 8 corresponding to the first opening 43, that is, the first opening 43 and the second opening 81 correspond to and are connected. There can be multiple first openings 43, which allows for multiple second openings 81, with each first opening 43 corresponding to one second opening 81.

[0108] Since the etching rate of the second mask layer 8 is less than that of the initial mask layer 40, even after the initial mask layer 40 (including the first region 41 and the second region 42) has been completely etched, the second mask layer 8 with the second opening 81 can still be formed on the step structure 23 to ensure the formation of the subsequent virtual channel hole.

[0109] like Figure 4d As shown, virtual channel holes 5 are formed through the first opening 43 and the second opening 81, penetrating the stepped structure 23 and extending into the base 1. There can be multiple virtual channel holes 5, with each first opening 43 and its corresponding second opening 81 corresponding to one virtual channel hole 5. Each step of the stepped structure 23 can correspond to at least one virtual channel hole 5.

[0110] Then, an insulating layer is filled into the first opening 43, the second opening 81, and the virtual channel hole 5 to form a virtual channel structure. Specifically, as shown... Figure 4e As shown, an insulating layer 6 is formed on the first mask layer 4, and the insulating layer 6 fills the first opening 43, the second opening 81, and the virtual channel hole 5. Figure 4fAs shown, the insulating layer 6 on the first mask layer 4 is removed, leaving only the insulating layer 6 in the first opening 43, the second opening 81, and the virtual channel hole 5. The insulating layer 6 in the first opening 43, the second opening 81, and the virtual channel hole 5 constitutes the virtual channel structure 51, which penetrates the step structure 23 and extends into the substrate 1. Each step of the step structure 23 corresponds to at least one virtual channel structure 51.

[0111] After forming the virtual channel structure 51, the first mask layer 4 and the second mask layer 8 can be retained. At this time, the virtual channel structure 51 penetrates the first mask layer 4, the second mask layer 8, and the step structure 23 and extends into the substrate 1. Then, a dielectric layer 7 is formed covering the first mask layer 4 and the virtual channel structure 51. The dielectric layer 7 fills the area above the step structure 23, making the upper surface of the dielectric layer 7 corresponding to the step region SS flush with the upper surface of the dielectric layer 7 corresponding to the core region Core. Figure 9 As shown.

[0112] After forming the virtual channel structure 51, the first mask layer 4 and the second mask layer 8 can also be removed, such as... Figure 4g As shown, at this point, the upper surface of the virtual channel structure 51 is slightly higher than the upper surface of its corresponding step. Then, the top of the virtual channel structure 51 can be etched so that the etched upper surface of the virtual channel structure 51 is flush with the upper surface of its corresponding step, or so that the height of the etched upper surface of the virtual channel structure 51 is slightly lower than the height of its corresponding step. For example... Figure 4h As shown, the upper surface of the etched virtual channel structure 51 is flush with the upper surface of the interlayer sacrificial layer 212 in its corresponding step. Then, as... Figure 4i As shown, a dielectric layer 7 is formed on the stack layer 2, covering the step structure 23 and the virtual channel structure 51. The dielectric layer 7 fills the area above the step structure 23, so that the upper surface of the dielectric layer 7 corresponding to the step region SS is flush with the upper surface of the dielectric layer 7 corresponding to the core region Core.

[0113] It should be noted that after removing the first mask layer 4 and the second mask layer 8, the top of the virtual channel structure 51 may not be etched (at this time, the upper surface of the virtual channel structure 51 is slightly higher than the upper surface of its corresponding step). The dielectric layer 7 covering the step structure 23 and the virtual channel structure 51 can be directly formed on the stack layer 2. The dielectric layer 7 fills the area above the step structure 23, so that the upper surface of the dielectric layer 7 corresponding to the step area SS is flush with the upper surface of the dielectric layer 7 corresponding to the core area Core.

[0114] Since the interlayer sacrificial layer 212 in stacked layer 2 needs to be replaced with a gate layer, after forming the virtual channel structure 51, a gate line slit needs to be formed in the core region Core, extending longitudinally through stacked layer 2 and into the substrate 1. The interlayer sacrificial layer 212 in stacked layer 2 is removed through the gate line slit. This embodiment reduces the depth of the virtual channel structure, thereby reducing the top dimension of the virtual channel structure, so that more virtual channel structures can be set within a unit area of ​​the step region SS, improving the support effect of stacked layer 2 and preventing stacked layer 2 from collapsing after the removal of the interlayer sacrificial layer 212.

[0115] like Figures 5 to 7 As shown, after removing the interlayer sacrificial layer 212, a gate layer 213 is formed between the interlayer insulating layers 211. The gate layer 213 includes, but is not limited to, tungsten, cobalt, copper, aluminum, doped silicon, or doped silicide. An insulating barrier layer 24 may also be formed between the gate layer 213 and the interlayer insulating layer 211, and a transition layer 25 may also be formed between the insulating barrier layer 24 and the gate layer 213. The insulating barrier layer 24 includes, but is not limited to, aluminum oxide, and the transition layer 25 includes, but is not limited to, titanium nitride, to improve the adhesion of the gate layer 213. Additionally, a slit structure 9 is formed in the gate line slits, such that the slit structure 9 longitudinally penetrates the stacked layer 2 and extends into the substrate 1. The slit structure 9 can be an insulating material such as silicon oxide, or a semiconductor material such as polysilicon. When the slit structure 9 is a semiconductor material, the slit structure 9 can be a common-source structure.

[0116] By applying different treatments to the film layers in the substrate 1 and the storage channel structure 3, the channel layer 31 in the storage channel structure 3 can be connected to the common source structure in different ways. In the first embodiment, such as... Figure 5 As shown, the processed substrate 1 includes a common source layer 11, which is a common source structure. The common source layer 11 can be an N-type doped or P-type doped polysilicon layer. A stacked structure 21 is located on the common source layer 11. The channel layer 31 in the memory channel structure 3 penetrates the stacked structure 21 and extends longitudinally into the common source layer 11 to connect with it. The memory dielectric layer 32 in the memory channel structure 3 is located on the common source layer 11 and is disposed around the channel layer 31. A slit structure 9 extends longitudinally through the stacked structure 21 and into the common source layer 11. The slit structure 9 can be an insulating material. A virtual channel structure 51 extends longitudinally through the stepped structure of the stepped region SS and into the common source layer 11.

[0117] The processed substrate 1 may also include an insulating dielectric layer 12 and conductive contacts 13. The insulating dielectric layer 12 is located on the side of the common source layer 11 opposite to the stack layer 2, and the conductive contacts 13 penetrate the insulating dielectric layer 12 and extend into the common source layer 11.

[0118] In the second embodiment, such as Figure 6As shown, the processed substrate 1 includes a first semiconductor layer 14, a second semiconductor layer 15, and a third semiconductor layer 16. The second semiconductor layer 15 is located on the first semiconductor layer 14, the third semiconductor layer 16 is located on the second semiconductor layer 15, and the stacked structure 21 is located on the third semiconductor layer 16. The first semiconductor layer 14, the second semiconductor layer 15, and the third semiconductor layer 16 can all be N-type doped or P-type doped polycrystalline silicon layers.

[0119] The channel layer 31 in the memory channel structure 3 longitudinally penetrates the stacked structure 21, the third semiconductor layer 16, and the second semiconductor layer 15, and extends into the first semiconductor layer 14. The memory dielectric layer 32 in the memory channel structure 3 surrounds the channel layer 31. The second semiconductor layer 15 laterally penetrates the memory dielectric layer 32 to connect with the channel layer 31; that is, the memory dielectric layer 32 is disconnected at the second semiconductor layer 15 to ensure that the second semiconductor layer 15 can connect with the channel layer 31. The second semiconductor layer 15 can serve as an epitaxial layer. The slit structure 9 may include a common-source structure 91 and an insulating layer 92. The common-source structure 91 longitudinally penetrates the stacked structure 21 and the third semiconductor layer 16, and extends into the second semiconductor layer 15. The insulating layer 92 surrounds the common-source structure 91. The slit structure 9 may also include a transition layer 93, which is located between the common-source structure 91 and the insulating layer 92. The virtual channel structure 51 extends longitudinally through the step structure of the step region SS, the third semiconductor layer 16 and the second semiconductor layer 15 and into the first semiconductor layer 14.

[0120] In the third embodiment, such as Figure 7 As shown, substrate 1 includes substrate 17, which can be a semiconductor substrate, such as a silicon substrate, or a substrate including other element semiconductors or compound semiconductors. An epitaxial layer 18 can be disposed at the bottom of the channel layer 31 in the memory channel structure 3, such that the channel layer 31 is connected to the substrate 17 through the epitaxial layer 18. A memory dielectric layer 32 is disposed around the channel layer 31 in the memory channel structure 3. Slit structure 9 can include a common source structure 91 and an insulating layer 92. The common source structure 91 extends longitudinally through the stacked structure 21 and into the substrate 17, and the insulating layer 92 is disposed around the common source structure 91. Slit structure 9 can also include a transition layer 93, which is located between the common source structure 91 and the insulating layer 92. A doped region 19 is disposed in the substrate 17 at the bottom of slit structure 9, such that the common source structure 91 is connected to the doped region 19 through the transition layer 93. The doped region 19 can be an N-type doped region or a P-type doped region. The virtual channel structure 51 extends longitudinally through the stepped structure of the stepped region SS and into the substrate 17.

[0121] As described above, the semiconductor device provided in this embodiment of the invention can provide a substrate and a stacked layer on the substrate. The stacked layer has a stepped structure, forming a virtual channel structure that penetrates the stepped structure and extends into the substrate. Then, a dielectric layer is formed that covers the stepped structure and the virtual channel structure, so that the virtual channel structure is only located in the stepped structure and the substrate below the dielectric layer. This reduces the depth of the virtual channel structure, thereby reducing the difference between the top and bottom dimensions of the virtual channel structure. That is, it reduces the top dimension of the virtual channel structure and increases the bottom dimension. The increased bottom dimension of the virtual channel structure can improve the word line bending problem at the bottom of the virtual channel structure, while the decreased top dimension of the virtual channel structure can increase the connection window of the contact structure and improve the performance of the semiconductor device.

[0122] Accordingly, embodiments of the present invention also provide a semiconductor device that can be manufactured by the semiconductor device manufacturing method described in the above embodiments.

[0123] like Figure 8 and Figure 9 As shown, this embodiment provides a semiconductor device, including a substrate 1, a stack layer 2, a virtual channel structure 51, and a dielectric layer 7.

[0124] The substrate 1 can be a substrate, such as a silicon substrate, or a substrate including semiconductors of other elements or compound semiconductors. The substrate 1 can include multiple stacked semiconductor layers, such as polycrystalline silicon. The substrate 1 may also include other film layers, which are not specifically limited here. The film layer structure in the substrate 1 can be found in [reference needed]. Figures 5 to 7 This will not be elaborated on further here.

[0125] Stack layer 2 is located on substrate 1. Stack layer 2 may include stack structure 21 and cover layer 22 located on stack structure 21. Stack structure 21 includes multiple vertically alternating gate layers 213 and interlayer insulating layers 211. The number of stacked gate layers 213 and interlayer insulating layers 211 is not limited, such as 48 layers, 64 layers, 128 layers, etc.

[0126] Stack layer 2 may include a core region (SS) and a step region (Core). For details on the connection relationship between the core region (SS) and the step region (Core), please refer to [link / reference needed]. Figure 2a and Figure 2bThe details are omitted here. A storage channel structure 3 is formed in the core area of ​​stack layer 2, extending longitudinally through the stack structure 21 and into the substrate 1. A cover layer 22 is located on the stack structure 21 and covers the storage channel structure 3. The storage channel structure 3 includes an isolation layer 33, a channel layer 31 surrounding the isolation layer 33, and a storage medium layer 32 surrounding the channel layer 31. The storage medium layer 32 includes a tunnel layer (not shown in the figure) surrounding the channel layer 31, a charge storage layer (not shown in the figure) surrounding the tunnel layer, and a charge blocking layer (not shown in the figure) surrounding the charge storage layer. A slit structure 9 is also formed in the core area of ​​stack layer 2. The specific connection relationship between the channel layer 31 and the slit structure 9 in the storage channel structure 3 can be found in [reference needed]. Figures 5 to 7 This will not be elaborated on further here.

[0127] The step region SS of stack layer 2 forms a step structure 23. The step structure 23 includes multiple steps, each step can correspond to a gate layer 213 and an interlayer insulating layer 211 located on the gate layer 213.

[0128] The virtual channel structure 51 extends longitudinally through the step structure 23 and into the base 1. Each step in the step structure 23 can correspond to at least one virtual channel structure 51. The upper surface of the virtual channel structure 51 can be flush with the upper surface of the corresponding step; the upper surface of the virtual channel structure 51 can also be slightly higher than the upper surface of the corresponding step, such as... Figure 8 As shown; the upper surface of the virtual channel structure 51 can also be slightly lower than the upper surface of the corresponding step, for example, the upper surface of the virtual channel structure 51 is flush with the upper surface of the gate layer 213 in the corresponding step, such as Figure 9 As shown.

[0129] The dielectric layer 7 is located on the stack layer 2 and covers the step structure 23 and the virtual channel structure 51. The dielectric layer 7 fills the top of the step structure 23, so that the dielectric layer 7 on the step area SS of the stack layer 2 is flush with the upper surface of the dielectric layer 7 on the core area Core of the stack layer 2.

[0130] Furthermore, such as Figure 10 As shown, the semiconductor device may further include a first mask layer 4, which is located on the step structure 23 and may also be located on the core region of the stack layer 2. A virtual channel structure 51 extends through the first mask layer 4, that is, the virtual channel structure 51 longitudinally penetrates the first mask layer 4 and the step structure 23 and extends into the substrate 1. A dielectric layer 7 is located on the first mask layer 4 and covers the virtual channel structure 51.

[0131] Furthermore, such as Figure 11As shown, the semiconductor device may further include a second mask layer 8, which is located between the step structure 23 and the first mask layer 4. The second mask layer 8 may also be located between the core region of the stacked layer 2 and the first mask layer 4. The virtual channel structure 51 also penetrates the second mask layer 8, that is, the virtual channel structure 51 longitudinally penetrates the first mask layer 4, the second mask layer 8, and the step structure 23 and extends into the substrate 1. The dielectric layer 7 is located on the first mask layer 4 and covers the virtual channel structure 51.

[0132] The semiconductor device provided in this embodiment of the invention can form a virtual channel structure by providing a substrate and a stacked layer on the substrate, the stacked layer having a stepped structure, forming a virtual channel structure that penetrates the stepped structure and extends into the substrate, and then forming a dielectric layer covering the stepped structure and the virtual channel structure, so that the virtual channel structure is only located in the stepped structure and the substrate below the dielectric layer, reducing the depth of the virtual channel structure, thereby reducing the difference between the top and bottom dimensions of the virtual channel structure, that is, reducing the top dimension of the virtual channel structure and increasing the bottom dimension. The increase in the bottom dimension of the virtual channel structure can improve the word line bending problem corresponding to the bottom of the virtual channel structure, and the decrease in the top dimension of the virtual channel structure can increase the connection window of the contact structure, thereby improving the performance of the semiconductor device.

[0133] See Figure 12 This is a schematic diagram of the memory structure provided in an embodiment of the present invention.

[0134] like Figure 12 As shown, the memory includes a memory array structure 100 and a peripheral structure 200 connected to the memory array structure 100. The memory array structure 100 may include the semiconductor devices described in the above embodiments, which will not be elaborated further here.

[0135] The storage array structure 100 can be a non-volatile memory array structure, such as NAND flash memory or NOR flash memory. The peripheral structure 200 can include devices such as CMOS (Complementary Metal-Oxide-Semiconductor), SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), FPGA (Field Programmable Gate Array), CPU (Central Processing Unit), and Xpoint chip.

[0136] Specifically, the peripheral structure 200 can be located on the storage array structure 100, and the peripheral structure 200 is connected to the storage array structure 100. The storage array structure 100 and the peripheral structure 200 can also adopt other architectural forms, such as the peripheral structure 200 being located below the storage array structure 100, i.e., a PUC (periphery under core array) architecture, or the peripheral structure 200 being arranged side by side with the storage array structure 100, i.e., a PNC (periphery near core array) architecture, etc., without specific limitations here.

[0137] The memory provided in this embodiment of the invention can improve memory performance.

[0138] In summary, although the present invention has been disclosed above with reference to preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, a stacked structure is formed on the substrate, a storage channel structure is formed in the core area of ​​the stacked structure that runs longitudinally through the stacked structure and extends into the substrate, a cover layer is formed on the stacked structure that covers the storage channel structure, the stacked structure and the cover layer constitute a stack layer, and a step structure is formed in the step area of ​​the stack layer; A virtual channel structure is formed that penetrates the stepped structure and extends into the substrate; A dielectric layer is formed covering the stepped structure and the virtual channel structure; The step of forming a virtual channel structure that penetrates the stepped structure and extends into the substrate includes: A second mask layer is formed on the surface of the stepped structure, and an initial mask layer is formed on the second mask layer. The initial mask layer includes a first region and a second region, and the etching rate of the second mask layer is less than the etching rate of the initial mask layer. The initial mask layer and the second mask layer are etched such that the etching rate of the first region is greater than that of the second region, so as to form a first opening in the first region of the initial mask layer, thereby obtaining a first mask layer, and forming a second opening in the second mask layer corresponding to the first opening; Virtual channel holes are formed through the first opening and the second opening, penetrating the stepped structure and extending into the substrate; The virtual channel structure is formed within the virtual channel hole.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The initial mask layer is an amorphous layer; The step of processing the initial mask layer includes: The amorphous layer is irradiated with a laser to crystallize the first or second region of the amorphous layer.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of forming the virtual channel structure within the virtual channel hole includes: An insulating layer is filled into the virtual channel hole and the first opening to form the virtual channel structure.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, After the step of forming the virtual channel structure within the virtual channel hole, the method further includes: Remove the first mask layer.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of forming the virtual channel structure within the virtual channel hole includes: An insulating layer is filled into the virtual channel hole, the first opening, and the second opening to form the virtual channel structure.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step structure includes multiple steps, and each step corresponds to at least one virtual channel structure. Prior to the step of forming the dielectric layer covering the stepped structure and the virtual channel structure, the method further includes: The top of the virtual channel structure is etched so that the height of the upper surface of the etched virtual channel structure is lower than the height of the upper surface of the corresponding step.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step structure includes multiple steps, and each step corresponds to at least one virtual channel structure. Prior to the step of forming the dielectric layer covering the stepped structure and the virtual channel structure, the method further includes: The top of the virtual channel structure is etched so that the upper surface of the etched virtual channel structure is flush with the upper surface of the corresponding step.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that, The first mask layer is also formed on the core region corresponding to the stack layer.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that, The second mask layer is also formed on the core region corresponding to the stack layer.

10. The method for fabricating a semiconductor device according to claim 1 or 4, characterized in that, After the step of forming the virtual channel structure within the virtual channel hole, the method further includes: Remove the second mask layer.

11. The method for fabricating a semiconductor device according to claim 1, characterized in that, The upper surface of the medium layer corresponding to the step area is flush with the upper surface of the medium layer corresponding to the core area.

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