A resistive memory device based on multiple resistive switching layers and a method for manufacturing the same

Abstract

The present invention discloses a resistive memory device based on multiple resistive switching layers and a preparation method thereof, and belongs to the technical field of semiconductor and CMOS hybrid integrated circuits. The present invention realizes a resistive switching memory device with high retention based on the traditional CMOS process, and its core lies in that the resistive switching layer is composed of an interception characteristic film and a resistive switching material film with resistive switching characteristics alternately stacked to form a multi-layer resistive switching layer structure. The present invention can effectively suppress the low retention of the device by adjusting the potential barrier at the interface in order to reduce or even eliminate the resistive switching layer ion migration problem existing in the crossbar structure of the resistive switching memory. At the same time, the multi-layer resistive switching layer structure is also conducive to increasing the number of states of the device, paving the way for large-scale integration and commercialization of resistive switching memory.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor and CMOS hybrid integrated circuits, and in particular relates to a resistive switching memory based on multiple resistive switching layers and a preparation method thereof. Background Art

[0002] As the limit of Moore's Law approaches, the disadvantages of the von Neumann structure are becoming more and more obvious, manifested in low storage efficiency and high power consumption. At the same time, with the iteration and update of Internet technology, artificial intelligence technology has put forward higher requirements for storage devices. Non-von Neumann structure, specifically manifested in the increasing demand for new non-volatile devices for near-storage and storage-computing integration technology, among which resistive random access memory (RRAM) has become a strong competitor to replace traditional flash memory with its simple three-layer structure (upper electrode, resistive switching layer, lower electrode), low power consumption, high-density integration, fast read and write speed and other advantages. Under low operating voltage, interface RRAM has two states "high resistance HRS" and "low resistance LRS", corresponding to the "1" and "0" states in digital circuits. The corresponding physical image is that under the action of electric field, oxygen vacancies (oxygen ions) migrate to form non-metallic conductive areas; when there is a Schottky barrier between the electrode and the functional layer, the accumulation of oxygen vacancies at the interface will cause the change of barrier height, thereby affecting the resistive switching process, which is similar to the switching process controlled by oxygen vacancy conductive filaments. Interface-type RRAM has many features, such as high erase and write endurance of 10 12 , switching speed is less than 1ns, etc. With the optimization of process and design, multi-bit RRAM has gradually become widely circulated, and the number of states has increased from 1bit to 2bit, etc.

[0003] However, for interface-type RRAM devices, its reliability has always been a research issue, such as the retention characteristics of the device, which is manifested as the length of time the device state (such as "0" and "1" states) is maintained. In the storage array, when voltage is applied through the word line and the bit line to change the resistance of the device, the oxygen-rich region becomes wider, oxygen vacancy conductive filaments are formed, the barrier at the interface decreases, and the device changes from HRS to LRS. However, with the passage of time, process errors and the influence of the surrounding environment, such as poor inter-layer contact, heat from adjacent devices, leakage current provided by surrounding selected memory devices, etc., the migration of ions in the device's resistive layer will cause the compound oxygen vacancies and corresponding conductive filament changes, which may cause the filament to break and change the stored information.

[0004] In order to solve the retention problem faced by resistive memory arrays, current research mainly focuses on changing materials or adjusting the thickness of the resistive layer. For example, changing the mixing ratio of the resistive layer material and oxygen (changing the AO x The value of x in the equation is 1. Try different materials such as (SiOx ,HfO x ,TaO x ,VO x The purpose of improving retention is to increase the resistance layer (such as from 10A to 100A), or to increase the wrapping layer (such as SiNx) around the device. However, the selection of multiple materials will bring their own defects, such as the decrease in the number of states (most of some materials can only reach less than 2 bits of state number), and the improvement of retention is not obvious. Summary of the invention

[0005] In view of the above-mentioned shortcomings, the present invention proposes a resistive memory device, which utilizes traditional CMOS technology to realize a resistive memory device with high retention, and adjusts the potential barrier at the interface to reduce or even eliminate the ion migration problem of the resistive layer in the crossbar structure of the resistive memory.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is as follows:

[0007] A resistive memory is characterized in that the resistive switching layer of the resistive switching memory is composed of an interception characteristic film and a resistive switching material film with resistive switching characteristics alternately stacked to form an n-layer resistive switching layer structure, where n≥3.

[0008] The resistive material film is made of transition metal oxide with resistive properties, with a thickness of 5nm-100nm; or made of organic material, with a thickness of 200nm-500nm; the transition metal oxide is TaO x , HfO x 、SiO x or SrTiO 3 The organic material is parylene.

[0009] The interception characteristic film is made of SiO X , BN, graphene, graphite, etc., with a thickness of 1nm to 10nm.

[0010] A method for preparing a resistive random access memory comprises the following steps:

[0011] 1) defining a bottom electrode pattern and preparing a bottom electrode on a substrate according to the pattern;

[0012] 2) Depositing a resistive material film on the bottom electrode by PVD (physical vapor deposition), ALD (atomic layer deposition) or CVD (chemical vapor deposition);

[0013] 3) Depositing an interception characteristic film on the resistive material film by using a PVD or ALD method, and performing a corresponding annealing process according to the material properties;

[0014] 4) Repeat steps 2) and 3)

[0015] 5) defining a bottom electrode lead-out hole pattern, and etching a bottom electrode lead-out hole in the resistive material film and the intercepting characteristic film according to the pattern;

[0016] 6) Define the top electrode pattern and prepare the top electrode on the modified layer according to the pattern.

[0017] Furthermore, the method of defining the pattern in steps 1), 5) and 6) is to define the pattern on the photoresist using photolithography technology.

[0018] Furthermore, the preparation methods of the bottom electrode and the top electrode include PVD and evaporation deposition methods.

[0019] Furthermore, the substrate is made of silicon or glass; the bottom electrode and the top electrode are made of active materials or inert materials, such as W, Au, TiN, Pt, etc., with a thickness of 10nm-400nm.

[0020] Furthermore, the resistive material film is made of transition metal oxide with resistive properties, with a thickness of 5nm-50nm; or made of organic material, with a thickness of 200nm-500nm.

[0021] Furthermore, the interception characteristic film is made of graphene, BN, SiOx, etc., and has a thickness of 1nm-10nm.

[0022] The present invention proposes a resistive memory based on multiple resistive switching layers and a preparation method thereof. The interface potential barrier between the layers is adjusted to optimize the migration of oxygen vacancies. By rationally designing the combination of resistive switching material film, interception characteristic film and electrode material, the current-voltage characteristics of the resistive switching memory device can be optimized, so that the resistive switching memory exhibits high state retention characteristics. The resistive switching memory also has high reliability characteristics on the basis of combining the multiple advantages of interfacial RRAM. The resistive switching layer that originally forms a small amount / single conductive wire is divided into multiple conductive wires by using multiple interception characteristic films, and the probability of oxygen vacancy migration is reduced by raising the energy barrier of ion migration at the interface; the problem of resistance state change originally caused by oxygen vacancy migration is optimized, so the low retention of the device can be effectively suppressed. At the same time, the multi-resistive switching layer structure of the device is also conducive to increasing the number of states of the device. The present invention paves the way for large-scale integration and commercialization of resistive switching memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1-7 Corresponding to the implementation steps of each embodiment.

[0024] Figure 8 for Figure 1-7 Legend for . DETAILED DESCRIPTION

[0025] In order to make the above features and advantages of the present invention more obvious and easy to understand, the following is a detailed description of the implementation examples with reference to the accompanying drawings.

[0026] The present embodiment provides a resistive random access memory based on a multi-resistive random access layer and a preparation method thereof. The resistive random access memory uses a silicon substrate, TiN as a bottom electrode material, and TaO 2 (or its non-chemically matched oxide) as the resistive material film, using graphene and thin layer SiO 2 As the intercepting characteristic film, TiN is used as the top electrode material.

[0027] SiO 2 and TaO 2 All are materials compatible with standard CMOS processes. 2 The resistive random access memory has ultra-fast switching speed, high switching ratio, multiple states, good retention characteristics, and is simple to prepare and very controllable. 2 The ability to restrict ion movement in the direction perpendicular to the plane, the combination of the advantages of these materials, coupled with reasonable physical mechanism design and adjustment of the barrier height, not only meets the requirements of compatibility with CMOS processes, but also achieves good performance and reliability characteristics of resistive random access memory, which is of great significance for the improvement of the integration density of the crossbar structure array of resistive random access memory and large-scale production.

[0028] The preparation method of the resistive random access memory is as follows:

[0029] 1) Define the bottom electrode pattern on the photoresist using photolithography technology, deposit TiN bottom electrode material on the silicon substrate using PVD method with a thickness of 70nm, and then remove the photoresist, such as Figure 1 As shown;

[0030] 2) A layer of TaO is deposited on the bottom electrode using the ALD method 2 The resistive material film has a thickness of 6nm, such as Figure 2 As shown;

[0031] 3) Using the ALD method to deposit a layer of SiO on the resistive material film 2 The interception film is used to adjust the interface barrier and has a thickness of 3 nm. Figure 3 As shown;

[0032] 4) A layer of TaO is deposited on the bottom electrode using the ALD method 2 The resistive material film has a thickness of 6nm, such as Figure 4 As shown;

[0033] 5) A multi-layer graphene interception film is deposited on the resistive material film by ALD method for adjusting the interface barrier, with a thickness of about 2 to 10 layers, such as Figure 5 As shown;

[0034] 6) First, use photolithography technology to define the bottom electrode lead hole pattern on the photoresist, and then remove the photoresist, such as Figure 6 As shown;

[0035] 7) Using photolithography technology to define the top electrode pattern on the photoresist, using PVD method to deposit TiN top electrode material on the band modification layer with a thickness of 100nm, and then removing the photoresist to obtain the resistive memory, such as Figure 7 shown.

[0036] It can be seen from the above embodiments that the transition metal oxide resistive material film and the interception characteristic film can be prepared by either PVD method or ALD method. Compared with the PVD method, the ALD method can prepare thinner films; the CVD method is used to prepare organic materials as resistive material films.

[0037] The above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit the same. A person skilled in the art may modify or make equivalent substitutions for the technical solutions of the present invention without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to the claims.

Claims

1. A method for preparing a resistive memory, wherein the resistive switching layer of the resistive switching memory is composed of an interception characteristic film and a resistive switching material film having a resistive switching characteristic alternately stacked, comprising the following steps: 1) Define the bottom electrode pattern and prepare the bottom electrode on the substrate; 2) Depositing a resistive material film on the bottom electrode by physical vapor deposition, atomic layer deposition or chemical vapor deposition; 3) Using PVD or ALD method to deposit an interception characteristic film on the resistive material film, the interception characteristic film is made of SiO X , BN, graphene or graphite material, with a thickness of 1nm~10nm; 4) Repeating steps 2) and 3) to form a resistive switching layer structure consisting of an intercepting characteristic film and a resistive switching material film alternately stacked; 5) Define the bottom electrode lead-out hole pattern, and etch the bottom electrode lead-out hole in the resistive material film and the intercepting characteristic film; 6) Define the top electrode pattern and prepare the top electrode.

2. The method for preparing a resistive random access memory according to claim 1, wherein: The method for defining the pattern in steps 1), 5) and 6) is to define the pattern on the photoresist using photolithography technology.

3. The method for preparing a resistive random access memory according to claim 1, wherein: In the step 1), the substrate is made of silicon or glass.

4. The method for preparing a resistive random access memory according to claim 1, wherein: In the steps 1), 5) and 6), the bottom electrode and the top electrode are made of W, Au, TiN or Pt, with a thickness of 10nm-400nm; the preparation methods of the bottom electrode and the top electrode include PVD and evaporation deposition methods.

5. The method for preparing a resistive random access memory according to claim 1, wherein: The resistive material film in step 2) is made of transition metal oxide with resistive properties and has a thickness of 5nm-100nm; or is made of organic material and has a thickness of 200nm-500nm.

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