A relaxation type clock circuit supporting external synchronization, an oscillator and a smart terminal

Abstract

The application provides a kind of support for external synchronization relaxation type clock circuit, oscillator and intelligent terminal, belong to electronic technical field.This application embodiment includes external synchronization circuit and the fixed frequency circuit of external synchronization circuit electric connection, external synchronization circuit is used to realize to external synchronization signal SYNC shaping;Fixed frequency circuit includes mutually electric connection switch circuit, transmission gate circuit and single operational amplifier circuit, switch circuit and clock capacitor C one end are connected single operational amplifier circuit negative input end, transmission gate circuit connects single operational amplifier circuit positive input end;External synchronization circuit connects the input end of switch circuit.This application can generate the pulse OS signal of same frequency and controllable pulse width through external synchronization circuit, and can output the target frequency required by user through the fixed frequency circuit, and the circuit stability is good, and the periodic signal output precision is strong;It can effectively solve the problem that the circuit stability and clock precision are influenced by difference frequency noise in existing switch circuit.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and more particularly to a relaxation clock circuit, oscillator, and smart terminal that supports external synchronization. Background Technology

[0002] In smart terminal devices, clocks are indispensable for both circuit design and communication. Clocks are the starting point for system operation. In the operation of the circuit, clocks act as the vanguard of data changes. Usually, data changes accompany the rising and falling edges of the clock, which enables the terminal device to perform various functions. The higher the system clock frequency, the faster the data processing speed will be, which will greatly improve the system's performance and the user experience.

[0003] Due to the importance of clocks, the design of clock circuits is crucial. With the rapid development of chips, higher clock frequencies are needed to achieve higher processing speeds. However, traditional ring oscillators and multivibrators are suitable for low-frequency applications, and frequency deviation occurs when used at high frequencies. Relaxation oscillator IC technology combines high-frequency bipolar transistors and silicon CMOS IC technology, enabling oscillators to operate at higher frequencies.

[0004] However, in switching power supplies, electromagnetic interference and noise accompany the circuit throughout its entire lifespan, typically operating in the range of several hundred kHz to 1 MHz. Due to electromagnetic and noise interference, especially when certain frequencies are close to those of the power switches connected in parallel or series, the system exhibits beat frequency noise. Because beat frequency noise is very low, conventional filters are ineffective, making loop compensation difficult. While narrow-bandwidth low-pass filters and ripple cancellation circuits can reduce beat frequency noise, complete elimination requires frequency synchronization control. Currently, this cannot be achieved simultaneously. Therefore, the design of existing switching power supplies becomes more challenging due to beat frequency noise, resulting in poor clock accuracy. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a relaxation clock circuit, oscillator and smart terminal that supports external synchronization, which aims to effectively solve the problem of circuit stability and clock accuracy affected by difference frequency noise in existing switching circuits.

[0006] The technical solution adopted by the present invention to solve the above-mentioned technical problems is as follows:

[0007] A first aspect of the present invention provides a relaxation clock circuit that supports external synchronization, comprising an external synchronization circuit and a fixed frequency circuit electrically connected to the external synchronization circuit, wherein the external synchronization circuit is used to implement SYNC shaping of the external synchronization signal, and the fixed frequency circuit is used to fix the clock frequency.

[0008] The fixed frequency circuit includes a switching circuit, a transmission gate circuit, and a single operational amplifier circuit that are electrically connected to each other. The switching circuit is connected in parallel with a clock capacitor C. One end of the switching circuit and one end of the clock capacitor C are both connected to the negative input terminal of the single operational amplifier circuit. The transmission gate circuit is connected to the positive input terminal of the single operational amplifier circuit.

[0009] The output terminal of the external synchronization circuit is connected to the input terminal of the switching circuit, and the external synchronization circuit includes a monostable circuit.

[0010] In some embodiments, the switching circuit includes a first switch M1 and a second switch M2, the first switch M1 and the second switch M2 are connected in series, the first switch M1 is a PMOS transistor, the second switch M2 is an NMOS transistor, the gate of the first switch M1 is connected to the gate of the second switch M2, and the drain of the first switch M1 is connected to the drain of the second switch M2 and together connected to the negative input terminal of the single operational amplifier circuit.

[0011] In some embodiments, the clock capacitor C is connected in parallel with the second switch M2 circuit, one end of the clock capacitor C is connected to the source of the second switch M2, and the other end of the clock capacitor C is connected to the drain of the second switch M2.

[0012] In some embodiments, the transmission gate circuit includes a first transmission gate TG1 and a second transmission gate TG2, the first transmission gate TG1 and the second transmission gate TG2 are connected in parallel, the first transmission gate TG1 is an NMOS transistor, the second transmission gate TG2 is a PMOS transistor, the drain of the first transmission gate TG1 is connected to the drain of the second transmission gate TG2, and the source of the first transmission gate TG1 is connected to the source of the second transmission gate TG2 and together they are connected to the positive input terminal of the single op-amp circuit.

[0013] In some embodiments, the external synchronization circuit further includes a NAND gate circuit, the output terminal of the monostable circuit and the CLK signal output terminal are both connected to the input terminal of the NAND gate circuit, and the output terminal of the NAND gate circuit is connected to the gate of the first switch M1 and the second switch M2.

[0014] In some embodiments, the monostable circuit includes three inverters connected in series, all of which are inverted aspect ratio inverters.

[0015] A second aspect of the present invention also provides an oscillator, including a relaxation clock circuit supporting external synchronization, the relaxation clock circuit supporting external synchronization including an external synchronization circuit and a fixed frequency circuit electrically connected to the external synchronization circuit, the external synchronization circuit being used to implement SYNC shaping of the external synchronization signal, and the fixed frequency circuit being used to fix the clock frequency.

[0016] The fixed frequency circuit includes a switching circuit, a transmission gate circuit, and a single operational amplifier circuit that are electrically connected to each other. The switching circuit is connected in parallel with a clock capacitor C. One end of the switching circuit and one end of the clock capacitor C are both connected to the negative input terminal of the single operational amplifier circuit. The transmission gate circuit is connected to the positive input terminal of the single operational amplifier circuit.

[0017] The output terminal of the external synchronization circuit is connected to the input terminal of the switching circuit, and the external synchronization circuit includes a monostable circuit.

[0018] In some embodiments, the switching circuit includes a first switch M1 and a second switch M2, the first switch M1 and the second switch M2 are connected in series, the first switch M1 is a PMOS transistor, the second switch M2 is an NMOS transistor, the gate of the first switch M1 is connected to the gate of the second switch M2, and the drain of the first switch M1 is connected to the drain of the second switch M2 and together connected to the negative input terminal of the single op-amp.

[0019] In some embodiments, the transmission gate circuit includes a first transmission gate TG1 and a second transmission gate TG2, the first transmission gate TG1 and the second transmission gate TG2 are connected in parallel, the first transmission gate TG1 is an NMOS transistor, the second transmission gate TG2 is a PMOS transistor, the drain of the first transmission gate TG1 is connected to the drain of the second transmission gate TG2, and the source of the first transmission gate TG1 is connected to the source of the second transmission gate TG2 and together connected to the positive input terminal of the single op-amp.

[0020] This application also provides a smart terminal, including a relaxation clock circuit that supports external synchronization, wherein the relaxation clock circuit that supports external synchronization is any of the relaxation clock circuits that support external synchronization described above.

[0021] The relaxation clock circuit, oscillator, and intelligent system with external synchronization provided in this invention can generate a pulse OS signal with the same frequency and controllable pulse width through the external synchronization circuit, and can output a fixed and periodic target frequency required by the user through the fixed frequency circuit. The circuit has good stability and high accuracy of periodic signal output. This application can effectively solve the problem of circuit stability and clock accuracy affected by difference frequency noise in existing switching circuits. Attached Figure Description

[0022] Figure 1This is a schematic diagram of the hardware structure of a mobile terminal according to the present invention;

[0023] Figure 2 A communication network system architecture diagram provided for an embodiment of the present invention;

[0024] Figure 3 A block diagram of a relaxation clock circuit structure supporting external synchronization is provided in an embodiment of the present invention;

[0025] Figure 4 A circuit structure diagram of a relaxation clock circuit supporting external synchronization is provided for an embodiment of the present invention;

[0026] Figure 5 A circuit structure diagram of a fixed-frequency circuit for a relaxation-type clock circuit supporting external synchronization, provided in an embodiment of the present invention;

[0027] Figure 6 This is a transmission gate circuit structure diagram of a relaxation clock circuit supporting external synchronization provided in an embodiment of the present invention;

[0028] Figure 7 This is a circuit diagram of a one-shot module for a relaxation clock circuit that supports external synchronization, provided in an embodiment of the present invention.

[0029] Figure 8 This is a circuit structure block diagram of an oscillator provided in an embodiment of the present invention. Detailed Implementation

[0030] To make the technical problems, solutions, and beneficial effects of this invention clearer and more understandable, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0031] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0032] Terminals can be implemented in various forms. For example, the terminals described in this invention may include mobile terminals such as mobile phones, tablets, laptops, handheld computers, personal digital assistants (PDAs), portable media players (PMPs), navigation devices, wearable devices, smart bracelets, pedometers, etc., as well as fixed terminals such as digital TVs and desktop computers.

[0033] The following description will use a mobile terminal as an example. Those skilled in the art will understand that, apart from elements specifically designed for mobile purposes, the construction according to embodiments of the present invention can also be applied to fixed-type terminals.

[0034] Please see Figure 1 This is a schematic diagram of the hardware structure of a mobile terminal implementing various embodiments of the present invention. The mobile terminal 100 may include: an RF (Radio Frequency) unit 101, a WiFi module 102, an audio output unit 103, an A / V (Audio / Video) input unit 104, a sensor 105, a display unit 106, a user input unit 107, an interface unit 108, a memory 109, a processor 110, and a power supply 111, etc. Those skilled in the art will understand that... Figure 1 The mobile terminal structure shown does not constitute a limitation on the mobile terminal. The mobile terminal may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0035] The following is combined with Figure 1 A detailed introduction to each component of the mobile terminal:

[0036] The radio frequency unit 101 can be used for receiving and transmitting signals during information transmission or calls. Specifically, it receives downlink information from the base station and processes it with the processor 110; additionally, it transmits uplink data to the base station. Typically, the radio frequency unit 101 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low-noise amplifier, and a duplexer. Furthermore, the radio frequency unit 101 can also communicate wirelessly with networks and other devices. The aforementioned wireless communications may use any communication standard or protocol, including but not limited to GSM (Global System of Mobile communication), GPRS (General Packet Radio Service), CDMA2000 (Code Division Multiple Access 2000), WCDMA (Wideband Code Division Multiple Access), TD-SCDMA (Time Division-Synchronous Code Division Multiple Access), FDD-LTE (Frequency Division Duplexing-Long Term Evolution), and TDD-LTE (Time Division Duplexing-Long Term Evolution).

[0037] WiFi is a short-range wireless transmission technology. Mobile terminals, through the WiFi module 102, can help users send and receive emails, browse web pages, and access streaming media, providing users with wireless broadband internet access. Although Figure 1 WiFi module 102 is shown, but it is understood that it is not a necessary component of a mobile terminal and can be omitted as needed without changing the nature of the invention.

[0038] The audio output unit 103 can convert audio data received by the radio frequency unit 101 or the WiFi module 102 or stored in the memory 109 into audio signals and output them as sound when the mobile terminal 100 is in call signal receiving mode, call mode, recording mode, voice recognition mode, broadcast receiving mode, etc. Furthermore, the audio output unit 103 can also provide audio output related to specific functions performed by the mobile terminal 100 (e.g., call signal receiving sound, message receiving sound, etc.). The audio output unit 103 may include a speaker, a buzzer, etc.

[0039] The A / V input unit 104 is used to receive audio or video signals. The A / V input unit 104 may include a graphics processing unit (GPU) 1041 and a microphone 1042. The GPU 1041 processes image data of still images or videos acquired by an image capture device (such as a camera) in video capture mode or image capture mode. The processed image frames can be displayed on the display unit 106. The image frames processed by the GPU 1041 can be stored in the memory 109 (or other storage medium) or transmitted via the radio frequency unit 101 or the WiFi module 102. The microphone 1042 can receive sound (audio data) in operating modes such as telephone call mode, recording mode, and voice recognition mode, and can process such sound into audio data. The processed audio (voice) data can be converted into a format that can be transmitted to a mobile communication base station via the radio frequency unit 101 in telephone call mode. The microphone 1042 can implement various types of noise cancellation (or suppression) algorithms to eliminate (or suppress) noise or interference generated during the reception and transmission of audio signals.

[0040] The mobile terminal 100 also includes at least one sensor 105, such as a light sensor, a motion sensor, and other sensors. Specifically, the light sensor includes an ambient light sensor and a proximity sensor. The ambient light sensor can adjust the brightness of the display panel 1061 according to the ambient light level, and the proximity sensor can turn off the display panel 1061 and / or backlight when the mobile terminal 100 is moved to the ear. As a type of motion sensor, the accelerometer sensor can detect the magnitude of acceleration in various directions (generally three axes). When stationary, it can detect the magnitude and direction of gravity and can be used for applications that recognize the phone's posture (such as landscape / portrait switching, related games, magnetometer posture calibration), vibration recognition-related functions (such as pedometer, tapping), etc. Other sensors that may be configured in the phone, such as fingerprint sensors, pressure sensors, iris sensors, molecular sensors, gyroscopes, barometers, hygrometers, thermometers, and infrared sensors, will not be described in detail here.

[0041] The display unit 106 is used to display information input by the user or information provided to the user. The display unit 106 may include a display panel 1061, which may be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), or the like.

[0042] User input unit 107 can be used to receive input numerical or character information, and generate key signal inputs related to user settings and function control of the mobile terminal. Specifically, user input unit 107 may include touch panel 1071 and other input devices 1072. Touch panel 1071, also known as touch screen, can collect touch operations on or near the user (such as operations performed by the user using a finger, stylus, or any suitable object or accessory on or near touch panel 1071), and drive corresponding connection devices according to a pre-set program. Touch panel 1071 may include two parts: a touch detection device and a touch controller. The touch detection device detects the user's touch position and the signal generated by the touch operation, and transmits the signal to the touch controller; the touch controller receives touch information from the touch detection device, converts it into touch point coordinates, sends it to processor 110, and can receive and execute commands from processor 110. In addition, touch panel 1071 can be implemented using various types such as resistive, capacitive, infrared, and surface acoustic wave. In addition to the touch panel 1071, the user input unit 107 may also include other input devices 1072. Specifically, other input devices 1072 may include, but are not limited to, one or more of the following: physical keyboard, function keys (such as volume control buttons, power buttons, etc.), trackball, mouse, joystick, etc., without being limited here.

[0043] Furthermore, the touch panel 1071 may cover the display panel 1061. When the touch panel 1071 detects a touch operation on or near it, it transmits the information to the processor 110 to determine the type of touch event. Subsequently, the processor 110 provides corresponding visual output on the display panel 1061 based on the type of touch event. Although in Figure 1 In this embodiment, the touch panel 1071 and the display panel 1061 are two independent components to realize the input and output functions of the mobile terminal. However, in some embodiments, the touch panel 1071 and the display panel 1061 can be integrated to realize the input and output functions of the mobile terminal. The specific implementation is not limited here.

[0044] Interface unit 108 serves as an interface through which at least one external device can connect to mobile terminal 100. For example, the external device may include a wired or wireless headset port, an external power supply (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device with an identification module, an audio input / output (I / O) port, a video I / O port, a headphone port, and so on. Interface unit 108 may be used to receive input (e.g., data, power, etc.) from the external device and transmit the received input to one or more elements within mobile terminal 100, or it may be used to transmit data between mobile terminal 100 and the external device.

[0045] The memory 109 can be used to store software programs and various data. The memory 109 may primarily include a program storage area and a data storage area. The program storage area may store the operating system, applications required for at least one function (such as sound playback, image playback, etc.), etc.; the data storage area may store data created based on the use of the mobile phone (such as audio data, phonebook, etc.). Furthermore, the memory 109 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0046] The processor 110 is the control center of the mobile terminal. It connects various parts of the mobile terminal via various interfaces and lines. By running or executing software programs and / or modules stored in the memory 109, and by calling data stored in the memory 109, it performs various functions and processes data of the mobile terminal, thereby providing overall monitoring of the mobile terminal. The processor 110 may include one or more processing units; preferably, the processor 110 may integrate an application processor and a modem processor. The application processor mainly handles the operating system, user interface, and applications, while the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into the processor 110.

[0047] The mobile terminal 100 may also include a power supply 111 (such as a battery) that supplies power to various components. Preferably, the power supply 111 can be logically connected to the processor 110 through a power management system, thereby enabling functions such as charging, discharging, and power consumption management through the power management system.

[0048] although Figure 1 As not shown, the mobile terminal 100 may also include a Bluetooth module, etc., which will not be described in detail here.

[0049] To facilitate understanding of the embodiments of the present invention, the communication network system on which the mobile terminal of the present invention is based is described below.

[0050] Please see Figure 2 , Figure 2 This invention provides a communication network system architecture diagram. The communication network system is an LTE system based on the universal mobile communication technology. The LTE system includes a UE (User Equipment) 201, an E-UTRAN (Evolved UMTS Terrestrial Radio Access Network) 202, an EPC (Evolved Packet Core) 203, and the operator's IP services 204, which are connected in sequence.

[0051] Specifically, UE201 can be the aforementioned terminal 100, which will not be elaborated here.

[0052] E-UTRAN202 includes eNodeB2021 and other eNodeB2022s. Among them, eNodeB2021 can connect to other eNodeB2022s via backhaul (e.g., X2 interface), and eNodeB2021 connects to EPC203. eNodeB2021 can provide UE201 with access to EPC203.

[0053] EPC203 may include MME (Mobility Management Entity) 2031, HSS (Home Subscriber Server) 2032, other MMEs 2033, SGW (Serving Gateway) 2034, PGW (Packet Data Network Gateway) 2035, and PCRF (Policy and Charging Rules Function) 2036, etc. Among them, MME2031 is the control node that handles signaling between UE201 and EPC203, providing bearer and connection management. HSS2032 provides registers to manage functions such as the Home Location Register (not shown in the diagram) and stores user-specific information such as service characteristics and data rates. All user data can be sent through SGW2034. PGW2035 can provide UE 201 IP address allocation and other functions. PCRF2036 is the policy and charging control decision point for service data flow and IP bearer resources. It selects and provides available policy and charging control decisions for the policy and charging enforcement function unit (not shown in the figure).

[0054] IP services 204 may include the Internet, intranet, IMS (IP Multimedia Subsystem), or other IP services.

[0055] Although the above description uses the LTE system as an example, those skilled in the art should understand that the present invention is not only applicable to the LTE system, but also to other wireless communication systems, such as GSM, CDMA2000, WCDMA, TD-SCDMA, and future new network systems, etc., which are not limited here.

[0056] Based on the aforementioned mobile terminal hardware structure and communication network system, various embodiments of the method of the present invention are proposed.

[0057] Example 1:

[0058] This application provides a relaxation-type clock circuit that supports external synchronization. Please refer to [link to relevant documentation]. Figure 3 and Figure 6 The relaxation-type clock circuit supporting external synchronization includes an external synchronization circuit 301 and a fixed frequency circuit 302 electrically connected to the external synchronization circuit 301. The external synchronization circuit 301 is used to implement SYNC shaping of the external synchronization signal, and the fixed frequency circuit 302 is used to fix the clock frequency.

[0059] The fixed frequency circuit 302 includes a switching circuit 3021, a transmission gate circuit 3022 (hereinafter referred to as a CMOS transmission gate), and a single operational amplifier circuit 3023 that are electrically connected to each other. The switching circuit 3021 is connected in parallel with a clock capacitor C. One end of the switching circuit 3021 and the clock capacitor C are both connected to the negative input terminal of the single operational amplifier circuit 3023. The transmission gate circuit 3022 is connected to the positive input terminal of the single operational amplifier circuit 3023.

[0060] The output terminal of the external synchronization circuit 301 is connected to the input terminal of the switching circuit 3021. The external synchronization circuit 301 includes a monostable circuit 3011.

[0061] Please see Figures 4 to 6 The switching circuit 3021 includes a first switch M1 and a second switch M2, which are connected in series. The first switch M1 is a PMOS transistor, and the second switch M2 is an NMOS transistor. The gate of the first switch M1 is connected to the gate of the second switch M2, and the drain of the first switch M1 is connected to the drain of the second switch M2 and together they are connected to the negative input terminal of the single operational amplifier circuit 3023.

[0062] The clock capacitor C is connected in parallel with the second switch M2 circuit. One end of the clock capacitor C is connected to the source of the second switch M2, and the other end of the clock capacitor C is connected to the drain of the second switch M2.

[0063] The transmission gate circuit 3022 includes a first transmission gate TG1 and a second transmission gate TG2. The first transmission gate TG1 and the second transmission gate TG2 are connected in parallel. The first transmission gate TG1 is an NMOS transistor, and the second transmission gate TG2 is a PMOS transistor. The drain of the first transmission gate TG1 is connected to the drain of the second transmission gate TG2, and the source of the first transmission gate TG1 is connected to the source of the second transmission gate TG2 and together they are connected to the positive input terminal of the single operational amplifier circuit 3023.

[0064] The external synchronization circuit 301 further includes a NAND gate circuit 3012. The output terminal of the monostable circuit 3011 and the CLK signal output terminal are both connected to the input terminal of the NAND gate circuit 3012. The output terminal of the NAND gate circuit 3012 is connected to the gate of the first switch M1 and the second switch M2.

[0065] The monostable circuit 3011 includes three inverters connected in series, all of which are inverted aspect ratio inverters.

[0066] The working principle and process of the relaxation clock circuit supporting external synchronization described in this application are as follows:

[0067] When the system powers on, the voltage across the clock capacitor C is low. This low voltage causes the CLK output to go low, turning on the first switch M1 and turning off the second switch M2. Current source I1 begins charging the clock capacitor C, resulting in a voltage V across the clock capacitor C. c The voltage continues to rise until it reaches the threshold value V. H At this time, the comparator output changes, and the CLK signal goes high. During the charging phase, the voltage across the clock capacitor C changes linearly with time t:

[0068]

[0069]

[0070] Charging time:

[0071]

[0072] After CLK transitions to a high level, the first switch M1 is turned off and the second switch M2 is turned on. Capacitor C discharges with a constant current I2, resulting in a voltage V across the capacitor. c It continues to decline until it reaches the threshold V. L At this time, the comparator output is high, and the CLK signal returns to a low level. During the discharge phase, the voltage across the capacitor changes linearly with time t:

[0073]

[0074]

[0075] Discharge time:

[0076]

[0077] Oscillator clock cycle:

[0078] T osc =T1+T2 (3-7)

[0079] Oscillator clock frequency:

[0080]

[0081] As analyzed in formulas (3-1) to (3-8) above, the capacitor continuously charges and discharges under the clock voltage V. c The circuit generates a periodic sawtooth wave voltage; CLK outputs a periodic square wave signal, which is the output of the fixed frequency circuit 302.

[0082] Depend on Figure 5 As can be seen from the basic structure of a fixed-frequency circuit, during the charging phase, CLK outputs low, and transmission gate TG1 opens. At this time, the comparator threshold is V. H During the discharge phase, CLK outputs high, and transmission gate TG2 opens. At this time, the comparator's threshold is V. L The transmission gate (TG3022) is used to control the transmission of input signals. For example... Figure 6 As shown, the transmission gate consists of a PMOS transistor connected in parallel with an NMOS transistor. Since an NMOS single-transistor transmission gate can reliably transmit low levels, and a PMOS single-transistor transmission gate can reliably transmit high levels, connecting these two complementary MOS transistors in parallel allows for the simultaneous and efficient transmission of both high and low levels. When S is high, the transmission gate is open, and the output signal perfectly reflects the input signal.

[0083] like Figure 4 In the external synchronization circuit, the one-shot module (one-shot, monostable circuit, also known as a monostable multivibrator) can shape the external synchronization signal SYNC. When there is no external synchronization application, whether the SYNC signal is high or low, the one-shot module outputs OS, which remains constant high. The OS signal does not interfere with the operation of the fixed-frequency circuit 302, meaning that the fixed-frequency circuit 302 operates in its inherent oscillator mode. When the external clock signal SYNC is triggered, the one-shot module detects the rising edge pulse of SYNC and outputs a negative pulse signal OS with a certain pulse width. During the charging process of the clock capacitor C, if the OS negative pulse is triggered, the second switch M2 is opened, and the clock capacitor C discharges prematurely. Once the voltage V on the clock capacitor C... c Down to V L At this time, the fixed-frequency circuit 302 output changes, the first switch M1 turns on, and the clock capacitor C begins to charge. This continues until the rising edge of the SYNC signal triggers the one_shot module, causing the clock capacitor C to discharge again. Thus, the OS signal replaces the clock capacitor voltage V. c The rising threshold V H This forces the fixed-frequency circuit 302 to output a frequency that follows the external synchronization signal SYNC.

[0084] The external clock signal SYNC generates a pulse OS with the same frequency and controllable pulse width through the one_shot module. The one_shot module itself is a monostable circuit. The output high level is the steady state. When the external input frequency flips (a rising edge appears), a transition state is generated, the output is pulled low, and after holding a fixed low pulse, the output flips high again.

[0085] Please see Figure 7 This is the monostable circuit diagram of the one_shot module, including three inverters connected in series. These inverters are all inverted width-to-length ratio inverters used to control the pulse width of the signal OS. By appropriately adjusting the parameters so that the duty cycle of OS is less than 10% when the external periodic signal SYNC is input, the clock capacitor voltage V is ensured. c Descending to V L Previously, the one_shot output signal OS returned to a steady state and went high.

[0086] Compared to existing oscillators that consist of two operational amplifiers or Schmitt triggers, which result in the operational amplifiers occupying chip area and the Schmitt trigger threshold becoming unstable due to process and temperature drift, the fixed-frequency circuit 302 described in this application uses a single operational amplifier structure, which can eliminate the instability problems caused by the influence of process and temperature on the circuit.

[0087] The relaxation clock circuit supporting external synchronization described in this application embodiment can effectively realize the external synchronization function, and the circuit structure design is simple. The external synchronization circuit 301 can generate a pulse OS signal with the same frequency and controllable pulse width, and the fixed frequency circuit 302 can output a fixed and periodic target frequency required by the user. The circuit has good stability and the periodic signal output has high accuracy. This application can effectively solve the problem of circuit stability and clock accuracy affected by difference frequency noise in existing switching circuits.

[0088] Example 2:

[0089] This application also provides an oscillator; please refer to [link / reference]. Figure 8 The oscillator includes a relaxation clock circuit supporting external synchronization. The relaxation clock circuit supporting external synchronization includes an external synchronization circuit 301 and a fixed frequency circuit 302 electrically connected to the external synchronization circuit 301. The external synchronization circuit 301 is used to implement SYNC shaping of the external synchronization signal, and the fixed frequency circuit 302 is used to fix the clock frequency. The fixed frequency circuit 302 includes a switching circuit 3021, a transmission gate circuit 3022 (hereinafter referred to as a CMOS transmission gate), and a single operational amplifier circuit 3023 electrically connected to each other. The switching circuit 3021 has a clock capacitor C connected in parallel. One end of the switching circuit 3021 and the clock capacitor C are both connected to the negative input terminal of the single operational amplifier circuit 3023, and the transmission gate circuit 3022 is connected to the positive input terminal of the single operational amplifier circuit 3023.

[0090] The output terminal of the external synchronization circuit 301 is connected to the input terminal of the switching circuit 3021. The external synchronization circuit 301 includes a monostable circuit 3011.

[0091] The external synchronization circuit 301 and the fixed frequency circuit 302 are basically the same in structure and working principle as the external synchronization circuit 301 and the fixed frequency circuit 302 in Embodiment 1 above, and will not be described again here.

[0092] The vibrator described in this application embodiment, by setting a relaxation-type clock circuit that supports external synchronization, can effectively achieve external synchronization compared to existing oscillators. Moreover, the circuit structure design is simple. The external synchronization circuit 301 can generate a pulse OS signal with the same frequency and controllable pulse width. The fixed frequency circuit 302 can output a fixed and periodic target frequency required by the user. The circuit has good stability and the periodic signal output has high accuracy. This application can effectively solve the problem of circuit stability and clock accuracy affected by difference frequency noise in existing switching circuits.

[0093] Example 3:

[0094] According to an embodiment of the present invention, a smart terminal is provided, wherein the smart terminal is provided with a relaxation clock circuit that supports external synchronization. The relaxation clock circuit that supports external synchronization has a structure and working principle that are basically the same as the relaxation clock circuit that supports external synchronization described in the above embodiment, and will not be described again here.

[0095] The smart terminal described in this application embodiment, by setting a relaxation-type clock circuit that supports external synchronization, can ensure the stability of circuit information transmission and the accuracy of the clock in the smart terminal, and can effectively improve the user experience.

[0096] In one embodiment, the smart terminal described in this application stores a computer program. When the computer program is executed by a processor, it implements the working process and principle described in Embodiment 1 above, which will not be repeated here.

[0097] The memory in this embodiment can be used to store software programs and various data. The memory may primarily include a program storage area and a data storage area. The program storage area may store the operating system, applications required for at least one function, etc.; the data storage area may store data created based on the use of the mobile phone, etc. Furthermore, the memory may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0098] According to an example of this embodiment, the working principle and process in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium. For example, in this embodiment, the program can be stored in the storage medium of a computer system and executed by at least one processor in the computer system to implement the processes of the embodiments including the methods described above. The storage medium includes, but is not limited to, magnetic disks, USB flash drives, optical disks, read-only memory (ROM), etc.

[0099] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0100] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0101] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0102] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A relaxation-type clock circuit supporting external synchronization, characterized in that, It includes an external synchronization circuit and a fixed frequency circuit electrically connected to the external synchronization circuit. The external synchronization circuit is used to implement SYNC shaping of the external synchronization signal, and the fixed frequency circuit is used to fix the clock frequency. The fixed frequency circuit includes a switching circuit, a transmission gate circuit, and a single operational amplifier circuit that are electrically connected to each other. The switching circuit is connected in parallel with a clock capacitor C. One end of the switching circuit and one end of the clock capacitor C are both connected to the negative input terminal of the single operational amplifier circuit. The transmission gate circuit is connected to the positive input terminal of the single operational amplifier circuit. The switching circuit includes a first switch M1 and a second switch M2, wherein the first switch M1 and the second switch M2 are connected in series. The output terminal of the external synchronization circuit is connected to the input terminal of the switching circuit. The external synchronization circuit includes a monostable circuit. The monostable circuit includes three inverters connected in series, and all of the inverters are inverters with inverted aspect ratio. The external synchronization circuit also includes a NAND gate circuit. The output terminal of the monostable circuit and the output terminal of the CLK signal are both connected to the input terminal of the NAND gate circuit. The output terminal of the NAND gate circuit is connected to the first switch M1 and the second switch M2. The transmission gate circuit includes a first transmission gate TG1 and a second transmission gate TG2. The first transmission gate TG1 and the second transmission gate TG2 are connected in parallel. The first transmission gate TG1 is an NMOS transistor, and the second transmission gate TG2 is a PMOS transistor. The drain of the first transmission gate TG1 is connected to the drain of the second transmission gate TG2, and the source of the first transmission gate TG1 is connected to the source of the second transmission gate TG2 and together they are connected to the positive input terminal of the single op-amp circuit.

2. The relaxation clock circuit supporting external synchronization according to claim 1, characterized in that, The first switch M1 is a PMOS transistor, the second switch M2 is an NMOS transistor, the gate of the first switch M1 is connected to the gate of the second switch M2, and the drain of the first switch M1 is connected to the drain of the second switch M2 and together they are connected to the negative input terminal of the single op-amp circuit.

3. The relaxation clock circuit supporting external synchronization according to claim 2, characterized in that, The clock capacitor C is connected in parallel with the second switch M2 circuit. One end of the clock capacitor C is connected to the source of the second switch M2, and the other end of the clock capacitor C is connected to the drain of the second switch M2.

4. An oscillator, characterized in that, The system includes a relaxation clock circuit that supports external synchronization. The relaxation clock circuit that supports external synchronization includes an external synchronization circuit and a fixed frequency circuit electrically connected to the external synchronization circuit. The external synchronization circuit is used to implement SYNC shaping of the external synchronization signal, and the fixed frequency circuit is used to fix the clock frequency. The fixed frequency circuit includes a switching circuit, a transmission gate circuit, and a single operational amplifier circuit that are electrically connected to each other. The switching circuit is connected in parallel with a clock capacitor C. One end of the switching circuit and one end of the clock capacitor C are both connected to the negative input terminal of the single operational amplifier circuit. The transmission gate circuit is connected to the positive input terminal of the single operational amplifier circuit. The switching circuit includes a first switch M1 and a second switch M2, wherein the first switch M1 and the second switch M2 are connected in series. The output terminal of the external synchronization circuit is connected to the input terminal of the switching circuit. The external synchronization circuit includes a monostable circuit. The monostable circuit includes three inverters connected in series, and all of the inverters are inverters with inverted aspect ratio. The transmission gate circuit includes a first transmission gate TG1 and a second transmission gate TG2. The first transmission gate TG1 and the second transmission gate TG2 are connected in parallel. The first transmission gate TG1 is an NMOS transistor, and the second transmission gate TG2 is a PMOS transistor. The drain of the first transmission gate TG1 is connected to the drain of the second transmission gate TG2, and the source of the first transmission gate TG1 is connected to the source of the second transmission gate TG2 and together they are connected to the positive input terminal of the single op-amp.

5. The oscillator according to claim 4, characterized in that, The first switch M1 is a PMOS transistor, the second switch M2 is an NMOS transistor, the gate of the first switch M1 is connected to the gate of the second switch M2, and the drain of the first switch M1 is connected to the drain of the second switch M2 and together they are connected to the negative input terminal of the single op-amp.

6. A smart terminal, characterized in that, Includes a relaxation clock circuit that supports external synchronization, wherein the relaxation clock circuit that supports external synchronization is the relaxation clock circuit that supports external synchronization as described in any one of claims 1 to 3.

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