Semiconductor device

Abstract

This application provides a semiconductor device comprising a semiconductor substrate having a transistor portion and a diode portion. At the diode portion end of the transistor portion when viewed from above, the transistor portion has an injection suppression region for suppressing the injection of carriers of a second conductivity type. Both the transistor portion and the diode portion have a base region of a second conductivity type on the front side of the semiconductor substrate. The transistor portion also has an emitter region of a first conductivity type and an extractor region of a second conductivity type with a doping concentration higher than that of the base region on the front side of the semiconductor substrate. The injection suppression region does not have an emitter region or an extractor region.

Description

Technical Field

[0001] This invention relates to semiconductor devices. Background Technology

[0002] Conventionally, in semiconductor devices in which transistor sections such as insulated gate bipolar transistors (IGBTs) and diode sections are formed on the same substrate, it is known to provide a contact layer in the transistor section with an impurity concentration higher than that in the anode layer of the diode section (for example, Patent Document 1).

[0003] Patent documents

[0004] Patent Document 1: International Publication No. 2016 / 030966 Summary of the Invention

[0005] Technical issues

[0006] In such a semiconductor device, during freewheeling in the diode section, holes are supplied not only from the anode layer but also from the cathode layer, where electron current flows into the transistor section and holes are injected from the contact layer. Therefore, the reverse recovery current increases, leading to increased inverter losses.

[0007] Technical solution

[0008] In a first aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a transistor portion and a diode portion, and at the diode portion side end of the transistor portion when viewed from above the semiconductor substrate, the transistor portion has an injection suppression region for suppressing the injection of second conductivity type charge carriers.

[0009] Both the transistor section and the diode section have a base region of a second conductivity type on the front side of the semiconductor substrate. The transistor section also has an emitter region of a first conductivity type and an extractor region of a second conductivity type with a doping concentration higher than that of the base region on the front side of the semiconductor substrate. The emitter region and the extractor region may not be provided in the implantation suppression region.

[0010] When viewed from above, the width of the implantation suppression region in the arrangement direction of the transistor and diode sections can be 20 μm or more and 900 μm or less.

[0011] When viewed from above, an injection suppression region may be provided between the end of the diode section in the extending direction and the outer periphery of the active region.

[0012] When viewed from above the semiconductor substrate, the area of ​​the diode section can be more than 10% of the combined area of ​​the diode section and the injection suppression region.

[0013] When viewed from above the semiconductor substrate, the total area of ​​the diode section can be more than 1.4% and less than 22% of the area of ​​the semiconductor device.

[0014] The doping concentration of the base region in the implantation suppression region can be lower than or equal to the doping concentration of the base region in the diode section.

[0015] The doping concentration of the base region in the implantation suppression region can be 1×10⁻⁶. 16 cm －3 Above and 5×10 19 cm －3 the following.

[0016] The doping concentration of the base region of the diode can be 1×10⁻⁶. 16 cm －3 Above and 1×10 18 cm －3 the following.

[0017] The doping concentration in the extraction region can be 5 × 10⁻⁶. 18 cm －3 Above and 5×10 20 cm －3 the following.

[0018] Both the transistor section and the diode section have a base region of a second conductivity type on the front side of the semiconductor substrate. The transistor section and the implantation suppression region also have an emitter region of a first conductivity type and an extractor region of a second conductivity type with a doping concentration higher than that of the base region on the front side of the semiconductor substrate. When viewed from above, the ratio of the emitter region to the extractor region in the implantation suppression region can be lower than the ratio of the emitter region to the extractor region in the transistor section.

[0019] The transistor section and the injection suppression region have multiple mesa sections, which extend between multiple trench sections along the extension direction of the transistor section and the diode section. The multiple trench sections extend along the extension direction and are arranged along the arrangement direction of the transistor section and the diode section. In the mesa section of the injection suppression region, either the emitter region or the extraction region can be configured to be adjacent to the emitter region disposed on the mesa section adjacent to the transistor section side.

[0020] The multiple trench portions include gate trench portions and dummy trench portions. The injection suppression region may have dummy trench portions but not gate trench portions.

[0021] The multiple trench portions include gate trench portions and dummy trench portions. The dummy ratio in the injection suppression region can be higher than the dummy ratio in the transistor portion excluding the injection suppression region. The dummy ratio is the ratio of the number of dummy trench portions to the total number of gate trench portions and dummy trench portions.

[0022] The emitter region of the injection suppression region can be configured on the mesa adjacent to the gate trench.

[0023] The dummy ratio in the injection suppression region can be above 75% and below 87.5%.

[0024] The dummy ratio in the transistor section, excluding the injection suppression region, can be above 0% and below 75%.

[0025] The emission region of the injection suppression region can be adjacent to the extraction region in the extension direction.

[0026] The mesa adjacent to the diode section in the injection suppression region may not have an emitter region configured.

[0027] When viewed from above, the length of the extracted region in the extending direction of the transistor and diode sections can be 0.5 μm or more.

[0028] When viewed from above, the length of the extracted region can be 0.3 μm or more in the arrangement direction of the transistor and diode sections.

[0029] In the injection suppression region, the base region can be configured in the portion where neither the emitter nor the extractor region is configured.

[0030] The semiconductor substrate may also have an accumulation region of the first conductivity type inside.

[0031] It should be noted that the above description of the invention does not list all the essential features of the invention. Furthermore, sub-combinations of these feature groups can also constitute an invention. Attached Figure Description

[0032] Figure 1A This is a partial top view of the semiconductor device 100 of Embodiment 1 of this invention.

[0033] Figure 1B It means Figure 1A The diagram of section a-a' in the figure.

[0034] Figure 1C This is a diagram illustrating the operation of the diode section 80 of the semiconductor device 100 when it is turned on.

[0035] Figure 2A This is a diagram showing an example of the front view of the comparative example semiconductor device 1100.

[0036] Figure 2B It means Figure 2A The diagram of section a-a' in the figure.

[0037] Figure 2C This is a diagram illustrating the operation of the diode section 80 of the semiconductor device 1100 when it is turned on.

[0038] Figure 3A It is a graph showing the relationship between the width of the injection suppression region 90 and the reverse recovery loss.

[0039] Figure 3BIt is a graph showing the relationship between the width of the injection suppression region 90 and the conduction loss.

[0040] Figure 4A This is a top view of the semiconductor device 100 of Embodiment 1 of this invention.

[0041] Figure 4B yes Figure 4A A magnified view of part A.

[0042] Figure 4C It is a graph showing the relationship between the width of the injection suppression region 90 and the reverse recovery loss.

[0043] Figure 5A This is a partial cross-sectional view of the semiconductor device 200 of Embodiment 2 of this invention.

[0044] Figure 5B This is a graph showing the relationship between the doping concentration of the base region 94 in the implantation suppression region 90 and the reverse recovery loss.

[0045] Figure 5C It is a graph showing the relationship between the doping concentration of the base region 94 in the implantation suppression region 90 and the conduction loss.

[0046] Figure 6A This is a partial top view of the semiconductor device 300 of Embodiment 3 of this invention.

[0047] Figure 6B yes Figure 6A A magnified view of part B in the image.

[0048] Figure 7A This is a partial top view of the semiconductor device 400 of Embodiment 4 of this implementation.

[0049] Figure 7B It means Figure 7A The diagram of section a-a' in the figure.

[0050] Figure 7C This diagram illustrates the operation of the diode section 80 of the semiconductor device 400 when it is turned on.

[0051] Figure 8A This is a partial cross-sectional view of the semiconductor device 500 of Embodiment 5 of this invention.

[0052] Figure 8B This is a partial top view of semiconductor device 500.

[0053] Figure 8C This is a partial top view of semiconductor device 500.

[0054] Figure 8D This is a partial top view of semiconductor device 500.

[0055] Symbol Explanation

[0056] 10...Substrate, 11...Trap region, 12...Emitter region, 14...Base region, 15...Ejection region, 16...Accumulation region, 17...Plug region, 18...Drift region, 20...Buffer zone, 21...Front side, 22...Collector region, 23...Back side, 24...Collector, 25...Connection portion, 29...Linear portion, 30...Dummy trench portion, 31...Front end portion, 32...Dummy insulating film, 34...Dummy conductive portion, 38...Interlayer insulating film, 39...Linear portion, 40...Gate trench portion, 41...Front end portion, 42...Gate insulating film, 44...Gate conductive portion, 48...Gate channel, 49...Contact hole 50... Gate metal layer, 52... Emitter, 54... Contact hole, 56... Contact hole, 58... Contact hole, 60... Mesa section, 60a... First mesa section, 60b... Second mesa section, 60c... Third mesa section, 60d... Fourth mesa section, 61... Mesa section, 70... Transistor section, 80... Diode section, 82... Cathode region, 90... Implantation suppression region, 94... Base region, 100... Semiconductor device, 102... Edge, 160... Active region, 190... Edge termination structure, 200... Semiconductor device, 300... Semiconductor device, 400... Semiconductor device, 1100... Semiconductor device Detailed Implementation

[0057] The present invention will now be described through embodiments thereof, but these embodiments do not limit the invention as defined in the claims. Furthermore, the combinations of features described in the embodiments are not necessarily all necessary for the solution of the invention.

[0058] In this specification, one side parallel to the depth direction of the semiconductor substrate is referred to as "upper" and the other side as "lower". One of the two main surfaces of the substrate, layer or other component is referred to as the front surface and the other as the back surface. The "upper" and "lower" directions are not limited to the direction of gravity or the direction when mounting the semiconductor device.

[0059] In this specification, orthogonal coordinate axes of X, Y, and Z are sometimes used to illustrate technical matters. Orthogonal coordinate axes merely determine the relative positions of constituent elements and do not limit specific directions. For example, the Z-axis does not necessarily represent the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite directions. When a direction is referred to as the Z-axis without specifying positive or negative, it refers to a direction parallel to both the +Z-axis and the Z-axis.

[0060] In this specification, orthogonal axes parallel to the front and back surfaces of the semiconductor substrate are designated as the X-axis and Y-axis. An axis perpendicular to the front and back surfaces of the semiconductor substrate is designated as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. Additionally, in this specification, the direction including the X-axis and Y-axis and parallel to the front and back surfaces of the semiconductor substrate is sometimes referred to as the horizontal direction.

[0061] In this specification, the terms "same" or "equal" may also include cases with errors caused by manufacturing deviations, etc. Such errors are, for example, within 10%.

[0062] In this specification, the conductivity type of a doped region containing impurities is described as P-type or N-type. In this specification, impurities sometimes specifically refer to either an N-type donor or a P-type acceptor, and are sometimes referred to as dopant. In this specification, doping refers to the introduction of donors or acceptors into a semiconductor substrate to form a semiconductor exhibiting an N-type conductivity type or a P-type conductivity type.

[0063] In this specification, doping concentration refers to the concentration of donors or acceptors under thermal equilibrium conditions. In this specification, net doping concentration refers to the concentration obtained by adding the concentrations including charge polarity, with the donor concentration set as the concentration of positive ions and the acceptor concentration set as the concentration of negative ions. As an example, if the donor concentration is set as N... D Set the acceptor concentration to N A Then the net doping concentration at any position is N. D -N A .

[0064] Donors have the function of supplying electrons to semiconductors. Acceptors have the function of receiving electrons from semiconductors. Donors and acceptors are not limited to impurities themselves. For example, VOH defects formed by the combination of vacancies (V), oxygen (O), and hydrogen (H) in semiconductors function as electron donors.

[0065] In this specification, "P+" or "N+" indicates a higher doping concentration than "P" or "N" type, while "P-" or "N-" indicates a lower doping concentration than "P" or "N" type. Furthermore, "P++" or "N++" indicates a higher doping concentration than "P+" or "N+" type.

[0066] In this specification, chemical concentration refers to the concentration of impurities measured independently of the electroactivated state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration mentioned above can be determined by voltage-capacitance measurement (CV method). Alternatively, the carrier concentration measured by extended resistance measurement (SR method) can be used as the net doping concentration. The carrier concentration measured by CV or SR methods can be set to the value under thermal equilibrium conditions. Furthermore, in the N-type region, since the donor concentration is significantly greater than the acceptor concentration, the carrier concentration in this region can also be set as the donor concentration. Similarly, in the P-type region, the carrier concentration in this region can also be set as the acceptor concentration.

[0067] Furthermore, when the concentration distribution of donor, acceptor, or net dopant has a peak, that peak can be taken as the concentration of donor, acceptor, or net dopant in that region. When the concentration of donor, acceptor, or net dopant is approximately uniform, the average concentration of donor, acceptor, or net dopant in that region can be taken as the concentration of donor, acceptor, or net dopant.

[0068] The carrier concentration measured by the SR method can be lower than the donor or acceptor concentration. During the measurement of extended resistance, within the current flow range, the carrier mobility of the semiconductor substrate is sometimes lower than that in the crystalline state. This decrease in carrier mobility is caused by the disorder (disorder) of the crystal structure due to lattice defects, resulting in the dispersion of carriers.

[0069] The donor or acceptor concentration calculated from the carrier concentration measured by the CV or SR method can be lower than the chemical concentration of the element representing the donor or acceptor. For example, in silicon semiconductors, the donor concentration of phosphorus or arsenic (which acts as a donor), or the acceptor concentration of boron (which acts as an acceptor), is about 99% of their chemical concentration. On the other hand, in silicon semiconductors, the donor concentration of hydrogen (which acts as a donor) is about 0.1% to 10% of the chemical concentration of hydrogen.

[0070] [Example 1]

[0071] Figure 1A This is a partial top view of the semiconductor device 100 according to Embodiment 1 of this invention. The semiconductor device 100 includes a semiconductor substrate having a transistor section 70 including transistor elements such as IGBTs and a diode section 80 including diode elements such as freewheeling diodes (FWDs).

[0072] It should be noted that, in this specification, "top view" refers to viewing from the front side of the semiconductor substrate. In this example, the arrangement direction of the transistor section 70 and the diode section 80 when viewed from above is called the X-axis, the direction perpendicular to the X-axis on the front side of the semiconductor substrate is called the Y-axis, and the direction perpendicular to the front side of the semiconductor substrate is called the Z-axis.

[0073] The transistor section 70 and the diode section 80 may each have a length in the extending direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extending direction of the transistor section 70 and the diode section 80 may be the same as the length direction of each trench section described later.

[0074] The diode section 80 has an N+ type cathode region in the area that contacts the back side of the semiconductor substrate. In this specification, the area where the cathode region is provided is referred to as the diode section 80. That is, the diode section 80 is the area that overlaps with the cathode region when viewed from above. On the other hand, the transistor section 70 has a P+ type collector region in the area that contacts the back side of the semiconductor substrate.

[0075] The semiconductor device 100 in this example includes a gate trench 40, a dummy trench 30, a well region 11, an emitter region 12, a base region 14, and an extract region 15 disposed inside the front side of a semiconductor substrate. The gate trench 40 and the dummy trench 30 are examples of trench portions.

[0076] Furthermore, the semiconductor device 100 in this example includes a gate metal layer 50 and an emitter 52 disposed on the upper surface of the front side of a semiconductor substrate. The gate metal layer 50 and the emitter 52 are disposed separately from each other.

[0077] An interlayer insulating film is disposed between the emitter 52 and the gate metal layer 50 and the front side of the semiconductor substrate, but... Figure 1A (The text is omitted.) In this example, the interlayer insulating film has contact holes 49, 54, 56, and 58 that penetrate through it. Figure 1A In the middle, the shading lines of the oblique lines marked on each contact hole are shown.

[0078] The emitter 52 is disposed above the gate trench 40, the dummy trench 30, the well region 11, the emitter region 12, the base region 14, and the extraction region 15. The emitter 52 contacts the emitter region 12, the base region 14, and the extraction region 15 on the front side of the semiconductor substrate through the contact hole 54.

[0079] Furthermore, the emitter 52 is connected to the dummy conductive portion within the dummy trench portion 30 via contact hole 56 or contact hole 58. A connection portion 25, formed of a conductive material such as polycrystalline silicon doped with impurities, may be provided between the emitter 52 and the dummy conductive portion. The connection portions 25 are respectively disposed on the front side of the semiconductor substrate through an insulating film.

[0080] The gate metal layer 50 contacts the gate flow channel 48 through the contact hole 49. The gate flow channel 48 may be formed of polysilicon or the like, which is doped with impurities. The gate flow channel 48 is connected to the gate conductive portion within the gate trench portion 40 on the front side of the semiconductor substrate. The gate flow channel 48 is not electrically connected to the dummy conductive portion within the dummy trench portion 30 or to the emitter 52.

[0081] The gate channel 48 and the emitter 52 can be electrically separated by insulating materials such as interlayer insulating films and oxide films. In this example, the gate channel 48 is disposed from below the contact hole 49 to the front end of the gate trench portion 40. At the front end of the gate trench portion 40, the gate conductive portion is exposed on the front side of the semiconductor substrate and contacts the gate channel 48.

[0082] The emitter 52 and the gate metal layer 50 are formed of a conductive material containing metal. For example, they are formed of polycrystalline silicon, aluminum, or an aluminum-silicon alloy. Each electrode may have a barrier metal formed of titanium, titanium compounds, or the like in a layer beneath the region formed of aluminum.

[0083] Each electrode may also have a plug made of tungsten or the like within the contact hole. The plug may have a blocking metal on the side that contacts the semiconductor substrate, and tungsten is embedded in the plug in such a way as to contact the blocking metal, and is formed on the tungsten by aluminum or the like.

[0084] It should be noted that the plug is disposed in a contact hole that contacts the extraction region 15 or the base region 14. Furthermore, a P++ type plug region 17 with a higher doping concentration than the extraction region 15 is formed below the contact hole of the plug. This improves the contact resistance between the barrier metal and the extraction region 15. Additionally, the depth of the plug region 17 is approximately 0.1 μm or less, having a depth less than 10% of the depth of the extraction region 15.

[0085] The plug region 17 has the following characteristics. During the operation of the transistor section 70, the latch-up resistance is improved by increasing the contact resistance. On the other hand, during the operation of the diode section 80, without the plug region, the contact resistance between the blocking metal and the base region 14 is high, and the conduction loss and switching loss increase. However, by providing the plug region 17, the increase in conduction loss and switching loss can be suppressed.

[0086] The well region 11 is disposed overlapping the gate channel 48. The well region 11 is also disposed with a predetermined width within a range that does not overlap with the gate channel 48. In this example, the well region 11 is disposed such that it is separated from the end of the contact hole 54 in the Y-axis direction towards the gate channel 48 side. The well region 11 is a region of the second conductivity type with a higher doping concentration than the base region 14.

[0087] In this example, the base region 14 is P-type and the well region 11 is P+ type. In addition, the well region 11 is formed from the front side of the semiconductor substrate to a depth deeper than the lower end of the base region 14.

[0088] The transistor section 70 and the diode section 80 each have trench sections, and multiple trench sections are arranged along the arrangement direction. In this example, the transistor section 70 has one or more gate trench sections 40 and one or more dummy trench sections 30 alternately arranged along the arrangement direction. In this example, the diode section 80 has multiple dummy trench sections 30 arranged along the arrangement direction. In this example, the diode section 80 does not have gate trench sections 40.

[0089] In this example, the gate trench portion 40 may have two straight portions 39 (the trench portion that is straight along the extension direction) extending in an extension direction perpendicular to the arrangement direction, and a front end portion 41 connecting the two straight portions 39.

[0090] At least a portion of the front end portion 41 can be curved when viewed from above. The ends of the two straight portions 39 in the Y-axis direction are connected to each other via the front end portion 41 to the gate channel 48, thereby functioning as a gate electrode to the gate trench portion 40. On the other hand, by making the front end portion 41 curved, compared to ending with straight portions 39, the electric field concentration at the end under gate bias can be mitigated.

[0091] In the transistor section 70, dummy trench sections 30 are provided between each straight section 39 of the gate trench section 40. One dummy trench section 30 may be provided between each straight section 39, or multiple dummy trench sections 30 may be provided.

[0092] Furthermore, between each straight section 39, either a dummy trench portion 30 can be omitted, or a gate trench portion 40 can be provided. With this configuration, the electron current from the emitter region 12 can be increased, thereby reducing the on-state voltage.

[0093] The dummy trench portion 30 may have a straight shape extending in the extension direction, or it may have a straight portion 29 and a front end portion 31, similar to the gate trench portion 40. Figure 1A The semiconductor device 100 shown includes both a dummy trench portion 30 with a straight shape and a front end portion 31.

[0094] The diffusion depth of the well region 11 can be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are located within the well region 11 when viewed from above. That is, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 11. This mitigates the electric field concentration at the bottom of each trench portion.

[0095] In the arrangement direction, mezzanine portions are provided between each trench portion. A mezzanine portion refers to the area inside the semiconductor substrate that is sandwiched between the trench portions. As an example, the depth of the mezzanine portion extends from the front side of the semiconductor substrate to the lower end of the trench portion.

[0096] In this example, the mesa is clamped by adjacent trenches in the X-axis direction and is positioned on the front side of the semiconductor substrate, extending along the trenches in the extension direction (Y-axis direction). For example, in Figure 1B As will be described later, in this example, a mesa 60 is provided in the transistor section 70, and a mesa 61 is provided in the diode section 80. In this specification, when referred to simply as mesa, it refers to mesa 60 and mesa 61 respectively.

[0097] A base region 14 is provided on each facet of the transistor section 70. In each facet of the transistor section 70, at least one of a first conductivity type emitter region 12 and a second conductivity type extractor region 15 may be provided in the area sandwiched between the base regions 14 when viewed from above. In this example, the emitter region 12 is N+ type, and the extractor region 15 is P+ type. The emitter region 12 and the extractor region 15 may be disposed in the depth direction between the base region 14 and the front surface of the semiconductor substrate.

[0098] The mesa portion of the transistor section 70 has an emitter region 12 exposed on the front side of the semiconductor substrate. The emitter region 12 is provided in contact with the gate trench portion 40. An extractor region 15 exposed on the front side of the semiconductor substrate is provided on the mesa portion that contacts the gate trench portion 40.

[0099] The extraction area 15 and the emission area 12 in the platform are respectively provided from one groove portion to another in the X-axis direction. As an example, the extraction area 15 and the emission area 12 in the platform are alternately arranged along the extension direction of the groove portion (Y-axis direction).

[0100] In another example, the extraction area 15 and the emission area 12 on the platform surface can be arranged in a stripe pattern along the extension direction (Y-axis direction) of the groove portion. For example, the emission area 12 is provided in the area that contacts the groove portion, and the extraction area 15 is provided in the area that is held by the emission area 12.

[0101] However, in the transistor section 70, the emitter region 12 is not provided on the mesa adjacent to the injection suppression region 90 described later, but an extraction region 15 exposed on the front side of the semiconductor substrate is provided. The extraction region 15 can be provided in a region held by the base region 14 when viewed from above, in a manner that contacts the dummy trench section 30.

[0102] The emitter region 12 is not provided on the mesa of the diode section 80. A base region 14 may be provided on the upper surface of the mesa of the diode section 80. The base region 14 may be disposed on the entire mesa of the diode section 80.

[0103] A contact hole 54 is provided above each stage surface. The contact hole 54 is disposed in the region held by the base region 14 in its extending direction (Y-axis direction). In this example, the contact hole 54 is disposed above the extraction region 15, the base region 14, and the emission region 12. The contact hole 54 can be disposed at the center in the arrangement direction (X-axis direction) of the stage surface.

[0104] In the diode section 80, an N+ type cathode region 82 is provided in the region adjacent to the back side of the semiconductor substrate. On the back side of the semiconductor substrate, in the region where the cathode region 82 is not provided, a P+ type collector region 22 may be provided. Figure 1A In the diagram, the boundary between the cathode region 82 and the collector region 22 is represented by a dashed line.

[0105] The cathode region 82 is disposed separately from the well region 11 in the Y-axis direction. Therefore, by ensuring a sufficient distance between the cathode region 82 and the P-type region (well region 11) with a relatively high doping concentration and deep formation, hole injection from the well region 11 can be suppressed, thus reducing reverse recovery loss. In this example, the end of the cathode region 82 in the Y-axis direction is disposed further away from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In another example, the end of the cathode region 82 in the Y-axis direction may be disposed between the well region 11 and the contact hole 54.

[0106] When viewed from above the semiconductor substrate, the transistor section 70 has an injection suppression region 90 at the end on the diode section 80 side to suppress the injection of second conductivity type charge carriers.

[0107] In the implantation suppression region 90, a P+ type collector region 22 is provided on the back side of the semiconductor substrate. That is, the implantation suppression region 90 is part of the transistor section 70, but in this specification, the transistor section 70 and the implantation suppression region 90 are basically described separately.

[0108] Unlike the transistor section 70, the upper surface of the injection suppression region 90 does not have an emitter region 12 and an extraction region 15, but instead has a base region 14. Furthermore, unlike the transistor section 70, the injection suppression region 90 does not have a gate trench section 40, but instead has a dummy trench section 30.

[0109] It should be noted that, Figure 1A In this diagram, the injection suppression region 90 is shown as two mesa-shaped surfaces adjacent to the dummy trench portion 30, but is not limited thereto. The injection suppression region 90 may have more than two mesa-shaped surfaces.

[0110] Figure 1B It means Figure 1AThe diagram shows the a-a' section. The a-a' section is the XZ plane passing through the emitter region 12, the base region 14, the gate trench portion 40, and the dummy trench portion 30. In this example, the semiconductor device 100 has a substrate 10, an interlayer insulating film 38, an emitter 52, and a collector 24 in the a-a' section.

[0111] An interlayer insulating film 38 is disposed on the front side 21 of the substrate 10. The interlayer insulating film 38 is an insulating film such as silicate glass with added impurities such as boron or phosphorus. The interlayer insulating film 38 may be in contact with the front side 21, or an oxide film or other film may be disposed between the interlayer insulating film 38 and the front side 21. The interlayer insulating film 38 has... Figure 1A Contact hole 54 as described in the diagram.

[0112] An emitter 52 is disposed on the front side 21 of the substrate 10 and the upper surface of the interlayer insulating film 38. The emitter 52 is electrically contacted with the front side 21 through a contact hole 54 in the interlayer insulating film 38. A tungsten (W) or similar contact plug may also be disposed inside the contact hole 54. A collector 24 is disposed on the back side 23 of the substrate 10. The emitter 52 and the collector 24 are formed of a material containing metal.

[0113] The substrate 10 can be a silicon substrate, a silicon carbide substrate, or a gallium nitride or other nitride semiconductor substrate. In this example, the substrate 10 is a silicon substrate.

[0114] The substrate 10 has a drift region 18 of a first conductivity type. In this example, the drift region 18 is N-type. The drift region 18 may be a region remaining in the substrate 10 where no other doped regions are formed.

[0115] Above the drift region 18, one or more accumulation regions 16 can be provided along the Z-axis. The accumulation region 16 is a region formed by accumulating the same dopant as the drift region 18 at a higher concentration than the drift region 18. The doping concentration of the accumulation region 16 is higher than that of the drift region 18. By setting the accumulation region 16, the carrier injection promotion effect (IE effect) can be improved, and the on-state voltage can be reduced.

[0116] In the transistor section 70, an emitter region 12 is disposed above the base region 14 and in contact with the front surface 21. The emitter region 12 is disposed in contact with the gate trench section 40. The doping concentration of the emitter region 12 is higher than that of the drift region 18. As an example, the dopant of the emitter region 12 is arsenic (As), phosphorus (P), antimony (Sb), etc.

[0117] The arrangement direction of the injection inhibition region 90 ( Figure 1B The width A in the X-axis direction of the implantation suppression region 90 is 20 μm or more and 900 μm or less. In addition, the following formula (1) holds between the width A of the implantation suppression region 90 and the substrate thickness W of the semiconductor device 100.

[0118] A≤6W・・・[Equation(1)]

[0119] It should be noted that the substrate thickness W represents the thickness from the upper surface of the base region 14 of the diode section 80 to the lower surface of the cathode region 82. By increasing the substrate thickness W, the electron diffusion region of the cathode region 82 of the diode section 80 is increased, and therefore, according to equation (1), the reverse recovery and conduction losses are reduced.

[0120] Additionally, in the transistor section 70, on the mesa 60 on the side of the injection suppression region 90, an extraction region 15 is provided above the base region 14 in a manner that connects with the front surface 21. The extraction region 15 can be provided in a manner that contacts the dummy trench section 30.

[0121] A base region 14 exposed on the front side 21 is provided in the diode section 80 and the injection suppression region 90. The base region 14 of the diode section 80 operates as the anode.

[0122] A buffer 20 of a first conductivity type can be disposed below the drift region 18. In this example, the buffer 20 is N-type. The doping concentration of the buffer 20 is higher than that of the drift region 18. The buffer 20 can function as a field cutoff layer to prevent the depletion layer extending from the lower surface side of the base region 14 from reaching the collector region 22 and the cathode region 82.

[0123] In the transistor section 70 and the injection suppression region 90, a collector region 22 is provided below the buffer zone 20. The collector region 22 of the injection suppression region 90 can be provided in such a way that it contacts the cathode region 82 on the back side 23.

[0124] In the diode section 80, a cathode region 82 is provided below the buffer zone 20. The cathode region 82 can be provided at the same depth as the collector region 22 of the transistor section 70 and the injection suppression region 90. The diode section 80 can function as a freewheeling diode (FWD) that allows reverse-conducting freewheeling current to flow when the transistor section 70 is turned off.

[0125] A gate trench 40 and a dummy trench 30 are provided on the substrate 10. The gate trench 40 and the dummy trench 30 are arranged to extend from the front side 21 through the base region 14 and the accumulation region 16 to the drift region 18. The trench extending through the doped region is not limited to being manufactured in the order of forming the trench after forming the doped region. The case where the doped region is formed between the trenches after the trenches are formed is also included in the case where the trench extends through the doped region.

[0126] The gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 disposed on the front side 21. The gate insulating film 42 is disposed to cover the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding a semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is disposed inside the gate trench at a position closer to the inner side than the gate insulating film 42. The upper surface of the gate conductive portion 44 can be located in the same XY plane as the front side 21. The gate insulating film 42 insulates the gate conductive portion 44 from the substrate 10. The gate conductive portion 44 is formed of a semiconductor such as polysilicon doped with impurities.

[0127] The gate conductive portion 44 may be configured to be longer than the base region 14 in the depth direction. The gate trench portion 40 is covered by an interlayer insulating film 38 on the front side 21. If a predetermined voltage is applied to the gate conductive portion 44, an electron-based inversion layer channel is formed on the surface layer of the interface in the base region 14 that contacts the gate trench.

[0128] The dummy trench portion 30 can have the same structure as the gate trench portion 40 in the XZ cross section. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 disposed on the front side 21. The dummy insulating film 32 is disposed to cover the inner wall of the dummy trench. The dummy insulating film 32 can be formed by oxidizing or nitriding a semiconductor on the inner wall of the dummy trench. The dummy conductive portion 34 is disposed inside the dummy trench at a position further inward than the dummy insulating film 32. The upper surface of the dummy conductive portion 34 can be located in the same XY plane as the front side 21. The dummy insulating film 32 insulates the dummy conductive portion 34 from the substrate 10. The dummy conductive portion 34 can be formed of the same material as the gate conductive portion 44.

[0129] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered by an interlayer insulating film 38 on the front side 21. It should be noted that the bottom of the dummy trench portion 30 and the gate trench portion 40 can be a downwardly convex curved surface (curved in cross-section).

[0130] Figure 1C This is a diagram illustrating the operation of the diode section 80 of the semiconductor device 100 when it is turned on. Figure 1C and Figure 2B Similarly, it means Figure 1A The a-a' section. In Figure 1C In the diagram, the black arrows represent electron currents, and the hollow arrows represent hole currents.

[0131] When the diode section 80 is turned on, electron current flows from the cathode region 82 to the base region 14, which operates as the anode layer. If the electron current reaches the base region 14, conductivity modulation occurs, and hole current flows from the anode layer. However, since the base region 14 is also provided in the transistor section 70, an electron current diffuses from the cathode region 82 to the base region 14 of the transistor section 70 and the injection suppression region 90.

[0132] The electron current diffused toward the transistor section 70 promotes hole injection from the base region 14 and the extraction region 15 of the transistor section 70. The boron concentration in the extraction region 15 is two orders of magnitude higher than that in the base region 14, thus increasing the hole density of the substrate 10. As a result, time is spent until the holes disappear when the diode section 80 is turned off, thus increasing the reverse recovery peak current and the reverse recovery loss.

[0133] As a technique for suppressing hole current, a technique for setting a lifetime control region containing a lifetime control agent is known. The lifetime control region is formed to promote the disappearance of recombination of electrons and holes generated when the diode is turned on, thereby reducing reverse recovery losses. Examples of lifetime control agents include electron beams injected into the entire semiconductor substrate, helium injected at a predetermined depth, electron beams, or protons, etc. The lifetime control region is a crystal defect formed inside the semiconductor substrate by the injection of a lifetime control agent.

[0134] If a lifetime control agent is injected, the reverse recovery characteristics of the diode section 80 are improved, but the forward voltage of the transistor section 70 deteriorates. Therefore, there are methods such as limiting the lifetime control agent to the diode section 80 for injection, but in order to suppress hole injection from the extraction region 15, the lifetime control agent extends towards the transistor section 70.

[0135] However, if a lifetime control agent is injected into the transistor section 70, damage accumulates on the gate oxide film, leading to issues such as a decrease in threshold voltage. Therefore, it is more suitable for the operation of the semiconductor device 100 not to provide a lifetime control region in the transistor section 70.

[0136] In this example, no lifetime control region is provided inside the substrate 10. Instead, the semiconductor device 100 in this example has an injection suppression region 90 provided between the transistor section 70 and the diode section 80.

[0137] In addition to the base region 14, the transistor section 70 also has an extraction region 15 with a higher doping concentration than the base region 14 to prevent latch-up. However, since the transistor section 70 has an injection suppression region 90 on the diode section 80 side, the distance between the cathode region 82 and the base region 14 and extraction region 15 of the transistor section 70 becomes longer. As a result, when the diode section 80 is turned on, the electron current from the cathode region 82 flows into the base region 14 of the injection suppression region 90 and is suppressed from flowing into the transistor section 70. As a result, the hole current from the extraction region 15 of the transistor section 70 is reduced, thus improving the reverse recovery loss.

[0138] Next, the effect of the semiconductor device 100 will be explained by comparison with the semiconductor device 1100 of the comparative example.

[0139] Figure 2A This is a diagram showing an example of the front view of the comparative example semiconductor device 1100. Figure 2B It means Figure 2A A view of section a-a' in the figure. Here, elements common to semiconductor device 100 are labeled with the same reference numerals, and descriptions are omitted.

[0140] The semiconductor device 1100 includes a transistor section 70 and a diode section 80. The mesa section 60 of the transistor section 70 has an emitter region 12 and an extractor region 15 exposed on the front side 21 of the substrate 10. In the transistor section 70, the mesa section 60 adjacent to the diode section 80 does not have an emitter region 12, but has an extractor region 15.

[0141] Semiconductor device 100 and semiconductor device 1100 are similar in that they do not have a lifetime control region. However, semiconductor device 1100 differs from semiconductor device 100 in that it does not have an implantation suppression region 90.

[0142] Figure 2C This is a diagram illustrating the operation of the diode section 80 of the semiconductor device 1100 when it is turned on. Figure 2C and Figure 2B Similarly, it means Figure 2A The a-a' section. Here, the same reference numerals are used for elements common to the semiconductor device 100, and descriptions are omitted.

[0143] In the semiconductor device 1100, the cathode region 82 is disposed adjacent to the transistor section 70. Therefore, in the semiconductor device 1100, the distance between the cathode region 82 of the diode section 80 and the base region 14 and the extraction region 15 of the transistor section 70 is closer than the distance between the cathode region 82 of the diode section 80 and the base region 14 and the extraction region 15 of the transistor section 70 in the semiconductor device 100.

[0144] Therefore, when the diode section 80 is turned on, the electron current diffused from the cathode region 82 flows into the base region 14 and the extraction region 15 of the transistor section 70, promoting hole injection.

[0145] Furthermore, in the transistor section 70 of the semiconductor device 1100, the extraction region 15, which has a higher doping concentration than the base region 14, is disposed adjacent to the diode section 80. Therefore, in the semiconductor device 1100, more holes are injected into the substrate 10 from the extraction region 15.

[0146] If the hole density increases, the time spent after the diode section 80 is turned off until the holes disappear will be longer. Therefore, in the semiconductor device 1100, the reverse recovery current, reverse recovery loss, and conduction loss are greater than in the semiconductor device 100.

[0147] In contrast, the semiconductor device 100 provides an injection suppression region 90 without the extraction region 15 on the diode section 80 side, thereby increasing the distance between the cathode region 82 and the transistor section 70, and thus suppressing hole injection. This reduces reverse recovery current, reverse recovery loss, and conduction loss.

[0148] Figure 3A This is a graph showing the relationship between the width of the injection suppression region 90 and the reverse recovery loss. Here, the width of the injection suppression region 90 refers to the alignment direction (…). Figures 1A to 2C The distance between the end of the transistor section 70 and the end of the diode section 80 in the X-axis direction.

[0149] When the width of the injection suppression region 90 is 0, it corresponds to the semiconductor device 1100 of the comparative example where the injection suppression region 90 is not provided and the transistor section 70 and the diode section 80 are adjacent.

[0150] like Figure 3A As shown in the graph, the larger the width of the injection suppression region 90, the lower the reverse recovery loss. If the width of the injection suppression region 90 is increased from 0 to 200 μm, the reverse recovery loss is reduced by approximately 36.5%.

[0151] Figure 3B This is a graph showing the relationship between the width of the injection suppression region 90 and the conduction loss. Due to the reverse recovery current of the diode section 80 with the added counter arm, the conduction loss of the transistor section 70 is related to the reverse recovery loss. (As shown...) Figure 3B As shown in the graph, if the width of the injection suppression region 90 is increased from 0 to 200 μm, the conduction loss is reduced by 30.5%.

[0152] Therefore, according to Figure 3A as well as Figure 3BIt can be seen that the larger the width of the injection suppression region 90, the lower the reverse recovery loss, and with the reduction of reverse recovery loss, the conduction loss also decreases.

[0153] Figure 4A This is a top view of the semiconductor device 100 according to Embodiment 1 of this invention. Figure 4A The image shows the positions obtained by projecting each component onto the front surface 21 of the substrate 10. It should be noted that... Figure 4A Only a portion of the components of the semiconductor device 100 are shown; some components are omitted.

[0154] The substrate 10 of the semiconductor device 100 has two sets of end edges 102 that are opposite to each other when viewed from above. Figure 4A In the middle, the X-axis and Y-axis are parallel to a certain end edge 102.

[0155] An active region 160 is provided on the substrate 10. The active region 160 is the region from which the main current flows along the depth direction from the emitter region 12 of the substrate 10 when the semiconductor device 100 is operated. Alternatively, the region surrounded by the gate channel 48 when viewed from above may also be considered as the active region 160. It should be noted that an emitter is provided above the active region 160, but... Figure 4A Omitted in .

[0156] At least one of a transistor portion 70 and a diode portion 80 is provided in the active region 160. In this example, the transistor portion 70 and the diode portion 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) in the front side 21 of the substrate 10. In other examples, only one of the transistor portion 70 and the diode portion 80 may be provided in the active region 160.

[0157] The semiconductor device 100 may have more than one pad on top of the substrate 10. As an example, Figure 4A The semiconductor device 100 shown has a gate pad G in the active region 160. When the semiconductor device 100 is mounted, the gate pad G can be connected to an external circuit via wiring such as wires.

[0158] A gate potential is applied to the gate pad G. The gate pad G is electrically connected to the gate channel 48, which surrounds the active region 160 and is electrically connected to the gate conductive portion of the gate trench portion 40 of the active region 160.

[0159] The gate channel 48 is disposed between the active region 160 and the edge termination structure 190 of the substrate 10 when viewed from above. The gate channel 48 may be formed of a metal with aluminum as the main component, such as polysilicon or aluminum-silicon alloy.

[0160] In this example, the semiconductor device 100 has an edge termination structure 190 between the active region 160 and the edge 102. The edge termination structure 190 is disposed between the gate channel 48 and the edge 102. The edge termination structure 190 mitigates the electric field concentration on the front side 21 of the substrate 10.

[0161] The edge termination structure 190 may have multiple guard rings. Each guard ring is a P-type region that contacts the front side 21 of the substrate 10. By providing multiple guard rings, the depletion layer on the upper surface side of the active region 160 can extend outwards, ensuring the withstand voltage of the semiconductor device 100. The edge termination structure 190 may also include at least one of a field plate arranged in an annular shape surrounding the gate flow channel 48 and a surface electric field reduction section.

[0162] In addition, the semiconductor device 100 may also include a temperature sensing unit (not shown) that is a PN junction diode formed of polysilicon or the like, and a current sensing unit (not shown) that performs the same operation as the transistor unit provided in the active region 160.

[0163] Figure 4B yes Figure 4A A magnified view of part A. Figure 4B Indicates from above (at) Figure 4B An example of an injection suppression region 90° is observed looking downwards (from the positive Z-axis side) to the negative Z-axis side.

[0164] The injection suppression region 90 is also disposed between the extension direction (Y-axis direction) end of the diode section 80 and the outer periphery (gate channel 48) of the active region 160. That is, when viewed from above, both the extension direction end and the alignment direction (X-axis direction) end of the diode section 80 are surrounded by the injection suppression region 90.

[0165] exist Figure 4B In the middle, the area S1 of the diode section 80 and the area S2 of the injection suppression region 90 satisfy the following equation (2).

[0166] S1≥(S1+S2) / 10···[Equation (2)]

[0167] By satisfying equation (2), the smaller the area S1 of the diode section 80, or the larger the total area (S1+S2) of the diode section 80 and the injection suppression region 90, the more effectively hole injection from the transistor section 70 is suppressed, and the lower the reverse recovery and conduction losses. However, reducing the area S1 of the diode section 80 increases the on-state voltage and the thermal resistance of the package. Therefore, to ensure the injection suppression region 90 while reducing the on-state voltage, the area S2 of the substrate 10 is increased.

[0168] On the other hand, if it is desired to increase the total area (S1+S2) of the diode section 80 and the injection suppression region 90, the area of ​​the substrate 10 is also increased by S2. Conversely, if the impact of inverter losses is minimal even when the on-state voltage increases, or if the thermal resistance of the package structure is good and the temperature rise of the diode section 80 is good, the area S1 of the diode section 80 can be reduced without increasing the area of ​​the substrate 10. Therefore, the ratio of the area S1 of the diode section 80 to the total area (S1+S2) of the diode section 80 can be 10% or more.

[0169] If equation (2) is considered, the total area of ​​the diode section 80, when viewed from above, can be more than 1.4% and less than 22% of the area of ​​the semiconductor device 100.

[0170] Figure 4C This is a graph showing the relationship between the width of the injection suppression region 90 and the reverse recovery loss. The solid line represents the reverse recovery loss when the area of ​​the diode section 80 is fixed and the area of ​​the transistor section 70 (i.e., the width of the collector region 22) is reduced in accordance with the increase in the width of the injection suppression region 90. The dashed line represents the reverse recovery loss when the area of ​​the diode section 80 (i.e., the width of the cathode region 82) is reduced in accordance with the increase in the width of the injection suppression region 90.

[0171] like Figure 4C As shown in the graph, if the width of the injection suppression region 90 is increased, the reverse recovery loss is reduced both when the area of ​​the diode section 80 is fixed and when the area of ​​the diode section 80 is reduced.

[0172] However, when the area of ​​the diode section 80 is reduced, if the width of the injection suppression region 90 is increased from 0 μm to 50 μm, the reverse recovery loss is reduced by approximately 30%. In contrast, when the area of ​​the diode section 80 is fixed, the reduction in reverse recovery loss remains at 21%. Therefore, it can be seen that reducing the area of ​​the diode section 80 significantly reduces the reverse recovery loss by 9% compared to fixing the area of ​​the diode section 80.

[0173] [Example 2]

[0174] Figure 5A This is a partial cross-sectional view of the semiconductor device 200 of Embodiment 2 of this invention. Here, elements common to the semiconductor device 100 are labeled with the same reference numerals, and descriptions are omitted.

[0175] In the implantation suppression region 90 of the semiconductor device 200, a base region 94 of a second conductivity type is provided instead of the base region 14. The doping concentration of the base region 94 can be 1×10⁻⁶. 16 cm -3Above and 5×10 19 cm -3 the following.

[0176] It should be noted that the doping concentration of base region 14 can be 1×10⁻⁶. 16 cm -3 Above and 1×10 18 cm -3 The doping concentration of extraction region 15 can be 5 × 10⁻⁶. 18 cm -3 Above and 5×10 20 cm -3 the following.

[0177] By making the doping concentration of base region 94 lower than that of extraction region 15, the effect of suppressing hole injection from transistor section 70 can be improved. If the concentration of base region 14 is lower than that of base region 94, the hole injection suppression effect can be further improved.

[0178] Furthermore, the processing method for distinguishing the doping concentrations of base region 14 and base region 94 is as follows. When the doping concentration of base region 94 is higher than that of base region 14, both base regions 14 and 94 are doped, and then a mask is used in base region 14, leaving base region 94 untouched for doping. Conversely, when the doping concentration of base region 94 is lower than that of base region 14, different masks are used to dope base regions 14 and 94.

[0179] Furthermore, since the doping concentrations of base region 94 and base region 14 are equal, the same mask can be used for processing. Therefore, no additional mask is required, which improves processability and reduces chip cost by reducing the mask.

[0180] Figure 5B This is a graph showing the relationship between the doping concentration of the base region 94 in the implantation suppression region 90 and the reverse recovery loss. Here, as an example, boron is implanted as an impurity.

[0181] exist Figure 5B In this process, seven patterns are set within the width range of 10 μm to 250 μm for the implantation suppression region 90. Within each pattern, the boron doping concentration of the base region 94 is adjusted from 10 μm to 10 μm. 19 cm -3 The order of magnitude decreased to 10 16 cm -3 Observe the changes in reverse recovery loss on the order of magnitude.

[0182] First, the doping concentration in base region 94 is 10 times that of the same reference concentration as in extraction region 15. 19 cm -3At the order of magnitude, regardless of the width of the implantation suppression region 90, the improvement in reverse recovery loss is 1.2%, showing no significant difference. However, if the doping concentration of the base region 94 is reduced from the baseline concentration, the dependence on the width of the implantation suppression region 90 increases, and the reverse recovery loss is significantly reduced.

[0183] Even if the doping concentration of the base region 94 is reduced to 10 16 cm -3 On the order of magnitude, in a pattern with a width of 10 μm in the implantation suppression region 90, the reverse recovery loss was also reduced by approximately 5.9%, which was not significantly different from the reverse recovery loss at the baseline concentration. In contrast, in a pattern with a width of 250 μm in the implantation suppression region 90, the reverse recovery loss was significantly reduced to approximately 46%.

[0184] Figure 5C This is a graph showing the relationship between the doping concentration of the base region 94 in the implantation suppression region 90 and the conduction loss. The width of the implantation suppression region 90 is set to be equal to... Figure 5B Since they are the same, the explanation is omitted.

[0185] according to Figure 5C The curves also show that, while reducing the doping concentration of the base region 94, a larger width of the implantation suppression region 90 results in a more effective reduction in conduction loss. Furthermore, 10 17 cm -3 The concentration is on the same order of magnitude as the doping concentration in base region 14.

[0186] [Example 3]

[0187] Figure 6A This is a partial top view of the semiconductor device 300 according to Embodiment 3 of this invention. Here, elements common to the semiconductor device 100 are labeled with the same reference numerals, and descriptions are omitted.

[0188] Like semiconductor devices 100 and 200, the implantation suppression region 90 of semiconductor device 300 has a dummy trench portion 30 but lacks a gate trench portion 40. However, unlike semiconductor devices 100 and 200, the implantation suppression region 90 of semiconductor device 300 has an emitter region 12 and an extractor region 15 exposed on the front side 21. However, the ratio of emitter region 12 to extractor region 15 in the implantation suppression region 90 is lower than that in the transistor portion 70.

[0189] like Figure 6A As shown, in the injection suppression region 90, the emitter region 12 and the extraction region 15 are fewer than in the transistor section 70. Furthermore, in the injection suppression region 90, a base region 14 is provided in the portion where the emitter region 12 and the extraction region 15 are not provided.

[0190] That is, in the transistor section 70, the emitter region 12 and the extractor region 15 extend along the extension direction (in Figure 6A The regions are arranged alternately in the Y-axis direction, but in the injection suppression region 90, the extraction region 15 is arranged around the emission region 12, and the base region 14 is arranged around it.

[0191] Therefore, in semiconductor device 300, by reducing the ratio of the extraction region 15 in the injection suppression region 90, hole injection can be suppressed, and losses can be reduced. Furthermore, since the injection suppression region 90 of semiconductor devices 100 and 200 does not have an emitter region 12, no electron current flows through the emitter region 12. However, in semiconductor device 300, since the injection suppression region 90 has an emitter region 12, electron current flows through it. Therefore, compared to semiconductor devices 100 and 200, the on-state voltage can be reduced.

[0192] Figure 6B yes Figure 6A A magnified view of part B in the diagram. Here, the configuration of the emission region 12 and the extraction region 15 in the injection suppression region 90 is mainly explained.

[0193] exist Figure 6B In this design, the mesa portion of the transistor section 70 adjacent to the injection suppression region 90 is designated as the first mesa portion 60a, the mesa portion of the injection suppression region 90 adjacent to the transistor section 70 is designated as the second mesa portion 60b, the mesa portion adjacent to the second mesa portion 60b is designated as the third mesa portion 60c, and the mesa portion adjacent to the diode section 80 is designated as the fourth mesa portion 60d.

[0194] It should be noted that the injection inhibition zone 90 in this example has three facets, namely the second facet 60b to the fourth facet 60d, but the number of facets is not limited to this.

[0195] In the second to fourth facets 60b, either the emission area 12 or the extraction area 15 is arranged adjacent to the emission area 12 located on the facet adjacent to the negative side of the X-axis.

[0196] In the first facepiece 60a, six emission zones 12 and six extraction zones 15 are alternately arranged in the Y-axis direction. Three emission zones 12 of the six emission zones 12 of the first facepiece 60a are adjacent to three emission zones 12 arranged in the second facepiece 60b, and the remaining three emission zones 12 are adjacent to three extraction zones 15 arranged in the second facepiece 60b.

[0197] The three emission zones 12 of the second faceplate 60b are adjacent to the three emission zones 12 of the third faceplate 60c. Alternatively, an extraction zone 15 can be configured on the third faceplate 60c to replace a portion of the configured three emission zones 12.

[0198] In the second faceplate 60b and the third faceplate 60c, the emitter region 12 is adjacent to the extractor region 15 in the Y-axis direction. That is, the positive and negative Y-axis sides of the emitter region 12 are surrounded by the extractor region 15. As a result, holes generated in conductivity modulation can be extracted to the extractor region 15, thereby improving latch-up tolerance.

[0199] In the second face 60b and the third face 60c, a base region 14 is provided in the area where the emission region 12 and the extraction region 15 are not configured.

[0200] The fourth faceplate 60d does not have a transmission region 12. The fourth faceplate 60d has an extraction region 15, which is adjacent to the transmission region 12 of the third faceplate 60c located on the negative X-axis side. In the fourth faceplate 60d, a base region 14 is provided in the area where the extraction region 15 is not provided.

[0201] Alternatively, if the third face 60c, which is adjacent to the fourth face 60d on the negative X-axis, does not have a transmission region 12, then only the base region 14 may be configured on the fourth face 60d.

[0202] As described above, the proportion of the extraction region 15 in each facet of the injection suppression region 90 is less than the proportion of the extraction region 15 in the facet adjacent to the negative side of the X-axis. That is, the proportion of the extraction region 15 in the second facet 60b is less than the proportion of the extraction region 15 in the first facet 60a. The proportion of the extraction region 15 in the third facet 60c is less than the proportion of the extraction region 15 in the second facet 60b. The proportion of the extraction region 15 in the fourth facet 60d is less than the proportion of the extraction region 15 in the third facet 60c, and greater than the proportion of the extraction region 15 in the facet 61 of the diode section 80 adjacent to the positive side of the X-axis.

[0203] By increasing the width of the injection suppression region 90, the number of third face plates 60c can be increased. By increasing the number of third face plates 60c, the proportion of the extraction region 15 in the injection suppression region 90 can be reduced, thereby reducing reverse recovery loss and conduction loss.

[0204] Furthermore, since the emitter region 12 is provided on the third face 60c, the area of ​​the region where the transistor part operates is increased, which can reduce the conduction voltage.

[0205] In addition, Figure 6B In the injection suppression region 90, the extraction region 15 is configured to cover the entire mesa in the X-axis direction, but it can also be about half the length of the mesa in the X-axis direction. In the injection suppression region 90, the length of the extraction region 15 in the X-axis direction can be 0.3 μm or more.

[0206] Furthermore, in the injection suppression region 90, the length of the extraction region 15 in the Y-axis direction is less than or equal to the length of the extraction region 15 of the transistor section 70 in the Y-axis direction. In the injection suppression region 90, the length of the extraction region 15 in the Y-axis direction can be 0.5 μm or more. This allows for improved latch-up tolerance while suppressing hole injection.

[0207] It should be noted that, Figure 6B The shaded area of ​​the contact hole 54 shown is provided with a plug area 17.

[0208] [Example 4]

[0209] Figure 7A This is a partial top view of the semiconductor device 400 of Embodiment 4 of this implementation. Figure 7B It means Figure 7A A view of section a-a' in the figure. Here, elements common to semiconductor device 100 are labeled with the same reference numerals, and descriptions are omitted.

[0210] In this example, a plurality of gate trench portions 40 are provided in the transistor portion 70 along the arrangement direction, and a plurality of dummy trench portions 30 are provided in the diode portion 80 along the arrangement direction.

[0211] In this example, the transistor section 70 is a full-gate structure without the dummy trench section 30. The gate trench sections 40 are connected to the adjacent gate trench sections 40 via the front end section 41.

[0212] Figure 7C This diagram illustrates the operation of the diode section 80 of the semiconductor device 400 when it is turned on. Figure 7C and Figure 7B Similarly, it means Figure 7A The a-a' section. Here, the same reference numerals are used for elements common to the semiconductor device 100, and descriptions are omitted.

[0213] according to Figure 7C It can be seen that by providing the injection suppression region 90, hole injection from the transistor section 70 is suppressed, and reverse recovery loss is improved. Therefore, in the all-gate semiconductor device 400, the same effect as that of the semiconductor devices 100-300 in which the transistor section 70 is provided with the dummy trench section 30 can be obtained.

[0214] [Example 5]

[0215] Figure 8A This is a partial cross-sectional view of the semiconductor device 500 of Embodiment 5 of this invention. Figure 8A It indicates that what will be said later. Figure 8B and Figure 8CThe figure shows a section a-a'. Section a-a' is the XZ plane that includes the gate trench portion 40 and the dummy trench portion 30 and passes through the extraction region 15 and the base region 14. Here, the same reference numerals are used for elements common to the semiconductor device 100, and descriptions are omitted.

[0216] In this example, the transistor section 70 has a gate trench section 40 and a dummy trench section 30 disposed along the X-axis direction. It should be noted that... Figure 8A In this paper, the gate insulating film 42 and the dummy insulating film 32 are omitted.

[0217] In this example, the implantation suppression region 90 differs from that in semiconductor devices 100-400, having a gate trench portion 40 and a dummy trench portion 30 disposed along the X-axis direction. However, the dummy ratio in the implantation suppression region 90 is higher than the dummy ratio in the transistor portion 70. Here, the dummy ratio refers to the ratio of the number of dummy trench portions 30 to the total number of gate trench portions 40 and dummy trench portions 30.

[0218] exist Figure 8A In the example shown, in the transistor section 70, one gate trench section 40 and two dummy trench sections 30 are alternately arranged in the X-axis direction. The dummy ratio of this arrangement is approximately 67%.

[0219] Furthermore, in the injection suppression region 90, one gate trench portion 40 and three dummy trench portions 30 are alternately arranged in the X-axis direction. The dummy ratio of this arrangement is 75%.

[0220] On the other hand, the diode section 80 has a dummy trench section 30 disposed along the X-axis direction, but does not have a gate trench section 40. Therefore, the dummy ratio of the diode section 80 is 100%.

[0221] Therefore, in the semiconductor device 500, the dummy ratio of the diode section 80 is higher than that of the injection suppression region 90, and the dummy ratio of the injection suppression region 90 is higher than that of the transistor section 70.

[0222] It should be noted that a dummy trench portion 30 is disposed at the boundary between the transistor portion 70 and the injection suppression region 90, but this is not a limitation. A gate trench portion 40 may also be disposed at the boundary between the transistor portion 70 and the injection suppression region 90. A dummy trench portion 30 may also be disposed at the boundary between the injection suppression region 90 and the diode portion 80.

[0223] Furthermore, in the semiconductor device 500, a plug is disposed in a contact hole that contacts the extraction region 15 or the base region 14. Additionally, a P++ type plug region 17 with a higher doping concentration than the extraction region 15 is formed below the contact hole of the plug.

[0224] Figure 8B This is a partial top view of semiconductor device 500. Figure 8B The transistor section 70 is shown as the center. In this example, the transistor section 70 has a gate trench section 40 and a dummy trench section 30 disposed along the X-axis direction.

[0225] exist Figure 8B In the example shown, in the transistor section 70, two dummy trench sections 30 are arranged between the straight sections 39 of the two gate trench sections 40. The front end section 41 connects the ends of the two straight sections 39 in the Y-axis direction to the gate channel 48.

[0226] In this example, the dummy ratio of the transistor section 70 is 0% or more and 75% or less. In the transistor section 70, the ratio of the number of gate trench sections 40 to the number of dummy trench sections 30 can be 1:0 (so-called full gate structure), 1:1 (a structure in which one gate trench section 40 and one dummy trench section 30 are alternately arranged in the X-axis direction), 1:2 (a structure in which one gate trench section 40 and two dummy trench sections 30 are alternately arranged in the X-axis direction), or 1:3 (a structure in which one gate trench section 40 and three dummy trench sections 30 are alternately arranged in the X-axis direction).

[0227] Figure 8C This is a partial top view of semiconductor device 500. Figure 8C The injection suppression region 90 is shown as the center. In this example, the injection suppression region 90 has a gate trench portion 40 and a dummy trench portion 30 disposed along the X-axis direction.

[0228] exist Figure 8C In the example shown, in the injection suppression region 90, three dummy trench portions 30 are arranged between the straight portions 39 of the two gate trench portions 30. The front end portion 41 connects the ends of the two straight portions 39 in the Y-axis direction to the gate channel 48.

[0229] In the implantation suppression region 90, the emitter region 12 is disposed on the mesa portion 60 adjacent to the gate trench portion 40. Furthermore, in the implantation suppression region 90, the emitter region 12 and the extraction region 15 are alternately disposed in the Y-axis direction.

[0230] In the injection suppression region 90, a base region 14 is provided in the portion where the emission region 12 and the extraction region 15 are not provided. That is, in the injection suppression region 90, the base region 14 is provided in the stage 60 adjacent to the dummy trench portion 30 instead of the emission region 12 and the extraction region 15.

[0231] The dummy ratio of the injection suppression region 90 is higher than that of the transistor section 70, and the emitter region 12 and the extraction region 15 are disposed on the mesa section 60 adjacent to the gate trench section 40. Therefore, the ratio of the emitter region 12 to the extraction region 15 in the injection suppression region 90 is lower than that in the transistor section 70. As a result, hole injection is suppressed, and reverse recovery loss is improved.

[0232] In other words, by reducing the extraction region 15 in the implantation suppression region 90, as illustrated in Example 2, the same effect as reducing the doping concentration of the base region 94 of the implantation suppression region 90 can be obtained.

[0233] On the other hand, since the injection suppression region 90 has the emitter region 12, an electron current flows through it. As a result, the injection suppression region 90 locally performs transistor operation, which can suppress the variation of the turn-on voltage.

[0234] Furthermore, the positive and negative Y-axis sides of the emitter region 12 are surrounded by the extraction region 15. As a result, since holes generated during conductivity modulation can be extracted to the extraction region 15, latch-up tolerance can be improved.

[0235] In this example, the dummy ratio of the injection suppression region 90 is 75% or more and 87.5% or less. In the injection suppression region 90, the ratio of the number of gate trench portions 40 to the number of dummy trench portions 30 can be 1:3 (a structure in which one gate trench portion 40 and three dummy trench portions 30 are alternately arranged in the X-axis direction), 1:4 (a structure in which one gate trench portion 40 and four dummy trench portions 30 are alternately arranged in the X-axis direction), 1:5 (a structure in which one gate trench portion 40 and five dummy trench portions 30 are alternately arranged in the X-axis direction), 1:6 (a structure in which one gate trench portion 40 and six dummy trench portions 30 are alternately arranged in the X-axis direction), or 1:7 (a structure in which one gate trench portion 40 and seven dummy trench portions 30 are alternately arranged in the X-axis direction).

[0236] Figure 8D This is a partial top view of semiconductor device 500. Figure 8D and Figure 8C Similarly, the injection suppression region 90 is used as the center for representation. Figure 8D A variation of the configuration of the gate trench portion 40 and the dummy trench portion 30 in the injection suppression region 90 is shown. For comparison with... Figure 8C The same structure is used, so the explanation is omitted.

[0237] exist Figure 8DIn the example shown, in the injection suppression region 90, seven dummy trench portions 30 are arranged between the straight portions 39 of the two gate trench portions 30. The front end portion 41 connects the ends of the two straight portions 39 in the Y-axis direction to the gate channel 48.

[0238] That is, in Figure 8D In the example shown, in the injection suppression region 90, one gate trench portion 40 and seven dummy trench portions 30 are alternately arranged in the X-axis direction. The dummy ratio of this arrangement is 87.5%.

[0239] thus, Figure 8C The configuration shown is such that the dummy ratio of the injection suppression region 90 is minimized (a structure in which one gate trench portion 40 and three dummy trench portions 30 are alternately arranged in the X-axis direction). Figure 8D This indicates that the dummy ratio of the injection suppression region 90 is maximized (a structure in which one gate trench portion 40 and seven dummy trench portions 30 are alternately arranged in the X-axis direction).

[0240] In the semiconductor device 500, the dummy ratio of the injection suppression region 90 is made higher than that of the transistor section 70, and is set to... Figures 8C to 8D The range shown allows for localized transistor operation within the injection suppression region 90, thereby suppressing variations in the on-state voltage and inhibiting hole injection, thus improving reverse recovery losses.

[0241] The present invention has been described above using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. As can be seen from the claims, such modifications or improvements can also be included within the technical scope of the present invention.

[0242] The execution order of actions, processes, steps, and stages in the apparatus, system, program, and method shown in the claims, specification, and drawings can be implemented in any order, unless specifically stated as "earlier than" or "before," and unless the results of previous processes are used in subsequent processes. Even if the flow of actions in the claims, specification, and drawings is described using terms such as "firstly" or "next" for convenience, it does not mean that they must be implemented in this order.

Claims

1. A semiconductor device, characterized in that, It includes a semiconductor substrate, which has a transistor section and a diode section. At the diode-side end of the transistor section when viewed from above on the semiconductor substrate, the transistor section has an injection suppression region that suppresses the injection of second-conductivity type charge carriers. The semiconductor device further includes a plurality of trench portions extending along the extending directions of the transistor portion and the diode portion, and arranged along an arrangement direction. Both the transistor portion and the diode portion have a base region of a second conductivity type on the front side of the semiconductor substrate. The transistor portion further comprises an emitter region of a first conductivity type and an extractor region of a second conductivity type with a doping concentration higher than that of the base region on the front side of the semiconductor substrate. In the injection suppression region, in the arrangement direction of the plurality of trenches, the emission region and the extraction region are not provided from one trench to the next adjacent trench.

2. The semiconductor device as claimed in claim 1, characterized in that, When viewed from above, the width of the injection suppression region in the arrangement direction of the transistor portion and the diode portion is 20 μm or more and 900 μm or less.

3. The semiconductor device as claimed in claim 1, characterized in that, When viewed from above, the injection suppression region is also disposed between the end of the diode portion in the extending direction and the outer periphery of the active region.

4. The semiconductor device as claimed in claim 2, characterized in that, When viewed from above, the injection suppression region is also disposed between the end of the diode portion in the extending direction and the outer periphery of the active region.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, When viewed from above, the area of ​​the diode portion is more than 10% of the combined area of ​​the diode portion and the injection suppression region.

6. The semiconductor device according to any one of claims 1 to 4, characterized in that, When viewed from above, the total area of ​​the diode portion is more than 1.4% and less than 22% of the area of ​​the semiconductor device.

7. The semiconductor device as claimed in claim 5, characterized in that, When viewed from above, the total area of ​​the diode portion is more than 1.4% and less than 22% of the area of ​​the semiconductor device.

8. The semiconductor device according to any one of claims 1 to 4, characterized in that, The doping concentration of the base region in the implantation suppression region is lower than or equal to the doping concentration of the base region in the diode portion.

9. The semiconductor device as claimed in claim 5, characterized in that, The doping concentration of the base region in the implantation suppression region is lower than or equal to the doping concentration of the base region in the diode portion.

10. The semiconductor device as claimed in claim 6, characterized in that, The doping concentration of the base region in the implantation suppression region is lower than or equal to the doping concentration of the base region in the diode portion.

11. The semiconductor device as claimed in claim 7, characterized in that, The doping concentration of the base region in the implantation suppression region is lower than or equal to the doping concentration of the base region in the diode portion.

12. The semiconductor device as claimed in claim 8, characterized in that, The doping concentration of the base region in the implantation suppression region is 1×10⁻⁶. 16 cm －3 Above and 5×10 19 cm －3 the following.

13. The semiconductor device as claimed in claim 9, characterized in that, The doping concentration of the base region in the implantation suppression region is 1×10⁻⁶. 16 cm －3 Above and 5×10 19 cm －3 the following.

14. The semiconductor device as claimed in claim 10, characterized in that, The doping concentration of the base region in the implantation suppression region is 1×10⁻⁶. 16 cm －3 Above and 5×10 19 cm －3 the following.

15. The semiconductor device as claimed in claim 11, characterized in that, The doping concentration of the base region in the implantation suppression region is 1×10⁻⁶. 16 cm －3 Above and 5×10 19 cm －3 the following.

16. The semiconductor device according to any one of claims 1 to 4, characterized in that, The doping concentration of the base region of the diode is 1×10⁻⁶. 16 cm －3 Above and 1×10 18 cm －3 the following.

17. The semiconductor device according to any one of claims 1 to 4, characterized in that, The doping concentration of the extraction region is 5 × 10⁻⁶. 18 cm －3 Above and 5×10 20 cm －3 the following.

18. A semiconductor device, characterized in that, It includes a semiconductor substrate, which has a transistor section and a diode section. At the diode-side end of the transistor section when viewed from above on the semiconductor substrate, the transistor section has an injection suppression region that suppresses the injection of second-conductivity type charge carriers. Both the transistor portion and the diode portion have a base region of a second conductivity type on the front side of the semiconductor substrate. The transistor portion and the injection suppression region further have an emitter region of a first conductivity type and an extractor region of a second conductivity type with a doping concentration higher than that of the base region on the front side of the semiconductor substrate. When viewed from above, the ratio of the area of ​​the emitter region and the extractor region in the implantation suppression region to the area of ​​the implantation suppression region is lower than the ratio of the area of ​​the emitter region and the extractor region in the transistor portion to the area of ​​the transistor portion. The transistor portion and the injection suppression region have multiple mesa portions, which extend between multiple trench portions along the extending direction of the transistor portion and the diode portion. The multiple trench portions extend along the extending direction and are arranged along the arrangement direction of the transistor portion and the diode portion. On the mesa section of the injection suppression region closest to the diode portion, the extraction region is positioned corresponding to the emitter region on the adjacent mesa section on the transistor portion side.

19. The semiconductor device as claimed in claim 18, characterized in that, On the mesa portion of the injection suppression region closest to the diode portion, the extraction region and the base region are alternately arranged in the extending direction.

20. The semiconductor device as claimed in claim 18, characterized in that, In the mesa section of the injection suppression region, either the emitter region or the extractor region is configured to be adjacent to the emitter region disposed on the mesa section adjacent to the transistor portion side.

21. The semiconductor device as claimed in claim 19, characterized in that, In the mesa section of the injection suppression region, either the emitter region or the extractor region is configured to be adjacent to the emitter region disposed on the mesa section adjacent to the transistor portion side.

22. The semiconductor device as claimed in claim 20, characterized in that, The plurality of trench portions include gate trench portions and dummy trench portions. The injection suppression region has a dummy trench portion but no gate trench portion.

23. The semiconductor device as claimed in claim 21, characterized in that, The plurality of trench portions include gate trench portions and dummy trench portions. The injection suppression region has a dummy trench portion but no gate trench portion.

24. The semiconductor device as claimed in claim 20, characterized in that, The plurality of trench portions include gate trench portions and dummy trench portions. The dummy ratio in the injection suppression region is higher than the dummy ratio in the transistor portion excluding the injection suppression region. The dummy ratio is the ratio of the number of dummy trench portions to the total number of gate trench portions and dummy trench portions.

25. The semiconductor device as claimed in claim 21, characterized in that, The plurality of trench portions include gate trench portions and dummy trench portions. The dummy ratio in the injection suppression region is higher than the dummy ratio in the transistor portion excluding the injection suppression region. The dummy ratio is the ratio of the number of dummy trench portions to the total number of gate trench portions and dummy trench portions.

26. The semiconductor device as claimed in claim 24, characterized in that, The emitter region of the injection suppression region is disposed on a mesa adjacent to the gate trench portion.

27. The semiconductor device as claimed in claim 25, characterized in that, The emitter region of the injection suppression region is disposed on a mesa adjacent to the gate trench portion.

28. The semiconductor device as claimed in claim 24, characterized in that, The dummy ratio in the injection suppression region is above 75% and below 87.5%.

29. The semiconductor device as claimed in claim 25, characterized in that, The dummy ratio in the injection suppression region is above 75% and below 87.5%.

30. The semiconductor device as claimed in claim 26, characterized in that, The dummy ratio in the injection suppression region is above 75% and below 87.5%.

31. The semiconductor device as claimed in claim 27, characterized in that, The dummy ratio in the injection suppression region is above 75% and below 87.5%.

32. The semiconductor device as claimed in claim 28, characterized in that, The dummy ratio in the transistor section, excluding the injection suppression region, is 0% or more and 75% or less.

33. The semiconductor device as claimed in claim 29, characterized in that, The dummy ratio in the transistor section, excluding the injection suppression region, is 0% or more and 75% or less.

34. The semiconductor device as claimed in claim 30, characterized in that, The dummy ratio in the transistor section, excluding the injection suppression region, is 0% or more and 75% or less.

35. The semiconductor device as claimed in claim 31, characterized in that, The dummy ratio in the transistor section, excluding the injection suppression region, is 0% or more and 75% or less.

36. The semiconductor device according to any one of claims 20 to 35, characterized in that, The emission region of the injection suppression region is adjacent to the extraction region in the extension direction.

37. The semiconductor device according to any one of claims 20 to 35, characterized in that, The emitter region is not configured on the mesa adjacent to the diode portion in the injection suppression region.

38. The semiconductor device as claimed in claim 36, characterized in that, The emitter region is not configured on the mesa adjacent to the diode portion in the injection suppression region.

39. The semiconductor device according to any one of claims 18 to 35, characterized in that, When viewed from above, the length of the extracted region is 0.5 μm or more in the extending direction of the transistor portion and the diode portion.

40. The semiconductor device according to any one of claims 18 to 35, characterized in that, When viewed from above, the length of the extracted region is 0.3 μm or more in the arrangement direction of the transistor portion and the diode portion of the semiconductor substrate.

41. The semiconductor device according to any one of claims 18 to 35, characterized in that, In the injection suppression region, the base region is configured in the portion where the emission region and the extraction region are not configured.

42. The semiconductor device according to any one of claims 1 to 4, 18 to 35, characterized in that, The semiconductor substrate also has an accumulation region of a first conductivity type inside.

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