Electronic device and operating method thereof, solid state disk controller, memory device

Abstract

An electronic device and an operating method thereof, a solid state disk controller, and a memory device are provided. The electronic device includes a cache memory including a memory space storing a first cache group including a plurality of sector data and a plurality of dirty bits, each of the plurality of dirty bits indicating whether a corresponding sector data of the plurality of sector data is modified, a memory controller connected to a plurality of data lines and a data mask line to receive the plurality of sector data and the plurality of dirty bits from the cache memory, set a logic level of a data mask signal based on a logic level of each of the plurality of dirty bits, and output the plurality of sector data through the plurality of data lines and the data mask signal through the data mask line, and a memory device connected to the plurality of data lines and the data mask line to receive the plurality of sector data through the plurality of data lines and the data mask signal through the data mask line.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0110638, filed on August 31, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to semiconductor memory, and more specifically, to electronic devices, systems-on-a-chip, and methods of operating electronic devices. Background Technology

[0004] Semiconductor memories are classified as either volatile memories (e.g., static random access memory (SRAM) or dynamic random access memory (DRAM)) that lose stored data when power is off, or non-volatile memories (e.g., flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or ferroelectric RAM (FRAM)) that retain stored data even when power is off.

[0005] Cache memory can support higher access speeds than main memory. Because a portion of the data stored in main memory is stored in cache memory, the speed of access based on processor requests can be improved. Summary of the Invention

[0006] Embodiments of this disclosure provide an electronic device, a system-on-a-chip, and a method of operating the electronic device that minimizes power consumption with improved stability.

[0007] According to an embodiment of the present invention, an electronic device includes: a cache memory including a memory space for storing a first cache group including a plurality of sector data and a plurality of dirty bits, each of the plurality of dirty bits indicating whether a corresponding sector data in the plurality of sector data has been modified; a memory controller connected to a plurality of data lines and a data shield line, the memory controller being configured to receive the plurality of sector data and the plurality of dirty bits from the cache memory, set a logic level of a data shield signal based on the logic level of each of the plurality of dirty bits, and output the plurality of sector data through the plurality of data lines and output the data shield signal through the data shield line; and a storage device connected to the plurality of data lines and the data shield line, the storage device being configured to receive the plurality of sector data through the plurality of data lines and receive the data shield signal through the data shield line.

[0008] According to an embodiment of the present invention, an operating method of an electronic device is provided. The electronic device includes a cache memory, a storage device, and a memory controller. The cache memory includes a memory space for storing a first cache group comprising a plurality of sector data and a plurality of dirty bits. Each dirty bit indicates whether corresponding sector data in the plurality of sector data stored in the cache memory has been modified. The memory controller is located between the cache memory and the storage device. The method includes: the memory controller setting a logic level of a data mask signal based on the logic level of each dirty bit; the memory controller issuing a first mask write (MWR) command to the storage device via a command / address (CA) line connected to the storage device; and the memory controller sending the plurality of sector data stored in the cache memory to the storage device via a plurality of data lines connected to the storage device, and sending the data mask signal to the storage device via the data mask lines connected to the storage device.

[0009] According to an embodiment of the present invention, a solid-state drive (SSD) controller includes: a cache memory, the cache memory including a storage device and a cache memory interface circuit, the storage device being used to store a first cache group, the first cache group including first sector data and second sector data, and a first dirty bit and a second dirty bit respectively associated with the first sector data and the second sector data; the cache memory interface circuit being used to flush the first sector data and / or the second sector data to an external storage device based on the logic level of each of the first dirty bit and the second dirty bit. The cache memory interface circuit includes a data masking control circuit, the data masking control circuit generating a data masking signal and outputting the data masking signal to the external storage device. The data masking control circuit sets the logic level of the data masking signal based on the logic level of each of the first dirty bit and the second dirty bit. The logic level of each of the first dirty bit and the second dirty bit represents a state where the corresponding sector data in the first sector data and the second sector data is in a dirty state and a clean state.

[0010] According to an embodiment of the present invention, a storage device includes: a memory cell array comprising a plurality of memory cells; an input / output circuit for receiving a plurality of sector data via a plurality of data lines; and control logic circuitry for: receiving a first mask write (MWR) command via a command / address (CA) line; receiving a data mask signal via a data mask line; and, in response to the data mask signal, selectively storing the plurality of sector data in the memory cell array. The data mask signal is generated by an external memory controller based on a plurality of dirty bits respectively associated with the plurality of sector data.

[0011] According to an embodiment of the present invention, a cache memory system includes a cache memory and a processor. The cache memory includes memory space configured to store a first cache set comprising a plurality of sectors of data and a plurality of dirty bits, each of the plurality of dirty bits indicating whether a corresponding sector of the plurality of sectors of data has been modified. The processor is configured to perform a flush operation on the first cache set to output the plurality of sectors of data and the plurality of dirty bits to an external memory controller. The size of the first cache set is the same as the size of a cache line, which is the smallest access unit of data in the flush operation.

[0012] According to an embodiment of the present invention, a memory controller includes a data masking control circuit. The data masking control circuit receives multiple sector data and multiple dirty bits from an external cache memory, each dirty bit indicating whether the corresponding sector data in the multiple sector data has been modified. Based on the multiple dirty bits, a data masking signal is generated; the multiple sector data is output to an external storage device via multiple data lines; and the data masking signal is output to the external storage device via data masking lines. Attached Figure Description

[0013] The above and other objects and features of this disclosure will become apparent from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0014] Figure 1 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0015] Figure 2 It is used to describe Figure 1 A diagram illustrating the cache structure of an electronic device.

[0016] Figures 3A to 3C It is a diagram illustrating the operation of an electronic device.

[0017] Figure 4This is a diagram used to describe a cache group according to embodiments of the present disclosure.

[0018] Figures 5A to 5C It is shown Figure 1 A diagram illustrating the operation of an electronic device.

[0019] Figure 6 It is shown Figure 1 A flowchart of the operation of the memory controller.

[0020] Figure 7 It is shown in detail Figure 6 The timing diagram for the operation of S400.

[0021] Figure 8 It is shown in detail Figure 1 A block diagram of the storage device.

[0022] Figure 9A and Figure 9B It is used to describe Figure 1 Timing diagram of the operation of the storage device.

[0023] Figures 10A to 10C It is shown Figure 1 A flowchart of the operation of an electronic device.

[0024] Figure 11 This is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0025] Figure 12 It is shown Figure 11 Block diagram of the memory controller.

[0026] Figure 13 This is a block diagram illustrating an SSD system according to the present disclosure. Detailed Implementation

[0027] Hereinafter, embodiments of the present disclosure will be described in detail and clearly to the extent that those skilled in the art can readily implement the present disclosure.

[0028] Figure 1 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure. (Refer to...) Figure 1 The electronic device 1000 may include a system-on-a-chip (SoC) 1100 and a storage device 1200. In embodiments, the electronic device 1000 may be one of a variety of computing devices such as a desktop computer, laptop computer, workstation, server, smartphone, tablet computer, digital camera, and black box.

[0029] SoC 1100 can control the overall operation of electronic device 1000. For example, SoC 1100 can be an application processor (AP) that controls the overall operation of electronic device 1000. SoC 1100 can run an operating system, program, or application executable on electronic device 1000.

[0030] SoC 1100 can store data in storage device 1200, or can read data stored in storage device 1200. SoC 1100 may include processor 1110, cache memory device 1120 (i.e., cache memory), and memory controller 1130. Processor 1110 can perform various operations of electronic device 1000 and can process data.

[0031] In response to a signal received from processor 1110, cache device 1120 may store data or provide the data stored therein to processor 1110. Cache device 1120 may support higher access speeds than storage device 1200. For example, since a portion of the data stored in storage device 1200 is stored in cache device 1120, the speed of access according to requests from processor 1110 can be improved. In embodiments, cache device 1120 may be a static random access memory (SRAM) device, but this disclosure is not limited thereto.

[0032] In this embodiment, cache device 1120 may generate dirty information (DI). Cache device 1120 may send the dirty information (DI) and data to memory controller 1130. The dirty information (DI) may indicate whether cached data loaded from memory device 1200 has been updated.

[0033] The memory controller 1130 can control the memory device 1200. For example, the memory controller 1130 can send address ADDR, command CMD, control signal CTRL and data mask signal DM to the memory device 1200 to control the memory device 1200, and can exchange data "DATA" with the memory device 1200 via data line DQ.

[0034] The storage device 1200 can operate under the control of the memory controller 1130. For example, in response to a signal received from the memory controller 1130, the storage device 1200 can store data "DATA" or can provide the stored data "DATA" to the memory controller 1130. In embodiments, the storage device 1200 may be a dynamic random access memory (DRAM) device, but this disclosure is not limited thereto.

[0035] In embodiments, the memory controller 1130 and the storage device 1200 may communicate with each other via a given interface. The given interface may be a Low Power Double Data Rate (LPDDR) interface, but this disclosure is not limited thereto. For example, the given interface may include at least one of the following interfaces: DDR interface, Universal Serial Bus (USB) interface, Multimedia Card (MMC) interface, Peripheral Component Interconnect (PCI) interface, Fast PCI (PCIe) interface, Advanced Technology Attachment (ATA) interface, Serial ATA (SATA) interface, Parallel ATA (PATA) interface, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Device (IDE) interface, Mobile Industrial Processor Interface (MIPI), and High Speed ​​Non-Volatile Memory (NVMe) interface.

[0036] In one embodiment, the memory controller 1130 may include a data masking control circuit 1131. The data masking control circuit 1131 may receive dirty information DI from the cache device 1120. Based on the received dirty information DI, the data masking control circuit 1131 may output a data masking signal DM via a data masking line.

[0037] When processor 1110 sends a write request, the data to be written can be temporarily stored in cache device 1120 without being immediately sent to memory device 1200. After the data is stored in cache device 1120, a write completion signal can be sent to processor 1110 without writing the data to memory device 1200. This write operation is called a "write-back write operation". In contrast, when processor 1110 sends a write request, the data to be written can be stored in cache device 1120 and immediately sent to memory device 1200. A write completion signal can be sent to processor 1110 after the data is stored in memory device 1200. This write operation is called a "write-through write operation".

[0038] When a write operation is performed in write-back mode, a line fill operation (i.e., a cache fill operation) can be performed from storage device 1200 to cache device 1120, during which data corruption may occur. A line fill operation can refer to the following operation: when a cache miss occurs in cache device 1120, the data corresponding to the cache miss is read from storage device 1200 and the read data is stored in cache device 1120. If an error exists on the interface (e.g., communication between storage device 1200 and cache device 1120) or on cache device 1120 during the line fill operation, corrupted data will be stored in cache device 1120. Furthermore, when a flush operation is performed on the cache line containing corrupted data, the corrupted data will be stored in storage device 1200.

[0039] In an embodiment, a cache line may be the smallest unit of access for a read or write request sent by the processor 1110 to the storage device 1200. The size of each cache line may be, for example, 32 bytes or 64 bytes, but this disclosure is not limited thereto.

[0040] Traditional electronic devices access storage devices in units of cache lines and manage dirty information in units of cache lines. Traditional electronic devices can perform line-filling or flushing operations on all cache lines. In this case, when a portion of the data contained in a cache line is corrupted, the corrupted portion can be stored in the storage device.

[0041] In contrast, the electronic device 1000 according to an embodiment of the present disclosure can manage dirty information in units of sectors smaller than cache lines. The electronic device 1000 can generate a data mask signal DM based on the dirty information managed in units of sectors, and can perform write operations on the storage device 1200 in units of sectors. Therefore, for data consistency between the cache device 1120 and the storage device 1200, sectors in the cache device 1120 that have not been updated by the processor 1110 can be excluded from storage in the storage device 1200. Based on the above description, unnecessary data storage operations can be minimized, thus reducing errors in the storage device 1200. The operation of the electronic device 1000 according to the present disclosure will be described with reference to the following drawings.

[0042] Figure 2 It is used to describe Figure 1 A diagram illustrating the cache structure of an electronic device. For ease of description, components unnecessary for describing the cache structure of cache device 1120 will be omitted.

[0043] Cache device 1120 may include multiple cache sets CS1 to CSn. A cache set CS may include cache lines and cache entries. A cache entry may include a valid bit "V", a dirty bit "D", and a tag. In an embodiment, the format of the cache set CS includes fields for storing data of the cache line and fields for storing information of the cache entry.

[0044] Storage device 1200 may include multiple cache lines CL1 to CLm. The multiple cache lines CL1 to CLm may indicate the storage space corresponding to the unit of data accessed according to the request of processor 1110.

[0045] A portion of the data stored in storage device 1200 may be stored in cache device 1120. In an embodiment, the first cache line CL1 may correspond to the first cache group CS1, the second cache line CL2 may correspond to the second cache group CS2, the third cache line CL3 may correspond to the third cache group CS3, and the m-th cache line CLm may correspond to the n-th cache group CSn.

[0046] A cache line can include sectors S1 through S4, numbered one through four. Sectors S1 through S4 can have the same size. For example, when the cache line size is 64 bytes, the sector size can be 16 bytes.

[0047] A tag can indicate address information about cached data stored in each cache set. In an embodiment, a tag can be information indicating the cache line corresponding to cached data among cache lines CL1 to CLm of storage device 1200. A tag can be used to determine whether data corresponding to an address received from processor 1110 exists in cache device 1120. A tag can be used to determine whether there is a cache hit or a cache miss. A cache hit indicates that the data corresponding to the address received from processor 1110 exists in cache device 1120. A cache miss indicates that the data corresponding to the address received from processor 1110 does not exist in cache device 1120.

[0048] The dirty bit "D" can indicate whether the cache data has been updated after it has been stored in the corresponding cache set. The dirty bit "D" can also indicate whether the cache data is identical to the corresponding data stored in storage device 1200. If no update has been performed, the dirty bit "D" can be maintained to indicate a clean state. If an update has been performed, the dirty bit "D" can be set to indicate a dirty state.

[0049] In an embodiment, the dirty bit "D" may have one of a first logical value and a second logical value. The first logical value of the dirty bit "D" indicates that the cached data associated with the dirty bit "D" and the corresponding data stored in the storage device 1200 are the same. The second logical value of the dirty bit "D" indicates that the cached data associated with the dirty bit "D" has been updated, and that the cached data and the corresponding data stored in the storage device 1200 are different.

[0050] The valid bit "V" can indicate whether valid data has been loaded from storage device 1200 into the corresponding cache set. The valid bit "V" can have one of a first logical value and a second logical value. The second logical value of the valid bit "V" indicates an enabled state where valid data has been loaded from storage device 1200 into the corresponding cache set of cache device 1120, while the first logical value of the valid bit "V" indicates a disabled state where valid data has not been loaded from storage device 1200 into the corresponding cache set of cache device 1120. In an embodiment, when SoC 1100 is powered on, the valid bit "V" can be initialized to the first logical value, and when valid data is loaded from storage device 1200 into cache device 1120, the valid bit "V" changes to have the second logical value. In embodiments where processor 1110 includes multiple processor cores, the valid bit "V" can be reset to the first logical value during use.

[0051] Each of a plurality of cache lines CL1 to CLm can be selected or identified by an address provided by processor 1110. For example, at least one cache line among the plurality of cache lines CL1 to CLm can be selected by an address provided by processor 1110, and an access operation can be performed on the selected cache line.

[0052] Each of a plurality of cache sets CS1 to CSn can be selected or identified by at least a portion (e.g., partial address) of the address provided by processor 1110. At least one cache set of the plurality of cache sets CS1 to CSn can be selected by at least a portion of the address provided by processor 1110, and an access operation can be performed on the selected cache set.

[0053] A tag may include at least a portion or the remainder of an address provided from processor 1110. For example, a cache hit may be determined when at least one of multiple cache groups CS1 to CSn is selected by an address or at least a portion of an address, and that address is included in the tag of the selected cache group. Alternatively, a cache miss may be determined when at least one of multiple cache groups CS1 to CSn is selected by at least a portion of an address, and that address is not included in the tag of the selected cache group.

[0054] Figures 3A to 3C This is a diagram illustrating the operation of an electronic device. For the sake of brevity and ease of description, it is assumed that cache device 1120 includes first to third cache storage spaces for storing first to third cache groups CS1 to CS3, respectively, and that storage device 1200 includes first to third memory storage spaces for storing first to third cache lines CL1 to CL3. In the following, unless otherwise stated, cache groups CS1 to CS3 refer to the cache storage spaces of cache device 1120; and cache lines CL1 to CL3 refer to the memory storage spaces of storage device 1200, unless otherwise stated. Furthermore, it is assumed that first cache line CL1 corresponds to first cache group CS1, second cache line CL2 corresponds to second cache group CS2, and third cache line CL3 corresponds to third cache group CS3. For example, first cache group CS1 may be associated with first cache line CL1 to store its data, second cache group CS2 may be associated with second cache line CL2 to store its data, and third cache group CS3 may be associated with third cache line CL3 to store its data. Assume that sector data A1, A2, A3, and A4 are stored in the first cache line CL1, and sector data B1, B2, B3, and B4 are stored in the third cache line CL3. However, this disclosure is not limited thereto.

[0055] Reference Figure 1 , Figure 2 and Figure 3AThe processor 1110 can perform a line-filling operation, causing data in the third cache line CL3 of the memory device 1200 to be stored in the third cache set CS3 of the cache device 1120. In an embodiment, multiple sectors of data B1, B2, B3, and B4 of the third cache line CL3 can be stored in the third cache set CS3. A line-filling operation from the third cache line CL3 to the third cache set CS3 is performed using a valid bit "V" with a first logic value indicating a disabled state. After the line-filling operation, the valid bit "V" of the third cache set CS3 can be changed to a second logic value indicating an enabled state, and the dirty bit "D" of the third cache set CS3 can be set to the first logic value. The third tag TAG3 of the third cache set CS3 can store the address information of the third cache line CL3. For example, the third tag TAG3 of the third cache set CS3 can store the address information of the third cache line CL3, which corresponds to the memory address of the third cache line CL3 in the storage device 1200 where multiple sector data B1, B2, B3, and B4 are stored. In an embodiment, the address information of the third cache line CL3 stored in the third tag TAG3 of the third cache set CS3 can be a part of the memory address of the third cache line CL3, which can be the block address of the multiple sector data B1, B2, B3, and B4.

[0056] However, during the line-filling operation from storage device 1200 to cache device 1120, an interface error may occur in the data sent from storage device 1200 to cache device 1120, or a cache memory error may occur when the data is stored in cache device 1120.

[0057] In an embodiment, processor 1110 may perform a line-filling operation such that data in the first cache line CL1 of storage device 1200 is stored in the first cache set CS1 of cache device 1120. After the line-filling operation, the first cache set CS1 may store multiple sectors of data A1, A2', A3, and A4, wherein sector data A2' is considered to be corrupted due to an interface or cache memory error, and the sectors A1, A2', A3, and A4 stored in the first cache set CS1 of cache device 1120 are different from the sectors A1, A2, A3, and A4 stored in the first cache line CL1 of storage device 1200. For ease of description, it is assumed that the second sector data A2 of the first cache line CL1 may be corrupted due to an interface or cache memory error and may be stored as the second corrupted sector data A2'. In an embodiment, a line-filling operation from the first cache line CL1 to the first cache set CS1 is performed on the first cache set CS1 using a valid bit "V" having a first logic value indicating a disabled state. After the row filling operation, the valid bit "V" of the first cache group CS1 can be changed to a second logical value indicating the enabled state, and the dirty bit "D" of the first cache group CS1 can be set to a first logical value. The first tag TAG1 of the first cache group CS1 can store the address information of the first cache line CL1. For example, the first tag TAG1 of the first cache group CS1 can store the address information of the first cache line CL1, which corresponds to the memory address of the first cache line CL1 in which multiple sector data A1, A2, A3 and A4 are stored in the storage device 1200. In an embodiment, the address information of the first cache line CL1 stored in the first tag TAG1 of the first cache group CS1 can be a part of the memory address of the first cache line CL1, which can be the block address of multiple sector data A1, A2, A3 and A4.

[0058] Reference Figure 3B The processor 1110 can perform a write operation in write-back mode. The processor 1110 can send a write request to the cache device 1120 for the first address ADDR1 of the third sector S3 indicating the first cache line CL1. In an embodiment, the processor 1110 can send a write request to the cache device 1120 including the first address ADDR1 and sector data A3'.

[0059] The cache device 1120 can compare the first address ADDR1 and the first tag TAG1, and can determine whether the data corresponding to the first address ADDR1 is stored in the first cache set CS1. When the first tag TAG1 indicates the memory address of the first cache line CL1, the cache device 1120 can determine that a cache hit has occurred. The cache device 1120 can store the sector data A3' in the third sector S3 of the first cache set CS1 of the cache device 1120.

[0060] In response to a cache hit determination, cache device 1120 can set the dirty bit "D" of the first cache set CS1 to a second logic value. After a row-filling operation from storage device 1200 to cache device 1120, the sector data A3 stored in the first cache set CS1 is updated, and the dirty bit "D" of the first cache set CS1 can be set to a second logic value indicating that the cached data stored therein is in a dirty state.

[0061] Reference Figure 3CWhen a flush request is received from processor 1110 for a second address ADDR2 indicating the first cache line CL1, or when a flush operation is determined by internal operations of cache device 1120, cache device 1120 may perform a flush operation on the first cache set CS1. For example, a flush operation may be performed to write cached data from the first cache set CS1 to storage device 1200. After a write-back operation, the cached data in the first cache set CS1 may differ from the data stored in the first cache line CL1 of storage device 1200 associated with the second address ADDR2. A flush operation may be performed to update the data stored in the first cache line CL1 of storage device 1200 using the cached data in the first cache set CS1. For example, a flush operation may be triggered in response to a flush request from processor 1110 when processor 1110 determines that an application running on processor 1110 needs data stored in the second address ADDR2 of the first cache line CL1, or when processor 1110 receives a notification from another processor (e.g., another master device other than processor 1110) that the other processor will access the first cache line CL1 to retrieve data stored therein. Since the data associated with the first cache line CL1 of storage device 120 stored in the first cache group CS1 of cache device 1120 was updated in a previous write-back operation, the data in the first cache line CL1 needs to be updated with cached data stored in the first cache group CS1 before the application or another processor accesses the first cache line CL1 accessed using the second address ADDR2. In embodiments, a flush operation may be triggered based on the internal operation of cache device 1120 based on a cache management algorithm. In this embodiment, since the number of cache sets of cache device 1120 is limited, flushing operations can be performed periodically or in response to cache misses for new cache line filling operations.

[0062] The cache device 1120 can select a victim cache set from multiple cache sets to perform a flush operation. In an embodiment, assuming the first cache set CS1 is selected as the victim cache set, the cache device 1120 can determine whether the first cache set CS1 is in a dirty or clean state. Because the dirty bit "D" of the first cache set CS1 has a second logic value, the cache device 1120 can determine that the first cache set CS1 is in a dirty state. In an embodiment, the cache device 1120 can select the first cache set CS1 as the victim cache set from multiple cache sets and perform a flush operation on the first cache set CS1. For example, when the address information stored in the first tag TAG1 of the first cache set CS1 matches the second address ADDR2 of the flush request, a flush request for the second address ADDR2 is issued to the cache device 1120.

[0063] The cache device 1120 can perform a flush operation on the first cache set CS1. The cache device 1120 can send a write request to the storage device 1200 to the second address ADDR2 indicated by the first tag TAG1 and to the storage device 1200 to send multiple sector data A1, A2', A3' and A4 stored in the first cache set CS1.

[0064] In response to a write request during a flush operation, storage device 1200 can store multiple sector data A1, A2', A3', and A4 in the first cache line CL1 indicated by the second address ADDR2. The second corrupted sector data A2' can also be stored in the first cache line CL1. If only the third sector S3 of the first cache set CS1 is updated without updating the second sector S2 of the first cache set CS1, and all sector data A1, A2', A3', and A4 stored in the first cache set CS1 are again stored in storage device 1200, corrupted data will be stored in storage device 1200. This will lead to a system error.

[0065] Figure 4 This is a diagram illustrating a cache group according to embodiments of the present disclosure. (Refer to...) Figure 2 and Figure 4 A cache set may include cache lines and cache entries. A cache entry may include a valid bit "V", a dirty bitmap (D1, D2, D3, D4), and a tag. A cache line may include N sectors (N is a positive number), and the dirty bitmap may include N dirty bits corresponding to each of the N sectors. For the sake of simplicity and ease of description, it is assumed that the dirty bitmap includes the first to fourth dirty bits D1 to D4, and the cache line includes the first to fourth sectors S1 to S4. However, this disclosure is not limited thereto.

[0066] The first to fourth dirty bits D1 to D4 can correspond to the first to fourth sectors S1 to S4, respectively. For example, the first dirty bit D1 can indicate dirty information about the first sector S1, the second dirty bit D2 can indicate dirty information about the second sector S2, the third dirty bit D3 can indicate dirty information about the third sector S3, and the fourth dirty bit D4 can indicate dirty information about the fourth sector S4. (See reference...) Figure 2 The label TAG, the valid bit "V", and the first to fourth sectors S1 to S4 are described, so additional descriptions will be omitted to avoid repetition.

[0067] Figures 5A to 5C It is shown Figure 1 This is a diagram illustrating the operation of an electronic device. For the sake of brevity and ease of description, it is assumed that cache device 1120 includes first to third cache groups CS1 to CS3, and storage device 1200 includes first to third cache lines CL1 to CL3. For ease of description, it is assumed that the first cache line CL1 corresponds to the first cache group CS1, the second cache line CL2 corresponds to the second cache group CS2, and the third cache line CL3 corresponds to the third cache group CS3. It is assumed that sector data A1, A2, A3, and A4 are stored in the first cache line CL1, and sector data B1, B2, B3, and B4 are stored in the third cache line CL3. However, this disclosure is not limited thereto.

[0068] Processor 1110 can perform line filling operations on the third cache line CL3. (See reference...) Figure 3A The line filling operation associated with the third cache line CL3 is described, so additional descriptions will be omitted to avoid repetition. However, since dirty information is managed on a sector-by-sector basis, the first to fourth dirty bits D1 to D4 of the third cache set CS3 can all be initialized to the first logical value and changed to the second logical value depending on whether the cache data associated with each of the first to fourth dirty bits D1 to D4 has been updated.

[0069] During the line-filling operation from storage device 1200 to cache device 1120, cached data stored in the first cache group CS1, the second cache group CS2, and the third cache group CS3 may have interface errors or cache memory errors.

[0070] In one embodiment, processor 1110 may perform a line-filling operation, such that data in the first cache line CL1 of storage device 1200 is stored in the first cache set CS1 of cache device 1120. (See reference...) Figure 3AAs described, multiple sector data A1, A2', A3, and A4 can be stored in a first cache set CS1. This has already been described above, so additional descriptions will be omitted to avoid repetition. However, the first to fourth dirty bits D1 to D4 of the first cache set CS1 can be initialized to a first logical value, and can be changed to a second logical value depending on whether the cache data associated with each of the first to fourth dirty bits D1 to D4 has been updated.

[0071] Reference Figure 5B The processor 1110 can perform a write-back operation. The processor 1110 can send a write request to the cache device 1120 for a first address ADDR1 indicating the third sector S3 of the first cache line CL1. In an embodiment, the processor 1110 can send a write request including the first address ADDR1 and sector data A3' to the cache device 1120. The cache device 1120 can store the sector data A3' in the third sector S3 of the first cache set CS1.

[0072] The cache device 1120 can set the third dirty bit D3 of the first cache set CS1 to a second logic value. For example, after a line-filling operation from the memory device 1200 to the cache device 1120, the third sector S3 of the first cache set CS1 is updated, and the dirty bit D3 of the first cache set CS1 associated with the third sector S3 can be set to a second logic value indicating that the cached data stored therein is in a dirty state.

[0073] Reference Figure 5C When a flush request for a second address ADDR2 indicating a first cache line CL1 is received from the processor 1110, or when a flush operation is determined by the internal operation of the cache device 1120, the cache device 1120 may perform a flush operation on the first cache group CS1.

[0074] The cache device 1120 can send to the memory controller 1130 a write request to the second address ADDR2 indicated by the first tag TAG1, multiple sector data A1, A2', A3' and A4 stored in the first cache group CS1, and dirty information DI.

[0075] The dirty information DI may include a dirty bitmap or first to fourth dirty bits D1 to D4. The first to fourth dirty bits D1 to D4 of the dirty information DI may respectively correspond to the first to fourth dirty bits D1 to D4 of the first cache set CS1. Figure 5BIn the embodiments, the first dirty bit D1, the second dirty bit D2, and the fourth dirty bit D4 of the dirty information DI may have a first logical value, which indicates that the cache data associated with them stored in the first cache group CS1 is in a clean state, and the third dirty bit D3 of the dirty information DI may have a second logical value, which indicates that the cache data associated with it stored in the first cache group CS1 is in a dirty state.

[0076] The data masking control circuit 1131 of the memory controller 1130 can receive dirty information DI. The memory controller 1130 can generate a data masking signal DM in response to the second address ADDR2, multiple sector data A1, A2', A3', and A4, and the dirty information DI. In an embodiment, since the first dirty bit D1, the second dirty bit D2, and the fourth dirty bit D4 of the dirty information DI have a first logic value indicating a clean state, the data masking signal DM corresponding to the first sector data A1, the second sector data A2', and the fourth sector data A4 can have a second logic value indicating an enabled state, in which the sector data associated with the data masking signal DM having the second logic value is masked. Since the third dirty bit D3 of the dirty information DI has a second logic value indicating a dirty state, the data masking signal DM corresponding to the third sector data A3' can have a first logic value indicating a disabled state, in which the sector data associated with the data masking signal DM having the first logic value is stored in the storage device 1200. The memory controller 1130 can send a data shielding signal DM to the storage device 1200 via a data shielding line. This will be described in more detail with reference to the accompanying drawings.

[0077] In response to a write request during a flush operation, cached data of the first cache set CS1 can be selectively stored in the storage device 1200 based on the data mask signal DM. For example, because the data mask signal DM corresponding to the first sector data A1, the second sector data A2', and the fourth sector data A4 has a second logic value indicating an enabled state, the first sector data A1, the second sector data A2', and the fourth sector data A4 in the cached data stored in the first cache set CS1 are not stored in the storage device 1200. For example, based on the data mask signal DM, during a flush operation, the first sector data A1, the second sector data A2', and the fourth sector data A4 in the cached data of the first cache set CS1 are not used to update the data stored in the storage device 1200, or during a flush operation, the first sector data A1, the second sector data A2', and the fourth sector data A4 in the cached data stored in the first cache set CS1 can be blocked or masked. Masking can refer to the fact that cached data associated with the data masking signal DM, which indicates that data masking operation is enabled, is not stored or written to the storage device 1200. Thus, the second corrupted sector data A2' of the first cache set CS1 is not stored in the storage device 1200. The data masking signal DM associated with the third sector data A3' has a first logic value indicating that data masking operation is disabled, and the third sector data A3' of the cached data stored in the first cache set CS1 can be stored in the memory cell array of the storage device 1200 without being masked by the data masking operation.

[0078] As described above, according to embodiments of the present disclosure, in an electronic device 1000 performing a write-back operation, each cache group may include storage space for storing multiple dirty bits associated with multiple sectors. When the electronic device 1000 manages dirty bits in units of sectors smaller than cache lines, the electronic device 1000 can determine the clean or dirty state of each sector. The cache device 1120 may send dirty information DI to the memory controller 1130. The memory controller 1130 may generate a data mask signal DM based on the dirty information DI. The storage device 1200 may receive the data mask signal DM via a data mask line. During a flush operation, the storage device 1200 may selectively store cached data in the storage device 1200 based on the data mask signal DM.

[0079] During a line-filling operation from storage device 1200 to cache device 1120, data may be corrupted due to interface or cache errors, and the corrupted data may be stored in cache device 1120. Subsequently, when the corrupted data can be flushed to storage device 1200, the corrupted data can be masked to prevent interface or cache errors from propagating to storage device 1200.

[0080] The electronic device 1000 according to embodiments of this disclosure can store data in the storage device 1200 in units of sectors based on dirty information DI and data masking signal DM. Therefore, some cached data corresponding to sector data is not updated during cache operations and is not stored in the storage device 1200 during flush operations. Thus, current consumption during flush operations can be reduced, and power consumption of the electronic device 1000 is minimized. An improved electronic device can be provided.

[0081] Figure 6 It is shown Figure 1 A flowchart of the operation of the memory controller is provided. For ease of description, it is assumed that the memory controller 1130 exchanges data via the first to sixteenth data lines DQ1 to DQ16. Additionally, it is assumed that the memory controller 1130 includes a data shield line for the first to sixteenth data lines DQ1 to DQ16 (see [link to documentation]). Figure 1 However, this disclosure is not limited thereto.

[0082] For ease of description, it is assumed that the size of a cache line is 64 bytes. However, this disclosure is not limited thereto. In the embodiments, it is assumed that the burst length BL is set to 32 (BL = 32) to transmit data corresponding to the cache line via the first to sixteenth data lines DQ1 to DQ16. For example, the data corresponding to the cache line may be cached data stored in a cache group associated with that cache line, and the data transfer from cache device 1120 to memory device 1200 can be achieved, for example, by performing a write operation with a burst length of 32 on memory device 1200.

[0083] Reference Figure 5C and Figure 6In operation S100, the memory controller 1130 may receive a write request from the processor 1110. For example, a write request may be issued during a flush operation. In an embodiment, the memory controller 1130 may receive an address, a write request (or write command) including dirty information DI, and write data “DATA”. The dirty information DI may include first to fourth dirty bits D1 to D4 or a dirty bitmap. The write data “DATA” may include first sector data A1, second sector data A2', third sector data A3', and fourth sector data A4. In an embodiment, the write data “DATA” may correspond to cached data stored in a cache device.

[0084] In operation S200, the memory controller 1130 can sequentially arrange the write data "DATA" (e.g., 64 bytes) in 32 rows, each row having 16 bits, and output 16 bits using the first to sixteenth data lines DQ1 to DQ16 in each burst operation. In a burst operation with a burst length BL (=32), 16 bits are output 32 times via the first to sixteenth data lines DQ1 to DQ16. For example, the memory controller 1130 can arrange first sector data A1 so that it is output through data lines DQ1 to DQ16 during the first to eighth burst lengths, arrange second sector data A2' so that it is output through data lines DQ1 to DQ16 during the ninth to sixteenth burst lengths, arrange third sector data A3' so that it is output through data lines DQ1 to DQ16 during the seventeenth to twenty-fourth burst lengths, and arrange fourth sector data A4 so that it is output through data lines DQ1 to DQ16 during the twenty-fifth to thirty-second burst lengths.

[0085] The written data "DATA" may include first to thirty-second input data Din_1 to Din_32. In an embodiment, the written data "DATA" may include: first input data Din_1 to be sent to data lines DQ1 to DQ16 during a first burst length, second input data Din_2 to be sent to data lines DQ1 to DQ16 during a second burst length, third input data Din_3 to be sent to data lines DQ1 to DQ16 during a third burst length, and fourth input data Din_4 to be sent to data lines DQ1 to DQ16 during a fourth burst length. The remaining input data Din_5 to Din_32 are structurally similar to input data Din_1 to Din_4, and therefore additional descriptions will be omitted to avoid repetition.

[0086] That is, the first sector data A1 can correspond to the first to eighth input data Din_1 to Din_8, the second sector data A2' can correspond to the ninth to sixteenth input data Din_9 to Din_16, the third sector data A3' can correspond to the seventeenth to twenty-fourth input data Din_17 to Din_24, and the fourth sector data A4 can correspond to the twenty-fifth to thirty-second input data Din_25 to Din_32.

[0087] In operation S300, the memory controller 1130 can generate a data mask signal DM based on dirty information DI. The data mask signal DM can include first to thirty-second data mask signals DM1 to DM32 corresponding to burst length BL (=32), so that each burst operation can be masked using the corresponding data mask signals of the first to thirty-second data mask signals DM1 to DM32. Data mask signals DM1 to DM32 can each correspond to multiple input data Din_1 to Din_32. For example, the first data mask signal DM1 can indicate masking information regarding the first input data Din_1, the second data mask signal DM2 can indicate masking information regarding the second input data Din_2, the third data mask signal DM3 can indicate masking information regarding the third input data Din_3, and the fourth data mask signal DM4 can indicate masking information regarding the fourth input data Din_4. The remaining data mask signals DM5 to DM32 are structurally similar to data mask signals DM1 to DM4, and therefore additional descriptions will be omitted to avoid repetition.

[0088] In an embodiment, when the dirty bit of the dirty information DI has a first logic value, the corresponding cached data stored in cache device 1120 is not stored in storage device 120 because it is in a clean state. For example, storage device 1200 can mask the corresponding cached data that is in a clean state. In response to the dirty information DI, memory controller 1130 can set the data masking signal DM to a second logic value indicating that the data masking operation is enabled. When the dirty bit of the dirty information DI has a second logic value, the corresponding cached data is in a dirty state, and the corresponding cached data can be stored in storage device 1200. Memory controller 1130 can set the data masking signal DM to a first logic value indicating that the data masking operation is disabled. (Refer to...) Figure 7 A more comprehensive description of the method for generating data shielding signals.

[0089] In operation S400, the memory controller 1130 can output write data "DATA" and a data mask signal DM synchronously with the data strobe signal DQS during the masked write operation MWR. In an embodiment, the memory controller 1130 can send write data via data lines DQ1 to DQ16 in response to the data strobe signal DQS. For example, the memory controller 1130 can generate the data strobe signal DQS and can output write data synchronously with the data strobe signal DQS via data lines DQ1 to DQ16. The memory controller 1130 can output the data mask signal DM synchronously with the data strobe signal DQS via the data mask lines.

[0090] Figure 7 It is shown in detail Figure 6 The timing diagram for the S400 operation is shown below. (Refer to...) Figure 1 and Figure 7 The memory controller 1130 can output write data and a data mask signal DM synchronously with the data strobe signal DQS. In an embodiment, the memory controller 1130 can send write data via data lines DQ1 to DQ16 based on the data strobe signal DQS. For example, the memory controller 1130 can output write data synchronously with the rising and falling edges of the data strobe signal DQS via data lines DQ1 to DQ16. The memory controller 1130 can also output the data mask signal DM synchronously with the data strobe signal DQS via the data mask lines.

[0091] In the embodiments, reference is made to Figure 5C Assume that the dirty information DI includes a first dirty bit D1 with a first logical value, a second dirty bit D2 with a first logical value, a third dirty bit D3 with a second logical value, and a fourth dirty bit D4 with a first logical value. Assume that multiple sectors of data A1, A2', A3', and A4 will be sent to the storage device 1200. However, this disclosure is not limited thereto. As described above, the first logical value can represent a clean state, indicating that the associated cached data has not been changed since the data was uploaded from the storage device to the cache device, and the second logical value can represent a dirty state, indicating that the associated cached data has been changed after the upload.

[0092] Because the first dirty bit D1 of the dirty information DI has a first logic value, the first sector data A1 stored in the cache device 1120 is not stored in the storage device 120; because the second dirty bit D2 of the dirty information DI has a first logic value, the second sector data A2' stored in the cache device 1120 is not stored in the storage device 1200. Because the third dirty bit D3 of the dirty information DI has a second logic value, the third sector data A3' stored in the cache device 1120 is stored in the storage device 1200; because the fourth dirty bit D4 of the dirty information DI has a first logic value, the fourth sector data A4 is not stored in the storage device 1200.

[0093] For example, the masking of the first to eighth input data Din_1 to Din_8 corresponding to the first sector data A1 can be enabled, the masking of the ninth to sixteenth input data Din_9 to Din_16 corresponding to the second sector data A2' can be enabled, the masking of the seventeenth to twenty-fourth input data Din_17 to Din_24 corresponding to the third sector data A3' can be disabled, and the masking of the twenty-fifth to thirty-second input data Din_25 to Din_32 corresponding to the fourth sector data A4 can be enabled.

[0094] For example, the first to eighth data masking signals DM1 to DM8, which correspond to the first to eighth input data Din_1 to Din_8 respectively, can have a second logic value; the ninth to sixteenth data masking signals DM9 to DM16, which correspond to the ninth to sixteenth input data Din_9 to Din_16 respectively, can have a second logic value; the seventeenth to twenty-fourth data masking signals DM17 to DM24, which correspond to the seventeenth to twenty-fourth input data Din_17 to Din_24 respectively, can have a first logic value; and the twenty-fifth to thirty-second data masking signals DM25 to DM32, which correspond to the twenty-fifth to thirty-second input data Din_25 to Din_32 respectively, can have a second logic value.

[0095] In this embodiment, the first logic value corresponds to a logic low level, and the second logic value corresponds to a logic high level. The data masking signal DM may be at a logic high level during a first time period T1, a logic high level during a second time period T2, a logic low level during a third time period T3, and a logic high level during a fourth time period T4.

[0096] In this embodiment, the data mask signal DM may correspond to the data mask (DM_n) signal specified in the DDR 4.0 specification. The electronic device 1000 can enable or disable the data mask function by setting the mode register. The electronic device 1000 can enable or disable the data mask function via the tenth address A10 of the fifth mode register MR5. The electronic device 1000 can disable the data mask function by setting the tenth address A10 of the fifth mode register MR5 to "0", and can enable the data mask function by setting the tenth address A10 of the fifth mode register MR5 to "1".

[0097] In the embodiments, reference is made to Figure 5C The memory controller 1130 can receive dirty information DI, which includes: a first dirty bit D1 with a first logic value, a second dirty bit D2 with a first logic value, a third dirty bit D3 with a second logic value, and a fourth dirty bit D4 with a first logic value. The memory controller 1130 can send a DM_n signal based on the dirty information DI.

[0098] For example, unlike Figure 7 As shown, the memory controller 1130 can mask the first to eighth input data Din_1 to Din_8 by setting the DM_n signal to a logic low level during the first time period T1, mask the ninth to sixteenth input data Din_9 to Din_16 by setting the DM_n signal to a logic low level during the second time period T2, not mask the seventeenth to twenty-fourth input data Din_17 to Din_24 by setting the DM_n signal to a logic high level during the third time period T3, and mask the twenty-fifth to thirty-second input data Din_25 to Din_32 by setting the DM_n signal to a logic low level during the fourth time period T4.

[0099] Figure 8 It is shown in detail Figure 1 A block diagram of the storage device. (Refer to...) Figure 1 and Figure 8 The storage device 1200 may include a storage cell array 1210, a row decoder 1220, a column decoder 1230, a control logic circuit 1240, and an input / output (I / O) circuit 1250.

[0100] The memory cell array 1210 may include multiple memory cells. Each memory cell may be a DRAM cell including a storage capacitor and a transistor, but this disclosure is not limited thereto. The multiple memory cells may be connected to multiple word lines and multiple bit lines.

[0101] Row decoder 1220 can select at least one word line from multiple word lines under the control of control logic circuit 1240, and can drive the selected word line. Column decoder 1230 can select at least one bit line from multiple bit lines under the control of control logic circuit 1240, and can drive the selected bit line.

[0102] The control logic circuit 1240 can receive address ADDR, command CMD, and control signal CTRL from the memory controller 1130, and can control the components of the memory device 1200 based on the received signals. The control logic circuit 1240 can receive data shield signal DM from the memory controller 1130 via the data shield line.

[0103] The control logic circuit 1240 can selectively store data in the memory cell array 1210 based on the data masking signal DM. In an embodiment, when the data masking signal DM has a first logic value, the control logic circuit 1240 can store the corresponding input data in the memory cell array 1210. When the data masking signal DM has a second logic value, the control logic circuit 1240 does not store the corresponding input data in the memory cell array 1210.

[0104] The input / output circuit 1250 can receive write data "DATA" from the memory controller 1130 via data lines DQ1 to DQ16, which is received together with the data strobe signal DQS.

[0105] As described above, in the electronic device 1000 according to embodiments of the present disclosure, dirty bits can be managed in units of sectors smaller than cache lines, dirty information can be provided to the memory controller, and the storage device can selectively store data based on the data mask signal DM. As a result, system stability can be improved, and power consumption can be minimized.

[0106] Figure 9A and Figure 9B It is used to describe Figure 1 The timing diagram for the operation of the storage device. (Refer to...) Figure 9A and Figure 9B This describes the Masked Write (MWR) operation. MWR operations can correspond to various operations supported by various standard interfaces defined by the Joint Electronic Equipment Committee (JEDEC) standards, such as Low Power Double Data Rate (LPDDR) DRAM, Double Data Rate (DDR) DRAM, and Graphics DDR (GDDR) standards. (See reference...) Figure 1 and Figure 9A Electronic device 1000 can be based on Figure 9A The timing diagram shown executes a mask write operation.

[0107] Electronic device 1000 can perform data masking and data bus inversion (DBI) functions via the data mask inversion (DMI) signal. Electronic device 1000 can enable or disable each of the data masking and data bus inversion functions by setting the mode register. Electronic device 1000 can enable or disable the data bus inversion function via the seventh opcode OP[7] of the third mode register MR3. Electronic device 1000 can enable or disable the data masking function via the fifth opcode OP[5] of the thirteenth mode register MR13.

[0108] Electronic device 1000 can enable the data bus inversion function by setting the seventh opcode OP[7] of the third mode register MR3 to "1", and can disable the data bus inversion function by setting the seventh opcode OP[7] to "0". Electronic device 1000 can enable the data masking function by setting the fifth opcode OP[5] of the thirteenth mode register MR13 to "0", and can disable the data masking function by setting the fifth opcode OP[5] to "1".

[0109] First, it will be described how MWR operation is implemented when the data masking function is enabled and the data bus inversion function is disabled. In the embodiment, the data mask inversion (DMI) signal is used as described above. Figures 1 to 7 The data masking signal under discussion. For example, the memory controller 1130 can send a burst length BL via the command / address signal CA at a first time t1, and can send the bank address BA, column address CA, and auto-precharge AP via the command / address signal CA at a second time t2. The burst length BL, bank address BA, column address CA, and auto-precharge AP sent at the first time t1 and the second time t2 can constitute a first MWR command MWR-1. In an embodiment, the burst length BL included in the first MWR command MWR-1 can be distinguished from the bank address BA, column address CA, and auto-precharge AP included in the first MWR command MWR-1 by setting the chip select signal CS to a logic high level at the first time t1 and setting the chip select signal CS to a logic low level at the second time t2.

[0110] Immediately following the transmission of the first MWR command MWR-1, the electronic device 1000 can transmit column addresses CAn via the command / address signal CA at a third time t3 and a fourth time t4, respectively. These two column addresses CAn can constitute a second CAS command CAS-2. In an embodiment, the two column addresses CAn included in the second CAS command CAS-2 can be distinguished from each other by setting the chip select signal CS to a logic high level at the third time t3 and setting the chip select signal CS to a logic low level at the fourth time t4.

[0111] In this embodiment, Table 1 below shows the command truth table for the first MWR command MWR-1 and the second CAS command CAS-2 based on the LPDDR 4.0 specification protocol.

[0112] [Table 1]

[0113]

[0114] As shown in Table 1 above, the first MWR command MWR-1 and the second CAS command CAS-2 can be sent by controlling the chip select signal CS and multiple command / address signals CA. For example, the command / address signals CA may include command / address signals CA0 to CA5. The memory controller 1130 can send the first part of the first MWR command MWR-1 by setting the chip select signal CS and the second command / address signals CA2 and CA3 to "H" (high) and setting the 0th command / address signal CA0, the first command / address signal CA1, the fourth command / address signal CA4, and the fifth command / address signal CA5 to "L" (low) at the first rising edge R1 of the clock signal CK_t (e.g., at the first time t1). The memory controller 1130 can send the second part of the first MWR command MWR-1 by setting the chip select signal CS to "L" and setting the 0th to the second memory bank addresses BA0 to BA2 to the 0th to the second command / address signals CA0 to CA2 respectively at the second rising edge R2 of the clock signal CK_t (e.g., at the second time t2), setting the fourth command / address signal CA4 to the ninth column address C9, and setting the fifth command / address signal CA5 to the auto precharge AP. For example, the memory controller 1130 can send the first MWR command MWR-1 by setting the chip select signal CS and multiple command / address signals CA0 to CA5 at the two rising edges R1 and R2 of the clock signal CK_t according to the command truth table shown in Table 1 above. Similarly, the memory controller 1130 can send the first part of the second CAS command CAS-2 by setting the chip select signal CS and the first command / address signals CA1 and CA4 to "H", setting the 0th command / address signal CA0, the second command / address signal CA2 and the third command / address signal CA3 to "L", and setting the eighth column address C8 to the fifth command / address signal CA5 at the first rising edge R1 of the clock signal CK_t (e.g., at the third time t3) after sending the first MWR command MWR-1. Afterwards, the memory controller 1130 can send the second part of the second CAS command CAS-2 by setting the chip select signal CS to "L" and setting the second to seventh column addresses C2 to C7 to the 0th to fifth command / address signals CA0 to CA5 respectively. For example, the memory controller 1130 can send the second CAS command CAS-2 by setting the chip select signal CS and multiple command / address signals CA0 to CA5 at the two rising edges R1 and R2 of the clock signal CK_t according to the command truth table shown in Table 1 above.

[0115] In this embodiment, the data strobe signal DQS can be switched after a write wait time WL has elapsed from the time t4 when the second CAS command CAS-2 is sent (i.e., at time t5). Input data can be sent synchronously via the data line DQ in conjunction with the data strobe signal DQS. The data mask inversion signal DMI can also be sent synchronously in conjunction with the data strobe signal DQS.

[0116] In the embodiments, reference is made to Figure 5C The memory controller 1130 can receive dirty information DI, which includes: a first dirty bit D1 with a first logic value, a second dirty bit D2 with a first logic value, a third dirty bit D3 with a second logic value, and a fourth dirty bit D4 with a first logic value. The memory controller 1130 can send a DMI signal based on the dirty information DI.

[0117] For example, the memory controller 1130 can be used as a reference as described above. Figures 1 to 7 The described data masking signal, DMI signal, is set to a logic high level during the first time period T1 to mask the first to eighth input data Din_1 to Din_8. The ninth to sixteenth input data Din_9 to Din_16 can be masked by setting DMI signal to a logic high level during the second time period T2. The seventeenth to twenty-fourth input data Din_17 to Din_24 can be left unmasked by setting DMI signal to a logic low level during the third time period T3. The twenty-fifth to thirty-second input data Din_25 to Din_32 can be masked by setting DMI signal to a logic high level during the fourth time period T4.

[0118] Reference Figure 9B Description: How MWR operation is implemented when both data masking and data bus reversal are enabled. The first MWR command MWR-1 and the second CAS command CAS-2 have been described more comprehensively above, so additional descriptions will be omitted to avoid repetition.

[0119] Because the data bus inversion function is enabled, a high logic level for the DMI signal indicates that the corresponding data has been inverted, while a low logic level for the DMI signal indicates that the corresponding data has not been inverted. That is, compared to... Figure 9A Unlike other controllers, when the data bus inversion function is enabled, the memory controller 1130 does not use the DMI signal in the data masking function. In contrast, the memory controller 1130 can send masked write data via data lines DQ1 to DQ16.

[0120] For example, data corresponding to the case where the DMI signal is set to logic low and the number of 1s in the data bits transmitted through the second to seventh data lines DQ2 to DQ7 is 5 or more can be considered as masked data, or data corresponding to the case where the DMI signal is set to logic low and the number of 1s in the data bits transmitted through the tenth to fifteenth data lines DQ10 to DQ15 is 5 or more can be considered as masked data.

[0121] In the embodiments, reference is made to Figure 5C The memory controller 1130 can receive dirty information DI, which includes a first dirty bit D1 with a first logic value, a second dirty bit D2 with a first logic value, a third dirty bit D3 with a second logic value, and a fourth dirty bit D4 with a first logic value. The memory controller 1130 can generate masking data based on the dirty information DI.

[0122] In this embodiment, the memory controller 1130 can set the DMI signal to a logic low level during the first time period T1 to the fourth time period T4. Because the third dirty bit D3 is set to the second logic value, the data corresponding to the third dirty bit D3 can be left unmasked. The seventeenth to twenty-fourth input data Din_17 to Din_24 can remain unchanged. Conversely, because the first dirty bit D1, the second dirty bit D2, and the fourth dirty bit D4 are set to the first logic value, the data corresponding to the first dirty bit D1, the second dirty bit D2, and the fourth dirty bit D4 can be masked. Before transmission, the first to eighth input data Din_1 to Din_8, the ninth to sixteenth input data Din_9 to Din_16, and the twenty-fifth to thirty-second input data Din_25 to Din_32 can be changed to masked data. In each of the first time period T1, the second time period T2, and the fourth time period T4, the number of 1s sent to the data bits of the second to seventh data lines DQ2 to DQ7 can be at least 5 or more, or the number of 1s sent to the data bits of the tenth to fifteenth data lines DQ10 to DQ15 can be at least 5 or more.

[0123] As described above, the memory controller 1130 can be based on a reference Figures 9A to 9B The described MWR operation provides input data and data masking signals to storage device 1200.

[0124] Figure 10A This illustrates an embodiment. Figure 1 A flowchart illustrating the operation of an electronic device. (Refer to...) Figure 1 , Figure 2 and Figure 4In operation S1010, the processor 1110 may send a read request including a first address ADDR1 to the cache device 1120. The first address ADDR1 may be an address corresponding to a memory space in the memory device 1200 where the read data is stored.

[0125] In operation S1020, in response to a read request, cache device 1120 can determine whether the data corresponding to the first address ADDR1 is stored in cache device 1120. For example, cache device 1120 can determine whether a cache hit or a cache miss has occurred based on the tag TAG. Cache device 1120 can determine whether a cache hit or a cache miss has occurred based on the result of comparing the tag TAG with the first address ADDR1 from processor 1110, or the result of comparing the tag TAG with at least a portion of the first address ADDR1.

[0126] In an embodiment, cache device 1120 can select from a plurality of cache groups a cache group that includes a tag TAG corresponding to the first address ADDR1 or at least a portion of the first address ADDR1, and can read the tag TAG of the selected cache group. Cache device 1120 can compare the tag TAG with the first address ADDR1 to determine whether a cache hit or a cache miss has occurred. However, this disclosure is not limited thereto. For example, various methods can be used to determine whether a cache hit or a cache miss has occurred. When a cache hit is determined to have occurred, in operation S1140, cache device 1120 can send first data DATA1 corresponding to the first address ADDR1 to processor 1110.

[0127] When a cache miss is detected, cache device 1120 performs operation S1030. To allocate a new cache set for storing data corresponding to the first address ADDR1 from processor 1110, cache device 1120 may select a cache set from multiple cache sets whose valid bit "V" is the first logical value. If there are no remaining cache sets in cache device 1120 with a valid bit "V" as the first logical value, a sacrifice cache set may be selected from multiple cache sets for flushing. In embodiments, cache device 1120 may select the sacrifice cache set, for example, by selecting the least recently used cache set (LRU), the most recently used cache set (MRU), or the first-in-first-out cache set (FIFO).

[0128] In operation S1040, cache device 1120 can determine whether the sacrificed cache set is in a dirty state. In an embodiment, cache device 1120 can determine that the sacrificed cache set is in a dirty state when at least one of the multiple dirty bits D1 to D4 of the sacrificed cache set indicates a second logic value. When the sacrificed cache set is not in a dirty state (i.e., in a clean state), in operation S1080, cache device 1120 can send cache information INFO including cache miss information without performing a flush operation on the sacrificed cache set. When the sacrificed cache set is in a dirty state, cache device 1120 performs operation S1050 to perform a flush operation on the sacrificed cache set.

[0129] In operation S1050, cache device 1120 may send cache information INFO to processor 1110. In an embodiment, the cache information INFO may include information about the sacrificed cache set.

[0130] In operation S1060, processor 1110 may, in response to cache information INFO including information about the sacrificed cache set, perform a flush operation associated with the sacrificed cache set. Processor 1110 may send a write request to memory controller 1130. In an embodiment, processor 1110 may send a write request including an address indicating a cache line of memory device 1200 corresponding to the sacrificed cache set. Processor 1110 may send dirty information DI including first to fourth dirty bits D1 to D4 of the sacrificed cache set to memory controller 1130. Processor 1110 may send cache data of the sacrificed cache set to memory controller 1130.

[0131] In operation S1070, based on the dirty information DI, cached data, and a write request including an address, the memory controller 1130 can send a data mask signal DM along with cached data from the sacrifice cache set to the storage device 1200. In an embodiment, the memory controller 1130 can receive a write request including an address, the dirty information DI, and the cached data. The memory controller 1130 can sequentially arrange the cached data such that the cached data is output to the first to sixteenth data lines DQ1 to DQ16 at a predetermined number of times (e.g., burst length). The memory controller 1130 can generate the data mask signal DM based on the dirty information DI. The memory controller 1130 can output the data and the data mask signal DM synchronously with the data strobe signal DQS. This has already been described above, so additional descriptions will be omitted to avoid repetition.

[0132] In operation S1080, cache device 1120 may send cache information INFO to processor 1110. In an embodiment, the cache information INFO may include cache miss information regarding the first address ADDR1.

[0133] In this embodiment, when the sacrifice cache set is in a dirty state, operation S1080 can be omitted, and in operation S1050, cache device 1120 can send cache information INFO including cache miss information about the first address ADDR1. Alternatively, the order of operations S1030 to S1070 and operation S1080 can be changed, or operations S1030 to S1070 can be executed in parallel with operation S1080. Figure 10A The flowchart in the document is only one embodiment, and operations S1020 to S1040 can be executed by processor 1110.

[0134] In operation S1080, in response to cache information INFO including cache miss information, processor 1110 can identify that the data corresponding to the first address ADDR1 is not stored in cache device 1120. In this case, processor 1110 can send a read request to memory controller 1130.

[0135] In an embodiment, during operation S1090, processor 1110 may send a read request to memory controller 1130 including a second address ADDR2, which indicates at least one cache line among a plurality of cache lines CL1 to CLm of memory device 1200. A cache line may be the smallest unit of data sent by processor 1110 to memory device 1200 in a read or write request. Therefore, when the first address ADDR1 does not indicate at least one of the plurality of cache lines CL1 to CLm, processor 1110 may send a read request to memory device 1200 for the second address ADDR2, which indicates a cache line including the first address ADDR1.

[0136] When the first address ADDR1 points to at least one of multiple cache lines CL1 to CLm, the first address ADDR1 and the second address ADDR2 can be the same. In contrast, when the first address ADDR1 is not the starting address of a cache line but points to any space within a cache line, the first address ADDR1 and the second address ADDR2 can be different.

[0137] In operation S1100, the memory controller 1130 may send a read request to the memory device 1200. In an embodiment, the memory controller 1130 may send a command and a second address ADDR2 to the memory device 1200. In operation S1110, in response to the read request, the memory device 1200 may output the second data DATA2 to the memory controller 1130.

[0138] In operation S1120, the memory controller 1130 may send the second data DATA2 received from the memory device 1200 to the cache device 1120. In operation S1130, the cache device 1120 may store the second data DATA2 in the sacrificial cache set. The cache device 1120 may initialize the dirty bits D of the sacrificial cache set. For example, the cache device 1120 may set multiple dirty bits D1 to D4 of the sacrificial cache set to a first logic value.

[0139] Thus, during the execution of operations S1100 to S1130, data may be corrupted at the interface, or corrupted data may be stored when the data is stored in cache device 1120. When a line-filling operation is performed from storage device 1200 to cache device 1120, data stored in storage device 120 may not be corrupted for the same address, but corrupted data may be stored in cache device 1120.

[0140] In operation S1140, cache device 1120 can send first data DATA1 corresponding to the first address ADDR1 to processor 1110. The size of first data DATA1 can be equal to or less than the size of the cache line. The size of second data DATA2 can be equal to the size of the cache line.

[0141] Figure 10B This illustrates an embodiment. Figure 1 A flowchart illustrating the operation of an electronic device. (Refer to...) Figure 1 , Figure 2 and Figure 4 In operation S2010, the processor 1110 can send a write request including the first address ADDR1 and the first data DATA1 to the cache device 1120.

[0142] In operation S2020, in response to a write request, cache device 1120 can determine whether the data corresponding to the first address ADDR1 is stored in cache device 1120. Cache device 1120 can determine whether a cache hit or a cache miss has occurred based on the tag. (See reference...) Figure 10AThis has been described in detail, so additional descriptions will be omitted to avoid repetition. When a cache hit is determined to have occurred, the method proceeds to operation S2140. When a cache miss is determined to have occurred, the method proceeds to operation S2030.

[0143] Operations S2030 to S2130 and Figure 10A Operations S1030 to S1130 are the same, therefore additional descriptions will be omitted to avoid repetition. In operation S2140, cache device 1120 may store the first data DATA1 received from processor 1110.

[0144] In one embodiment, upon receiving first data DATA1 of size equal to a cache line from processor 1110, all first to fourth sector data of the cache set can be updated. Alternatively, upon receiving first data DATA1 of size equal to a sector from processor 1110, only specific sector data among multiple sector data of the cache set can be updated.

[0145] In operation S2150, cache device 1120 may set at least one dirty bit corresponding to the first data DATA1 to a second logic value indicating a dirty state. In an embodiment, when first data DATA1 of size equal to the cache line is received from processor 1110, all first to fourth dirty bits D1 to D4 may be set to the second logic value. Alternatively, when the first address ADDR1 indicates the third sector S3 and first data DATA1 of size equal to the sector is received from processor 1110, only the third dirty bit D3 may be set to the second logic value.

[0146] Because processor 1110 sends a write-back request, only the data stored in cache device 1120 can be updated, while the data stored in storage device 1200 is not updated. The data stored in cache device 1120 may differ from the data stored in storage device 1200, the latter corresponding to the updated data in cache device 1120.

[0147] Figure 10C This illustrates an embodiment. Figure 1 A flowchart illustrating the operation of an electronic device. (Refer to...) Figure 1 , Figure 2 and Figure 4 In operation S3010, the processor 1110 can send a write request including the first address ADDR1 and the first data DATA1 to the cache device 1120.

[0148] In operation S3020, in response to a write request, cache device 1120 can determine whether the data corresponding to the first address ADDR1 is stored in cache device 1120. Cache device 1120 can determine whether a cache hit or a cache miss has occurred based on the tag. (See reference...) Figure 10A This has been described in detail, so additional descriptions will be omitted to avoid repetition. When a cache hit is determined to have occurred, the method proceeds to operation S3140. When a cache miss is determined to have occurred, the method proceeds to operation S3030.

[0149] Operations S3030 to S3150 and Figure 10B Operations S2030 to S2150 are the same, therefore additional descriptions will be omitted to avoid repetition. In operation S3160, processor 1110 may send a write request in a write-through mode, including the second address ADDR2, dirty information DI, and data, to memory controller 1130. The dirty information DI may include the first to fourth dirty bits DI1 to DI4 of the cache set corresponding to the second address ADDR2. Because processor 1110 sends a write-through mode request in operation S3010, both the data stored in cache device 1120 and the data stored in memory device 1200 can be updated.

[0150] In operation S3170, based on dirty information DI, data, and a write request including a second address ADDR2, memory controller 1130 can send a data mask signal DM along with data from processor 1110 to storage device 1200. In an embodiment, memory controller 1130 can receive a write request including an address, dirty information DI, and data. Memory controller 1130 can sequentially arrange the data into data bits corresponding to the burst length to output it to the first through sixteenth data lines DQ1 through DQ16. Memory controller 1130 can generate the data mask signal DM based on the dirty information DI. Memory controller 1130 can output data and the data mask signal DM synchronously with the data strobe signal DQS. This has already been described above, so additional descriptions will be omitted to avoid repetition.

[0151] As described above, the electronic device 1000 according to this disclosure can manage dirty information in sectors smaller than cache lines. The electronic device 1000 can generate a data masking signal based on the dirty information managed in sectors, and can perform write operations on the memory device 1200 in sectors. Therefore, sectors of the cache device 1120 that have not been updated by the processor 1110 may not be stored in the memory device 1200. Based on the above description, unnecessary data storage operations can be minimized, thereby reducing errors in the memory device 1200.

[0152] Figure 11 This is a block diagram illustrating a storage device according to an embodiment of the present disclosure. (Refer to...) Figure 11 The storage device 2000 includes a memory controller 2100, buffer memory 2200, and non-volatile (NVM) storage device 2300. In embodiments, the storage device 2000 may be a high-capacity storage medium such as a solid-state drive (SSD), a universal serial bus (USB) memory, a hard disk drive, or a USB memory stick.

[0153] The memory controller 2100 can exchange data in response to a request from a host (not shown). In response to a request from the host, the memory controller 2100 can read data from the non-volatile storage device 2300, temporarily store the read data in the buffer memory 2200, and provide the read data to the host. Additionally, in response to a request from the host, the memory controller 2100 can temporarily store the data "DATA" received from the host in the buffer memory 2200, and then program the data "DATA" into the non-volatile storage device 2300.

[0154] To perform the above operations, the memory controller 2100 can provide address, command, and control signals to the non-volatile memory device 2300, and can exchange data with the non-volatile memory device 2300. To perform the above operations, the memory controller 2100 can provide address, command, control signals, and data masking signal DM to the buffer memory 2200, and can exchange data with the buffer memory 2200.

[0155] The memory controller 2100 can manage or control the non-volatile memory device 2300. In embodiments, the memory controller 2100 can perform various maintenance operations associated with the non-volatile memory device 2300, such as mapping table management, bad block management, and wear leveling.

[0156] The buffer memory 2200 can operate under the control of the memory controller 2100. For example, in response to a signal received from the memory controller 2100, the buffer memory 2200 can store data or provide the stored data to the memory controller 2100. In embodiments, the buffer memory 2200 may be a dynamic random access memory (DRAM) device, but this disclosure is not limited thereto.

[0157] Buffer memory 2200 may store a mapping table associated with non-volatile storage device 2300. In an embodiment, buffer memory 2200 may temporarily store data received from the host. Alternatively, buffer memory 2200 may temporarily store data read from non-volatile storage device 2300.

[0158] In response to a signal received from memory controller 2100, non-volatile memory device 2300 may output data or may program the received data. In embodiments, non-volatile memory device 2300 may include NAND flash memory. However, embodiments are not limited to this. For example, non-volatile memory device 2300 may include volatile memory such as static RAM (SRAM), DRAM, or synchronous DRAM (SDRAM), or non-volatile memory such as read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory devices, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or ferroelectric RAM (FRAM).

[0159] Figure 12 It is shown Figure 11 A block diagram of the memory controller. (Refer to...) Figure 11 and Figure 12 The memory controller 2100 may include a processor 2110, a cache device 2120, a read-only memory (ROM) 2130, a host interface circuit 2140, a buffer memory interface circuit 2150, and a flash memory interface circuit 2160.

[0160] The processor 2110 can control the overall operation of the memory controller 2100. The cache device 2120 can be a static random access memory (SRAM) device. The ROM 2130 can store various information necessary for the memory controller 2100 to operate in firmware form.

[0161] In an embodiment, various information required to control the non-volatile storage device 2300 (e.g., flash translation layer and mapping table) can be stored in the cache device 2120 or the buffer memory 2200, and this information can be managed or driven by the processor 2110.

[0162] Cache device 2120 can support access speeds higher than those of buffer memory 2200. Since a portion of the data stored in buffer memory 2200 is stored in cache device 2120, the speed of access according to requests from processor 2110 can be improved. Cache device 2120 may include multiple cache sets. Cache device 2120 may manage dirty bits on a sector-by-sector basis rather than on a cache line basis. In an embodiment, cache device 2120 may include first to fourth dirty bits. (See also...) Figure 4 The cache set has been described in detail, so additional descriptions will be omitted to avoid duplication.

[0163] The memory controller 2100 can communicate with external devices (e.g., a host) via host interface circuitry 2140. In embodiments, host interface circuitry 2140 may be based on at least one of various interfaces such as: Double Data Rate (DDR) interface, Universal Serial Bus (USB) interface, Multimedia Card (MMC) interface, Peripheral Component Interconnect (PCI) interface, Fast PCI (PCIe) interface, Advanced Technology Attachment (ATA) interface, Serial ATA (SATA) interface, Parallel ATA (PATA) interface, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Device (IDE) interface, Mobile Industrial Processor Interface (MIPI), and High-Speed ​​Non-Volatile Memory (NVMe) interface.

[0164] The memory controller 2100 can communicate with the buffer memory 2200 via the buffer memory interface circuit 2150. In embodiments, the memory controller 2100 can provide various signals to the buffer memory 2200 via the buffer memory interface circuit 2150. In embodiments, the buffer memory interface circuit 2150 may include a DRAM interface such as a Double Data Rate (DDR) interface, a Low Power DDR (LPDDR) interface, or a Universal Serial Bus (USB) interface.

[0165] The buffer memory interface circuit 2150 may include a data masking control circuit 2151, the operation of which is similar to that of the referenced data masking control circuit 2151. Figures 4 to 11 As discussed, the data masking control circuit 2151 can receive dirty information DI from the cache device 2120. Based on the received dirty information DI, the data masking control circuit 2151 can output a data masking signal DM through the data masking line, causing the buffer memory interface circuit 2150 to perform a flushing operation using a masked write operation.

[0166] The memory controller 2100 can communicate with the non-volatile memory device 2300 via the flash interface circuit 2160. In embodiments, the memory controller 2100 can provide various signals (e.g., CLE, ALE, RE / , WE / , CMD, ADDR, SQRI, and DT) to the non-volatile memory device 2300 based on the flash interface circuit 2160. In embodiments, the flash interface circuit 2160 may include a NAND interface, such as a switchable NAND interface or an open NAND flash interface (ONFI).

[0167] Figure 12 The memory controller 2100 shown is exemplary, and this disclosure is not limited thereto. The memory controller 2100 may also include various components such as an error correction code (ECC) engine and a randomizer.

[0168] For reference Figures 1 to 10C As described, the storage device 2000 according to embodiments of this disclosure can manage dirty information in units of sectors smaller than cache lines. The storage device 2000 can output a data mask signal DM to the buffer memory 2200 via a data mask line based on the dirty information. The buffer memory 2200 does not store outdated sector data in the cache device 2120 based on the data mask signal DM.

[0169] Figure 13 This is a block diagram illustrating an SSD system 3000 according to an embodiment of the present disclosure. (Refer to...) Figure 13 The SSD system 3000 includes the host 3100 and the SSD 3200.

[0170] The SSD 3200 exchanges signals SIG with the host 3100 via signal connector 3201 and is powered by PWR via power connector 3202. The SSD 3200 includes an SSD controller 3210, multiple flash memory modules 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240. In an embodiment, the SSD controller 3210 can manage dirty information on a sector-by-sector basis and can generate data masking signals based on the dirty information, see reference... Figures 1 to 12 This has been described. Therefore, outdated sectors in the cache device will not be stored in the buffer memory 2200. Based on the above description, unnecessary data storage operations can be minimized, thus reducing errors in the buffer memory 3240.

[0171] SSD controller 3210 can control multiple flash memory modules 3221 to 322n in response to a SIG signal received from host 3100. The multiple flash memory modules 3221 to 322n can operate under the control of SSD controller 3210. Auxiliary power supply 3230 is connected to host 3100 via power connector 3202. Auxiliary power supply 3230 can be charged by power PWR supplied from host 3100. When power PWR cannot be stably supplied from host 3100, auxiliary power supply 3230 can power SSD 3200.

[0172] According to this disclosure, since dirty information is stored in the cache device in units of sectors smaller than cache lines, and the dirty information is provided to the memory controller, the memory controller can generate a data mask signal. The memory device can selectively store data based on the data mask signal received from the memory controller. This prevents outdated data from the cache device from being stored in the memory device. Therefore, an electronic device and a method of operation of a system-on-a-chip electronic device with improved stability and minimized power consumption are provided.

[0173] Although this disclosure has been described with reference to embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of this disclosure as set forth by the appended claims.

Claims

1. An electronic device, comprising: A cache memory, the cache memory including memory space configured to store a first cache group, the first cache group including multiple sector data and multiple dirty bits, each of the multiple dirty bits indicating whether the corresponding sector data in the multiple sector data has been modified; A memory controller, connected to multiple data lines and data shielding lines, and configured to: Receive the plurality of sector data and the plurality of dirty bits from the cache memory. The logic level of the data masking signal is set based on the logic level of each of the plurality of organ positions, and The multiple sector data are output through the multiple data lines, and the data shielding signal is output through the data shielding line; as well as A storage device, connected to the plurality of data lines and the data shielding line, and configured to: Data from the multiple sectors is received through the multiple data lines, and The data shielding signal is received through the data shielding line. Wherein, the size of each sector of the plurality of sector data is smaller than the size of a cache line, and The cache line is the smallest unit of data to be sent to the storage device in response to a write request from the memory controller.

2. The electronic device according to claim 1, in, The memory controller is further configured to send a first mask write command to the memory device via multiple command / address lines before outputting the multiple sector data to the memory device via the multiple data lines.

3. The electronic device according to claim 2, in, The memory controller is also configured to: The data masking function of the storage device is enabled based on the logical value of the first opcode, the logical value of the first opcode being stored in the first mode register of the storage device, wherein the memory controller sends the first mask write command to the storage device whose data masking function has been enabled, and The data bus inversion function of the storage device is disabled based on the logical value of the second opcode, and the logical value of the second opcode is stored in the second mode register of the storage device. The data shield line is the data inversion line of the storage device whose data bus inversion function has been disabled.

4. The electronic device according to claim 3, in, The memory controller is further configured to: write first sector data from the plurality of sector data stored in the cache memory to the storage device during a first time period, and write second sector data from the plurality of sector data stored in the cache memory during a second time period after the first time period. The memory controller is further configured to send the data masking signal to the memory device, and The memory controller is further configured to: Based on the logic level of the first dirty bit associated with the first sector data, set the logic level of the data masking signal to be applied during the first time period; and Based on the logic level of the second dirty bit associated with the second sector data, set the logic level of the data masking signal to be applied during the second time period.

5. The electronic device according to claim 4, in, The memory controller, in response to the logic level of the first dirty bit indicating that the first sector data has not been modified, disables the data masking signal during the first time period, causing the storage device, in response to the first mask write command and the disabled data masking signal, to prevent the first sector data from being stored in the storage device. The memory controller, in response to the logic level of the second dirty bit indicating that the second sector data has been modified, enables the data masking signal during the second time period, causing the storage device to store the second sector data received from the memory controller in response to the first mask write command and the enabled data masking signal.

6. A method of operating an electronic device, the electronic device comprising a cache memory, a storage device, and a memory controller, the cache memory including a memory space configured to store a first cache group, the first cache group including a plurality of sector data and a plurality of dirty bits, each of the plurality of dirty bits indicating whether corresponding sector data in the plurality of sector data stored in the cache memory has been modified, the memory controller being located between the cache memory and the storage device, the method comprising: The memory controller sets the logic level of the data masking signal based on the logic level of each of the plurality of dirty bits; The memory controller sends a first mask write command to the memory device via a command / address line connected to the memory device. as well as The memory controller sends the data from the multiple sectors stored in the cache memory to the memory device via multiple data lines connected to the memory device, and sends the data shielding signal to the memory device via a data shielding line connected to the memory device. Wherein, the size of each sector of the plurality of sector data is smaller than the size of a cache line, and The cache line is the smallest unit of data to be sent to the storage device in response to a write request from the memory controller.

7. The method according to claim 6, in, The transmission of the multiple sector data and the data shielding signal includes: During a first time period, the memory controller outputs the first sector data of the plurality of sector data stored in the cache memory via the plurality of data lines; and During the second time period, the memory controller outputs the second sector data from the plurality of sector data stored in the cache memory via the plurality of data lines. The logic level for setting the data shielding signal includes: Based on the logic level of the first dirty bit associated with the first sector data, set the logic level of the data masking signal to be applied during the first time period; and Based on the logic level of the second dirty bit associated with the second sector data, set the logic level of the data masking signal to be applied during the second time period.

8. The method according to claim 6, in, The transmission of the multiple sector data and the data shielding signal includes: After a given time elapsed since the first mask write command was issued, the memory controller outputs the plurality of sector data to the memory device via the plurality of data lines connected to the memory device.

9. The method of claim 6, further comprising: The memory controller enables the data masking function of the storage device based on the logical value of the first opcode, and the logical value of the first opcode is stored in the first mode register of the storage device; and The memory controller disables the data bus inversion function of the memory device based on the logical value of the second opcode, and the logical value of the second opcode is stored in the second mode register of the memory device. The first mask write command is sent to the storage device that has enabled the data masking function and disabled the data bus inversion function.

10. A solid-state drive controller, comprising: A cache memory, the cache memory including a storage device configured to store a first cache set, the first cache set including first sector data and second sector data, and a first dirty bit and a second dirty bit respectively associated with the first sector data and the second sector data; and A buffer memory interface circuit is configured to flush the first sector data and / or the second sector data to an external storage device based on the logic level of each of the first and second dirty bits. Specifically, when the first dirty bit indicates a dirty state and the second dirty bit indicates a clean state, the buffer memory interface circuit masks the first sector data to generate first masked sector data. During a first time period, the first masked sector data is output to the external storage device through multiple data lines, and during a second time period, the second sector data is output to the external storage device through the same multiple data lines. Wherein, the size of each sector in the first sector data and the second sector data is smaller than the size of a cache line, and The cache line is the smallest unit of data to be sent to the external storage device in response to a write request from the buffer memory interface circuit.

11. The solid-state drive controller according to claim 10, in, The buffer memory interface circuit is configured to send a first mask write command to the external storage device via a command / address line connected to the external storage device before outputting the first sector data and / or the second sector data to the external storage device via multiple data lines connected to the external storage device.

12. The solid-state drive controller according to claim 10, in, The buffer memory interface circuit is also configured to: Data masking is enabled based on the first opcode stored in the first mode register of the external storage device. as well as The data bus inversion function is disabled based on the second opcode stored in the second mode register of the external storage device.

13. The solid-state drive controller according to claim 10, in, The buffer memory interface circuit is also configured to disable the shielding signal to be output through the data shielding line during the first time period and the second time period.

14. A storage device comprising: A storage cell array, wherein the storage cell array comprises a plurality of storage cells; Input / output circuitry, configured to receive data from multiple sectors via multiple data lines; and Control logic circuit, the control logic circuit being configured as follows: Receive the first mask write command via the command / address line; Receive data shielding signals via data shielding cable; as well as In response to the data masking signal, the data of the plurality of sectors is selectively stored in the storage cell array; The data masking signal is generated by the external memory controller based on multiple dirty bits associated with the data of the multiple sectors. Wherein, the size of each sector of the plurality of sector data is smaller than the size of a cache line, and The cache line is the smallest unit of data to be sent to the storage device in response to a write request from the external memory controller.

15. The storage device according to claim 14, in, The control logic circuit is further configured to: In response to a logic high level of the data shielding signal, the storage of a first sector of the plurality of sector data in the memory cell array is prevented. The first sector data was received during the period when the data shielding signal is at the logic high level. as well as In response to a logic low level of the data masking signal, a second sector of the plurality of sector data is stored in the memory cell array, the second sector data being received during the period when the data masking signal is at the logic low level.

16. The storage device of claim 14, further comprising: Multiple mode registers, including a second mode register and a first mode register. The control logic circuit is further configured as follows: Based on the first opcode stored in the first mode register, the data masking function is enabled; and Based on the second opcode stored in the second mode register, the data bus inversion function is disabled.

17. The storage device according to claim 14, in, After a given time elapsed since the first mask write command was received, the input / output circuit receives the multiple sector data via the multiple data lines.

Images