Storage device for performing high-speed link initialization and storage system including the same

Abstract

A storage device configured to perform a high-speed link initialization and a storage system including the same are provided. The storage system performs data communication through a connected transmission channel and a connected reception channel among a plurality of channels between a host and the storage device. The host transmits an activation period of the connected transmission channel that is less than a first time period to the connected reception channel, and the storage device receives the activation period of the connected reception channel that is less than the first time period. The host and the storage device perform the link initialization in a high-speed mode through the connected transmission channel and the connected reception channel based on the activation period that is less than the first time period.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0107418, filed on August 25, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to apparatuses and methods, and more specifically, to a storage device for performing high-speed link initiation and a storage system including the storage device. Background Technology

[0004] A storage system can include a host and storage devices. The host can connect to the storage device via various standard interfaces, such as Universal Flash Storage (UFS), Serial ATA (SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), and embedded Multi-Media Card (eMMC). High-speed operation between the host and storage device is advantageous when the storage system is used in mobile devices, as is faster link startup between them. Summary of the Invention

[0005] According to one aspect of the present invention, a link startup method for a device including multiple channels is provided. The method includes: establishing data communication through a connected transmitting channel and a connected receiving channel among the multiple channels; setting the length of an activation period to be less than a first time period, in which the line of the connected transmitting channel has a negative differential line voltage (DIF-N); transmitting the activation period less than the first time period from the connected transmitting channel to the connected receiving channel; receiving the activation period less than the first time period from the connected receiving channel; and performing link startup in high-speed mode through the connected transmitting channel and the connected receiving channel based on the activation period less than the first time period.

[0006] According to another aspect of the present invention, a method for link initiation between a first device and a second device interconnected by multiple channels is provided. The method includes: the first device switching the line of at least one of the multiple channels from a zero differential line voltage (DIF-Z) state to a negative differential line voltage (DIF-N) state; the second device monitoring whether a channel switching from the DIF-Z state to the DIF-N state exists; as a result of the monitoring, the second device identifying the connected channel switching from the DIF-Z state to the DIF-N state; and when the connected channel is identified, performing link initiation between the first device and the second device in high-speed mode.

[0007] According to another aspect of the present invention, an apparatus is provided, comprising: an interface configured to transmit and receive data via an interconnection unit connected thereto through a plurality of channels; a plurality of transmitters included in the interconnection unit, at least one of the transmitters being configured to perform data communication via a connected transmission channel and a connected reception channel among the plurality of channels, and to transmit to the connected reception channel an activation period of the connected transmission channel, the activation period being less than a first time period, and during the activation period, the lines of the connected transmission channel having a negative differential line voltage (DIF-N); and a plurality of receivers included in the interconnection unit, wherein the apparatus is configured to perform link initiation in high-speed mode via the connected transmission channel and the connected reception channel based on an activation period less than the first time period.

[0008] According to another aspect of the present invention, an apparatus is provided, comprising: an interface configured to transmit and receive data via an interconnect unit connected thereto through a plurality of channels; a plurality of receivers included in the interconnect unit, at least one of the receivers being configured to perform data communication via a connected transmit channel and a connected receive channel among the plurality of channels, and to receive an activation period of the connected receive channel, the activation period being less than a first time period, and during the activation period, the line of the connected receive channel having a negative differential line voltage (DIF-N); and a plurality of transmitters included in the interconnect unit, wherein the apparatus is configured to perform link initiation in high-speed mode via the connected transmit channel and the connected receive channel based on an activation period less than the first time period.

[0009] According to another aspect of the present invention, an apparatus is provided, comprising: an interface including an interconnect unit having multiple channels connected thereto, the interface being configured to perform data communication via connected transmit channels and connected receive channels among the multiple channels; multiple receivers included in the interconnect unit, the multiple receivers being configured to monitor whether a connected receive channel exists among the multiple channels, and to identify the existence of a connected receive channel as a result of the monitoring, wherein the line of the connected receive channel is switched from zero differential line voltage (DIF-Z) to negative differential line voltage (DIF-N); and multiple transmitters included in the interconnect unit, wherein the apparatus is configured to perform link initiation in high-speed mode via the connected transmit channels and the connected receive channels when a connected receive channel is identified. Attached Figure Description

[0010] Exemplary embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a block diagram illustrating an example embodiment of a storage system according to a concept of the present invention;

[0012] Figure 2 It is shown Figure 1 A diagram showing the interface between the host and storage devices;

[0013] Figure 3 It is shown Figure 2 A diagram showing the status of the circuit;

[0014] Figure 4 This is a state diagram based on the length of the activation period of the line, according to an exemplary embodiment of the present invention.

[0015] Figure 5 This is a flowchart illustrating a method for operating a storage system according to an exemplary embodiment of the present invention;

[0016] Figure 6 This is a flowchart illustrating a method for operating a storage system according to an exemplary embodiment of the present invention;

[0017] Figure 7 It is shown Figure 5 and Figure 6 A flowchart of the link startup sequence;

[0018] Figure 8 This is a flowchart illustrating a method for operating a storage system according to an exemplary embodiment of the present invention;

[0019] Figure 9 This is a flowchart illustrating a method for operating a storage system according to an exemplary embodiment of the present invention;

[0020] Figure 10 This is a flowchart illustrating a method for operating a storage system according to an exemplary embodiment of the present invention;

[0021] Figure 11A and Figure 11B These are flowcharts illustrating methods for operating a storage system according to exemplary embodiments of the present invention;

[0022] Figure 12 This is a diagram illustrating a system in which a storage device, according to an exemplary embodiment of the present invention, is applied;

[0023] Figure 13 This is a diagram illustrating a Universal Flash Memory (UFS) system according to an exemplary embodiment of the present invention;

[0024] Figures 14A to 14C This is a diagram showing the shape of a UFS card;

[0025] Figure 15 This is a block diagram illustrating an example embodiment of a non-volatile memory (NVM) storage device according to a concept of the present invention;

[0026] Figure 16 This is a block diagram illustrating an NVM storage device according to an exemplary embodiment of the concept of the present invention;

[0027] Figure 17 It is shown Figure 16 Example block diagram of a memory device;

[0028] Figure 18 This is a diagram illustrating an example embodiment of a 3DV-NAND structure applicable to UFS devices according to an invention; and

[0029] Figure 19 This is a diagram illustrating a BVNAND structure applicable to UFS devices, based on an example embodiment of the concept according to the present invention. Detailed Implementation

[0030] Figure 1 This is a block diagram illustrating an example embodiment of a storage system according to a concept of the present invention.

[0031] refer to Figure 1 The storage system 10 may include a host 20 and / or a storage device 30. The host 20 and storage device 30 may be interconnected according to the interface protocols defined in the Universal Flash Storage (UFS) specification; therefore, storage device 30 may include a UFS storage device, and host 20 may include a UFS host. However, the inventive concept is not limited thereto, and storage device 30 and host 20 may be interconnected according to various standard interfaces.

[0032] Host 20 can control data processing operations related to storage device 30, such as data read operations, data write operations, etc. Host 20 can refer to a data processing device capable of processing data, such as a central processing unit (CPU), processor, microprocessor, or application processor (AP). Host 20 can execute an operating system (OS) and / or various applications. In an example embodiment, storage system 10 can be included in a mobile device, and host 20 can be implemented by an AP. In an embodiment, host 20 can be implemented by a system-on-a-chip (SoC) and thus embedded in an electronic device.

[0033] In some example embodiments, host 20 may include interconnect unit 22 and / or host controller 24. Interconnect unit 22 may provide an interface 40 between host 20 and storage device 30. Interconnect unit 22 may include a physical layer and a data link layer. The physical layer of interconnect unit 22 may include physical components for exchanging data with storage device 30, and may also include at least one transmitter TX, at least one receiver RX, etc. Interconnect unit 22 of host 20 may include, for example, four transmitters TX1 to TX4 and four receivers RX1 to RX4. The data link layer of interconnect unit 22 may manage the transmission and synthesis of data, and may also manage data integrity and errors.

[0034] Storage device 30 may include interconnect unit 32, storage controller 34 and / or non-volatile memory 36. Storage controller 34 may control non-volatile memory 36 to write data to non-volatile memory 36 in response to a write request from host 20, or may control non-volatile memory 36 to read data stored in non-volatile memory 36 in response to a read request from host 20.

[0035] Interconnect unit 32 can provide an interface 40 between storage device 30 and host 20. For example, interconnect unit 32 may include a physical layer and a data link layer. The physical layer of interconnect unit 32 may include physical components for exchanging data with host 20, and may also include at least one receiver RX, at least one transmitter TX, etc. Interconnect unit 32 of storage device 30 may include, for example, four receivers RX1 to RX4 and four transmitters TX1 to TX4. The data link layer of interconnect unit 32 can manage the transmission and synthesis of data, and can also manage data integrity and errors.

[0036] In the example embodiment, when the storage system 10 is a mobile device, the physical layers of interconnect units 22 and 32 can be defined by the "M-PHY" specification, and their link layers can be defined by the "UniPro" specification. M-PHY and UniPro are interface protocols proposed by the Mobile Industry Processor Interface (MIPI) Alliance. Each of the link layers of interconnect units 22 and 32 may include a physical adaptation layer, and the physical adaptation layer can control the physical layer, such as the management of data symbols or power management.

[0037] The transmitter TX included in the interconnect unit 22 of the host 20 and the receiver RX included in the interconnect unit 32 of the storage device 30 can form a channel, such as Figure 2 As shown. Furthermore, the transmitters TX included in the interconnect unit 32 of the storage device 30 and the receivers RX included in the interconnect unit 22 of the host 20 can also form a channel. In some example embodiments, the number of transmitters TX1 to TX4 and receivers RX1 to RX4 included in the interconnect unit 22 of the host 20 are shown to be equal to the number of receivers RX1 to RX4 and transmitters TX1 to TX4 included in the interconnect unit 32 of the storage device 30, respectively. According to example embodiments, the number of transmitters and receivers included in the interconnect unit 22 of the host 20 may differ from the number of transmitters and receivers included in the interconnect unit 32 of the storage device 30. Furthermore, the capabilities of the host 20 may differ from the capabilities of the storage device 30.

[0038] Each of host 20 and storage device 30 can identify the physical connection channel and perform processing for receiving information from the other device, such as link initiation. Host 20 and storage device 30 can execute a link initiation sequence before exchanging data. By executing the link initiation sequence, host 20 and storage device 30 can exchange and identify information about the respective numbers of transmitters and receivers, information about the physical connection channel, information about the capabilities of the other device, etc. After the link initiation sequence is completed, host 20 and storage device 30 can be configured into a connection state in which host 20 and storage device 30 can stably exchange data with each other.

[0039] The link startup sequence can be executed during initialization operations, which occur when storage system 10 is first used, or during the booting operation of storage system 10. Additionally, the link startup sequence can be executed during error recovery operations. Because the link startup sequence requires the exchange of information about host 20 and storage device 30, it can take a considerable amount of time to execute. For example, when storage device 30 executes the link startup sequence in low-speed mode, it may take even longer to complete the link startup operation. A link startup operation requiring a longer time may degrade the capabilities of storage system 10.

[0040] The host controller 24 can control the host 20 to perform data communication through the connected transmit and receive channels among the multiple channels included in the interconnect unit 22. The host controller 24 can issue an activation period for the connected transmit channel, which is shorter than a first time period, and can control the host 20 to enter a high-speed mode. The host controller 24 can also issue an activation period longer than the first time period through the connected transmit channel, and can control the host 20 to enter a low-speed mode. Therefore, the host 20 can initiate the link between the host 20 and the storage device 30 in either high-speed or low-speed mode.

[0041] The storage controller 34 can perform data communication through the transmit and receive channels of the multiple channels included in the interconnect unit 32. The storage controller 34 can control the storage device 30 to enter a high-speed mode based on the activation period of the receive channel of the connection being shorter than a first time period, and control the storage device 30 to enter a low-speed mode based on the activation period of the receive channel of the connection being longer than the first time period. Therefore, the storage device 30 can perform link startup between the host 20 and the storage device 30 in either high-speed or low-speed mode.

[0042] The non-volatile memory 36 may include a plurality of memory cells, including, for example, flash memory cells. In an example embodiment, the plurality of memory cells may include NAND flash memory cells. However, the inventive concept is not limited thereto, and in other example embodiments, the plurality of memory cells may include resistive memory cells, such as resistive random access memory (RRAM), phase-change RAM (PRAM), or magnetic RAM (MRAM).

[0043] In some example embodiments, storage device 30 may be implemented as a DRAM-free device, and a DRAM-free device may refer to a device that does not include a DRAM cache. In some example embodiments, storage controller 34 may not include a DRAM controller. For example, storage device 30 may use a portion of non-volatile memory 36 as buffer memory.

[0044] In some example embodiments, storage device 30 may include internal memory embedded in an electronic device. For example, storage device 30 may include an embedded UFS memory device, an embedded multimedia card (eMMC), or a solid-state drive (SSD). However, the inventive concept is not limited thereto, and storage device 30 may include non-volatile memory (e.g., one-time programmable read-only memory (OTPROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), mask ROM, flash ROM, etc.). In some example embodiments, storage device 30 may include external memory removable from the electronic device. For example, storage device 30 may include at least one of a UFS memory card, a compact flash (CF) card, a secure digital (SD) card, a micro SD card, a mini SD card, an extreme digital (xD) card, or a memory stick.

[0045] Storage system 10 can be implemented by, for example, electronic devices such as personal computers (PCs), laptops, mobile phones, smartphones, tablet PCs, personal digital assistants (PDAs), enterprise digital assistants (EDAs), digital still cameras, digital video cameras, audio equipment, portable multimedia players (PMPs), personal navigation devices or portable navigation devices (PNDs), MP3 players, handheld game consoles, or e-book readers. Furthermore, storage system 10 can also be implemented by various electronic devices, such as wearable devices like watches or head-mounted displays (HMDs).

[0046] Figure 2 It is shown Figure 1 A diagram showing the interface 40 between the host 20 and the storage device 30. (The description will follow.) Figure 2 The concepts of LANE, LINE, and LINK in interface 40 are explained below. For ease of description, they are referred to as... Figure 1 Among the multiple transmitters and multiple receivers in interconnect units 22 and 32, the transmitter TX1 of interconnect unit 22 of host 20 and the receiver RX1 of interconnect unit 32 of storage device 30 will be described representatively.

[0047] refer to Figure 2Interface 40 can support multiple channel LANEs. Each channel LANE is a unidirectional, single-signal, information-carrying transmission channel. A channel LANE may include a transmitter TX1, a receiver RX1, and a line LINE providing point-to-point interconnection between the transmitter TX1 and the receiver RX1. The transmitter TX1 or receiver RX1 has a differential output or input line interface corresponding to two signaling pins (PINs). The pins are represented by DP (positive node) representing the differential signal and DN (negative node) representing the differential signal, respectively. TX or RX can be added as a selective prefix to each of the DP and DN in the pins to represent a pin of the transmitter TX1 or a pin of the receiver RX1. The line LINE consists of two differential lines that connect the pins of the transmitter TX1 and the receiver RX1 to each other. These lines are transmission lines.

[0048] Interface 40 includes at least one channel LANE in each direction. The number of channel LANEs in each direction does not need to be symmetrical. The link LINK may include one or more channel LANEs providing bidirectional data transmission capabilities and channel management units 21 and 31 in each direction. Although Figure 2 The channel management units 21 and 31 are shown to be separate from the controllers 24 and 34, respectively. However, the inventive concept is not limited thereto, and the channel management units 21 and 31 may be included in the controllers 24 and 34, respectively.

[0049] Figure 3 It is shown Figure 2 A diagram showing the status of a LINE line.

[0050] refer to Figure 2 and Figure 3 The LINE can be in the DIF-Z state with a near-zero differential line voltage, or in the DIF-N state with a negative differential line voltage. Alternatively, although in Figure 3 Although not shown, a line can be in one of the following states: DIF-P (with a positive differential line voltage), DIF-Q (representing a high impedance state), or DIF-X (neither DIF-N nor DIF-P). In some example embodiments, the differential line voltage can be defined as the value obtained by subtracting the voltage of the line connected to the negative node from the voltage of the line connected to the positive node.

[0051] In the line LINE between transmitter TX1 and receiver RX1, when transmitter TX1 is in a sleep state (hereinafter referred to as "HIBERN8 state"), which is a power-saving state under ultra-low power conditions, receiver RX1 can keep the line LINE in the DIF-Z state. During the DIF-Z state from time point T1 to time point T2, the line LINE is in the HIBERN8 state. The time period between time point T1 and time point T2 is called the sleep period T. HIBERN8 .

[0052] At time T2, transmitter TX1 can switch the LINE to the DIF-N state to signal the exit from the HIBERN8 state. In some example embodiments, receiver RX1 can detect the DIF-N state of the LINE and identify that the links on both sides of transmitter TX1 and receiver RX1 are operational and have exited the HIBERN8 state. The time period between time T1 and time T2 (during which the LINE is in the DIF-N state) is called the active period T. ACTIVATE In the example embodiment, the activation period T ACTIVATE The length can be less than approximately 0.9 milliseconds. In the example embodiment, the activation period T ACTIVATE The length can be equal to or greater than approximately 0.9 milliseconds.

[0053] For example, when the LINE is active during period T ACTIVATE When the length is less than 0.9 milliseconds, transmitter TX1 and receiver RX1 can enter high-speed mode (HS-MODE), and the link between transmitter TX1 and receiver RX1 can perform link initiation operation in HS-MODE. When the LINE is active for a period T... ACTIVATE When the length is equal to or greater than 0.9 milliseconds, transmitter TX1 and receiver RX1 can enter low-speed mode (LS-MODE), and the links on both sides of transmitter TX1 and receiver RX1 can perform link initiation operations in LS-MODE. LS-MODE can correspond to pulse width modulation (PWM) mode. The following will refer to... Figure 7 Describe the link startup operation.

[0054] Figure 4 This is an example embodiment of the invention based on the activation period T of the LINE. ACTIVATE The state diagram of the length.

[0055] refer to Figure 2 , Figure 3 and Figure 4 When the LINE is activated during the T periodACTIVATE When the length is less than 0.9 milliseconds, transmitter TX1 and receiver RX1 can transition from HIBERN8 state 41 to high-speed mode state 45. This occurs when the line LINE is active for a period T. ACTIVATE When the length is equal to or greater than 0.9 milliseconds, the transmitter TX1 and receiver RX1 can switch from HIBERN8 state 41 to low-speed mode state 43.

[0056] Figure 5 This is a flowchart illustrating a method for operating a storage system according to an exemplary embodiment of the present invention. Figure 5 Show Figure 1 The operation of host 20 in storage system 10.

[0057] refer to Figure 1 , Figure 2 and Figure 5 During operation S510, host 20 can exit the HIBERN8 state. Host 20 can switch the LINE of a connected channel LANE among multiple channel LANEs to the DIF-N state and exit the HIBERN8 state. A connected channel LANE refers to an available channel LANE among multiple channel LANEs.

[0058] In operation S520, host 20 can determine the active period T during which the line LINE of the connected channel LANE is in the DIF-N state. ACTIVATE Is the length less than the first time interval T? HS The first time period T HS It could be, for example, 0.9 milliseconds. According to the example embodiment, the first time period T... HS It can be set to something other than 0.9 milliseconds. For example, the first time period T HS It can have values ​​less than 0.9 milliseconds, and it can also have values ​​greater than 0.9 milliseconds (e.g., 1.6 milliseconds).

[0059] As determined in operation S520, during the active period T of the connected channel LANE. ACTIVATE The length is less than the first time period T HS At this point, the method proceeds to operation S550, and in operation S550, host 20 can execute the link start sequence LSS in high-speed mode HS-MODE.

[0060] As determined in operation S520, during the active period T of the connected channel LANE. ACTIVATE The length is equal to or greater than the first time interval T HS At this point, the method proceeds to operation S530, and in operation S530, host 20 can execute the link initiation sequence LSS in low-speed mode LS-MODE.

[0061] Figure 6 This is a flowchart illustrating a method for operating a storage system according to an exemplary embodiment of the present invention. Figure 6 Show Figure 1 The operation of storage device 30 in storage system 10.

[0062] refer to Figure 1 , Figure 2 and Figure 6 In operation S620, storage device 30 can determine the active period T during which the line LINE of the connected channel LANE is in the DIF-N state. ACTIVATE Is the length less than the first time interval T? HS Before operating S620, the LINE can be in a non-DIF-N state, for example, in a DIF-Z state. First time period T HS It could be, for example, 0.9 milliseconds. According to the example embodiment, the first time period T... HS It can be set to something other than 0.9 milliseconds. For example, the first time period T HS It can have values ​​less than 0.9 milliseconds, and it can also have values ​​greater than 0.9 milliseconds (e.g., 1.6 milliseconds).

[0063] As determined in operation S620, during the active period T of the connected channel LANE. ACTIVATE The length is equal to or greater than the first time interval T HS At this point, the method can proceed to operations S625 and S630. In operation S625, storage device 30 can exit the HIBERN8 state, and then in operation S630, storage device 30 can execute the Link Start Sequence (LSS) in low-speed mode (LS-MODE).

[0064] As determined in operation S620, during the active period T of the connected channel LANE. ACTIVATE The length is less than the first time period T HS At this point, the method proceeds to operations S640 and S650. In operation S640, storage device 30 can exit the HIBERN8 state. In some example embodiments, storage device 30 can detect the DIF-N state of a LINE that has been transitioned by host 20 for signaling notification of exiting the HIBERN8 state, and can exit the HIBERN8 state. In operation S650, storage device 30 can execute the Link Initiation Sequence (LSS) in High Speed ​​Mode (HS-MODE).

[0065] Figure 7 It is shown Figure 5 and Figure 6 The flowchart of the Link Startup Sequence (LSS). Figure 7 The Link Initiation Sequence (LSS) is executed in a multi-phase handshake manner, in which UniPro trigger events are exchanged to establish initial bidirectional link communication in the connected LANE (i.e., the available LANE).

[0066] refer to Figure 1 , Figure 2 and Figure 7 In phase S710, host 20 can generate a LINE-RESET, reset the transmitter TX of the connected LANE channel, and send a message indicating that the transmitter TX has been reset. Storage device 30 can receive the LINE-RESET, reset the receiver RX of the connected LANE channel, and send a message indicating that the receiver RX has been reset. The LINE-RESET can be configured to reset or clear all physical layer attributes of interconnect units 22 and 32 to their default values. Host 20 and storage device 30 can exchange information about the LINE-RESET with each other. Phase S710 can be referred to as Line Reset Phase S710. After executing Line Reset Phase S710, Link Start Sequence (LSS) can be started.

[0067] A Link Start Sequence (LSS) can be defined by a specific phase. A trigger event can be used in each phase of the LSS, and each trigger event can be sent multiple times.

[0068] In the first phase S720 of the Link Initiation Sequence (LSS), the LSS can locate the connected channel LANE. To this end, host 20 can send a first trigger event TRG_UPR0 through all transmit channel LANEs. Host 20 can continue sending the first trigger event TRG_UPR0 until a channel LANE connected to storage device 30 (i.e., an available receive channel LANE) receives the first trigger event message. The first trigger event TRG_UPR0 sent by host 20 may include the physical channel number of the transmit channel LANE of host 20 through which the corresponding trigger was sent.

[0069] Furthermore, in the first phase S720, storage device 30 can send the first trigger event TRG_UPR0 through all transmit channels LANE. Storage device 30 can continue sending the first trigger event TRG_UPR0 until a channel LANE connected to host 20 (i.e., an available receive channel LANE) receives the first trigger event message. The first trigger event TRG_UPR0 sent by storage device 30 may include the physical channel number of the transmit channel LANE of storage device 30 through which the corresponding trigger is sent.

[0070] In the second phase S730 of the Link Start Sequence (LSS), the LSS can be realigned with the data channel. To do this, host 20 can send a second trigger event TRG_UPR1 through all transmit channels LANE. Host 20 can continue sending the second trigger event TRG_UPR1 until a channel LANE connected to storage device 30 (i.e., an available receive channel LANE) receives the second trigger event message. The second trigger event TRG_UPR1 sent by host 20 may include information about the transmit channel LANE connected to host 20.

[0071] Furthermore, in the second phase S730, storage device 30 can send the second trigger event TRG_UPR1 through all transmit channels LANE. Storage device 30 can continue sending the second trigger event TRG_UPR1 until a channel LANE connected to host 20 (i.e., an available receive channel LANE) receives the second trigger event message. The second trigger event TRG_UPR1 sent by storage device 30 may include information about the transmit channel LANE connected to storage device 30.

[0072] In the third stage S740 of the Link Initiation Sequence (LSS), the LSS can reflect the number of available LANEs (lanes) connecting the host 20 and storage device 30 in the physical layer attributes of interconnect units 22 and 32. To this end, the host 20 can send a third trigger event TRG_UPR2 through a connected transmit LANE (i.e., an available transmit LANE). The host 20 can continue sending the third trigger event TRG_UPR2 until a receive LANE (i.e., an available receive LANE) connected to the storage device 30 receives the third trigger event message. The third trigger event TRG_UPR2 sent by the host 20 may include the logical channel number of the transmit LANE connected to the host 20.

[0073] Furthermore, in the third phase S740, storage device 30 can send a third trigger event TRG_UPR2 via a transmit channel LANE (i.e., an available transmit channel LANE) connected to storage device 30. Storage device 30 can continue sending the third trigger event TRG_UPR2 until a receive channel LANE (i.e., an available receive channel LANE) connected to host 20 receives the third trigger event message. The third trigger event TRG_UPR2 sent by storage device 30 may include a logical channel number related to the transmit channel LANE connected to storage device 30.

[0074] When executing the third stage S740 of the Link Startup Sequence (LSS), host 20 and storage device 30 may have already matched logical channel numbers for the available LANE. At this point, host 20 and storage device 30 can terminate the Link Startup Sequence (LSS) and perform a capability exchange.

[0075] In phase S750, in order to communicate the architectural requirements of interconnect units 22 and 32, host 20 and storage device 30 can exchange and identify information about the capabilities (CAP) of each other's devices. The architectural requirements of interconnect units 22 and 32 may include, for example, bandwidth, timers, speed gears, termination / non-termination, scrambling, etc. Phase S750 may be referred to as capability exchange phase S750. When performing capability exchange phase S750, interconnect units 22 and 32 collect information about the capabilities (CAP) of each other's devices and can set the physical layer attributes of interconnect units 22 and 32 based on the collected information about the capabilities (CAP).

[0076] In phase S760, to provide a reliable data link, host 20 and storage device 30 can exchange control frames (AFCs). For this purpose, each of host 20 and storage device 30 can send an initial data frame to the other device, and the device that has received the data frame can send a control frame (AFC) back to the device that sent the data frame. The control frame (AFC) can be configured differently from the data frame, and the control frame (AFC) can be used to enable the sending device to recognize that the data frame has been correctly received, and can also be used to notify the available buffer space in the data link layer.

[0077] Figure 8 This is a flowchart illustrating a method for operating a storage system according to an exemplary embodiment of the present invention. Figure 8 Show Figure 1 The operation of the host 20 and storage device 30 in the storage system 10.

[0078] refer to Figure 8 During operation S810, host 20 can exit the HIBERN8 state. Host 20 can switch the LINE of the connected transmit channel LANE in multiple channel LANEs to the DIF-N state and exit the HIBERN8 state.

[0079] In operation S820, host 20 can send an activation period T indicating that the line LINE of the connected transmission channel LANE is in the DIF-N state. ACTIVATE This makes the activation period T ACTIVATE The length is less than the first time period T HS The host 20 issues an activation signal during period T. ACTIVATE The length is less than the first time period T HSActivation period T ACTIVATE Afterwards, host 20 can enter high-speed mode HS-MODE. First time period T HS It could be, for example, 0.9 milliseconds. According to the example embodiment, the first time period T... HS It can be set to something other than 0.9 milliseconds. For example, the first time period T HS It can have values ​​less than 0.9 milliseconds, and it can also have values ​​greater than 0.9 milliseconds (e.g., 1.6 milliseconds).

[0080] Host 20 can send the activation period T of the connected transmit channel LANE to the receive channel LANE connected to storage device 30. ACTIVATE The activation period T ACTIVATE Less than the first time period T HS Storage device 30 can identify the active period T of the connected transmission channel LANE. ACTIVATE The length is less than the first time period T HS You can exit HIBERN8 mode while operating S840 and then enter HS-MODE.

[0081] In operating the S830 and S850, the host 20 and storage device 30 can perform in high-speed mode (HS-MODE) as previously referenced. Figure 7 The Link Startup Sequence (LSS) has been described. The LSS may include, for example, line reset, exchange of trigger events, exchange of capability information, and exchange of control frames. In operations S830 and S850, after the LSS is completed in High Speed ​​Mode (HS-MODE), host 20 and storage device 30 can each be configured to a connection state that allows host 20 and storage device 30 to stably exchange data with each other.

[0082] Figure 9 This is a flowchart illustrating a method for operating a storage system according to an exemplary embodiment of the present invention. Figure 9 Show Figure 1 The operation of the host 20 and storage device 30 in the storage system 10.

[0083] refer to Figure 9 During operation S910, host 20 can exit the HIBERN8 state. Host 20 can switch the LINE of the connected transmit channel LANE in multiple channel LANEs to the DIF-N state and exit the HIBERN8 state.

[0084] In operation S920, host 20 can send an activation period T indicating that the line LINE of the connected transmission channel LANE is in the DIF-N state. ACTIVATE This makes the activation period TACTIVATE The length is equal to or greater than the first time interval T HS The host 20 issues an activation signal during period T. ACTIVATE The length is equal to or greater than the first time interval T HS The active period T of the LANE transmission channel of the connection ACTIVATE Afterwards, host 20 can enter low-speed mode LS-MODE. First time period T HS It could be, for example, 0.9 milliseconds. According to the example embodiment, the first time period T... HS It can be set to something other than 0.9 milliseconds.

[0085] Host 20 can send the activation period T of the connected transmit channel LANE to the receive channel LANE connected to storage device 30. ACTIVATE The activation period T ACTIVATE Equal to or greater than the first time period T HS Storage device 30 can identify the active period T of the connected transmission channel LANE. ACTIVATE The length is equal to or greater than the first time interval T HS You can exit HIBERN8 mode in S940 and then enter LS-MODE.

[0086] In operating S930 and S950, host 20 and storage device 30 can execute the Link Startup Sequence (LSS) in low-speed mode (LS-MODE), as already referenced. Figure 7 The Link Startup Sequence (LSS) has been described. It may include, for example, line reset, exchange of trigger events, exchange of capability information, and exchange of control frames. In operations S930 and S950, after the Link Startup Sequence (LSS) is completed in Low Speed ​​Mode (LS-MODE), host 20 and storage device 30 can each be configured to a connection state that allows host 20 and storage device 30 to stably exchange data with each other.

[0087] Figure 10 This is a flowchart illustrating a method for operating a storage system according to an exemplary embodiment of the present invention. Figure 10 Show operation Figure 1 The method of storage device 30 in storage system 10, and the method is an alternative to the one already referenced Figure 6 An example of the method for operating storage device 30 as described is given.

[0088] refer to Figure 1 , Figure 2 and Figure 10 In operation S1020, storage device 30 can determine the active period T during which the line LINE of the connected channel LANE is in the DIF-N state. ACTIVATEIs the length less than the first time interval T? HS Before operating S1020, the LINE of the connected LANE channel can be, for example, in DIF-Z state instead of DIF-N state. First time period T HS It could be, for example, 0.9 milliseconds. According to the example embodiment, the first time period T... HS It can be set to something other than 0.9 milliseconds. For example, the first time period T HS It can have values ​​less than 0.9 milliseconds, and it can also have values ​​greater than 0.9 milliseconds (e.g., 1.6 milliseconds).

[0089] As determined in operation S1020, during the activation period T of the connected channel LANE... ACTIVATE The length is equal to or greater than the first time interval T HS At this point, the method proceeds to operations S1025 and S1030. In operation S1025, storage device 30 can exit the HIBERN8 state, and then in operation S1030, the link start sequence LSS can be executed in low-speed mode LS-MODE.

[0090] As determined in operation S1020, during the activation period T of the connected channel LANE... ACTIVATE The length is less than the first time period T HS Then, the method proceeds to operations S1040, S1044, and S1050. In operation S1040, storage device 30 receives a first trigger event TRG_UPR0 from host 20 via the connected channel LANE. The first trigger event TRG_UPR0 may include the physical channel number of the transmit channel LANE of the host 20 that triggered it. Upon receiving the first trigger event TRG_UPR0, storage device 30 can locate the channel LANE connected to storage device 30. In operation S1044, storage device 30 can exit the HIBERN8 state, and then, in operation S1050, the Link Start Sequence (LSS) can be executed in high-speed mode (HS-MODE).

[0091] Figure 11A and Figure 11B Each of these is a flowchart illustrating a method for operating a storage system according to an exemplary embodiment of the concept of the present invention. Figure 11A and Figure 11B Each shows the operation Figure 1 The methods for storage device 30 in storage system 10, and these methods are alternatives to those already referenced. Figure 6 An example of the method for operating storage device 30 as described is given.

[0092] refer to Figure 1 , Figure 2 and Figure 11A In operation S1120, storage device 30 can monitor whether the line of any one of the multiple channel LANEs has changed from the DIF-Z state to the DIF-N state. In other words, storage device 30 can monitor whether there are any connected channel LANEs among the multiple channel LANEs.

[0093] As a result of the monitoring in operation S1120, when a connected channel LANE exists, storage device 30 proceeds to operation S1140. In operation S1140, storage device 30 can exit the HIBERN8 state. In some example embodiments, storage device 30 can detect that the DIF-N state of the connected channel LANE has been signaled by host 20 to exit the HIBERN8 state, and can then exit the HIBERN8 state.

[0094] In some example embodiments, in response to detecting that host 20 has exited the HIBERN8 state, storage device 30 can exit the HIBERN8 state and begin sending LINE-RESET without waiting for the time during which the LINE switched by host 20 exits the DIF-N state (i.e., the time during which host 20 terminates activation T). ACTIVATE And start sending the LINE-RESET (the time when the LINE reset begins). Therefore, because the storage device 30 is allowed to exit the HIBERN8 state more quickly, the waiting time can be further reduced. When the storage device 30 detects that the LINE converted by the host 20 has exited the DIF-N state while sending the LINE-RESET, the storage device 30 can identify the length of the period during which the LINE was in the DIF-N state as the active period T. ACTIVATE The length.

[0095] In operation S1150, storage device 30 can identify the existence of a connected channel LANE and can execute the link start sequence LSS in high-speed mode HS-MODE.

[0096] refer to Figure 1 , Figure 2 and Figure 11B In operation S1110b, storage device 30 can exit the HIBERN8 state in response to sensing that host 20 has exited the HIBERN8 state.

[0097] In operation S1120b, storage device 30 can monitor whether the LINE of any one of the multiple channel LANEs has changed from the DIF-Z state to the DIF-N state. In other words, storage device 30 can monitor whether there are any connected channel LANEs among the multiple channel LANEs.

[0098] As a result of the monitoring in operation S1120b, when a connected channel LANE exists, storage device 30 proceeds to operation S1150b. In operation S1150b, storage device 30 can identify the existence of a connected channel LANE and can execute the Link Start Sequence (LSS) in high-speed mode (HS-MODE).

[0099] Figure 12 This is a diagram illustrating a system in which a storage device, according to an exemplary embodiment of the present invention, is applied. Figure 12 The system 1000 can essentially include mobile systems such as mobile phones, smartphones, tablet PCs, wearable devices, healthcare devices, or Internet of Things (IoT) devices. However, Figure 12 The system 1000 is not limited to mobile systems, but may also include PCs, laptops, servers, media players, or automotive devices such as navigation devices. In the following text, letters added to the end of the reference numerals (e.g., the 'a' in 1200a or the 'a' in 1300a) are used to distinguish multiple circuits performing the same function from one another.

[0100] refer to Figure 12 The system 1000 may include a main processor 1100, memories 1200a and 1200b and / or storage devices 1300a and 1300b, and may additionally include one or more of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470 and / or a connection interface 1480.

[0101] The main processor 1100 can control the overall operation of the system 1000, and more specifically, can control the operation of other components constituting the system 1000. The main processor 1100 can be implemented by a general-purpose processor, a special-purpose processor, an application processor, etc.

[0102] The main processor 1100 may include one or more CPU cores 1110, and may also include a controller 1120 for controlling memories 1200a and 1200b and / or storage devices 1300a and 1300b. According to an example embodiment, the main processor 1100 may also include an accelerator block 1130, which is dedicated circuitry for high-speed data computation, such as artificial intelligence (AI) data computation. The accelerator block 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may be implemented by a separate chip physically independent of other components.

[0103] Memory 1200a and 1200b can be used as main memory devices and can include volatile memory such as SRAM and / or DRAM, or can include non-volatile memory such as PRAM and / or RRAM. Memory 1200a and 1200b can also be implemented in the same package as the main processor 1100.

[0104] Storage devices 1300a and 1300b can be used as non-volatile storage devices for storing data regardless of whether they are powered on, and can have a relatively larger storage capacity than memories 1200a and 1200b. Storage devices 1300a and 1300b may include storage controllers 1310a and 1310b, and non-volatile memory (NVM) storage devices 1320a and 1320b that store data under the control of storage controllers 1310a and 1310b, respectively. NVM storage devices 1320a and 1320b may include V-NAND flash memory with a two-dimensional (2D) or three-dimensional (3D) structure, or may include another type of non-volatile memory, such as PRAM and / or RRAM.

[0105] Storage devices 1300a and 1300b may be included in system 1000 while being physically separate from the main processor 1100, or may be implemented in the same package as the main processor 1100. Furthermore, storage devices 1300a and 1300b may be in the form of memory cards, and thus can be detachably coupled to other components of system 1000 via an interface such as connection interface 1480 described below. Storage devices 1300a and 1300b may include, but are not limited to, devices applying standard specifications such as UFS.

[0106] Image capture device 1410 can capture still images or moving images and may include a camera, video camera and / or webcam.

[0107] User input device 1420 can receive various types of data input by the user of system 1000, and may include a touchpad, keypad, keyboard, mouse and / or microphone.

[0108] Sensor 1430 can sense various physical quantities that can be obtained from outside the system 1000, and can convert the sensed physical quantities into electrical signals. Sensor 1430 may include a temperature sensor, a pressure sensor, a brightness sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyroscope.

[0109] Communication device 1440 can perform signal transmission and reception between system 1000 and other devices outside system 1000 according to various communication protocols. Communication device 1440 may include an antenna, transceiver, and / or modem.

[0110] The display 1450 and the speaker 1460 can be used as output devices to output visual and auditory information to the user of the system 1000, respectively.

[0111] The power supply device 1470 can suitably convert the power provided by the battery (not shown) embedded in the system 1000 and / or an external power source, and thus provide the converted power to each component of the system 1000.

[0112] The connection interface 1480 provides connectivity between the system 1000 and external devices connected to and capable of exchanging data with the system 1000. The connection interface 1480 can be implemented using various interfaces, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCIe, NVM Fast (NVMe), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card interface, Multimedia Card (MMC) interface, Embedded Multimedia Card (eMMC) interface, Universal Flash (UFS), Embedded Universal Flash (eUFS), and Compact Flash (CF) card interface.

[0113] Figure 13 This is a diagram illustrating an example embodiment of a UFS system 2000 according to a concept of the present invention. The UFS system 2000 is a system conforming to the UFS standard announced by the Joint Electronic Equipment Commission (JEDEC) and may include a UFS host 2100, a UFS device 2200, and a UFS interface 2300. Figure 12 The above description of System 1000 can also be applied to Figure 13 UFS system 2000, unless related to... Figure 13 This contradicts the following description.

[0114] refer to Figure 13 UFS host 2100 and UFS device 2200 can connect to each other via UFS interface 2300. When Figure 12 When the main processor 1100 is an application processor, the UFS host 2100 can be implemented as part of the corresponding application processor. The UFS host controller 2110 and host memory 2140 can respectively correspond to… Figure 12 The main processor 1100 includes a controller 1120 and memory 1200a and 1200b. The UFS device 2200 can correspond to... Figure 12 Storage devices 1300a and 1300b, and the UFS device controller 2210 and NVM storage device 2220 can respectively correspond to Figure 12 The storage controllers 1310a and 1310b and the NVM storage devices 1320a and 1320b are included.

[0115] UFS host 2100 may include UFS host controller 2110, application 2120, UFS drive 2130, host memory 2140, and / or UFS interconnect (UIC) layer 2150. UFS device 2200 may include UFS device controller 2210, NVM storage device 2220, storage interface 2230, device memory 2240, UIC layer 2250, and / or regulator 2260. NVM storage device 2220 may include multiple storage cells 2221, and each storage cell 2221 may include V-NAND flash memory with a 2D or 3D structure, or may include another type of non-volatile memory, such as PRAM and / or RRAM. UFS device controller 2210 and NVM storage device 2220 may be connected to each other via storage interface 2230. Storage interface 2230 may be implemented to conform to standards such as Toggle or ONFI.

[0116] Application 2120 may refer to a program designed to communicate with UFS device 2200 to use the functionality of UFS device 2200. Application 2120 may send input-output requests to UFS drive 2130 to perform input to UFS device 2200 and output from UFS device. Input-output requests may refer to, but are not limited to, data read requests, write requests, and / or discard requests.

[0117] UFS drive 2130 can manage UFS host controller 2110 through UFS Host Controller Interface (HCI). UFS drive 2130 can translate input-output requests generated by application 2120 into UFS commands defined by the UFS standard, and can transmit the translated UFS commands to UFS host controller 2110. One input-output request can be translated into multiple UFS commands. While UFS commands may be essentially commands defined by the SCSI standard, UFS commands can also be UFS standard-specific commands.

[0118] The UFS host controller 2110 can send UFS commands translated by the UFS driver 2130 to the UIC layer 2250 of the UFS device 2200 via the UIC layer 2150 and the UFS interface 2300. In this process, the UFS host register 2111 of the UFS host controller 2110 can act as a command queue.

[0119] The UIC layer 2150 of the UFS host 2100 may include MIPI M-PHY 2151 and MIPI UniPro 2152, and the UIC layer 2250 of the UFS device 2200 may also include MIPI M-PHY 2251 and MIPI UniPro 2252.

[0120] The UFS interface 2300 may include lines for transmitting a reference clock signal REF_CLK, lines for transmitting a hardware reset signal RESET_n about the UFS device 2200, a pair of lines for transmitting differential input signal pairs DIN_T and DIN_C, and a pair of lines for transmitting differential output signal pairs DOUT_T and DOUT_C.

[0121] The frequency value of the reference clock signal REF_CLK provided from the UFS host 2100 to the UFS device 2200 can be, but is not limited to, one of 19.2MHz, 26MHz, 338.4MHz, and 52MHz. Even when the UFS host 2100 is operating (i.e., even when data transmission and reception between the UFS host 2100 and the UFS device 2200 are being performed), the frequency value of the reference clock signal REF_CLK can be changed. The UFS device 2200 can generate clock signals with various frequencies from the reference clock signal REF_CLK received from the UFS host 2100 using a phase-locked loop (PLL) or similar mechanism. Furthermore, the UFS host 2100 can also set the data rate value between the UFS host 2100 and the UFS device 2200 based on the frequency value of the reference clock signal REF_CLK. In other words, the data rate value can be determined based on the frequency value of the reference clock signal REF_CLK.

[0122] The UFS interface 2300 can support multiple channels, and each channel can be implemented using differential pairs. For example, the UFS interface may include one or more receive channels and one or more transmit channels. Figure 13 In this configuration, the line pairs used to transmit differential input signals DIN_T and DIN_C can form a receiving channel, and the line pairs used to transmit differential output signals DOUT_T and DOUT_C ​​can form a transmitting channel. Although Figure 13 The diagram shows one transmit channel and one receive channel, but the number of transmit and receive channels can be changed.

[0123] The receive and transmit channels can transmit data serially, and due to the separate structure of the receive and transmit channels, full-duplex communication between the UFS host 2100 and the UFS device 2200 is permitted. That is, even when receiving data from the UFS host 2100 via the receive channel, the UFS device 2200 can still transmit data to the UFS host 2100 via the transmit channel. Furthermore, control data such as commands from the UFS host 2100 to the UFS device 2200, as well as user data that the UFS host 2100 intends to store in or read from the NVM storage device 2220 of the UFS device 2200, can be transmitted through the same channel. Therefore, in addition to a pair of receive channels and a pair of transmit channels, no further separate channels for data transmission are required between the UFS host 2100 and the UFS device 2200.

[0124] The UFS device controller 2210 of the UFS device 2200 can fully control the operation of the UFS device 2200. The UFS device controller 2210 can manage the NVM storage device 2220 through logical units (LUs) 2211, which are logical data storage units. The number of LUs 2211 can be, but is not limited to, 8. The UFS device controller 2210 may include a flash translation layer (FTL), and by using the address mapping information of the FTL, it can translate logical data addresses (e.g., logical block addresses (LBAs)) transmitted from the UFS host 2100 into physical data addresses, such as physical block addresses (PBAs). In the UFS system 2000, logical blocks used to store user data can have a specific range of sizes. For example, the minimum size of a logical block can be set to 4 kilobytes.

[0125] When a command from the UFS host 2100 is input to the UFS device 2200 through the UIC layer 2250, the UFS device controller 2210 can perform the operation according to the input command, and when the operation is completed, the UFS device controller 2210 can send a completion response to the UFS host 2100.

[0126] For example, when UFS host 2100 intends to store user data in UFS device 2200, UFS host 2100 can send a data storage command to UFS device 2200. When it receives a response from UFS device 2200 indicating that it is ready to receive user data, UFS host 2100 can send the user data to UFS device 2200. UFS device controller 2210 can temporarily store the received user data in device memory 2240, and based on the FTL address mapping information, can store the user data temporarily stored in device memory 2240 in a selected location of NVM storage device 2220.

[0127] As another example, when UFS host 2100 intends to read user data stored in UFS device 2200, UFS host 2100 can send a data read command to UFS device 2200. UFS device controller 2210, having received the data read command, can read the user data from NVM storage device 2220 based on the data read command, and can temporarily store the read user data in device memory 2240. During this data read process, UFS device controller 2210 can detect and correct errors in the read user data using embedded error correction code (ECC) circuitry (not shown). Furthermore, UFS device controller 2210 can send the user data temporarily stored in device memory 2240 to UFS host 2100. Additionally, UFS device controller 2210 may also include Advanced Encryption Standard (AES) circuitry (not shown), and the AES circuitry can encrypt or decrypt data input to UFS device controller 2210 using a symmetric key algorithm.

[0128] UFS host 2100 can store commands to be sent to UFS device 2200 in UFS host register 2111, which can be used as a command queue in sequence, and can send commands to UFS device 2200 in sequence. In some example embodiments, even while a previously sent command is still being processed by UFS device 2200 (i.e., even before UFS host 2100 receives a notification indicating that processing of a previously sent command has been completed by UFS device 2200), UFS host 2100 can send the next pending command in the command queue to UFS device 2200, so UFS device 2200 can also receive the next command from UFS host 2100 while processing a previously sent command. The maximum number of commands that can be stored in the command queue (i.e., the queue depth) can be, for example, 332. Furthermore, the command queue can be implemented as a circular queue type, wherein the start and end of the command sequence stored in the queue are indicated by a head pointer and a tail pointer, respectively.

[0129] Each of the plurality of memory cells 2221 may include a memory cell array and control circuitry for controlling the operation of the memory cell array. The memory cell array may include a 2D memory cell array or a 3D memory cell array. The memory cell array may include a plurality of memory cells, and each memory cell may be a single-level cell (SLC) storing 1 bit of information, or a cell storing 2 or more bits of information, such as a multi-level cell (MLC), triple-level cell (TLC), or quadruple-level cell (QLC). A 3D memory cell array may include vertically oriented vertical NAND strings, such that at least one memory cell is located on top of another memory cell.

[0130] VCC, VCCQ1, VCCQ2, etc., can be used as power supply voltage inputs to the UFS device 2200. VCC, as the main power supply voltage of the UFS device 2200, can have a value from 2.4V to 3.6V. VCCQ1, used to provide a voltage in a low voltage range, is mainly used in the UFS device controller 2210 and can have a value from 1.14V to 1.26V. VCCQ2, used to provide a voltage in a range higher than VCCQ1 and lower than VCC, is mainly used in the input-output interface of devices such as the MIPI M-PHY 2251 and can have a value from 1.7V to 1.95V. The aforementioned power supply voltages can be provided to the various components of the UFS device 2200 via a regulator 2260. The regulator 2260 can be implemented as a collection of unit regulators respectively connected to the aforementioned different power supply voltages.

[0131] Figures 14A to 14C This is a diagram showing the shape of a UFS card. (When referring to...) Figure 13 When the described UFS device 2200 is implemented in the form of a UFS card 4000, the appearance of the UFS card 4000 can be as follows: Figures 14A to 14C As shown.

[0132] Figure 14A An example top view of a UFS card 4000 is shown. (Reference) Figure 14A It can be confirmed that the UFS Card 4000 follows a shark-shaped design overall. Regarding... Figure 14A The UFS card 4000 can have size values ​​as listed in Table 1 below.

[0133] [Table 1]

[0134] T1 9.70 T2 15.00 T3 11.00 T4 9.70 T5 5.15 T6 0.25 T7 0.60 T8 0.75 T9 R0.80

[0135] Figure 14B An example showing a side view of a UFS card 4000. About Figure 14B The UFS card 4000 can have size values ​​as listed in Table 2 below.

[0136] [Table 2]

[0137] S1 0.74±0.06 S2 0.30 S3 0.52 S4 1.20 S5 1.05 S6 1.00

[0138] Figure 14C An example showing the bottom view of a UFS card 4000. (Reference) Figure 14C Multiple pins for electrical contact with the UFS slot can be formed on the bottom surface of the UFS card 4000, and the function of each pin will be described below. Based on the symmetry between the top and bottom surfaces of the UFS card 4000, refer to... Figure 14A Some of the dimensions described in Table 1 (e.g., T1 to T5 and T9) can also be applied. Figure 14C The image shows a bottom view of the UFS card 4000.

[0139] Multiple pins for electrical connection to the UFS host can be formed on the bottom surface of the UFS card 4000, and according to Figure 14C The total number of pins can be 12. Each pin can have a rectangular shape and a corresponding signal name, such as... Figure 14C As shown. General information about each pin can be found in Table 3 below, and also in the information above regarding... Figure 13 The given description.

[0140] [Table 3]

[0141]

[0142]

[0143] Figure 15 This is a block diagram illustrating an example embodiment of an NVM storage device according to a concept of the present invention.

[0144] refer to Figure 15 The NVM storage device 2220a may include a memory device 2224 and a memory controller 2222. The NVM storage device 2220a may support multiple paths CH1 to CHm, and the memory device 2224 may be connected to the memory controller 2222 via multiple paths CH1 to CHm. For example, the NVM storage device 2220a may be implemented by a storage device such as a solid-state drive (SSD).

[0145] Memory device 2224 may include a plurality of non-volatile memory devices NVM11 to NVMmn. Each of the non-volatile memory devices NVM11 to NVMmn may be connected to one of a plurality of paths CH1 to CHm via a corresponding path. For example, non-volatile memory devices NVM11 to NVM1n may be connected to a first path CH1 via paths W11 to W1n, and non-volatile memory devices NVM21 to NVM2n may be connected to a second path CH2 via paths W21 to W2n. In an example embodiment, each of the non-volatile memory devices NVM11 to NVMmn may be implemented by any memory cell capable of operating according to individual commands from memory controller 2222. For example, although each of the non-volatile memory devices NVM11 to NVMmn may be implemented by a chip or die, the inventive concept is not limited thereto.

[0146] The memory controller 2222 can send signals to and receive signals from the memory device 2224 through multiple channels CH1 to CHm. For example, the memory controller 2222 can send commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the memory device 2224 through channels CH1 to CHm, or it can receive data DATAa to DATAm from the memory device 2224.

[0147] The memory controller 2222 can select one of the non-volatile memory devices connected to the corresponding channel through each channel, and can send signals to and receive signals from the selected non-volatile memory device. For example, the memory controller 2222 can select non-volatile memory device NVM11 from the non-volatile memory devices NVM11 to NVM1n connected to the first channel CH1. The memory controller 2222 can send command CMDa, address ADDRa, and data DATAa to the selected non-volatile memory device NVM11 through the first channel CH1, or can receive data DATAa from the selected non-volatile memory device NVM11.

[0148] The memory controller 2222 can send signals to and receive signals from the memory device 2224 in parallel through different channels. For example, the memory controller 2222 can send the command CMDb to the memory device 2224 through the second channel CH2, while simultaneously sending the command CMDa to the memory device 2224 through the first channel CH1. For example, the memory controller 2222 can receive data DATAb from the memory device 2224 through the second channel CH2, while simultaneously receiving data DATAa from the memory device 2224 through the first channel CH1.

[0149] The memory controller 2222 can control the overall operation of the memory device 2224. The memory controller 2222 can control each of the non-volatile memory devices NVM11 to NVM1n connected to the paths CH1 to CHm by sending signals to the paths CH1 to CHm. For example, the memory controller 2222 can control the selection of one of the non-volatile memory devices NVM11 to NVM1n by sending the command CMDa and address ADDRa to the first path CH1.

[0150] Each of the non-volatile memory devices NVM11 to NVMmn can be operated under the control of the memory controller 2222. For example, non-volatile memory device NVM11 can program data DATAa according to the command CMDa, address ADDRa, and data DATAa provided to the first path CH1. For example, non-volatile memory device NVM21 can read data DATAb according to the command CMDb and address ADDRb provided to the second path CH2, and can send the read data DATAb to the memory controller 2222.

[0151] Although Figure 15 The memory device 2224 communicates with the memory controller 2222 through m paths and includes n non-volatile memory devices corresponding to each path, but the number of paths and the number of non-volatile memory devices connected to a path can vary.

[0152] Figure 16 This is a block diagram illustrating an NVM storage device according to an exemplary embodiment of the concept of the present invention. (Reference) Figure 16 The NVM storage device 2220b may include a memory device 2226 and a memory controller 2222. The memory device 2226 may correspond to a memory controller based on... Figure 15 One of the multiple pathways CH1 to CHm communicates with one of the non-volatile memory devices NVM11 to NVMmn via the memory controller 2222. The memory controller 2222 may correspond to... Figure 15 The memory controller 2222.

[0153] The memory device 2226 may include first pins to eighth pins P11 to P18, memory interface circuitry 2310, control logic circuitry 2320, and / or memory cell array 2330.

[0154] The memory interface circuit 2310 can receive the chip enable signal nCE from the memory controller 2222 via the first pin P11. The memory interface circuit 2310 can send signals to and receive signals from the memory controller 2222 via the second to eighth pins P12 to P18 based on the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (e.g., low level), the memory interface circuit 2310 can send signals to and receive signals from the memory controller 2222 via the second to eighth pins P12 to P18.

[0155] The memory interface circuit 2310 can receive the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE from the memory controller 2222 via pins 2 to 4, P12 to P14. The memory interface circuit 2310 can receive the data signal DQ from the memory controller 2222, or can send the data signal DQ to the memory controller 2222 via pin 7, P17. Command CMD, address ADDR, and data can be transmitted via the data signal DQ. For example, the data signal DQ can be transmitted via multiple data signal lines. In some example embodiments, pin 7, P17, may include multiple pins corresponding to multiple data signals.

[0156] The memory interface circuit 2310 can obtain the command CMD from the data signal DQ received during the enable period (e.g., high level state) of the command latch enable signal CLE based on the toggle timing of the write enable signal nWE. The memory interface circuit 2310 can also obtain the address ADDR from the data signal DQ received during the enable period (e.g., high level state) of the address latch enable signal ALE based on the toggle timing of the write enable signal nWE.

[0157] In the example embodiment, the write enable signal nWE can be held in a static state (e.g., high or low) and then can be switched between high and low. For example, the write enable signal nWE can be switched during a period in which command CMD or address ADDR is sent. Therefore, the memory interface circuit 2310 can obtain command CMD or address ADDR based on the switching timing of the write enable signal nWE.

[0158] The memory interface circuit 2310 can receive the read enable signal nRE from the memory controller 2222 via its fifth pin P15. The memory interface circuit 2310 can receive the data strobe signal DQS from the memory controller 2222 via its sixth pin P16, or send the data strobe signal DQS to the memory controller 2222.

[0159] In the data output operation of memory device 2226, before data DATA is output, memory interface circuit 2310 can receive a switched read enable signal nRE via pin 5 P15. Memory interface circuit 2310 can generate a switched data strobe signal DQS based on the switching of the read enable signal nRE. For example, memory interface circuit 2310 can generate a data strobe signal DQS that begins switching after a preset delay (e.g., tDQSRE) from the start time of the switching of the read enable signal nRE. Memory interface circuit 2310 can send a data signal DQ including data DATA based on the switching timing of the data strobe signal DQS. Therefore, data DATA can be sent to memory controller 2222 in alignment with the switching timing of the data strobe signal DQS.

[0160] In the data input operation of memory device 2226, when a data signal DQ including data DATA is received from memory controller 2222, memory interface circuit 2310 can receive a data strobe signal DQS that switches along with the data DATA from memory controller 2222. Memory interface circuit 2310 can obtain data DATA from data signal DQ based on the switching timing of data strobe signal DQS. For example, memory interface circuit 2310 can obtain data DATA by sampling data signal DQ at the rising and falling edges of data strobe signal DQS.

[0161] The memory interface circuit 2310 can send a ready / busy output signal nR / B via pin 8, P18. The memory interface circuit 2310 can send the status information of the memory device 2226 to the memory controller 2222 via the ready / busy output signal nR / B. When the memory device 2226 is in a busy state (i.e., when internal operations of the memory device 2226 are being executed), the memory interface circuit 2310 can send the ready / busy output signal nR / B indicating the busy state to the memory controller 2222. When the memory device 2226 is in a ready state (i.e., when internal operations of the memory device 2226 are not being executed or completed), the memory interface circuit 2310 can send the ready / busy output signal nR / B indicating the ready state to the memory controller 2222. For example, when memory device 2226 reads data DATA from memory cell array 2330 in response to a page read command, memory interface circuit 2310 may send a ready / busy output signal nR / B indicating a busy state (e.g., low level) to memory controller 2222. Similarly, when memory device 2226 programs data DATA into memory cell array 2330 in response to a programming command, memory interface circuit 2310 may send a ready / busy output signal nR / B indicating a busy state (e.g., low level) to memory controller 2222.

[0162] The control logic circuit 2320 can comprehensively control various operations of the memory device 2226. The control logic circuit 2320 can receive commands / addresses (CMD / ADDR) obtained from the memory interface circuit 2310. The control logic circuit 2320 can generate control signals for controlling other components of the memory device 2226 based on the received commands / addresses (CMD / ADDR). For example, the control logic circuit 2320 can generate various control signals for programming data DATA into or reading data DATA from the memory cell array 2330.

[0163] Under the control of the control logic circuit 2320, the memory cell array 2330 can store data DATA obtained from the memory interface circuit 2310. Under the control of the control logic circuit 2320, the memory cell array 2330 can output the stored data DATA to the control logic circuit 2320.

[0164] The memory cell array 2330 may include a plurality of memory cells. For example, the plurality of memory cells may include flash memory cells. However, the inventive concept is not limited thereto, and the memory cells may include RRAM cells, ferroelectric RAM (FRAM) cells, PRAM cells, thyristor RAM (TRAM) cells, or MRAM cells. In the following, exemplary embodiments of the inventive concept in which the memory cells are NAND flash memory cells will be described primarily.

[0165] The memory controller 2222 may include first pins to eighth pins P21 to P28 and controller interface circuitry 2410. The first pins to eighth pins P21 to P28 may correspond to the first pins to eighth pins P11 to P18 of the memory device 2226.

[0166] The controller interface circuit 2410 can send a chip enable signal nCE to the memory device 2226 via the first pin P21. The controller interface circuit 2410 can send signals to and receive signals from the memory device 2226 selected by the chip enable signal nCE via the second to eighth pins P22 to P28.

[0167] The controller interface circuit 2410 can send the command enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the memory device 2226 via pins 2 to 4 (P22 to P24). The controller interface circuit 2410 can send the data signal DQ to the memory device 2226 or receive the data signal DQ from the memory device 2226 via pin 7 (P27).

[0168] The controller interface circuit 2410 can send a data signal DQ including the command CMD or address ADDR along with a write enable signal nWE that is being switched. The controller interface circuit 2410 can send the data signal DQ including the command CMD by sending a command latch enable signal CLE with an enabled state, and the controller interface circuit 2410 can send the data signal DQ including the address ADDR by sending an address latch enable signal ALE with an enabled state.

[0169] The controller interface circuit 2410 can send the read enable signal nRE to the memory device 2226 via its fifth pin P25. The controller interface circuit 2410 can receive the data strobe signal DQS from the memory device 2226 or send the data strobe signal DQS to the memory device 2226 via its sixth pin P26.

[0170] In the data output operation of memory device 2226, controller interface circuit 2410 can generate a switching read enable signal nRE and send the read enable signal nRE to memory device 2226. For example, before data DATA is output, controller interface circuit 2410 can generate a read enable signal nRE that changes from a static state (e.g., high level or low level) to a switching state. Therefore, in memory device 2226, a data strobe signal DQS based on the switching of the read enable signal nRE can be generated. Controller interface circuit 2410 can receive a data signal DQ including data DATA and the switching data strobe signal DQS from memory device 2226. Controller interface circuit 2410 can obtain data DATA from data signal DQ based on the switching timing of data strobe signal DQS.

[0171] In the data input operation of memory device 2226, controller interface circuit 2410 can generate a switching data strobe signal DQS. For example, controller interface circuit 2410 can generate a data strobe signal DQS that changes from a static state (e.g., high or low) to a switching state before data DATA is transmitted. Controller interface circuit 2410 can send a data signal DQ, including data DATA, to memory device 2226 based on the switching timing of the data strobe signal DQS.

[0172] The controller interface circuit 2410 can receive the ready / busy output signal nR / B from the memory device 2226 via pin 8 P28. The controller interface circuit 2410 can determine the status information of the memory device 2226 based on the ready / busy output signal nR / B.

[0173] Figure 17 It is shown Figure 16 Example block diagram of a memory device. (See reference) Figure 17 The memory device 2226 may include control logic circuitry 2320, a memory cell array 2330, a page buffer unit 2340, a voltage generator 2350, and / or a row decoder 3394. Although in Figure 17 Not shown, but memory device 2226 may also include Figure 16 The memory interface circuit 2310 shown may also include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, etc.

[0174] The control logic circuit 2320 can comprehensively control various operations within the memory device 2226. The control logic circuit 2320 can output various control signals in response to commands CMD and / or addresses ADDR from the memory interface circuit 2310. For example, the control logic circuit 2320 can output voltage control signals CTRL_vol, row address X-ADDR, and column address Y-ADDR.

[0175] The memory cell array 2330 may include multiple memory cell blocks BLK1 to BLKz (where z is a positive integer), and each of the multiple memory cell blocks BLK1 to BLKz may include multiple memory cells. The memory cell array 2330 can be connected to the page buffer unit 2340 via bit line BL, and can be connected to the line decoder 3394 via word line WL, serial select line SSL, and ground select line GSL.

[0176] In an example embodiment, the memory cell array 2330 may include a 3D memory cell array, and the 3D memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells respectively connected to word lines vertically stacked on a substrate. U.S. Patent Publications 7,679,133, 8,553,466, 8,654,587, 8,559,235, and 2011 / 0233648 are incorporated herein by reference. In an example embodiment, the memory cell array 2330 may include a 2D memory cell array, and the 2D memory cell array may include a plurality of NAND strings arranged in row and column directions.

[0177] Page buffer unit 2340 may include multiple page buffers PB1 to PBn (where n is an integer equal to or greater than 3), and the multiple page buffers PB1 to PBn may be connected to memory cells via multiple bit lines BL. Page buffer unit 2340 may select at least one bit line BL in response to column address Y-ADDR. Page buffer unit 2340 may operate as a write driver or a sense amplifier depending on the operating mode. For example, during a programming operation, page buffer unit 2340 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line. During a read operation, page buffer unit 2340 may sense the data stored in the memory cell by sensing the current or voltage of the selected bit line.

[0178] The voltage generator 2350 can generate various voltages for performing programming, reading, and erasing operations based on the voltage control signal CTRL_vol. For example, the voltage generator 2350 can generate programming voltage, reading voltage, programming verification voltage, erasing voltage, etc., as word line voltage VWL.

[0179] In response to the row address X-ADDR, the row decoder 3394 can select one of multiple word lines WL and one of multiple string select lines SSL. For example, during a programming operation, the row decoder 3394 can apply a programming voltage and a programming verification voltage to the selected word line, and during a read operation, the row decoder 3394 can apply a read voltage to the selected word line.

[0180] Figure 18 This diagram illustrates an example embodiment of a 3D V-NAND structure applicable to a UFS device according to an embodiment of the present invention. When the storage module of the UFS device is implemented using 3D V-NAND flash memory, the multiple memory blocks constituting the storage module can be independently... Figure 18 The equivalent circuit shown is illustrated.

[0181] Figure 18 The memory block BLKi shown represents a 3D memory block formed in a 3D structure on a substrate. For example, multiple NAND strings included in the memory block BLKi can be formed in a direction perpendicular to the substrate.

[0182] refer to Figure 18 The memory block BLKi may include multiple memory NAND strings NS11 to NS33 connected between bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the multiple memory NAND strings NS11 to NS33 may include a string select transistor SST, multiple memory cells MC1 to MC8, and a ground select transistor GST. Although Figure 18 Each of the multiple memory NAND strings NS11 to NS33 is shown to include eight memory cells MC1 to MC8, but the inventive concept is not limited thereto.

[0183] The string select transistor SST can be connected to the corresponding string select line SSL1, SSL2, or SSL3. Multiple memory cells MC1 to MC8 can be connected to their respective gate lines GTL1 to GTL8. Gate lines GTL1 to GTL8 can correspond to word lines, and some of GTL1 to GTL8 can correspond to dummy word lines. The ground select transistor GST can be connected to the corresponding ground select line GSL1, GSL2, or GSL3. The string select transistor SST can be connected to the corresponding bit lines BL1, BL2, or BL3, and the ground select transistor GST can be connected to the common source line CSL.

[0184] Word lines at the same height (e.g., WL1) can be connected together, ground select lines GSL1, GSL2, and GSL3 can be separated from each other, and serial select lines SSL1, SSL2, and SSL3 can be separated from each other. Although Figure 18 The memory block BLKi is shown connected to eight gate lines GTL1 to GTL8 and three bit lines BL1, BL2 and BL3, but the inventive concept is not limited thereto.

[0185] Figure 19 This is a diagram illustrating a BVNAND structure applicable to UFS devices, based on an example embodiment of the concept according to the present invention.

[0186] refer to Figure 19 The memory device 2226 may have a chip-to-chip (C2C) structure. A C2C structure can refer to a structure formed by fabricating an upper chip including cell regions (CELL) on a first wafer, fabricating a lower chip including peripheral circuit regions (PERI) on a second wafer separate from the first wafer, and then bonding the upper and lower chips together. Here, the bonding process may include a method of forming bonding metals electrically connected on the uppermost metal layer of the upper chip and on the uppermost metal layer of the lower chip. For example, when using copper-to-copper (Cu-to-Cu) bonding, the bonding metal may include copper (Cu). However, the example embodiment may not be limited to this. For example, the bonding metal may also be formed of aluminum (Al) or tungsten (W).

[0187] Each of the peripheral circuit region PERI and cell region CELL of memory device 2226 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0188] The Peripheral Circuit Area (PERI) may include a first substrate 3210, an interlayer insulating layer 3215, a plurality of circuit elements 3220a, 3220b, and 3220c formed on the first substrate 3210, first metal layers 3230a, 3230b, and 3230c respectively connected to the plurality of circuit elements 3220a, 3220b, and 3220c, and second metal layers 3240a, 3240b, and 3240c formed on the first metal layers 3230a, 3230b, and 3230c. In an example embodiment, the first metal layers 3230a, 3230b, and 3230c may be formed of tungsten, which has a relatively high resistivity, and the second metal layers 3240a, 3240b, and 3240c may be formed of copper, which has a relatively low resistivity.

[0189] exist Figure 19In the illustrated example embodiment, although only the first metal layers 3230a, 3230b, and 3230c and the second metal layers 3240a, 3240b, and 3240c are shown and described, the example embodiment is not limited thereto, and one or more additional metal layers may be further formed on the second metal layers 3240a, 3240b, and 3240c. At least a portion of the one or more additional metal layers formed on the second metal layers 3240a, 3240b, and 3240c may be formed of aluminum or the like, having a lower resistivity than the copper used to form the second metal layers 3240a, 3240b, and 3240c.

[0190] An interlayer insulating layer 3215 may be disposed on the first substrate 3210 and cover multiple circuit elements 3220a, 3220b and 3220c, first metal layers 3230a, 3230b and 3230c and second metal layers 3240a, 3240b and 3240c. The interlayer insulating layer 3215 may include an insulating material, such as silicon oxide, silicon nitride, etc.

[0191] Lower bonding metals 3271b and 3272b can be formed on the second metal layer 3240b in the word line bonding area (WLBA). In the WLBA, the lower bonding metals 3271b and 3272b in the peripheral circuit area (PERI) can be electrically bonded to the upper bonding metals 3371b and 3372b in the cell area (CELL). The lower bonding metals 3271b and 3272b, as well as the upper bonding metals 3371b and 3372b, can be formed of aluminum, copper, tungsten, or the like. Furthermore, the upper bonding metals 3371b and 3372b in the cell area (CELL) can be referred to as first metal pads, and the lower bonding metals 3271b and 3272b in the peripheral circuit area (PERI) can be referred to as second metal pads.

[0192] A cell region may include at least one memory block. A cell region (CELL) may include a second substrate 3310 and a common source line 3320. On the second substrate 3310, multiple word lines 3331 to 3338 (e.g., 3330) may be stacked in a direction perpendicular to the upper surface of the second substrate 3310 (Z-axis direction). At least one string select line and at least one ground select line may be arranged above and below the multiple word lines 3330, respectively, and the multiple word lines 3330 may be disposed between the at least one string select line and the at least one ground select line.

[0193] In the bit line bonding area BLBA, the channel structure CH can extend in a direction perpendicular to the upper surface of the second substrate 3310 (Z-axis direction) and pass through multiple word lines 3330, at least one string select line, and at least one ground select line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer can be electrically connected to the first metal layer 3350c and the second metal layer 3360c. For example, the first metal layer 3350c can be a bit line contact, and the second metal layer 3360c can be a bit line. In an example embodiment, the bit line 3360c can extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 3310.

[0194] exist Figure 19 In the example embodiment shown, the area where the channel structure CH, bit line 3360c, etc., are disposed can be defined as the bit line bonding area BLBA. In the bit line bonding area BLBA, bit line 3360c can be electrically connected to circuit element 3220c that provides page buffer 3393 in peripheral circuit area PERI. Bit line 3360c can be connected to upper bonding metals 3371c and 3372c in cell area CELL, and upper bonding metals 3371c and 3372c can be connected to lower bonding metals 3271c and 3272c that are connected to circuit element 3220c connected to page buffer 3393.

[0195] In the word line bonding area (WLBA), multiple word lines 3330 can extend in a second direction (X-axis direction) parallel to the upper surface of the second substrate 3310 and perpendicular to the first direction, and can be connected to multiple cell contact plugs 3341 to 3347 (e.g., 3340). The multiple word lines 3330 and the multiple cell contact plugs 3340 can be connected to each other in pads provided by at least a portion of the multiple word lines 3330 extending at different lengths in the second direction. A first metal layer 3350b and a second metal layer 3360b can be sequentially connected to the upper portion of the multiple cell contact plugs 3340 connected to the multiple word lines 3330. The multiple cell contact plugs 3340 can be connected to the peripheral circuit region PERI via upper bonding metals 3371b and 3372b of the cell region CELL and lower bonding metals 3271b and 3272b of the peripheral circuit region PERI in the word line bonding area (WLBA).

[0196] Multiple unit contact plugs 3340 can be electrically connected to circuit element 3220b forming line decoder 3394 in peripheral circuit region PERI. In an example embodiment, the operating voltage of circuit element 3220b of line decoder 3394 may differ from the operating voltage of circuit element 3220c forming page buffer 3393. For example, the operating voltage of circuit element 3220c forming page buffer 3393 may be greater than the operating voltage of circuit element 3220b forming line decoder 3394.

[0197] A common source contact plug 3380 can be disposed in the external pad bonding area PA. The common source contact plug 3380 can be formed of a conductive material such as metal, metal compound, or polysilicon, and can be electrically connected to the common source line 3320. A first metal layer 3350a and a second metal layer 3360a can be sequentially stacked on top of the common source contact plug 3380. For example, the area in which the common source contact plug 3380, the first metal layer 3350a, and the second metal layer 3360a are disposed can be defined as the external pad bonding area PA.

[0198] Input-output pads 33205 and 3305 can be set in the external pad bonding area PA. (See reference) Figure 19 A lower insulating film 3201 covering the lower surface of the first substrate 3210 can be formed below the first substrate 3210, and a first input-output pad 3205 can be formed on the lower insulating film 3201. The first input-output pad 3205 can be connected to at least one of a plurality of circuit elements 3220a, 3220b, and 3220c disposed in the peripheral circuit region PERI via a first input-output contact plug 3203, and can be separated from the first substrate 3210 via the lower insulating film 3201. In addition, a side insulating film can be disposed between the first input-output contact plug 3203 and the first substrate 3210 to electrically separate the first input-output contact plug 3203 and the first substrate 3210.

[0199] refer to Figure 19 An upper insulating film 3301 covering the upper surface of the second substrate 3310 can be formed on the second substrate 3310, and a second input-output pad 3305 can be disposed on the upper insulating layer 3301. The second input-output pad 3305 can be connected to at least one of a plurality of circuit elements 3220a, 3220b, and 3220c disposed in the peripheral circuit region PERI via a second input-output contact plug 3303. In an example embodiment, the second input-output pad 3305 is electrically connected to circuit element 3220a.

[0200] According to the example embodiment, the second substrate 3310 and the common source line 3320 may not be located in the area where the second input-output contact plug 3303 is located. Furthermore, the second input-output pad 3305 may not overlap with the word line 3330 in the third direction (Z-axis direction). Reference Figure 19 The second input-output contact plug 3303 can be separated from the second substrate 3310 in a direction parallel to the upper surface of the second substrate 3310, and can pass through the interlayer insulating layer 3315 of the cell region to connect to the second input-output pad 3305.

[0201] According to an example embodiment, the first input-output pad 3205 and the second input-output pad 3305 can be selectively formed. For example, the memory device 2226 may include only the first input-output pad 3205 disposed on the first substrate 3210 or the second input-output pad 3305 disposed on the second substrate 3310. Optionally, the memory device 2226 may include the first input-output pad 3205 and the second input-output pad 3305.

[0202] In each of the external pad bonding area PA and bit line bonding area BLBA, which are respectively included in the cell area CELL and the peripheral circuit area PERI, the metal pattern set on the topmost metal layer can be set as a virtual pattern, or the topmost metal layer can be absent.

[0203] In the external pad bonding area PA, the memory device 2226 may include a lower metal pattern 3273a corresponding to an upper metal pattern 3372a formed in the uppermost metal layer of the cell region CELL, and having the same cross-sectional shape as the upper metal pattern 3372a of the cell region CELL in the uppermost metal layer of the peripheral circuit region PERI, so as to be connected to each other. In the peripheral circuit region PERI, the lower metal pattern 3273a formed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a contact. Similarly, in the external pad bonding area PA, an upper metal pattern 3372a corresponding to the lower metal pattern 3273a formed in the uppermost metal layer of the peripheral circuit region PERI and having the same shape as the lower metal pattern 3273a of the peripheral circuit region PERI may be formed in the uppermost metal layer of the cell region CELL.

[0204] Lower bonding metals 3271b and 3272b can be formed on the second metal layer 3240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 3271b and 3272b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 3371b and 3372b of the cell region CELL via copper-to-copper bonding.

[0205] Furthermore, in the bit line bonding region BLBA, an upper metal pattern 3392, corresponding to the lower metal pattern 3252 formed in the uppermost metal layer of the peripheral circuit region PERI and having the same cross-sectional shape as the lower metal pattern 3252 of the peripheral circuit region PERI, can be formed in the uppermost metal layer of the cell region CELL. No contacts may be formed on the upper metal pattern 3392 formed in the uppermost metal layer of the cell region CELL.

[0206] In the example embodiment, corresponding to the metal pattern formed in the uppermost metal layer of one of the cell region (CELL) and the peripheral circuit region (PERI), a reinforced metal pattern having the same cross-sectional shape as the metal pattern can be formed in the uppermost metal layer of the other of the cell region (CELL) and the peripheral circuit region (PERI). No contacts may be formed on the reinforced metal pattern.

[0207] One or more of the elements disclosed above may include or be implemented in one or more processing circuits, such as hardware including logic circuits; hardware / software combinations, such as a processor executing software; or combinations thereof. For example, more specifically, the processing circuits may include, but are not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0208] While the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. A method for link startup of a device comprising multiple channels, the method comprising: Data communication is established through the connected sending channel and the connected receiving channel among the multiple channels; The length of the activation period is set to be less than the first time period, during which the line of the connected transmission channel has a negative differential line voltage DIF-N; An activation period shorter than the first time period is sent from the transmission channel of the connection to the receiving channel of the connection; The connected receiving channel receives an activation period shorter than the first time period; It is determined that the activation period is shorter than the first time period; as well as Based on an activation period shorter than the first time period, the link startup is performed in high-speed mode through the transmission channel and the reception channel of the connection.

2. The method according to claim 1, wherein, The first time period was set to 0.9 milliseconds.

3. The method according to claim 1, wherein, The first time period was set to 1.6 milliseconds.

4. The method according to claim 1, further comprising: Set the length of the activation period of the transmission channel of the connection to be greater than the first time period; An activation period longer than the first time period is sent from the transmitting channel of the connection to the receiving channel of the connection; The receiving channel of the connection receives an activation period longer than the first time period; as well as Based on an activation period longer than the first time period, the link startup is performed in low-speed mode through the transmission channel and the reception channel of the connection.

5. The method according to claim 1, wherein, The transmission channel of the connection sends an activation period shorter than the first time period to the receiving channel of the connection, which includes the first device connected to the transmission channel of the connection entering the high-speed mode.

6. The method according to claim 1, wherein, The activation period received by the receiving channel of the connection for a period shorter than the first time period includes the second device connected to the receiving channel of the connection entering the high-speed mode.

7. The method according to claim 1, wherein, The activation period received by the connected receiving channel for periods shorter than the first time period includes: The second device connected to the receiving channel of the connection exits the sleep (HIBERN8) state, which is a power-saving state; Reset the physical layer properties of the interconnect unit of the second device to their default values; and The second device enters the high-speed mode.

8. The method according to claim 1, wherein, Performing the link startup in the high-speed mode via the transmission channel and the reception channel of the connection includes: Execute a first trigger event, wherein a first device connected to the transmit channel of the connection sends the physical channel number of the transmit channel of the connection to a second device connected to the receive channel of the connection, and wherein the second device sends the physical channel number of the receive channel of the connection to the first device; Execute a second trigger event, wherein the first device sends information about the transmission channel of the connection to the second device, and wherein the second device sends information about the reception channel of the connection to the first device; and A third trigger event is executed, wherein the first device sends the logical channel number of the transmission channel of the connection to the second device, and wherein the second device sends the logical channel number of the reception channel of the connection to the first device.

9. The method of claim 8 further comprises, before executing the first triggering event, resetting the physical layer attributes of the interconnection unit of the first device to default values, and resetting the physical layer attributes of the interconnection unit of the second device to default values.

10. The method of claim 8, further comprising: After the third triggering event is executed, the first device and the second device exchange capability information with each other, and the first device and the second device identify each other's capability information; as well as The first device and the second device exchange control frames indicating that the initial data frames sent between the first device and the second device have been correctly received, and the first device and the second device identify each other's control frames.

11. A method for initiating a link between a first device and a second device interconnected via multiple channels, the method comprising: The first device switches the line of at least one of the plurality of channels from the zero differential line voltage DIF-Z state to the negative differential line voltage DIF-N state; The second device monitors whether a channel transitions from the DIF-Z state to the DIF-N state; As a result of the monitoring, the second device identifies the channel of the connection that transitions from the DIF-Z state to the DIF-N state; as well as Based on the channel of the connection, the transition from the DIF-Z state to the DIF-N state is identified, and the link startup between the first device and the second device is performed in high-speed mode.

12. The method of claim 11, further comprising the first device switching the connected channel from the DIF-Z state to the DIF-N state and exiting the sleep (HIBERN8) state as a power-saving state.

13. The method according to claim 11, wherein, Performing the link initiation between the first device and the second device in the high-speed mode includes: Execute a first trigger event, wherein the first device sends the physical channel number of the channel of the connection in the first device to the second device, and wherein the second device sends the physical channel number of the channel of the connection in the second device to the first device; Execute a second trigger event, wherein the first device sends information about the channel connected in the first device to the second device, and wherein the second device sends information about the channel connected in the second device to the first device; and A third trigger event is executed, wherein the first device sends the logical channel number of the channel of the connection in the first device to the second device, and wherein the second device sends the logical channel number of the channel of the connection in the second device to the first device.

14. The method of claim 13 further comprises, before executing the first triggering event, resetting the physical layer attributes of the interconnection unit of the first device to default values, and resetting the physical layer attributes of the interconnection unit of the second device to default values.

15. The method of claim 13, further comprising: After the third triggering event is executed, the first device and the second device exchange capability information with each other, and the first device and the second device identify each other's capability information; as well as The first device and the second device exchange control frames indicating that the initial data frames sent between the first device and the second device have been correctly received, and the first device and the second device identify each other's control frames.

16. An apparatus comprising: The interface is configured to send and receive data through interconnecting units connected to it via multiple channels; The interconnect unit includes a plurality of transmitters, at least one of which is configured to perform data communication via a connected transmit channel and a connected receive channel among the plurality of channels, and to transmit an activation period of the connected transmit channel to the connected receive channel, the activation period being less than a first time period, and during the activation period, the line of the connected transmit channel having a negative differential line voltage DIF-N. and Includes multiple receivers in the interconnect unit, The device is configured to determine that the activation period is less than a first time period, and based on the determination that the activation period is less than the first time period, to perform link startup in high-speed mode through the transmission channel and the reception channel of the connection.

17. The device according to claim 16, wherein, The first time period was set to 0.9 milliseconds.

18. The device according to claim 16, wherein, The first time period was set to 1.6 milliseconds.

19. The device according to claim 16, wherein, At least one of the plurality of transmitters is configured to transmit an activation period of the transmission channel of the connection to the receiving channel of the connection, the activation period being longer than the first time period, and The device is also configured to perform the link startup in low-speed mode via the transmission channel and the reception channel of the connection, based on an activation period longer than the first time period.

20. The device according to claim 16, wherein, The device is also configured to: When the transmission channel of the connection transitions to the DIF-N state, it exits the sleep (HIBERN8) state, which is a power-saving state; and When the transmission channel of the connection is in an activation period shorter than the first time period, it enters the high-speed mode.

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