Data processing method and apparatus based on multiple cores

Abstract

The application discloses a multi-core-based data processing method and device, and relates to the field of computers. The method can avoid the problem that the processing core of a submitted WQE and the processing core of a CQE corresponding to the WQE are inconsistent in a multi-core scenario. The method is applied to a processor including at least two processing cores, the at least two processing cores correspond to at least one completion queue (CQ), and the at least one CQ includes a first CQ. The method includes the following steps: accessing the first CQ, the first CQ includes at least one completion queue entry (CQE), the at least one CQE includes a first CQE, and the first CQE includes indication information used for indicating one of the at least two processing cores; and processing the first CQE based on the indication information.

Description

Technical Field

[0001] This application relates to the field of computers, and in particular to a multi-core-based data processing method and apparatus. Background Technology

[0002] Remote direct memory access (RDMA) is a transport layer network protocol that uses queue pairs (QPs) for network transmission and reception of consumer data. For example... Figure 1 As shown, a QP consists of one send queue (SQ) and one receive queue (RQ). The SQ handles RDMA operations on the requesting end, while the RQ handles RDMA message processing on the responding end. The QP is associated with a completion queue (CQ).

[0003] At the requesting end of the RDMA operation, the processor, based on the work request (WR) submitted by the consumer process, submits a work queue element (WQE) in its corresponding SQ. The network interface card (NIC) then encapsulates the RDMA operation indicated by the WQE, along with the corresponding data, into a packet and sends it to the network through the port. When the NIC completes an RDMA operation indicated by a WQE, it writes a completion queue entry (CQE) to the CQ associated with that SQ. This allows the processor to notify the consumer, upon encountering the CQE, that a certain WR it submitted has completed its RDMA operation.

[0004] In existing technologies, if a processor includes multiple processing cores (e.g., processing core 0 and processing core 1), and these multiple processing cores correspond to a single QP, then when processing core 0 polls the CQEs in the CQ associated with that QP, it may poll and process the CQE corresponding to a WQE submitted by processing core 1. This results in a discrepancy between the processing core that submitted the WQE and the processing core that processed the corresponding CQE. Consequently, processing core 0 and processing core 1 need to perform context synchronization to process the business logic corresponding to that CQE. This increases the overhead of the computer system, thereby reducing its processing performance. Summary of the Invention

[0005] This application provides a multi-core-based data processing method and apparatus, which can avoid the problem of inconsistency between the processing core of the WQE and the processing core of the CQE corresponding to the WQE in a multi-core scenario, thereby reducing system overhead and improving system processing performance.

[0006] To achieve the above objectives, this application provides the following technical solution:

[0007] In a first aspect, this application provides a data processing method applied to a processor including at least two processing cores, each processing core corresponding to at least one completion queue (CQ), the at least one CQ including a first CQ. The method includes: accessing a first CQ, the first CQ including at least one completion queue entry (CQE), the at least one CQE including a first CQE, the first CQE including indication information for indicating one of the at least two processing cores; and processing the first CQE based on the indication information.

[0008] The multi-core data processing method provided in this application allows a processor core to process a CQE (Content Qualification Entity) based on the indication information in the CQE that specifies a particular processing core. This ensures that when a CQE indicates that an RNIC request has completed an RDMA operation, the processing core submitting the corresponding WQE (Warranty Qualification Entity) and the processing core processing the CQE are the same core. Thus, when processing the CQE's service, the core does not need to synchronize context with other cores, saving computer system overhead and improving system performance. Furthermore, since the application scenario of the multi-core data processing method provided in this application involves multiple processing cores sharing a single QP (Quality Buffer), this method saves computer system overhead, improves system performance, and does not affect the network scale of the computer equipment.

[0009] In one possible design approach, the first CQE is the head CQE of the first CQ.

[0010] In one possible design, the above "processing the first CQE based on the indication information" includes: if the indication information is the identity ID of any one of at least two processing cores, then the first CQE is processed through any one of the processing cores.

[0011] In another possible design, the processor and the Remote Direct Memory Access Network Interface Card (RNIC) communicate with each other. If the first CQE is used to indicate that the RNIC, as a requesting end, has completed a Remote Direct Memory Access (RDMA) operation, then the indication information is the ID of at least two processing cores. This "any processing core" is the one that submitted the work queue element (WQE) corresponding to the first CQE, which indicates the RDMA operation to be performed by the RNIC.

[0012] In another possible design, the RDMA operation described above includes any one of the following: a transmit operation, a transmit operation with an immediate value, a transmit operation with a remote memory failure indication, a read operation, a write operation, a write operation with an immediate value, or an atomic ATOMIC operation.

[0013] Through these possible designs, it can be ensured that when the CQE is used to indicate that the RNIC requesting end has completed an RDMA operation, the processing core of the WQE corresponding to the CQE and the processing core that processes the CQE are the same processing core. In this way, the processing core does not need to synchronize context with other processing cores when processing the CQE's service, thereby saving computer system overhead and improving computer system performance.

[0014] In another possible design, the RNIC includes at least one queue pair (QP), where a first QP is associated with the first CQ, and the first QP includes a first transmit queue (SQ). Prior to the "access to the first CQ," the method further includes: submitting a first WQE in the first SQ, the first WQE including the ID of any of the aforementioned processing cores, the first WQE being used by the RNIC to generate a first CQE; the indication information in the first CQE is the ID of that any of the processing cores.

[0015] With this possible design, the RNIC can generate a CQE (Content Qualification Entity) containing indication information based on the processing core ID carried in the WQE (Work Qualification Entity) submitted by the processor. This ensures that when the CQE indicates that the RNIC requesting the service has completed an RDMA operation, the processing core submitting the WQE and the processing core processing the CQE are the same core. Thus, when processing the CQE's service, the core does not need to synchronize its context with other cores, thereby saving computer system overhead and improving system performance.

[0016] In another possible design, the above-mentioned "processing the first CQE based on the indication information" includes: if the indication information is preset information, then the first CQE is processed by any one of the above-mentioned at least two processing cores.

[0017] In another possible design, if the first CQE is used to indicate that the RNIC, as a responding end, has completed receiving an RDMA message, then the aforementioned indication information is preset information. This RDMA message includes any one of the following: a send message, a send message with an immediate value, a send message with a remote memory failure indication, or a write message with an immediate value.

[0018] Secondly, this application provides a multi-core-based data processing method applied to a network interface card (NIC). The NIC is connected and communicates with a processor comprising at least two processing cores, each corresponding to at least one completion queue (CQ). The method includes: generating a first completion queue entry (CQE); and writing the first CQ into the at least one CQ. The first CQE includes indication information for indicating one of the at least two processing cores. The first CQE is used to process the first CQE based on the indication information when any of the at least two processing cores accesses it.

[0019] The multi-core data processing method provided in this application allows the NIC to write a generated CQE containing indication information for a specific processing core into the CQ. This enables the processing core in the processor to process the CQE based on the indication information in the CQE. This ensures that when a CQE indicates that an RNIC request has completed an RDMA operation, the processing core submitting the CQE and the processing core processing the CQE are the same core. Therefore, when processing the CQE, the core does not need to synchronize context with other cores, thus saving computer system overhead and improving computer system performance. Furthermore, since the application scenario of the multi-core data processing method provided in this application involves multiple processing cores sharing a single QP in a computer device, this method saves computer system overhead, improves computer system performance, and does not affect the network scale of the computer device.

[0020] In one possible design, the aforementioned NIC is a Remote Direct Memory Access Network Interface Card (RNIC).

[0021] In one possible design, if the first CQE is used to indicate that the RNIC, as the requesting end, has completed a remote direct memory access (RDMA) operation, then the indication information is the ID of any one of at least two processing cores; wherein, the processing core is the processing core that submitted the work queue element WQE corresponding to the first CQE, which is used to indicate the RDMA operation to be performed by the RNIC.

[0022] In another possible design, the RDMA operation described above includes any one of the following: a transmit operation, a transmit operation with an immediate value, a transmit operation with a remote memory failure indication, a read operation, a write operation, a write operation with an immediate value, or an atomic ATOMIC operation.

[0023] In another possible design, the NIC described above includes at least one queue pair (QP), where a first QP is associated with a first CQ, and the first QP includes a first transmit queue (SQ). The "generating a first completion queue entry (CQE)" described above includes generating a first CQE based on a first completion queue entry (WQE) in the first SQ. The first WQE is a WQE submitted by a first processing core out of at least two processing cores in the first SQ, and the first WQE includes the ID of the first processing core. The indication information in the first CQE is the ID of the first processing core.

[0024] In another possible design, if the aforementioned first CQE is used to indicate that the RNIC, as a responding end, has completed receiving an RDMA message, then the aforementioned indication information is preset information. The RDMA message includes any one of the following: a send message, a send message with an immediate value, a send message with a remote memory failure indication, or a write message with an immediate value.

[0025] Thirdly, this application provides a multi-core data processing apparatus. This multi-core data processing apparatus is used to execute any of the methods provided in the first aspect. This application can divide the multi-core data processing apparatus into functional modules according to any of the methods provided in the first aspect. For example, each function can be divided into its own functional modules, or two or more functions can be integrated into one processing module. For example, this application can divide the multi-core data processing apparatus into access units and processing units, etc., according to function. The descriptions of possible technical solutions and beneficial effects of the various functional modules described above can be found in the technical solutions provided in the first aspect or its corresponding possible designs, and will not be repeated here.

[0026] Fourthly, this application provides another multi-core data processing apparatus for executing any of the methods provided in the second aspect above. This application can divide the multi-core data processing apparatus into functional modules according to any of the methods provided in the second aspect above. For example, each function can be divided into its own functional modules, or two or more functions can be integrated into one processing module. For instance, this application can divide the multi-core data processing apparatus into a generation unit and a writing unit, etc., according to their functions. The descriptions of possible technical solutions and beneficial effects of the various functional modules described above can be found in the technical solutions provided in the second aspect above or its corresponding possible designs, and will not be repeated here.

[0027] Fifthly, this application provides a computer device including a processor and a network interface card (NIC). The processor includes at least two processing cores, each corresponding to at least one completion queue (CQ), and the at least two processing cores include a first processing core. The NIC includes at least one queue pair (QP), the at least one QP associated with the at least one CQ. The processor is configured to execute any of the methods provided in the first aspect above, and the NIC is configured to execute any of the methods provided in the second aspect above.

[0028] Sixthly, this application provides a computer-readable storage medium, such as a non-transient computer-readable storage medium. A computer program (or instructions) is stored thereon, which, when executed on a computer, causes the computer...

[0029] The computer executes any method provided by any possible implementation of the first or second aspect described above.

[0030] In a seventh aspect, this application provides a computer program product that, when run on a computer, causes any method provided by any possible implementation of the first or second aspect to be executed.

[0031] Eighthly, this application provides a chip system comprising: a processor, the processor being configured to retrieve and run a computer program stored in a memory, performing any of the methods provided in the implementation of the first aspect.

[0032] It is understood that any of the multi-core data processing devices, computer equipment, computer storage media, computer program products or chip systems provided above can be applied to the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects in the corresponding methods, and will not be repeated here.

[0033] In this application, the names of the aforementioned multi-core data processing devices do not limit the devices or functional modules themselves. In actual implementation, these devices or functional modules may appear under other names. As long as the functions of each device or functional module are similar to those in this application, they fall within the scope of the claims of this application and their equivalents.

[0034] These or other aspects of this application will become more readily apparent in the following description. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the data processing architecture of RDMA in the prior art;

[0036] Figure 2 This is a schematic diagram of the hardware structure of a computer device provided in an embodiment of this application;

[0037] Figure 3 A schematic diagram of a multi-core processor provided in an embodiment of this application;

[0038] Figure 4a A schematic diagram of a multi-core data processing architecture in a computer device provided in an embodiment of this application;

[0039] Figure 4b A schematic diagram of another multi-core-based data processing architecture in a computer device provided in an embodiment of this application;

[0040] Figure 5 A flowchart illustrating a multi-core-based data processing method provided in an embodiment of this application;

[0041] Figure 6 This application provides a schematic diagram of the structure of a multi-core data processing device according to an embodiment of the present application.

[0042] Figure 7 A schematic diagram of another multi-core data processing device provided in this application embodiment;

[0043] Figure 8 This is a schematic diagram of the structure of a chip system provided in an embodiment of this application;

[0044] Figure 9 This is a schematic diagram of the structure of a computer program product provided in an embodiment of this application. Detailed Implementation

[0045] To better understand the embodiments of this application, some terms or technologies involved in the embodiments of this application are explained below:

[0046] 1) RDMA operation

[0047] RDMA supports message types including send, send with immediate, and send with invalidate. These are two-sided operations, requiring processor involvement on both the requesting and responding ends.

[0048] RDMA supports memory operations including read, write, and atomic operations. These are unilateral operations, requiring no processor intervention at the response end; data reading and writing are performed through the network interface card (NIC) to access the storage space. Memory operations also include write operations with immediate values, which require processor intervention at the response end.

[0049] The execution processes of the send operation, the send operation with an immediate value, and the send operation with a remote memory failure indication are similar. The following text will only take the send operation as an example to briefly explain its execution process.

[0050] The execution process of read operations is similar to that of atomic operations. The following text will only take read operations as an example to briefly explain their execution process.

[0051] The execution process of write operations and write operations with immediate values ​​is similar on the requesting side. The following text will only take the write operation as an example to briefly explain its execution process.

[0052] For example, the execution process of transmit, read, and write operations supported by RDMA is as follows:

[0053] Send operation: Also known as a push operation. The requester pushes data to the responder without needing to know the data's location in the responder's storage. The responder's channel adapter places the data into the next available storage space in its QP, indicated by the WQE at the head of the RQ in the responder's QP. The WQE at the head of the RQ refers to the first WQE on the queue exit side of the RQ.

[0054] The requesting end can initiate an RDMA transmit operation by sending a send message, which includes the data to be pushed to the responding end (i.e., the data to be sent). The length of this data to be sent can be from 0 bytes to 2 bytes. 31 If the length of the data to be sent exceeds the path maximum transmission unit (PMTU) within a 4G (4GB) byte range, it will be segmented into multiple send messages according to the PMTU size for transmission. All data included in these multiple send messages constitutes a single message (i.e., the send message in this embodiment). Correspondingly, the responding end reassembles the received multiple send messages to obtain all the data of the send message.

[0055] For a reliable connection, once the responding end has received multiple send messages corresponding to the send message, it sends an acknowledgment (ACK) message to the requesting end to inform the requesting end that the send message has been received.

[0056] It should be understood that when a send operation with an immediate value is executed, its send message includes the immediate value in addition to the data to be sent. In this case, the data to be sent carried by one or more send messages constitutes a single message, which can be called a send message with an immediate value. Further details are omitted.

[0057] It should be understood that when a send operation with a remote memory failure indication is executed, its send message includes the remote memory failure indication information in addition to the data to be sent. In this case, the data to be sent carried by one or more send messages constitutes a single message, which can be called a send message with a remote memory failure indication. Further details are omitted.

[0058] Write operation: Used by the requesting end to write data to the virtual address of the responding end.

[0059] Before allowing the requesting end to perform an RDMA write operation, the responding end first allocates a memory space for access by the requesting end's QP (or QP group). The responding end sends the virtual address and length of this memory space to the requesting end that can access the memory region. For example, this information can be sent to the requesting end using the send operation described above.

[0060] The requesting end can initiate an RDMA write operation by sending a write message, which includes the data to be written to the responding end, the virtual address of the responding end's memory space, and its length. The length of the data to be written can be from 0 bytes to 2 bytes. 31 Similar to the sending operation, if the length of the data to be written is greater than the PMTU, it will be segmented into multiple write messages according to the PMTU size for transmission. The responding end then reassembles these multiple write messages to obtain the data to be written.

[0061] For a reliable connection, once the responding end has received multiple write messages corresponding to the data to be written, it sends an ACK message to the requesting end to inform it that the data to be written has been received.

[0062] It should be understood that a write operation with an immediate value includes the immediate value in addition to the data to be written in its write message. In this case, the data to be written carried by one or more write messages can be considered as a single message, which can be called a write message with an immediate value. Further details are omitted.

[0063] Read operation: Similar to the write operation in RDMA, it is used by the requesting end to read data from the virtual address of the responding end.

[0064] Before allowing the requesting end to perform an RDMA read operation, the responding end first allows the requesting end to access its virtual address, that is, sends the virtual address and length of the data to be read by the RDMA read operation to the requesting end. For example, the above information can be sent to the requesting end through the send operation described above.

[0065] The requesting end can initiate an RDMA read operation by sending a read request message, which includes the virtual address and length of the responding end's memory space. The responding end sends an RDMA read response message to the requesting end, which includes the data to be read. The length of the data to be read can be 0 bytes to 2 bytes. 31 If the length between bytes exceeds the PMTU, it will be segmented into multiple read response messages according to the PMTU size for transmission. The requesting end then reassembles these multiple read response messages to obtain the data to be read.

[0066] For a reliable connection, once the requesting end has received multiple read response messages corresponding to the data to be read, it indicates that the read operation has been completed.

[0067] 2) Other terms

[0068] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0069] In the embodiments of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0070] In this application, the term "at least one" means one or more, and the term "multiple" means two or more. For example, multiple second messages refer to two or more second messages. The terms "system" and "network" are often used interchangeably in this document.

[0071] It should be understood that the terminology used in the description of the various examples herein is for the purpose of describing particular examples only and is not intended to be limiting. As used in the description of the various examples and the appended claims, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0072] It should also be understood that the term "and / or" as used herein refers to and covers any and all possible combinations of one or more of the associated listed items. The term "and / or" describes an association between related objects, indicating that three relationships can exist; for example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Additionally, the character " / " in this application generally indicates that the preceding and following related objects are in an "or" relationship.

[0073] It should also be understood that, in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0074] It should be understood that determining B based on A does not mean determining B solely based on A; B can also be determined based on A and / or other information.

[0075] It should also be understood that the term “comprising” (also referred to as “includes”, “including”, “comprises” and / or “comprising”) as used in this specification specifies the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0076] It should also be understood that the term "if" can be interpreted as meaning "when" or "upon" or "in response to determination" or "in response to detection." Similarly, depending on the context, the phrases "if determination..." or "if detection [the stated condition or event]" can be interpreted as meaning "when determination..." or "in response to determination..." or "when detection [the stated condition or event]" or "in response to detection [the stated condition or event]."

[0077] It should be understood that the phrases "an embodiment," "an embodiment," and "a possible implementation" used throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment or implementation is included in at least one embodiment of this application. Therefore, the phrases "in an embodiment," "an embodiment," or "a possible implementation" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0078] To address the issue of high system overhead and low system performance caused by inconsistencies between the processing core that submits a WQE and the processing core that processes the corresponding CQE, a QP (Quality Level Builder) is typically established on the network interface card for each of the multiple processing cores. In other words, there is a one-to-one correspondence between the multiple processing cores and multiple QPs. Since each QP has its own associated CQ, each processing core has its own corresponding CQ. This eliminates the problem of inconsistencies between the processing core that submits the WQE and the processing core that processes the corresponding CQE.

[0079] However, when there are many processing cores, establishing one-to-one QPs for each core increases system memory consumption. Furthermore, a single network interface card can only support a limited number of QPs; allocating too many QPs to processing cores will reduce the network's scalability.

[0080] Based on this, this application provides a multi-core data processing method applicable to scenarios where multiple processing cores share a single QP. This method adds indication information to the CQE (Processing Quality Entry) to specify a particular processing core. This allows a processing core, when polling for a CQE, to return the CQE to the indicated core for processing based on this indication information. This avoids inconsistencies between the processing core submitting the WQE and the processing core processing the corresponding CQE, thereby reducing system overhead and improving system processing performance. Furthermore, since multiple processing cores share a QP, the scale of the device network is not reduced.

[0081] This application also provides a multi-core data processing device, which can be any device with computing capabilities, such as a general-purpose computer device.

[0082] refer to Figure 2 This application provides a schematic diagram of the hardware structure of a computer device. For example... Figure 2 As shown, the computer device 20 includes a processor 21, a memory 22, a communication interface 23, and a bus 24. The processor 21, the memory 22, and the communication interface 23 can be connected to each other via the bus 24.

[0083] Processor 21 is the control center of computer device 20. It can be a general-purpose central processing unit (CPU), or other general-purpose processors or dedicated processors. The general-purpose processor can be a microprocessor or any conventional processor. As an example, processor 21 may include one or more CPUs, for example... Figure 2 CPU 0 and CPU 1 are shown in the diagram.

[0084] The processor 21 integrates one or more processing cores, and multiple processing cores can process multiple tasks in parallel.

[0085] For example, such as Figure 3 As shown, processor 21 includes three processing cores: processing core 0, processing core 1, and processing core 2.

[0086] It is understandable that a consumer process can run through multiple processing cores. Here, "consumer" can refer to the entity that uses QP for data transmission and reception, generally referring to a software process, such as a software process based on the non-volatile memory express over fabric (NoF) protocol.

[0087] It should be understood that the multi-core-based data processing method provided in this application embodiment is applied to a scenario where a consumer process is run through multiple processing cores.

[0088] The memory 22 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but is not limited thereto.

[0089] In one possible implementation, the memory 22 can exist independently of the processor 21. The memory 22 can be connected to the processor 21 via a bus 24 and is used to store data, instructions, or program code. When the processor 21 calls and executes the instructions or program code stored in the memory 22, it can implement the multi-core-based data processing method provided in this embodiment of the application.

[0090] In another possible implementation, the memory 22 can also be integrated with the processor 21.

[0091] Communication interface 23 is used for connecting computer device 20 to other devices via a communication network, which may be Ethernet, radio access network (RAN), wireless local area network (WLAN), etc. Communication interface 23 may include a receiving unit for receiving data and a transmitting unit for sending data.

[0092] In this embodiment of the application, the communication interface 23 can be a network interface card (NIC). As an example, the communication interface 23 can be a Remote Direct Memory Access Network Interface Card (RDMA network interface card, RNIC).

[0093] RNICs can be standalone Peripheral Component Interconnect Express (PCIe) network cards, or they can be network interface units integrated into system-on-chip (SoC) chips; there are no restrictions on which one is chosen.

[0094] The RNIC is an external device of the computer device 20. Typically, the processor 21 of the computer device 20 can allocate a segment of memory for the RNIC and establish at least one QP on this segment of memory. That is, the RNIC includes at least one QP.

[0095] Taking QP a in at least one QP as an example, when QP a establishes a QP connection with QP b of the peer device of computer device 20, network communication between computer device 20 and the peer device can be realized.

[0096] QP connections include reliable and unreliable connections. When a QP connection is reliable, the responding end can send an ACK message to the requesting end after receiving the data sent by the requesting end, informing the requesting end that the responding end has finished receiving the data sent by the requesting end.

[0097] RNIC can also provide RDMA services to consumer processes running through one or more processing cores by performing RDMA operations, and support a consumer process to communicate with a peer process using a single QP connection.

[0098] It should be understood that when a consumer process communicates with a peer process through a QP connection, if the QP connection includes QP a of the local end (e.g., the requesting end, or the responding end), then one or more processing cores used to run the consumer process correspond to QP a. It can be seen that one processing core can correspond to one QP, and multiple processing cores can also correspond to one QP.

[0099] Since the multi-core-based data processing method provided in this application embodiment is applied to a scenario where a consumer process is run by multiple processing cores, that is, the multi-core-based data processing method provided in this application embodiment is applied to a scenario where multiple processing cores correspond to one QP.

[0100] Furthermore, any one of the at least one QPs mentioned above may include one SQ and one RQ. The QP may be associated with one or two CQs. If one QP is associated with one CQ, it means that the SQ and RQ in that QP share one CQ. If one QP is associated with two CQs, it means that the SQ and RQ in that QP are each associated with one CQ.

[0101] Taking any of the aforementioned QPs as QP a, and QP a associated with a CQ as an example, this CQ can be created by the processor 21 in preset memory. This CQ can include at least one CQE; of course, this CQ can also be empty, that is, it can have no CQE, and this is not limited. The processing core in the processor 21 corresponding to QP a can access or read the CQE in this CQ. Furthermore, the RNIC can also perform write operations on this CQ.

[0102] It should be understood that if QP a is associated with two CQs, these two CQs can be created by the processor 21 in preset memory. These two CQs include at least one CQE. The processing core in the processor 21 corresponding to QP a can access or read the CQE from these two CQs.

[0103] Bus 24 can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. This bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 2 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0104] It should be pointed out that, Figure 2 The structure shown does not constitute a limitation on the computer device 20, except... Figure 2 In addition to the components shown, the computer device 20 may include more or fewer components than illustrated, or combine certain components, or have different component arrangements.

[0105] Combination Figure 2 ,refer to Figure 4a , Figure 4a This application illustrates a multi-core-based data processing architecture in a computer device, as provided in an embodiment of this application. Figure 4a As shown, the data processing architecture includes a processor 41, which includes processing core 0, processing core 1, ..., and processing core n, where n is an integer greater than 1. A consumer process can run using all n processing cores, or it can run using only a portion of those n processing cores; there is no limitation on this. Figure 4a As shown, Figure 4a The consumer process shown runs using processing core 0 and processing core 1.

[0106] The data processing architecture also includes RNIC 42. RNIC 42 includes QP 421. Both processing core 0 and processing core 1 can communicate with the peer via the QP connection where QP 421 resides. QP 421 can be associated with CQ 43, that is, both SQ and RQ in QP 421 are associated with CQ 43, meaning that the SQ and RQ share CQ 43.

[0107] Combination Figure 2 ,refer to Figure 4b , Figure 4b This application illustrates another multi-core-based data processing architecture in a computer device, as provided in an embodiment of this application. Figure 4b As shown, the data processing architecture includes a processor 51, which includes processing core 0, processing core 1, ..., and processing core n, where n is an integer greater than 1. A consumer process can run using all n processing cores, or it can run using only a portion of the n processing cores; there is no limitation on this. Figure 4b As shown, Figure 4b The consumer process shown runs using processing core 0 and processing core 1.

[0108] The data processing architecture also includes an RNIC 52. The RNIC 52 includes a QP 521. Both processing core 0 and processing core 1 can communicate with the peer via the QP connection where the QP 521 resides. The QP 521 can be associated with two CQs, namely CQ 53 and CQ 54. Specifically, the SQ in the QP 521 can be associated with CQ 53, and the RQ in the QP 521 can be associated with CQ 54.

[0109] It should be understood that a computer device may include at least one processor, and each processor may include at least one processing core. Therefore, when a computer device includes multiple processors, at least one processing core of each of the multiple processors, and at least one QP on the RNIC of the computer device, can constitute the multi-core-based data processing architecture shown in Figure 4.

[0110] The method provided in the embodiments of this application is described below with reference to the accompanying drawings.

[0111] refer to Figure 5 , Figure 5 A flowchart illustrating a multi-core-based data processing method provided in an embodiment of this application is shown. This method can be applied to... Figure 4a or Figure 4b The illustrated computer device features a multi-core data processing architecture. The processor of the computer device includes at least two processing cores, including a first processing core, which a consumer process can use to run. The RNIC of the computer device includes at least one QP (Qualifier Pointer). The aforementioned consumer process running through the at least two processing cores can communicate with a peer process through the QP connection where the at least one QP resides; therefore, the at least one QP corresponds to the at least two processing cores. Since the at least one QP is associated with at least one CQ (Concurrent Qualifier), the at least two processing cores correspond to the at least one CQ.

[0112] This method can be executed by the first processing core. The method may include the following steps:

[0113] S101, The first processing core accesses the first CQ, the first CQ including at least one CQE, the at least one CQE including the first CQE.

[0114] The first CQ is any one of the at least one CQ mentioned above. The first CQE includes indication information for indicating one of the at least two processing cores mentioned above.

[0115] Here, the first CQE is the head CQE of the first CQ. Specifically, the head CQE of the first CQ refers to the first CQE located on the queue exit side of the first CQ.

[0116] Optionally, each CQE in the first CQ includes processing core indication information for indicating one of the at least two processing cores mentioned above.

[0117] Optionally, when the at least one CQ includes only the first CQ, the first processing core can directly access the first CQ. Specifically, the first processing core can access the first CQ starting from the header CQE of the first CQ.

[0118] The first processing core can access the first CQ randomly and actively. Alternatively, the first processing core can access the first CQ periodically and actively. Or, the first processing core can access the first CQ when it receives an interrupt signal triggered by the RNIC writing CQE into the first CQ.

[0119] For example, refer to Figure 4a If QP 421 is associated with CQ 43, which is the first CQ, and the first processing core is... Figure 4a The processing core 0 (or processing core 1) is shown. In this case, processing core 0 can access CQ 43.

[0120] Optionally, when the at least one CQ includes two or more CQs, the first processing core can access the first CQ by polling the at least one CQ.

[0121] The first processing core can randomly and actively poll the at least one CQ. Alternatively, the first processing core can periodically and actively poll the at least one CQ. Or, the first processing core can poll the at least one CQ when it receives an interrupt signal triggered by the RNIC writing CQE into the CQ.

[0122] For example, refer to Figure 4b The CQ associated with QP 521 includes CQ 53 and CQ 54. If the first processing core is processing core 0 (or processing core 1) and the first CQ is CQ 53, then processing core 0 can poll CQ 53 and CQ 54 to access CQ 53.

[0123] For ease of understanding, the following example describes the process of the first processing core accessing the first CQ.

[0124] In one possible implementation, when at least one CQ corresponding to the first processing core includes only the first CQ, the first processing core can directly access the first CQ.

[0125] Typically, when the first processing core accesses the first CQ, it begins accessing from CQE 1 in the first CQ header. If CQE 1 meets a preset condition, it is returned to the first processing core or another processing core corresponding to the first CQ for further processing. In this case, the next CQE after CQE 1 in the original first CQ becomes the CQE in the current first CQ header. The first processing core continues processing this header-located CQE until the CQE in the first CQ header no longer meets the preset condition, at which point it exits access to the first CQ.

[0126] In another possible implementation, when the first processing core corresponds to at least one CQ that includes multiple CQs, and the first CQ is any one of the multiple CQs, the first processing core can poll the multiple CQs in a preset order to access the first CQ.

[0127] As an example, if the multiple CQs include CQ 1, CQ 2, and CQ 3, the default order could be CQ 1→CQ 2→CQ 3, or CQ 3→CQ 2→CQ 1. There is no limitation on this.

[0128] The following example illustrates the process of a first processing core polling CQ1, CQ2, and CQ3 in the default order of CQ1→CQ2→CQ3, thereby enabling access to the first CQ through a polling CQE. The first CQ can be any one of CQ1, CQ2, or CQ3.

[0129] Optionally, the first processing core can poll CQ1 according to a preset order. When polling CQ1, the first processing core starts processing from CQE 1 at the beginning of CQ1. When CQE 1 meets the preset conditions, it returns CQE 1 to the first processing core or another processing core corresponding to CQ1 for further processing. In this case, the next CQE after CQE 1 in the original CQ1 becomes the CQE at the beginning of the current CQ1. Thus, the first processing core continues to process the CQE at the beginning of CQ1 until the CQE at the beginning of CQ1 no longer meets the preset conditions, at which point it exits the polling of CQ1.

[0130] Next, following a preset sequence, the first processing core can poll CQ2. When polling CQ2, the first processing core starts processing from CQE 2 in the CQ2 header. The specific polling process can be found in the description of the first processing core's polling of CQ1, and will not be repeated here. If the CQE in the CQ2 header does not meet the preset conditions, polling of CQ2 is terminated.

[0131] Next, following a preset sequence, the first processing core can poll CQ3. When polling CQ3, the first processing core starts processing from CQE 3 in the CQ3 header. The specific polling process can be found in the description of the first processing core's polling of CQ1, and will not be repeated here. If the CQE in the CQ3 header does not meet the preset conditions, the current polling session ends.

[0132] Of course, at least one of CQ 1, CQ 2, and CQ 3 mentioned above can be empty, meaning that CQ 1, CQ 2, or CQ 3 does not include CQE. An empty CQ indicates that the number of CQEs within CQ is 0 in the current state.

[0133] As an example, assuming CQ1 is empty, when the first processing core polls CQ1 in a preset order, if CQ1 is empty, the first processing core exits the polling of CQ1. Then, the first processing core continues to poll CQ2 and CQ3 in a preset order, which will not be elaborated here.

[0134] Optionally, when the first processing core polls at least one CQ, it can return up to m CQEs that meet preset conditions to the corresponding processing core for processing before exiting the polling. Here, m is a positive integer less than or equal to a preset threshold. This embodiment does not specifically limit the value of the preset threshold. That is, the first processing core can continuously return m CQEs that meet the preset conditions while polling at least one CQ.

[0135] As an example, let's assume m is 10. If the first processing core is polling at least one of the above CQs, it can continuously return 10 CQEs that meet the preset conditions to the corresponding processing core for processing. When the 10th CQE that meets the preset conditions is returned to the corresponding processing core, the first processing core exits the current polling.

[0136] S102, The first processing core processes the first CQE based on the instruction information of the first CQE.

[0137] If the first CQE is used to indicate that the RNIC, as the requesting end, has completed an RDMA operation, then the indication information in the first CQE is the identity document (ID) of any one of the at least two processing cores mentioned above. This "any one" processing core is the processing core that submitted the WQE corresponding to the first CQE. The correspondence between CQE and WQE is explained below and will not be repeated here.

[0138] RDMA operations include any one of the following: transmit operation, transmit operation with immediate value, transmit operation with remote memory failure indication, read operation, write operation, write operation with immediate value, or ATOMIC operation. For a detailed explanation of RDMA operations, please refer to the above text; it will not be repeated here.

[0139] If the first CQE is used to indicate that the RNIC, as a responding end, has completed receiving an RDMA message, then the indication information in the first CQE is preset information. This preset information is used to indicate that either of the at least two processing cores is allowed to process the first CQE. This is because, in a computer system, processing the received data by either processing core will not affect the performance of the computer system.

[0140] RDMA messages include any one of the following: a send message, a send message with an immediate value, a send message with a remote memory failure indication, or a write message with an immediate value. For details regarding send messages, send messages with immediate values, send messages with remote memory failure indications, or write messages with immediate values, please refer to the relevant descriptions of RDMA operations above; they will not be repeated here.

[0141] The preset information can be a preset value or a preset ID, and this application embodiment does not limit it.

[0142] The method for generating the first CQE in at least one of the above CQs can be found in the description below, which will not be repeated here.

[0143] In this case, if the above-mentioned indication information is the ID of the first processing core, then the first processing core obtains the first CQE and processes it.

[0144] In another scenario, if the aforementioned instruction information is preset information, the first processing core returns the first CQE to any one of the at least two processing cores for processing. For example, the first processing core returns the first CQE to itself for processing.

[0145] Optionally, if the above-mentioned indication information is preset information, the first processing core may randomly return the first CQE to any one of the at least two processing cores for processing.

[0146] Optionally, if the above-mentioned indication information is preset information, the first processing core may return the first CQE to one of the at least two processing cores for processing according to preset rules.

[0147] The preset rule could be that, based on the current load of the at least two processing cores, the first CQE is returned to one of the at least two processing cores for processing. For example, the first processing core could return the first CQE to the processing core with the lower load among the at least two processing cores for processing.

[0148] The preset rule can also be that, according to a preset order, the first CQE is returned to one of the at least two processing cores for processing. As an example, if the at least two processing cores include processing core 0 and processing core 1, then the preset order could be: processing core 0 → processing core 1 → processing core 0 → processing core 1, etc. This is not limited.

[0149] Of course, the preset rule can also be any other rule, and this application embodiment does not specifically limit it.

[0150] In another scenario, if the aforementioned instruction information is neither the preset information nor the ID of the first processing core, then the access (or polling) to the CQ where the first CQE is located is terminated.

[0151] It is understandable that if at least one CQ corresponding to the aforementioned at least two processing cores includes only the first CQ, then when the indication information in the first CQE is neither the preset information nor the ID of the first processing core, the first processing core will exit the current access to the first CQ. If at least one CQ corresponding to the aforementioned at least two processing cores includes multiple CQs, then when the indication information in the first CQE is neither the preset information nor the ID of the first processing core, the first processing core will exit the polling of the CQ containing the first CQE, and then poll the next CQ according to the preset order. It can be seen that the indication information of the first CQE includes the IDs of processing cores other than the first processing core.

[0152] It is understandable that when the first processing core accesses the first CQE, which is the header CQE of the first CQ, whether the indication information of the first CQE is the ID of the first processing core and whether it is preset information can be understood as whether the header CQE in the CQ satisfies the preset conditions when the first processing core accesses (or polls) the CQ as described in S101. In other words, when the first processing core accesses (or polls) any one of at least one CQ, the preset condition that the header CQE in the CQ needs to satisfy is that the indication information in the CQE is the ID of the first processing core or preset information.

[0153] The above describes the method provided in the embodiments of this application for the first processing core to execute. It should be understood that when there are multiple processing cores corresponding to at least one CQ, the multiple processing cores may randomly execute the methods described in S101-S102 above, or they may execute the methods described in S101-S102 above in a certain order, without limitation.

[0154] In this way, by executing the methods described in S101-S102, the at least two processing cores mentioned above can ensure that when the first CQE indicates that the RNIC has completed an RDMA operation, the processing core that submits the WQE corresponding to the first CQE and the processing core that processes the first CQE are the same processing core. Thus, when processing the service of the first CQE, this processing core does not need to synchronize its context with other processing cores, thereby saving computer system overhead and improving computer system performance.

[0155] The process of generating the first CQE in at least one of the above CQs in different scenarios is described below.

[0156] Scene 1

[0157] This scenario describes an RDMA operation performed when the RNIC acts as the requesting end.

[0158] In this scenario, after executing the RDMA operation indicated by the WQE, the RNIC generates a first CQE among the at least one CQs mentioned above. This first CQE includes indication information, which may be the ID of any one of at least two processing cores corresponding to the at least one CQ, including the first processing core. The any one of these processing cores is the one that submitted the WQE corresponding to the first CQE.

[0159] In a first possible implementation, the RNIC can generate the first CQE in at least one CQ based on the ID of the first processing core in the WQE submitted by the first processing core in the RNIC's SQ. The ID of the first processing core in the WQE is added to the WQE by the first processing core.

[0160] Specifically, the process by which the RNIC generates the first CQE in at least one CQ based on the ID of the first processing core in the WQE submitted by the first processing core in the RNIC's SQ may include the following steps:

[0161] Step 1: The first processing core submits the first WQE in the SQ of the corresponding QP. The first WQE includes the ID of the first processing core.

[0162] Specifically, after receiving the WR submitted by the consumer, the first processing core can submit the first WQE in the SQ of the QP corresponding to the first processing core based on the WR.

[0163] It is understandable that "commit" here can be interpreted as "write". That is, the first processing core can receive the consumer's WR and, based on that WR, write the first WQE into the SQ in the QP corresponding to the first processing core.

[0164] The first WQE is used to indicate the RDMA operation to be performed by the RNIC. Specifically, the first WQE indicates the RDMA operation to be performed by the RNIC through the operation type parameter in the first WQE.

[0165] When the RDMA operation is a transmit operation / transmit operation with immediate value / transmit operation with remote memory failure indication, the first WQE may include information such as the type of data to be transmitted and a pointer to the storage space of the data to be transmitted.

[0166] When the RDMA operation is a write operation / write operation with immediate value, the first WQE may include the storage space address on the requesting end of the operation for storing the data to be written, and the storage space address on the responding end of the operation for storing the data to be written.

[0167] When the RDMA operation is a read operation, the first WQE may include the storage space address on the read operation requesting end for storing the data to be read, and the storage space address on the read operation response end for storing the data to be read.

[0168] When the RDMA operation is an atomic operation, the first WQE may include the storage space address of the data to be operated on on the atomic operation response end.

[0169] Typically, upon receiving a WR, the first processing core sends a signal (often called a doorbell) to the RNIC to notify it to perform the RDMA operation indicated by the first WQE. This doorbell is the one applied to the requesting end.

[0170] For example, if the first processing core submits the first WQE based on the WR in the SQ of the corresponding QP, and the indicated RDMA operation is a send operation, then when the RNIC receives the doorbell, the RNIC can, according to the PMTU, segment the data to be sent specifically pointed to by the first WQE into one or more send messages and send them to the network.

[0171] For example, if the first processing core submits the first WQE based on the WR in the SQ of the corresponding QP, indicating that the RDMA operation is a write operation, then when the RNIC receives the doorbell, the RNIC can segment the data to be written specifically pointed to by the first WQE into one or more write messages according to the PMTU and send them to the network.

[0172] The first WQE also includes the ID of the first processing core. Optionally, the first processing core can first generate a traditional WQE based on the aforementioned WR. Then, the first processing core adds its own ID to the reserved field of the WQE. In this way, a first WQE including the ID of the first processing core is obtained.

[0173] As an example, refer to Figure 4a The first processing core can be Figure 4a The processing core shown is either processing core 0 or processing core 1. The first processing core is... Figure 4a Taking processing core 0 as an example, after receiving the consumer's WR, processing core 0 can submit WQE 1, i.e., the first WQE, in the SQ of the QP 421 corresponding to processing core 0 based on the WR.

[0174] Step 2: Based on the first WQE described above, RNIC generates a first CQE, wherein the first CQE includes the ID of the first processing core.

[0175] Specifically, after the RNIC completes the RDMA operation indicated by the first WQE, it generates the first CQE. The first CQE indicates that the RNIC, as the requesting end, has completed the RDMA operation indicated by the first WQE. Here, in this embodiment, the first WQE is referred to as the WQE corresponding to the first CQE.

[0176] If the RDMA operation described above is a send operation, the RNIC generates the first CQE after completing the transmission of a send message. Optionally, when the QP connection containing the SQ is a reliable connection, the RNIC can generate the first CQE after receiving an ACK packet from the responding RNIC. This ACK packet indicates that the send message sent by the RNIC has been received by the responding RNIC.

[0177] It should be understood that when an RDMA operation is a transmit operation with an immediate value or a transmit operation with a remote memory failure indication, the situation is similar to that of an RDMA operation as a transmit operation, and will not be elaborated here.

[0178] If the RDMA operation described above is a write operation, the RNIC generates the first CQE after completing the transmission of the data to be written. Optionally, when the QP connection containing the SQ is a reliable connection, the RNIC can generate the first CQE after receiving the ACK packet from the responding RNIC. The ACK packet indicates that the data to be written sent by the RNIC has been received by the responding RNIC.

[0179] It should be understood that when an RDMA operation is a write operation with an immediate value, the situation is similar to that of an RDMA operation that is a write operation, which will not be elaborated here.

[0180] If the RDMA operation described above is a read operation, then the RNIC generates the first CQE after receiving the read response message, that is, after receiving the data to be read.

[0181] It should be understood that when an RDMA operation is an atomic operation, the situation is similar to that when an RDMA operation is a read operation, which will not be elaborated here.

[0182] Optionally, after the RNIC completes the RDMA operation indicated by the first WQE, it can first generate a conventional CQE. Then, it copies the ID of the first processing core from the first WQE in the SQ to the reserved field of the conventional CQE, thereby obtaining a first CQE including the ID of the first processing core. In this case, the ID of the first processing core is the indication information in the first CQE.

[0183] As an example, refer to Figure 4a After the RDMA operation indicated by WQE 1 submitted by processing core 0 is completed, RNIC 42 can generate a conventional CQE. Then, RNIC 42 copies the ID of processing core 411 from WQE 1 into this CQE, thus obtaining CQE 1 including the ID of processing core 0, i.e., the first CQE.

[0184] Step 3: RNIC writes the first CQE into CQ.

[0185] After generating the first CQE, the RNIC can write the first CQE into the CQ associated with the aforementioned SQ. In this way, the processing core corresponding to the CQ can process the first CQE by executing the methods described in S101 to S102 above.

[0186] As an example, such as Figure 4a As shown, QP 421 is associated with CQ 43. Therefore, RNIC 42 can write CQE 1 into CQ43. Here, CQE 1 is a CQE generated by RNIC 42 after the RDMA operation indicated by WQE 1 in SQ is completed, and CQE 1 includes the ID of the processing core 0 that submitted WQE 1 in SQ.

[0187] Optionally, when the first CQE is used to indicate that the RNIC has completed sending a send message / send operation with an immediate value / send operation with a remote memory failure indication, the processing core that processes the first CQE may release the address space indicated by the first WQE corresponding to the first CQE when processing the first CQE. Of course, this is not the only possibility.

[0188] Optionally, when the first CQE is used to indicate that the RNIC has finished sending the data to be written, the processing core that processes the first CQE may, according to the needs of the consumer process, release the address space indicated by the first WQE corresponding to the first CQE, or retain the address space indicated by the first WQE corresponding to the first CQE, etc. The embodiments of this application do not limit this.

[0189] Thus, the first possible implementation described above can be simply understood as follows: The first processing core first adds its own ID to the WQE obtained based on WR, and then submits this WQE to the SQ in the QP corresponding to the first processing core. After the RDMA operation indicated by the WQE is executed, the RNIC can copy the ID of the first processing core from the WQE to the generated CQE, thus obtaining the first CQE described above. Finally, the RNIC writes the first CQE into the CQ associated with the aforementioned SQ.

[0190] In a second possible implementation, the RNIC can generate a first CQE in at least one CQ based on the ID of the first processing core in the WQE submitted by the first processing core in the RNIC's SQ. The ID of the first processing core in this WQE is added to the WQE by the RNIC.

[0191] Specifically, the process by which the RNIC generates the first CQE in at least one of the aforementioned CQs after completing the RDMA operation indicated by the WQE may include the following steps:

[0192] Step 1: RNIC obtains the ID of the first processing core.

[0193] When the RNIC is the network interface unit of the SoC chip, it is connected to the processing core via the SoC chip's internal system bus. Therefore, when the first processing core sends data to this network interface unit, it also carries its own ID. Consequently, when the first processing core submits a WQE to the SQ in the RNIC, it also carries its own ID.

[0194] Accordingly, RNIC can obtain the ID of the first processing core.

[0195] Step 2: RNIC adds the ID of the first processing core to the SQ submission WQE of the first processing core to RNIC, so as to obtain the first WQE including the ID of the first processing core.

[0196] The description of the first processing core submitting the first WQE in the SQ of the corresponding QP can be found in step 1 of the first possible implementation above. It will not be repeated here.

[0197] It should be understood that the RNIC may add the obtained ID of the first processing core to the reserved field of the WQE at any time after the first processing core submits the WQE to the SQ in the RNIC and before the RNIC completes the RDMA operation indicated by the WQE, so as to obtain a first WQE including the ID of the first processing core. The embodiments of this application do not limit this.

[0198] Step 3: Based on the first WQE described above, RNIC generates a first CQE, wherein the first CQE includes the ID of the first processing core.

[0199] The process by which RNIC generates the first CQE based on the first WQE described above can be referred to in the description of step 2 in the first possible implementation above, and will not be repeated here.

[0200] Step 4: RNIC writes the first CQE into CQ.

[0201] The process by which RNIC writes the first CQE into the CQ can be referred to in step 3 of the first possible implementation above, and will not be repeated here.

[0202] It should be noted that when the RNIC is a PCIe network card, the PCIe network card is usually connected to a PCIe interface. Due to the limitations of the PCIe protocol, the PCIe network card cannot directly obtain the ID of the processing core sending data to it. Therefore, this second possible implementation method is not applicable when the RNIC is a PCIe network card.

[0203] Thus, the second possible implementation described above can be simply understood as follows: the first processing core does not add its own ID to the WQE obtained based on WR, but instead carries its own ID when submitting the WQE to the SQ in the QP corresponding to the first processing core on the RNIC. In this way, the RNIC can obtain the ID of the first processing core submitting the WQE and add that ID to the WQE, thus obtaining a first WQE including the first processing core ID. After the RDMA operation indicated by the first WQE is executed, the RNIC can copy the first processing core ID from the first WQE to the generated CQE, thus obtaining the first CQE described above. Finally, the RNIC writes the first CQE into the CQ associated with the aforementioned SQ.

[0204] Scene 2

[0205] This scenario describes the situation where the RNIC acts as the responding end, receiving send messages, send messages with immediate values, send messages with remote memory failure indication, and write messages with immediate values.

[0206] In this scenario, the RNIC can generate a first CQE (Content Qualification Error) among at least one of the aforementioned CQs after receiving a send message, a send message with an immediate value, a send message with a remote memory failure indication, or a write message with an immediate value. This first CQE includes indication information, which may be preset information. Here, the preset information may be a preset value or a preset ID; this embodiment of the application does not limit this.

[0207] The following describes the process of generating the first CQE in at least one CQ, using the completion of a send message reception by the RNIC as an example. This process may include the following steps:

[0208] Step 1: After receiving the complete send message, the RNIC generates the first CQE. This first CQE includes preset information.

[0209] The first processing core can, upon receiving the WR submitted by the consumer, submit a second WQE (e.g., WQE) in the RQ within the QP corresponding to the first processing core, based on that WR. Figure 4a The second WQE (WQE 2) includes a pointer to a storage space capable of storing data and the size of that storage space. Thus, when the RNIC receives a send message from the requesting device, it writes the data from that send message into the storage space pointed to by the second WQE.

[0210] Thus, after the RNIC completes receiving a send message, it generates the first CQE. Here, in this embodiment of the application, the second WQE is referred to as the WQE corresponding to the first CQE.

[0211] Optionally, the RNIC can generate a traditional CQE after a send message is received. Then, the reserved fields in the CQE are set to preset information, thus obtaining a first CQE that includes the preset information. In this case, the preset information is the indication information in the first CQE.

[0212] Step 2: RNIC writes the first CQE into CQ.

[0213] After generating the first CQE, the RNIC can write the first CQE into the CQ associated with the aforementioned RQ. In this way, the processing core corresponding to the CQ can process the first CQE by executing the methods S101 to S102 described above.

[0214] As an example, such as Figure 4a As shown, QP 421 is associated with CQ 43. Therefore, RNIC 42 can write CQE 2 into CQ43. CQE 2 is a CQE generated by RNIC 42 after writing the data to be received into the storage space indicated by WQE 2 in RQ, and CQE 2 includes preset information.

[0215] Thus, the implementation of generating the first CQE in Scenario 2 described above can be simply understood as follows: The first processing core pre-submits the WQE in the RQ within the QP. Then, when the RNIC receives a send message, it writes the data from the send message into the storage space indicated by the WQE. After the RNIC finishes receiving the send message, it first generates a traditional CQE. Then, the RNIC sets the reserved fields in the CQE to preset information, thus obtaining the first CQE described above. Finally, the RNIC writes the first CQE into the CQ associated with the aforementioned RQ.

[0216] In summary, this application provides a multi-core-based data processing method. This method processes a CQE (Processing Qualifier) ​​that includes indication information for the processing core. This ensures that when the CQE indicates that an RNIC request has completed an RDMA operation, the processing core of the WQE (Web Qualifier) ​​corresponding to the CQE and the processing core processing the CQE are the same core. Thus, when processing the CQE's services, the processing core does not need to synchronize its context with other processing cores, thereby saving computer system overhead and improving computer system performance.

[0217] Furthermore, since the application scenario of this application embodiment is a scenario where multiple processing cores in a computer device share a single QP, the multi-core-based data processing method provided by this application embodiment can save the overhead of the computer system, improve the performance of the computer system, and not affect the network scale of the computer device.

[0218] The foregoing mainly describes the solutions provided by the embodiments of this application from a methodological perspective. To achieve the above functions, it includes corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should readily recognize that, based on the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0219] This application embodiment can divide the multi-core data processing device into functional modules according to the above method example. For example, each function can be divided into its own functional module, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0220] like Figure 6 As shown, Figure 6 A schematic diagram of the structure of a multi-core data processing apparatus 60 provided in an embodiment of this application is shown. This multi-core data processing apparatus 60 is applied to a processor including at least two processing cores, each corresponding to at least one completion queue (CQ), the at least one CQ including a first CQ. The multi-core data processing apparatus 60 is also used to execute the aforementioned multi-core data processing method, for example, to execute... Figure 5 The method is shown. The multi-core data processing device 60 may include an access unit 61 and a processing unit 62.

[0221] Access unit 61 is used to access a first CQ, which includes at least one completion queue entry CQE, and the at least one CQE includes a first CQE, which includes indication information for indicating one of at least two processing cores. Processing unit 62 is used to process the first CQE based on the indication information.

[0222] As an example, combined Figure 5The access unit 61 can be used to execute S101, and the processing unit 62 can be used to execute S102.

[0223] Optionally, the aforementioned first CQE is the header CQE of the first CQ.

[0224] Optionally, the processing unit 62 is specifically used to process the first CQE through any one of the at least two processing cores if the above indication information is the identity ID of any one of the processing cores.

[0225] As an example, combined Figure 5 The processing unit 62 can be used to execute S102.

[0226] Optionally, the aforementioned processor and Remote Direct Memory Access Network Interface Card (RNIC) communicate with each other. If the first CQE is used to indicate that the RNIC, as the requesting end, has completed a Remote Direct Memory Access (RDMA) operation, then the indication information is the ID of any one of at least two processing cores. This "any one" processing core is the one that submitted the work queue element (WQE) corresponding to the first CQE, which indicates the RDMA operation to be executed by the RNIC.

[0227] Optionally, the RDMA operation described above includes any one of the following: a transmit operation, a transmit operation with an immediate value, a transmit operation with a remote memory failure indication, a read operation, a write operation, a write operation with an immediate value, or an atomic ATOMIC operation.

[0228] Optionally, the aforementioned RNIC includes at least one queue pair QP, wherein a first QP of the at least one QP is associated with a first CQ, and the first QP includes a first transmit queue SQ. The multi-core data processing apparatus 60 further includes: a submission unit 63, configured to submit a first WQE in the first SQ before the access unit 61 accesses the first CQ, the first WQE including the ID of any processing core, the first WQE being used by the RNIC to generate a first CQE; the indication information in the first CQE is the ID of any processing core.

[0229] Optionally, the processing unit 62 is specifically used to process the first CQE by any one of at least two processing cores if the above-mentioned indication information is preset information.

[0230] As an example, combined Figure 5 The processing unit 62 can be used to execute S102.

[0231] Optionally, if the first CQE described above is used to indicate that the RNIC, as a responding end, has completed receiving an RDMA message, then the above indication information is preset information. The RDMA message includes any one of the following: a send message, a send message with an immediate value, a send message with a remote memory failure indication, or a write message with an immediate value.

[0232] For a detailed description of the above-mentioned optional methods, please refer to the foregoing method embodiments, which will not be repeated here. Furthermore, the explanation and description of the beneficial effects of any of the multi-core data processing devices 60 provided above can be found in the corresponding method embodiments, which will not be repeated here.

[0233] As an example, combined Figure 2 The multi-core data processing device 60 can be Figure 2 Any processing core in the processor 21. The functions implemented by the access unit 61, processing unit 62, and submission unit 63 in the multi-core data processing device 60 can all be implemented by executing the program code in the memory 22 through any processing core in the processor 21.

[0234] like Figure 7 As shown, Figure 7 A schematic diagram of another multi-core-based data processing device 70 provided in an embodiment of this application is shown. This multi-core-based data processing device 70 is applied to a network interface card (NIC), which communicates with a processor including at least two processing cores, each corresponding to at least one completion queue (CQ). The multi-core-based data processing device 70 includes a generation unit 71 and a writing unit 72.

[0235] A generation unit 71 is used to generate a first completion queue entry (CQE). A writing unit 72 is used to write the first CQE into the first CQ of the at least one CQ. The first CQE includes indication information for instructing one of the at least two processing cores. The first CQE is used to process the first CQE based on the indication information when either of the at least two processing cores accesses the first CQE.

[0236] Optionally, the NIC mentioned above is a Remote Direct Memory Access Network Interface Card (RNIC).

[0237] Optionally, if the first CQE is used to indicate that the RNIC, as the requesting end, has completed a Remote Direct Memory Access (RDMA) operation, then the indication information is the ID of any one of at least two processing cores. This "any one" processing core is the one that submitted the work queue element WQE corresponding to the first CQE, which indicates the RDMA operation to be executed by the RNIC.

[0238] Optionally, the RDMA operation described above includes any one of the following: a transmit operation, a transmit operation with an immediate value, a transmit operation with a remote memory failure indication, a read operation, a write operation, a write operation with an immediate value, or an atomic ATOMIC operation.

[0239] Optionally, the aforementioned NIC includes at least one queue pair (QP), where a first QP is associated with a first CQ, and the first QP includes a first transmit queue (SQ). The generation unit 71 is specifically configured to generate a first CQE based on a first WQE in the first SQ. The first WQE is a WQE submitted by the first processing core among the at least two processing cores in the first SQ, and the first WQE includes the ID of the first processing core. The indication information in the first CQE is the ID of the first processing core.

[0240] Optionally, if the first CQE described above is used to indicate that the RNIC, as a responding end, has completed receiving an RDMA message, then the above indication information is preset information. The RDMA message includes any one of the following: a send message, a send message with an immediate value, a send message with a remote memory failure indication, or a write message with an immediate value.

[0241] For a detailed description of the above-mentioned optional methods, please refer to the foregoing method embodiments, which will not be repeated here. Furthermore, the explanation and description of the beneficial effects of any of the multi-core data processing devices 70 provided above can be found in the corresponding method embodiments, which will not be repeated here.

[0242] As an example, combined Figure 2 The multi-core data processing device 70 can be Figure 2 Communication interface 23 in the middle.

[0243] This application embodiment also provides a chip system 80, such as Figure 8 As shown, the chip system 80 includes at least one processor and at least one interface circuit. As an example, when the chip system 80 includes one processor and one interface circuit, the processor can be... Figure 8 The processor 81 shown in the solid box (or the processor 81 shown in the dashed box) can be an interface circuit. Figure 8 The interface circuit 82 is shown in the solid box (or the dashed box). When the chip system 80 includes two processors and two interface circuits, the two processors include... Figure 8 The processor 81 shown in the solid box and the processor 81 shown in the dashed box, these two interface circuits include Figure 8Interface circuit 82 is shown in both solid and dashed boxes. This is not a limitation. It should be understood that any of the at least one processor described above includes at least two processing cores.

[0244] Processor 81 and interface circuit 82 can be interconnected via lines. For example, interface circuit 82 can be used to receive signals (e.g., signals from a requesting or responding end). As another example, interface circuit 82 can be used to send signals to other devices (e.g., processor 81). Exemplarily, interface circuit 82 can read instructions stored in memory and send those instructions to processor 81. When the instructions are executed by processor 81, the first processing core and RNIC can perform the steps in the above embodiments. Of course, the chip system may also include other discrete devices, and this application embodiment does not specifically limit this.

[0245] Another embodiment of this application provides a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the various steps in the method flow shown in the above method embodiments.

[0246] In some embodiments, the disclosed method may be implemented as computer program instructions encoded in a machine-readable format on a computer-readable storage medium or on other non-transitory media or articles of art.

[0247] Figure 9 A conceptual partial view of a computer program product provided in an embodiment of this application is shown schematically. The computer program product includes a computer program for executing computer processes on a computing device.

[0248] In one embodiment, a computer program product is provided using a signal carrying medium 90. The signal carrying medium 90 may include one or more program instructions that, when executed by one or more processors, can provide the above-mentioned... Figure 5 The described function or part of the function. Therefore, for example, refer to... Figure 5 One or more features of S101 to S102 can be assumed by one or more instructions associated with the signal carrying medium 90. Furthermore, Figure 9 The program instructions in the document also describe example instructions.

[0249] In some examples, the signal carrying medium 90 may include a computer-readable medium 91, such as, but not limited to, a hard disk drive, a compact disc (CD), a digital video optical disc (DVD), a digital magnetic tape, a memory, read-only memory (ROM), or random access memory (RAM), etc.

[0250] In some implementations, the signal carrying medium 90 may include a computer recordable medium 92, such as, but not limited to, a memory, a read / write (R / W) CD, a R / W DVD, and so on.

[0251] In some implementations, the signal carrying medium 90 may include a communication medium 93, such as, but not limited to, digital and / or analog communication media (e.g., fiber optic cables, waveguides, wired communication links, wireless communication links, etc.).

[0252] The signal-bearing medium 90 can be transmitted by a wireless communication medium 93 (e.g., a wireless communication medium conforming to the IEEE 802.11 standard or other transmission protocols). One or more program instructions can be, for example, computer-executable instructions or logical implementation instructions.

[0253] In some examples, such as targeting Figure 5 The first processing core described can be configured to provide various operations, functions, or actions in response to one or more program instructions via a computer-readable medium 91, a computer-recordable medium 92, and / or a communication medium 93.

[0254] It should be understood that the arrangements described herein are for illustrative purposes only. Therefore, those skilled in the art will understand that other arrangements and other elements (e.g., machines, interfaces, functions, sequences, and functional groups, etc.) can be used instead, and some elements may be omitted depending on the desired outcome. Furthermore, many of the described elements are functional entities that can be implemented as discrete or distributed components, or in any suitable combination and location with other components.

[0255] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, implementation can be, in whole or in part, in the form of a computer program product. This computer program product includes one or more computer instructions. When these computer instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device containing one or more servers, data centers, etc., that can be integrated with the medium. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state disks, SSDs).

[0256] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A multi-core-based data processing method, characterized in that, Applied to a processor, the processor including at least two processing cores, the at least two processing cores sharing a queue pair QP, the at least two processing cores corresponding to at least one completion queue CQ, the at least one CQ including a first CQ; the method includes: Access the first CQ, which includes at least one completion queue entry CQE; the at least one CQE includes a first CQE, which includes indication information for indicating one of the at least two processing cores; the indication information is the identity ID of any of the at least two processing cores; or the indication information is preset information for indicating that any of the at least two processing cores is allowed to process the first CQE. The first CQE is processed based on the indicated information; The processor and the Remote Direct Memory Access Network Interface Card (RNIC) are connected and communicate. If the first CQE is used to indicate that the RNIC, as the requesting end, has completed a remote direct memory access (RDMA) operation, then the indication information is the ID of any one of the at least two processing cores; Wherein, any one of the processing cores is a processing core that submits a work queue element WQE corresponding to the first CQE, and the WQE is used to indicate the RDMA operation to be executed by the RNIC.

2. The method according to claim 1, characterized in that, The first CQE is the header CQE of the first CQ.

3. The method according to claim 1 or 2, characterized in that, The process of processing the first CQE based on the indication information includes: If the indication information is the identity ID of any one of the at least two processing cores, then the first CQE is processed through any one of the processing cores.

4. The method according to claim 1, characterized in that, The RDMA operation includes any one of the following: a transmit operation, a transmit operation with an immediate value, a transmit operation with a remote memory failure indication, a read operation, a write operation, a write operation with an immediate value, or an atomic ATOMIC operation.

5. The method according to claim 1 or 4, characterized in that, The RNIC includes at least one queue pair QP, wherein the first QP of the at least one QP is associated with the first CQ; The first QP includes a first transmit queue SQ; Prior to accessing the first CQ, the method further includes: The first WQE is submitted in the first SQ, the first WQE includes the ID of any one of the processing cores, and the first WQE is used by the RNIC to generate the first CQE; the indication information in the first CQE is the ID of any one of the processing cores.

6. The method according to claim 1 or 2, characterized in that, The process of processing the first CQE based on the indication information includes: If the indication information is preset information, then the first CQE is processed by any one of the at least two processing cores.

7. The method according to claim 6, characterized in that, If the first CQE is used to indicate that the RNIC, as a responding end, has completed receiving an RDMA message, then the indication information is the preset information; The RDMA message includes any one of the following: a send message, a send message with an immediate value, a send message with a remote memory failure indication, or a write message with an immediate value.

8. A multi-core-based data processing method, characterized in that, The method is applied to a network interface card (NIC); the NIC communicates with a processor, the processor includes at least two processing cores, the at least two processing cores share a queue pair (QP), and the at least two processing cores correspond to at least one completion queue (CQ); the method includes: Generate the first completion queue entry (CQE); The first CQ in the at least one CQ is written into the first CQE; The first CQE includes indication information, which is used to indicate one of the at least two processing cores; the indication information is the identity ID of any one of the at least two processing cores; or the indication information is preset information, which is used to indicate that any one of the at least two processing cores is allowed to process the first CQE; the first CQE is used to process the first CQE based on the indication information when any one of the at least two processing cores accesses the first CQE. If the first CQE is used to indicate that the RNIC, as the requesting end, has completed a remote direct memory access (RDMA) operation, then the indication information is the ID of any one of the at least two processing cores; wherein, any one of the processing cores is the processing core that submitted the work queue element WQE corresponding to the first CQE, and the WQE is used to indicate the RDMA operation to be executed by the RNIC.

9. The method according to claim 8, characterized in that, The NIC is a Remote Direct Memory Access Network Interface Card (RNIC).

10. The method according to claim 8, characterized in that, The RDMA operation includes any one of the following: a transmit operation, a transmit operation with an immediate value, a transmit operation with a remote memory failure indication, a read operation, a write operation, a write operation with an immediate value, or an atomic ATOMIC operation.

11. The method according to claim 8 or 10, characterized in that, The NIC includes at least one queue pair QP, wherein the first QP of the at least one QP is associated with the first CQ; The first QP includes a first transmit queue SQ; The generation of the first completion queue entry (CQE) includes: The first CQE is generated based on the first WQE in the first SQ; Wherein, the first WQE is the WQE submitted by the first processing core among the at least two processing cores in the first SQ, and the first WQE includes the ID of the first processing core; the indication information in the first CQE is the ID of the first processing core.

12. The method according to claim 9, characterized in that, If the first CQE is used to indicate that the RNIC, as a responding end, has completed receiving an RDMA message, then the indication information is preset information; The RDMA message includes any one of the following: a send message, a send message with an immediate value, a send message with a remote memory failure indication, or a write message with an immediate value.

13. A multi-core based data processing device, characterized in that, Applied to a processor, the processor including at least two processing cores sharing a queue pair QP, the at least two processing cores corresponding to at least one completion queue CQ, the at least one CQ including a first CQ; the device includes: An access unit is configured to access the first CQ, which includes at least one completion queue entry (CQE); the at least one CQE includes a first CQE, which includes indication information. The indication information is used to indicate one of the at least two processing cores; the indication information is the identity ID of any of the at least two processing cores; or the indication information is preset information, which is used to indicate that any of the at least two processing cores is allowed to process the first CQE. A processing unit is configured to process the first CQE based on the indication information; The processor and the Remote Direct Memory Access Network Interface Card (RNIC) are connected and communicate. If the first CQE is used to indicate that the RNIC, as the requesting end, has completed a remote direct memory access (RDMA) operation, then the indication information is the ID of any one of the at least two processing cores; Wherein, any one of the processing cores is a processing core that submits a work queue element WQE corresponding to the first CQE, and the WQE is used to indicate the RDMA operation to be executed by the RNIC.

14. The apparatus according to claim 13, characterized in that, The first CQE is the header CQE of the first CQ.

15. The apparatus according to claim 13 or 14, characterized in that, The processing unit is specifically configured to process the first CQE through any one of the at least two processing cores if the indication information is the identity ID of the processing core.

16. The apparatus according to claim 13, characterized in that, The RDMA operation includes any one of the following: a transmit operation, a transmit operation with an immediate value, a transmit operation with a remote memory failure indication, a read operation, a write operation, a write operation with an immediate value, or an atomic ATOMIC operation.

17. The apparatus according to claim 13 or 16, characterized in that, The RNIC includes at least one queue pair QP, wherein the first QP of the at least one QP is associated with the first CQ; The first QP includes a first transmit queue SQ; The device further includes: The submission unit is configured to submit a first WQE in a first SQ before the access unit accesses the first CQ. The first WQE includes the ID of any one of the processing cores. The first WQE is used by the RNIC to generate the first CQE. The indication information in the first CQE is the ID of any one of the processing cores.

18. The apparatus according to claim 13 or 14, characterized in that, The processing unit is specifically configured to process the first CQE through any one of the at least two processing cores if the indication information is preset information.

19. The apparatus according to claim 18, characterized in that, If the first CQE is used to indicate that the RNIC, as a responding end, has completed receiving an RDMA message, then the indication information is the preset information; The RDMA message includes any one of the following: a send message, a send message with an immediate value, a send message with a remote memory failure indication, or a write message with an immediate value.

20. A multi-core based data processing device, characterized in that, An application is made to a network interface card (NIC); the NIC communicates with a processor, the processor including at least two processing cores, the at least two processing cores sharing a queue pair (QP), and the at least two processing cores corresponding to at least one completion queue (CQ); the device includes: A generation unit, used to generate the first completion queue entry (CQE); A writing unit is used to write the first CQE into the first CQ in the at least one CQ; The first CQE includes indication information, which is used to indicate one of the at least two processing cores; the indication information is the identity ID of any one of the at least two processing cores; or the indication information is preset information, which is used to indicate that any one of the at least two processing cores is allowed to process the first CQE; the first CQE is used to process the first CQE based on the indication information when any one of the at least two processing cores accesses the first CQE; if the first CQE is used to indicate that the RNIC as the requesting end has completed a remote direct memory access (RDMA) operation, then the indication information is the ID of any one of the at least two processing cores; wherein, any one of the processing cores is the processing core that submitted the work queue element WQE corresponding to the first CQE, and the WQE is used to indicate the RDMA operation to be executed by the RNIC.

21. The apparatus according to claim 20, characterized in that, The NIC is a Remote Direct Memory Access Network Interface Card (RNIC).

22. The apparatus according to claim 20, characterized in that, The RDMA operation includes any one of the following: a transmit operation, a transmit operation with an immediate value, a transmit operation with a remote memory failure indication, a read operation, a write operation, a write operation with an immediate value, or an atomic ATOMIC operation.

23. The apparatus according to claim 20 or 22, characterized in that, The NIC includes at least one queue pair QP, wherein a first QP of the at least one QP is associated with the first CQ; the first QP includes a first transmit queue SQ; The generation unit is specifically used to generate the first CQE based on the first WQE in the first SQ; Wherein, the first WQE is the WQE submitted by the first processing core among the at least two processing cores in the first SQ, and the first WQE includes the ID of the first processing core; the indication information in the first CQE is the ID of the first processing core.

24. The apparatus according to claim 21, characterized in that, If the first CQE is used to indicate that the RNIC, as a responding end, has completed receiving an RDMA message, then the indication information is preset information; The RDMA message includes any one of the following: a send message, a send message with an immediate value, a send message with a remote memory failure indication, or a write message with an immediate value.

25. A computer device, characterized in that, The computer device includes a processor and a network interface card (NIC); the processor includes at least two processing cores, each corresponding to at least one completion queue (CQ); the NIC includes at least one queue pair (QP), each QP associated with the at least one CQ. The processor is configured to perform the method as described in any one of claims 1-7, and the NIC is configured to perform the method as described in any one of claims 8-12.

26. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when run on a computer, causes the computer to perform the method as described in any one of claims 1-12.

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