Bubble burst register in a semiconductor device

Abstract

This application relates to a bubble-bursting register in a semiconductor device. An exemplary register circuit includes multiple time slots for storing corresponding address and data pairs. During a write operation, each of the multiple time slots preceding a specific time slot among the multiple time slots that is indicated as empty is shifted by one time slot to fill the specific time slot, such that a first-end time slot of the multiple time slots is available to receive a new write address and data pair. Each of the multiple time slots following the specific time slot retains an existing address and data pair.

Description

Technical Field

[0001] This disclosure relates generally to semiconductor devices, and more specifically to bubble burst registers in semiconductor devices. Background Technology

[0002] In some instances, semiconductor devices can use registers to store a limited amount of information. One type of register is the First-In-First-Out (FIFO) register. In a FIFO register, data is shifted through the register in chronological order, such that when it is full, the oldest data is pushed out as new data is received. When data is consumed from a specific time slot in the FIFO register, that time slot becomes empty. However, because the architecture of a FIFO register involves shifting new data into the register at the first time slot and shifting old data out at the second time slot, empty time slots remain in the register until they are shifted out of the old time slot. This can result in empty data time slots not being filled, leading to inefficient use of the FIFO register. Summary of the Invention

[0003] According to one aspect of this application, an apparatus is provided. The apparatus includes: a register circuit comprising a plurality of time slots for storing corresponding address and data pairs, wherein, during a write operation, each of the plurality of time slots preceding a specific time slot among the plurality of time slots indicated as empty is shifted by one time slot to fill the specific time slot, such that a first end time slot among the plurality of time slots is available to receive a new write address and data pair, wherein each of the plurality of time slots following the specific time slot retains an existing address and data pair.

[0004] According to another aspect of this application, an apparatus is provided. The apparatus includes: a flag path circuit configured to maintain a first flag signal corresponding to a first corresponding time slot of a register, a second flag signal corresponding to a second corresponding time slot of the register, and a third flag signal corresponding to a third corresponding time slot of the register located between the first and second corresponding time slots, wherein the first, second, and third flag signals are configured to indicate whether the first, second, and third data time slots are empty, respectively; and an address path circuit including: a first latch circuit corresponding to the first time slot and configured to store a first address; a second latch circuit corresponding to the second time slot and configured to store a second address; and... A third latch circuit, corresponding to a third time slot and configured to store a third address, wherein during a write operation, and in response to first and second flag signals indicating that the first and second time slots have valid data and a third flag signal indicating that the third time slot is empty, in response to the third flag signal indicating that the third time slot is empty, a first address is shifted to the third latch circuit to store the first address as the third address, and a new write address is shifted to the first latch circuit as the first address, wherein during the write operation, based on the shift of the first address to the third latch circuit, the third flag signal is switched to indicate that the third time slot contains valid data.

[0005] According to another aspect of this application, a method is provided. The method comprises: during a write operation: shifting each of the multiple time slots of a shift register before a specific time slot that is indicated to be empty by one time slot to fill the specific time slot, such that a first end time slot of the multiple time slots becomes available; shifting a new write address and data pair into the first end time slot; and retaining the existing address and data pair in the time slots following the specific time slot. Attached Figure Description

[0006] Figure 1 This is a schematic block diagram of a semiconductor device 100 according to an embodiment of the present disclosure.

[0007] Figure 2 This is a block diagram of a computing system 200 according to an embodiment of the present disclosure.

[0008] Figure 3A This is a block diagram of a logic circuit 300 of a semiconductor device for processing write commands according to an embodiment of the present disclosure.

[0009] Figure 3B This is a block diagram of logic circuit 301 of a semiconductor device for processing read commands according to an embodiment of the present disclosure.

[0010] Figure 4 This is a schematic block diagram of a bubble bursting register circuit of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 5The description illustrates the execution of a write operation according to embodiments of the present disclosure. Figure 4 A schematic block diagram of a portion of the bubble bursting register circuit.

[0012] Figure 6 The description illustrates the execution of a read operation according to embodiments of the present disclosure. Figure 4 A schematic block diagram of a portion of the bubble bursting register circuit.

[0013] Figure 7 This includes exemplary timing diagrams of read and write accesses associated with the bubble burst register according to embodiments of the present disclosure. Detailed Implementation

[0014] This disclosure describes an example of a bubble-bursting register or buffer architecture configured to fully utilize the register by selectively shifting received data to fill empty time slots, without waiting until the empty time slot is shifted out of the end time slot. The bubble-bursting register architecture includes flag circuitry and at least one data type circuit. The flag circuitry includes a corresponding flag for each time slot in the register, configured to indicate whether a particular time slot in the register currently holds valid data, and the data circuitry includes corresponding circuitry for each time slot to hold the received data. Thus, for a particular time slot, the corresponding flag indicates whether the data stored in the corresponding data circuitry is valid. When the corresponding flag for a particular time slot indicates invalid data (e.g., an empty time slot or bubble in the register), shifting new data into the register results in filling the empty time slot by shifting existing data from a previous time slot by one time slot, making the first end time slot available to shift in new data, while subsequent time slots storing valid data remain unaffected. For example, the register may include four data time slots, with all but a third time slot holding valid data. When new data is received, data from the second time slot can be shifted to fill an empty third time slot, data from the first time slot can be shifted to replace data in the second time slot, and new data can be shifted into the first time slot. In this example, the fourth time slot remains unaffected by the shifts.

[0015] In some instances, bubble burst registers can be used to store a finite subset of address and write data information in a semiconductor device configurable for low latency mode operation. That is, in low latency mode, the semiconductor device can use bubble burst registers to store write data instead of performing memory array accesses to execute read or write commands. Low latency operation mode can be configured to support full-speed computation for certain types of applications, such as artificial intelligence (AI) or machine learning (ML) applications. The computations performed by these applications can be iterative, data-intensive computations requiring frequent access to newly generated data.

[0016] Certain details are set forth below to provide a full understanding of embodiments of this disclosure. However, those skilled in the art will appreciate that embodiments of this disclosure can be practiced without these specific details. Furthermore, the specific embodiments of this disclosure described herein are provided by way of example and should not be intended to limit the scope of this disclosure to these specific embodiments. In other instances, well-known circuits, control signals, timing protocols, and software operations are not shown in detail to avoid unnecessarily obscuring this disclosure.

[0017] Figure 1 This is a schematic block diagram of a semiconductor device 100 according to an embodiment of the present disclosure. For example, the semiconductor device 100 may include a chip 135. Chip 135 may include a clock input circuit 105, an internal clock generator 107, an address command input circuit 115, an address decoder 120, a command decoder 125, a control circuit 121, a low latency register 122, multiple row decoders 130, a memory cell array 145 including a sense amplifier 150 and a transmission gate 195, multiple column decoders 140, multiple read / write amplifiers 165, input / output (I / O) circuitry 170, and a voltage generator 190. The semiconductor device 100 may include multiple external terminals, including address and command terminals coupled to a command / address bus 110, clock terminals CK and / or CK, data terminals DQ, DQS, and DM, and power supply terminals VDD, VSS, VDDQ, and VSSQ. Chip 135 may be mounted on a substrate, such as a memory module substrate, a motherboard, etc.

[0018] The memory cell array 145 includes multiple memory banks BANK0-N, each of which includes multiple word lines WL, multiple bit lines BL, and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BL. The number of memory banks BANK0-N may include 2, 4, 8, 16, or any other number of memory banks. Each of the memory banks BANK0-N may be divided into two or more memory planes (e.g., column planes), which may be selected by a column selection CS signal from the column decoder 140. In some instances, each of the memory banks BANK0-N may include 2, 4, 8, 16, 32, etc. The selection of the word lines WL for each memory bank is performed by the corresponding row decoder 130, while the selection of the bit lines BL is performed by the corresponding column decoder 140. Multiple sense amplifiers 150 are positioned for their respective bit lines BL and coupled to at least one corresponding local I / O line via a transmission gate TG 195, which acts as a switch. The local I / O line is further coupled to one of at least two main I / O line pairs.

[0019] Address / command input circuit 115 can receive address signals and memory address signals from the outside via command / address bus 110 at command / address terminals, and transmit the address signals and memory address signals to address decoder 120. Address decoder 120 can decode the address signals received from address / command input circuit 115, and provide row address signal XADD to row decoder 130 and column address signal YADD to column decoder 140. Address decoder 120 can also receive memory address signals and provide memory address signal BADD to row decoder 130 and column decoder 140.

[0020] Address / command input circuitry 115 can receive command signals from an external source (e.g., memory controller 105) at the command / address terminal via command / address bus 110 and provide the command signals to command decoder 125. Command decoder 125 can decode the command signals and generate various internal command signals. For example, internal command signals may include row command signals for selecting word lines, column command signals for selecting bit lines (e.g., read or write commands), and / or low latency enable bits for enabling the use of control circuitry 121 and / or low latency register 122.

[0021] Typically, when a read command is issued along with the row and column addresses, read data is read from the memory cell array 145 specified by the row and column addresses. The read / write amplifier 165 can receive the read data DQ and provide it to the I / O circuit 170. The I / O circuit 170 can provide the read data DQ, along with the data strobe signal at DQS and / or the data mask signal at DM, to the external location via the data terminal DQ. Similarly, when a write command is issued along with the row and column addresses, the input / output circuit 170 can receive the write data at the data terminal DQ, and together with the data strobe signal at DQS and / or the data mask signal at DM, and provide the write data to the memory cell array 145 via the read / write amplifier 165. Therefore, write data can be written to the memory cell specified by the row and column addresses.

[0022] However, in some instances, semiconductor device 100 may be configured to operate in a low latency mode by executing read or write commands using low latency register 122, rather than by performing access to memory cell array 145 to execute read or write commands. Control circuitry 121 may be configured to determine whether semiconductor device 100 is in a low latency mode (e.g., a first mode) or a normal mode (e.g., a second mode). The low latency operation mode may be configured to support full-speed computation for certain types of applications (e.g., artificial intelligence (AI) or machine learning (ML) applications). The computations performed by these applications may be iterative, data-intensive computations that require frequent access to newly generated data. Low latency register 122 may include registers capable of storing a finite subset of address and data information. Therefore, to support certain applications instead of writing certain data to memory cell array 145, control circuitry 121 may be configured to cause data to be read from or written to low latency register 122. The operation of the low latency register 122 can be synchronous and in response to the LCLK signal provided from the internal clock generator 107.

[0023] Control circuitry 121 can determine whether a low latency mode (e.g., using low latency register 122) or a normal mode (e.g., using memory cell array 145) should be used to execute access commands. In some instances, a processor unit (e.g., a memory control unit, memory processing unit, graphics processing unit, central processing unit, general-purpose graphics processing unit, system-on-a-chip, field-programmable gate array, or any other type of processing unit) can guide semiconductor device 100 to execute access commands in a low latency mode via one or more bits (e.g., low latency enable bits) included in command and address information, which can be provided to semiconductor device 100 via command and address bus 110.

[0024] Control circuitry 121 can decode command and address information to determine the value of a low latency enable bit. In response to a low latency enable bit having a first value that enables a low latency operation mode, control circuitry 121 can direct the execution of a command (e.g., read or write) received along with the command and address information to low latency register 122, either in parallel with directing the execution of the command to memory array 145, or as a supplement to directing the execution of the command to memory array 145.

[0025] For example, when in a low latency operation mode based on a low latency enable bit, and when the command is a read command, control circuitry 121 can provide the low latency enable bit and the read command to enable low latency register 122 to compare the address received along with the command and address information (e.g., provided from address decoder 120) with the address stored in low latency register 122. If a match is detected, low latency register 122 can provide the corresponding read data stored in low latency register 122 to I / O circuitry 170 in response to the read command. In an instance where the address is also provided to bank logic circuitry (e.g., row decoder 130 and / or column decoder 140) to initiate access to memory cell array 145, if an address match is found in low latency register 122, low latency register 122 can provide a "no match detected" unMATCH signal (e.g., active low) to cause the memory cell array 145 access process to pause or stop. If no match is found, the low latency register can set the unMATCH signal, which allows the memory bank logic circuitry to continue the memory cell array 145 access process to retrieve data from the memory cell array 145 based on the address. In addition to being able to provide data faster (e.g., with lower latency compared to accessing the memory cell array 145), the low latency register 122, configured to stop access to the memory cell array 145 before initiating access lines (e.g., column select lines, word lines, and / or bit lines BL and / or BL) and / or sense amplifier 150, reduces power consumption in the memory and reduces sensitivity to row hammer attacks.

[0026] When in a low latency operation mode based on a low latency enable bit and when the command is a write command, control circuitry 121 provides a low latency enable signal, a write command, and a write enable signal; address decoder 120 provides an address; and I / O circuitry 170 provides corresponding write data to low latency register 122 for storage. In response, low latency register 122 can store the address and write data received from I / O circuitry 170 in an available time slot. In some instances, if no time slot is available, control circuitry 121 can write write data to memory cell array 145 based on the address. Control circuitry 121 can determine if a time slot is available based on the register full signal REF FULL provided from low latency register 122. In other instances, when the REG FULL signal indicates that low latency register 122 is full, control circuitry 121 can push data from low latency register 122 to memory cell array 145. In some instances, if the low latency register 122 contains previously stored data corresponding to the received address, the previously stored data can be marked as invalid, and the new address and write data can be stored in a new timeslot. Storing write data in the low latency register 122 is faster than storing write data in the memory cell array 145, and provides faster access to stored write data compared to accessing write data stored in the memory cell array 145, which can improve the efficiency of certain applications.

[0027] In some instances, register 122 includes a bubble-bursting register or buffer architecture configured to fully utilize register 122 by selectively shifting received data to fill empty time slots, without waiting until an empty time slot is shifted out of the end time slot. Therefore, register 122 includes flag path circuitry, address path circuitry, and write data path circuitry. The flag path circuitry includes corresponding flag latch circuitry configured to provide a corresponding flag signal for each time slot in register 122. Each corresponding flag is configured to provide an indication of whether a specific time slot in the register currently holds valid address and data. The address path circuitry includes a first set of corresponding latch circuitry corresponding to the time slots of register 122 to store the received write address. The data path circuitry includes a second set of corresponding latch-type circuitry corresponding to the time slots of register 122, each latch-type circuitry configured to store the received write data. Flag signal switching indicates that a corresponding time slot has valid write and address data in response to being shifted into the corresponding time slot, and is configured to switch to indicate that the corresponding time slot is empty in response to a newer write address and data matching the write address being written to a different time slot or in response to reading write data from the corresponding time slot. When the corresponding flag of a particular time slot indicates invalid address and write data (e.g., an empty time slot or bubble in register 122), shifting new data into register 122 can result in filling the empty time slot by shifting the existing address and write data from the previous time slot by one time slot, making the first time slot available for shifting in new address and write data, while subsequent time slots storing valid address and write data remain unaffected. For example, register 122 may include four data time slots, all of which, except for the third time slot, retain valid address and write data. When a new address and write data are received, the address and write data from the second time slot can be shifted to fill the empty third time slot, the address and write data from the first time slot can be shifted to replace the address and write data in the second time slot, and the new address and write data can be shifted into the first time slot. In this example, the address and write data remaining in the fourth time slot can remain unaffected by the shift.

[0028] Turning to the description of external terminals included in semiconductor device 100, clock terminals CK and / CK can receive an external clock signal and a complementary external clock signal, respectively. The external clock signal (including the complementary external clock signal) can be provided to clock input circuit 105. Clock input circuit 105 can receive the external clock signal and generate an internal clock signal ICLK. Clock input circuit 105 can provide the internal clock signal ICLK to internal clock generator 107. Internal clock generator 107 can generate a phase-controlled internal clock signal LCLK based on the internal clock signal ICLK received from address / command input circuit 115 and a clock enable signal CKE. Although not limited thereto, a DLL circuit can be used as internal clock generator 107. Internal clock generator 107 can provide the phase-controlled internal clock signal LCLK to I / O circuit 170. I / O circuit 170 can use the phase controller internal clock signal LCLK as a timing signal for determining the output timing of read data.

[0029] The power supply terminals can receive power supply voltages VDD and VSS. These power supply voltages VDD and VSS can be supplied to voltage generator circuit 190. Voltage generator circuit 190 can generate various internal voltages VPP, VOD, VARY, VPERI, etc., based on the power supply voltages VDD and VSS. Internal voltage VPP is mainly used in line decoder 130, internal voltages VOD and VARY are mainly used in sense amplifier 150 included in memory cell array 145, and internal voltage VPERI is used in many other circuit blocks. The power supply terminals can also receive power supply voltages VDDQ and VSSQ. IO circuit 170 can receive power supply voltages VDDQ and VSSQ. For example, power supply voltages VDDQ and VSSQ can be the same voltages as power supply voltages VDD and VSS, respectively. However, dedicated power supply voltages VDDQ and VSSQ can be used in IO circuit 170.

[0030] Figure 2 This is a block diagram of a computing system 200 according to an embodiment of the present disclosure. The computing system 200 includes a processor unit 204 communicating with a cache 206 and DRAM 210. DRAM 210 may include a low latency register 212 configured for a low latency mode.

[0031] Processor unit 204 may include one or more processor units of any type, such as a memory control unit, memory processing unit, graphics processing unit, central processing unit, general-purpose graphics processing unit, system-on-a-chip, field-programmable gate array, etc. Processor unit 204 may be configured to execute instructions associated with one or more applications running in the computing system. Execution of instructions may require temporary storage of data for later instruction execution.

[0032] Cache 206 and DRAM 210 facilitate the storage of data generated by processor unit 204 during instruction execution. Cache 206 is typically configured to provide fast (e.g., low latency) access to frequently accessed data from DRAM 210. Cache 206 may have a smaller size than DRAM 210. In some instances, cache 206 may include multiple levels, each varying in size and / or access latency. For example, the L1 cache of cache 206 may have a smaller capacity than the L2 cache, but may also have lower latency. Cache 206 is typically configured to store copies of data stored at DRAM 210. For instance, cache 206 may store data retrieved from DRAM 210 during instruction execution and / or may store new data generated by processor unit 204 during instruction execution, where the new or updated data is eventually written to DRAM 210. Although a two-level cache is depicted in cache 206, it is understood that cache 206 may include only one level or may include three or more levels.

[0033] DRAM 210 can have a larger capacity than cache 206 (e.g., several orders of magnitude larger), but typically has a longer access latency. DRAM 210 can include any type and / or version of DRAM, including low-power DRAM, synchronous DRAM, Rambus DRAM, graphics processing DRAM, etc. Data generated by processor unit 204 during the execution of application instructions can be stored at DRAM 210. However, while data access operations associated with DRAM 210 can typically take much longer than those associated with cache 206, DRAM 210 can include a low latency register 212 configured to store data recognized by processor unit 204 as low latency data. Low latency register 212 can be a smaller capacity register capable of storing and retrieving data faster than data stored in the memory array of DRAM 210. In some instances, processor unit 204 can direct DRAM 210 to store low latency data at low latency register 212 via bits in command and address information. DRAM 210 may include FIFO registers, bubble registers, or any other type of register capable of storing addresses and data.

[0034] During operation, processor unit 204 can execute instructions associated with one or more applications. Applications can include any type of application that can be executed by processor unit 204. During execution, processor unit 204 can provide commands to write data to or read data from memory. Cache 206 and / or DRAM 210 can receive write and read commands and can perform access operations based on these commands. During normal operation, in response to a write command issued by processor unit 204, cache 206 can determine whether any block in cache 206 has data associated with the address corresponding to the write command, and if so, rewrite the data with new write data. The new write data can ultimately be stored in DRAM 210. If no block in cache 206 has data associated with the address, cache 206 can load the data associated with the address from DRAM 210, then rewrite the retrieved data with the new data, and then store the new data back in DRAM 210.

[0035] In response to a read command issued by processor unit 204, cache 206 can determine whether any block in cache 206 has data associated with the address corresponding to the read command, and if so, can return the data from that block. If no block in cache 206 has data associated with that address, cache 206 can load the data associated with that address from DRAM 210 into the block, and can then return the data.

[0036] However, in some instances, processor unit 204 may operate in a low latency mode to communicate directly with DRAM 210 to read and write data to the low latency register 212, rather than reading and writing data to the memory array of DRAM 210. Processor unit 204 can indicate the low latency mode by setting a low latency enable bit included in command and address information. The low latency operation mode can be configured to support full-speed computation for certain types of applications, such as artificial intelligence (AI) or machine learning (ML) applications. The computations performed by these applications can be iterative, data-intensive computations requiring frequent access to newly generated data. The low latency register 212 of DRAM 210 may include registers capable of storing a finite subset of address and data information. Therefore, to support certain applications, rather than writing certain data to the memory array of DRAM 210, DRAM 210 may be configured to cause data to be read from or written to the low latency register 212.

[0037] DRAM 210 can determine whether to use a low latency mode (e.g., using low latency register 212) or a normal mode (e.g., using a memory array) to execute access commands. The control circuitry of DRAM 210 can decode command and address information to determine the value of the low latency enable bit. In response to the low latency enable bit having a first value that enables low latency operation mode, the control circuitry can direct the execution of a command (e.g., read or write) received along with the command and address information to low latency register 212, either in parallel with directing the execution of the command to the memory array, or as a supplement to directing the execution of the command to the memory array. For example, when in a low latency operation mode based on the low latency enable bit, and when the command is a read command, the control circuitry can cause low latency register 212 to compare the address received along with the command and address information with the address stored in low latency register 212. If a match is detected, low latency register 212 can provide the corresponding data stored in low latency register 212 to processor unit 204 in response to the read command. In instances where an address is also provided to the memory bank logic circuitry (e.g., row decoders and / or column decoders) to initiate access to the memory array, if an address match is found in the low latency register 212, the low latency register 212 can provide a match signal to cause the memory array access process to pause or stop. If no match is found, the DRAM 210 can continue the memory array access process to retrieve data from the memory array based on the address. In addition to being able to provide data faster (e.g., with lower latency compared to access to the memory cell array), the low latency register 212, configured to stop memory array access before initiating access lines (e.g., word lines and / or bit lines) and / or sense amplifiers, reduces power consumption in the DRAM 210 and reduces sensitivity to rowhammer attacks.

[0038] When in a low latency operation mode based on a low latency enable bit and when the command is a write command, the control circuitry can provide the address and corresponding write data to the low latency register 212 for storage. In response, the low latency register 212 can store the address and corresponding write data in an available time slot. In some instances, if no time slot is available, the control circuitry can cause the write data to be written to the memory array based on the address. The control circuitry can determine whether a time slot is available based on a register full signal provided from the low latency register 212. In other instances, when the low latency register 212 is full, the control circuitry can cause data to be pushed from the low latency register 212 to the memory array. In some instances, if the low latency register 212 contains previously stored data corresponding to the received address, the previously stored data can be marked as invalid, and the new address and write data can be stored in a new time slot. The process of storing write data in the low latency register 212 is faster than storing write data in the memory array of DRAM 210, and provides faster access to stored write data compared to accessing write data stored in the memory array, which can improve the efficiency of certain applications.

[0039] In some instances, the low latency register 212 includes a bubble-bursting register or buffer architecture configured to fully utilize the low latency register 212 by selectively shifting received data to fill empty time slots, without waiting until an empty time slot is shifted out of the end time slot. Therefore, the low latency register 212 includes flag path circuitry, address path circuitry, and write data path circuitry. The flag path circuitry includes corresponding flag latch circuitry configured to provide a corresponding flag signal for each time slot in the low latency register 212. Each corresponding flag is configured to provide an indication of whether a specific time slot in the register currently holds valid address and data. The address path circuitry includes a first set of corresponding latch circuitry corresponding to the time slots of the low latency register 212 to store received write addresses. The data path circuitry includes a second set of corresponding latch-type circuitry corresponding to the time slots of the low latency register 212, each latch-type circuitry configured to store received write data. Flag signal switching indicates that a corresponding time slot has valid write and address data in response to being shifted into the corresponding time slot, and is configured to switch to indicate that the corresponding time slot is empty in response to a newer write address and data matching the write address being written to a different time slot or in response to reading write data from the corresponding time slot. When the corresponding flag of a particular time slot indicates invalid address and write data (e.g., an empty time slot or bubble in low latency register 212), shifting new data into low latency register 212 can result in filling the empty time slot by shifting existing address and write data from the previous time slot by one time slot, making the first time slot available to shift in new address and write data, while subsequent time slots storing valid address and write data remain unaffected. For example, low latency register 212 may include four data time slots, all of which, except for the third time slot, hold valid address and write data. When a new address and write data are received, the address and write data from the second time slot can be shifted to fill the empty third time slot, the address and write data from the first time slot can be shifted to replace the address and write data in the second time slot, and the new address and write data can be shifted into the first time slot. In this example, the address and write data remaining in the fourth time slot can remain unaffected by the shift.

[0040] Figure 3A This is a block diagram of logic circuitry 300 for processing write commands in a semiconductor device according to embodiments of the present disclosure. Logic circuitry 300 includes write control circuitry 321(1) coupled to a low latency register 322 and memory bank logic 340. Memory bank logic 340 is coupled to a memory array 345. In some instances, Figure 1 Semiconductor device 100 and / or Figure 2 The DRAM 210 with a low latency register 212 can achieve 300.

[0041] Write control circuitry 321(1) may include an AND gate 330 and an OR gate 332 coupled to the AND gate 333, and may be configured to receive a low latency enable bit LL, a write command WR, and a register full signal REG FULL. The AND gate 330 may be configured to apply AND logic to provide a high-active low latency enable signal LLEN to the low latency register 322 based on the value of the LL bit, the WR command, and the inverted REG FULL signal (via an inverter). The OR gate 332 may be configured to apply OR logic to the REF FULL signal and the inverted LL bit (via an inverter) to signal the AND gate 333. The AND gate 333 may be configured to apply AND logic to the WR command and the output of the OR gate 332 to provide a low-active LL enable signal LLENF.

[0042] Low latency register 322 can be configured to receive the LLEN signal, the WREN write enable signal, and the address and data corresponding to a write command. In response to the LLEN signal having a first value and the WREN signal indicating write capability, low latency register 322 can be configured to store the address and data in a timeslot. If low latency register 322 is full after storing the address and data, it can update the REF FULL signal to indicate that no timeslot is available. If the timeslot of low latency register 322 includes a previously stored address that matches the received address, it can mark the previously stored address timeslot as invalid when the received address is stored in a new timeslot. When the LLEN signal has a second value, low latency register 322 is not updated.

[0043] The memory bank logic 340 can be configured to receive an LLENF signal, a WREN signal, and an address and data corresponding to a write command. In response to the LLENF signal having a first value and the WREN signal indicating write capability, the memory bank logic 340 can be configured to set the control signal CTRL to cause the memory array 345 to perform a write access to store the received data at the location in the memory array 345 corresponding to the received address. If the LLENF signal has a second value, the memory bank logic 340 prevents write access to the memory array 345 via the CTRL signal.

[0044] Figure 3B This is a block diagram of logic circuitry 301 for processing read commands in a semiconductor device according to an embodiment of the present disclosure. Logic circuitry 301 includes read control circuitry 321(2) coupled to a low latency register 322 and memory bank logic 340. Memory bank logic 340 is coupled to a memory array 345. In some instances, Figure 1Semiconductor device 100 and / or Figure 2 The DRAM 210 with a low latency register 212 can implement 301. The logic circuit 301 may include previously mentioned... Figure 3A The logic circuit 300 describes the components. In Figure 3B Used with Figure 3A The same reference numerals are used to identify those elements, and the operation of common elements is as described above. Therefore, for the sake of brevity, a detailed description of the operation of these specific elements will not be repeated.

[0045] The read control circuit 321(2) may include an AND gate 334 and may be configured to receive the LL bit and the read command RD. The AND gate 334 may be configured to apply AND logic to provide a high-active low latency enable signal LLEN to the low latency register 322 based on the value of the LL bit and the RD command. The read control circuit 321(2) may also be configured to provide the RD command to the memory logic 340.

[0046] Low latency register 322 can be configured to receive the LLEN signal and the address corresponding to a read command. In response to the LLEN signal having a first value, low latency register 322 can be configured to search for a match between the received address and the address stored in the time slot of low latency register 322. If a match is detected, low latency register 322 can be configured to clear the unMATCH signal provided to memory logic 340 and provide the read data from the time slot corresponding to the matching address to the output. Low latency register 322 can also be configured to flag a flag associated with the matching address and data to indicate that data has been read, making the time slot available for storing new data. If no match is found, low latency register 322 can be configured to set the unMATCH signal to indicate that no match was detected.

[0047] The memory bank logic 340 can be configured to receive an RD command, an address, and a MATCH signal. In response to the RD command, the memory bank logic 340 can be configured to initiate a read access to the memory array 345 based on the address. In response to clearing the unMATCH signal, the memory bank logic 340 can pause or stop the read access before setting the CTRL signal to activate the access line and the sense amplifier. If the unMATCH signal is set, the memory bank logic 340 can continue the read access by setting the CTRL signal to perform a read access to the memory array 345, retrieving the location of the memory array 345 corresponding to the received address, and providing the read data.

[0048] In some instances, the low latency register 322 includes a bubble-bursting register or buffer architecture configured to fully utilize the low latency register 322 by selectively shifting received data to fill empty time slots, without waiting until an empty time slot is shifted out of the end time slot. Therefore, the low latency register 322 includes flag path circuitry, address path circuitry, and write data path circuitry. The flag path circuitry includes corresponding flag latch circuitry configured to provide a corresponding flag signal for each time slot in the low latency register 322. Each corresponding flag is configured to provide an indication of whether a specific time slot in the register currently holds valid address and data. The address path circuitry includes a first set of corresponding latch circuitry corresponding to the time slots of the low latency register 322 to store the received write address. The data path circuitry includes a second set of corresponding latch-type circuitry corresponding to the time slots of the low latency register 322, each latch-type circuitry configured to store the received write data. Flag signal switching indicates that a corresponding time slot has valid write and address data in response to being shifted into the corresponding time slot, and is configured to switch to indicate that the corresponding time slot is empty in response to a newer write address and data matching the write address being written to a different time slot or in response to reading write data from the corresponding time slot. When the corresponding flag of a particular time slot indicates invalid address and write data (e.g., an empty time slot or bubble in low latency register 322), shifting new data into low latency register 322 can result in filling the empty time slot by shifting existing address and write data from the previous time slot by one time slot, making the first time slot available to shift in new address and write data, while subsequent time slots storing valid address and write data remain unaffected. For example, low latency register 322 may include four data time slots, all of which, except for the third time slot, hold valid address and write data. When a new address and write data are received, the address and write data from the second time slot can be shifted to fill the empty third time slot, the address and write data from the first time slot can be shifted to replace the address and write data in the second time slot, and the new address and write data can be shifted into the first time slot. In this example, the address and write data remaining in the fourth time slot can remain unaffected by the shift.

[0049] In addition to being able to store and / or provide data faster (e.g., with lower latency compared to accesses of memory cell array memory array 345), it is configured to stop memory array accesses before starting access lines (e.g., word lines and / or bit lines) and / or sense amplifiers. Figure 3A and 3B The low latency register 322 can also reduce power consumption in semiconductor devices and reduce sensitivity to row hammer attacks.

[0050] Figure 4This is a schematic block diagram of a bubble burst register circuit 400 of a semiconductor device according to an embodiment of the present disclosure. The bubble burst register circuit 400 includes control circuitry 410; a flag / address path 421 having flag path circuitry 430, address matching logic circuitry 440, and address path circuitry 450; and a data / read path 422 having data path circuitry 460 and read data path circuitry 470. In some instances, Figure 1 Register 122, Figure 2 Low latency register 212 and / or Figure 3A and 3B Any one of the low latency registers 322 can implement the bubble burst register circuit 400.

[0051] Control circuitry 410 may include NAND gate 411 coupled to an AND gate formed by NAND gate 412 and inverter 413. Control circuitry 410 may also include multiplexers 415 and 416, each configured to complementary (e.g., active high and active low via inverter 414) write enable signal WREN. NAND gate 411 is configured to receive flag bits FLG<3:0> from flag path circuitry 430, each flag bit indicating whether a specific time slot of low latency register 400 holds valid data, and NAND gate 411 is configured to apply NAND logic to provide an output to NAND gate 412 (e.g., when all FLG<3:0> bits are set, the output of NAND gate 411 is set to a low logic value; otherwise, it is set to a high logic value). In addition to the output of NAND gate 411, NAND gate 412 is configured to receive clock signal CLK and low latency enable signal LLEN. Based on the output of NAND gate 411, the CLK signal, and the LLEN signal, NAND gate 412 is configured to provide an output to inverter 413, which inverts the output to provide write clock signal CLKW to circuits 420, 460, and 450.

[0052] Multiplexer 415 is configured to selectively provide a high-active WREN signal to address matching logic circuit 440 in response to a LLEN signal having a first value, and to provide a low-active WREN signal (via inverter 414) to address matching logic circuit 440 in response to a LLEN signal having a second value. Multiplexer 416 is configured to selectively provide a low-active WREN signal (via inverter 414) as a pass enable signal PSSEN in response to a LLEN signal having a first value, and to provide a low voltage VSS as a PSSEN signal in response to a LLEN signal having a second value.

[0053] Flag path circuit 430 of 420 includes a set of flag flip-flops 432(0)-(3), and address path circuit 450 of 420 includes a corresponding set of address flip-flops 452(0)-(3). In addition to the set of flag flip-flops 432(0)-(3), flag path circuit 430 also includes a set of NAND gates 434(0)-(2) and a set of transistors 436(0)-(2). In some instances, each of transistors 436(0)-(2) may include a p-type transistor enabled in response to a low logic signal input at the corresponding gate. Each of the flag flip-flop sets 432(1)-(3) is configured to receive the output of the preceding flip-flop in the flag flip-flop set 432(0)-(2) via transistor 436(0)-(2), wherein flag flip-flop 432(0) is configured to receive a high-state active flag signal FLGX and may provide a corresponding FLG<3:0> signal at the output. Each flag trigger 432(0)-(3) can respond to the CLKW signal at the output terminal to convert the corresponding input signal into the corresponding FLG<3:0> signal.

[0054] NAND gate 434(0) can be configured to receive FLG <0> Signals and PSSEN signals, and can be configured based on FLG. <0> Signals and PSSEN signals are used to apply NAND logic to transistor 436. <0> Provide FLGPSS <0> Signal. Transistor 436 <0> Can be configured to be based on FLGPSS <0> The signal value selectively converts FLG <0> The signal is provided to the input of the flag trigger 432(1).

[0055] NAND gate 434(1) can be configured to receive FLG <1> Signal, FLG <0> Signals and PSSEN signals, and can be configured based on FLG. <1> Signal, FLG <0> Signals and PSSEN signals are used to apply NAND logic to transistor 436. <1> And NAND gate 434(2) provides FLGPSS <1> Signal. Transistor 436 <1> Can be configured to be based on FLGPSS <1> The signal value selectively converts FLG <1> The signal is provided to the input of the flag trigger 432(2).

[0056] NAND gate 434(1) can be configured to receive low-state active FLGPSS (via inverter). <1> Signal, FLG <2> Signals and PSSEN signals, and can be configured to be active FLGPSS in low state. <1> Signal, FLG <2> The signal and PSSEN signal use NAND logic to convert FLGPSS <2> The signal is provided to transistor 436 <2> Transistor 436 <2> Can be configured to be based on FLGPSS <2> The signal value selectively converts FLG <2> The signal is provided to the input of the flag trigger 432(3).

[0057] The address matching logic circuit 440 of 420 includes a set of XNOR gates 442(0)-(3), a set of AND gates 444(0)-(3), and a set of pass gates 446(0)-(4). Each of the XNOR gates 442(0)-(3) is configured to compare the received address bit ADDX with the output address bit ADD<3:0> from the corresponding one of the address flip-flops 452(0)-(3) (e.g., using XNOR logic) and provide the result of the comparison to the corresponding one of the AND gates 444(0)-(3). Each of the AND gates 444(0)-(3) is configured to apply AND logic to compare the output of the corresponding one of the XNOR gates 442(0)-(3) with the corresponding FLG<3:0> signal to provide the corresponding read enable signals RDEN0-RDEN3. Therefore, each of the RDEN0-RDEN3 signals indicates that the corresponding ADD<3:0> bit is valid and it matches the received ADDX bit. In response to the output of multiplexer 415, each of the RDEN0-RDEN3 signals can be passed through the corresponding one of the pass gates 446(0)-(3) to reset the corresponding one of the flag trigger groups 432(0)-(3).

[0058] In addition to the set of address flip-flops 452(0)-(3), the address path circuit 450 also includes a set of transistors 454(0)-(2). Each of transistors 454(0)-(2) can be configured to selectively provide the corresponding ADD<2:0> address from the output of address flip-flops 452(0)-(2) to the input of a subsequent flip-flop in address flip-flops 452(1)-(3) in response to a FLGPSS<3:0> signal. In some instances, each of transistors 454(0)-(3) may include a p-type transistor enabled in response to a low logic signal input at the corresponding gate. Thus, each of the address flip-flop set 452(1)-(3) is configured to receive the output of the previous flip-flop in the address flip-flop set 452(0)-(2) via transistors 454(0)-(2) based on the FLGPSS<2:0> signal, wherein the first address flip-flop 452(0) is configured to receive the new address ADDX and may provide the corresponding ADD<3:0> address at its output. Each of the address flip-flops 452(0)-(3) can convert the corresponding input signal into the corresponding ADD<3:0> signal at the output in response to the CLKW signal.

[0059] The data path circuit 460 of the data / read path 422 may include a set of data flip-flops 462(0)-(3) and a set of transistors 464(0)-(2). Each of the transistors 464(0)-(2) may be configured to selectively provide the corresponding DATA<2:0> from the output of the data flip-flop 462(0)-(2) to the input of the subsequent flip-flop in the data flip-flop 462(1)-(3) in response to the FLGPSS<2:0> signal. In some instances, each of the transistors 464(0)-(2) may include a p-type transistor enabled in response to a low logic signal input at the corresponding gate. Thus, each of the data flip-flop group 462(1)-(3) is configured to receive the output of the previous flip-flop in the data flip-flop group 462(0)-(2) via the transistors 464(0)-(2) based on the FLGPSS<2:0> signal, wherein the first address flip-flop 452(0) is configured to receive new write data DATAX and may provide the corresponding DATA<3:0> at the output. Each of the data triggers 462(0)-(3) can respond to the CLKW signal at the output terminal to convert the corresponding input signal into the corresponding DATA<3:0> signal.

[0060] The read data path circuit 470 of the data / read path 422 may include corresponding pass gates 472(0)-(3), which are enabled to provide at the output one of DATA<3:0> as read data in response to a corresponding one of the RDEN0-RDEN3 signals (e.g., and the corresponding complementary RDENF0-RDENF3 signals) having a value indicating a match between the ADDX address and the corresponding valid (via FLG<3:0>) ADD<3:0> address.

[0061] Reference Figure 5 and 6 Describe the operation of the bubble bursting register circuit 400. Figure 5 The description illustrates the execution of a write operation according to embodiments of the present disclosure. Figure 4 A schematic block diagram of a portion 500 of the bubble bursting register circuit 400. Figure 6 The description illustrates the execution of a read operation according to embodiments of the present disclosure. Figure 4 A schematic block diagram of a portion of the bubble bursting register circuit 400 600. Figure 5 The bubble bursting register circuit 400 part 500 and Figure 6 The bubble bursting register circuit 400, portion 600 may include previously mentioned... Figure 4 The bubble bursting register circuit 400 describes the components. Figure 5 and 6 Used with Figure 4The same reference numerals are used to identify those elements, and the operation of common elements is as described above. Therefore, for the sake of brevity, a detailed description of the operation of these specific elements will not be repeated.

[0062] Go to Figure 5 During a write operation, NAND gates 434(0)-(2) and transistors 436(0)-(2) control whether FLG<2:0> provided from the output of the previous flip-flop in flag flip-flops 432(0)-(2) is provided to the input of the next flip-flop in flag flip-flops 432(1)-(3). Furthermore, transistors 454(0)-(2) control whether ADD<2:0> bits provided from the output of the previous flip-flop in address flip-flops 452(0)-(2) are provided to the input of the next flip-flop in address flip-flops 452(1)-(3). For example, NAND gate 434(1) receives FLG... <0> Signal, FLG <1> The FLG signal and the PSSEN signal. The PSSEN signal is triggered by the WREN signal, which indicates a write command. Therefore, during a write operation, the FLG... <0> Signal indicates ADD <0> Is the bit valid, and FLG? <1> Signal indicates ADD <1> Whether the bits are valid. If the FLG<1:0> signal indicates that both ADD<1:0> bits are valid, then NAND gate 434(1) can enable transistors 436(1) and 454(1) respectively to provide FLG to the inputs of flag flip-flop 432(2) and address flip-flop 452(1). <1> Signals and Add <1> In this case, the flag signal and address are passed to the right because all addresses are valid.

[0063] If FLG <1> Instructions for ADD <1> If the address is invalid (e.g., the time slot of bubble burst register 400 is empty), then the output of NAND gate 434(1) can disable transistors 436(1) and 454(1) to prevent invalid FLGs. <1> Signals and invalid ADDs <1> The address is propagated to flag trigger 432(2) and address trigger 452(2), respectively. Conversely, the shift in bubble burst register 400 will stop at the first empty time slot in bubble burst register 400.

[0064] Referencing the read enable / reset logic circuit 570, the XNOR gate 442(1) can compare whether the new address ADDX matches ADD. <1> The address, and if it matches, can reset the flag trigger 432(1) FLG. <1> Signal, to make ADD <1> Addresses are marked as invalid to avoid storing duplicate addresses in the bubble burst register 400. It should be understood that the same principle used for the read enable / reset logic 570 applies to other similar logic in 540 to cause the corresponding FLG<3:0> signal to reset in response to the detection of a matching address. Furthermore, although... Figure 5Not shown in the image, but Figure 4 The data path circuit 460 operates similarly to the address path circuit 450 during a write operation. That is, the address ADD<3:0> and the corresponding write data DATA<3:0> are paired together in the bubble burst register 400 and shifted together.

[0065] Go to Figure 6 During the read operation, the new write address ADDX is compared with ADD at XNOR gate 442(0). <1> Addresses are compared to determine if a match exists. The AND gate 444(0) receives the output of the XNOR gate 442(0) and the FLG. <0> Signal, and based on FLG <0> Signal AND XNOR gate 442 <0> A logical AND comparison between the outputs of ADD and DRDEN0 signals (e.g., and complementary DRDEN0 signals) is provided to the output. That is, if ADD... <0> The address matches the ADDX address, and ADD <0> Address valid (by FLG) <0> If the signal indicates that the AND gate 444(0) can provide the RDEN0 signal to enable the pass gate 472(0), then the pass gate 472(0) can provide the DATA signal at the output. <0> Data is read as data. Otherwise, DATA can be prevented through gate 472(0). <0> Data is provided to the output as read data (e.g., when the ADDX address is compared with ADD). <0> Address mismatch or ADD <0> (Invalid address).

[0066] Although Figure 4-6 The bubble burst register 400 depicted only illustrates a single address flip-flop and a single logic bit comparison for each time slot. However, it should be understood that the flag path circuit 430 and the address matching logic circuit 440 may include additional circuitry to store and compare each bit or subset of the address to detect matches between addresses, without departing from the scope of this disclosure. Additionally, the address path circuit 450 may also include additional flip-flops for each time slot to store each data bit corresponding to the address without departing from the scope of this disclosure. Although Figure 4-6 The bubble burst register 400 includes four time slots; however, it should be understood that the bubble burst register 400 can be extended to include any number of time slots without departing from the scope of this disclosure. Furthermore, although... Figure 5 and Figure 6 Only described Figure 4 The corresponding portions 500 and 600 of the bubble burst register 400 are described, but it should be understood that other similar portions of the bubble burst register 400 can operate similarly, and for the sake of brevity, descriptions of such operations are omitted.

[0067] Figure 7This includes an exemplary timing diagram 700 of read and write accesses associated with a bubble burst register according to embodiments of the present disclosure. The timing diagram can be derived from... Figure 1 Register 122, Figure 2 This is implemented using the low latency register 212. The ADDX signal, CLKW signal, FLG<3:0> signal, DATAX data, and DATAFF0 flip-flop can respectively correspond to... Figure 4-6 The ADDX, CLKW, FLG<3:0> signals, DATAX data, and data triggers 462(0)-(3). Time T0-T4 and T6-T7 describe the write operations associated with the bubble burst register, and time T4-T6 describes the read operations associated with the bubble burst register.

[0068] At time T0, in response to the CLKW signal, the first address ADD3 and the first write data Data3 are received on the DATAX signal at the input of the first trigger time slot (e.g., DATAFF0) of the bubble burst register, and FLG <0> The signal is converted to a high logic value. Between times T0 and T1, Data3, based on the CLKW signal, begins to transition to the output of the first flip-flop time slot / the input of the second flip-flop time slot (e.g., DATAFF1).

[0069] At time T1, in response to the CLKW signal, the second address ADD2 and the second write data Data2 are received on the DATAX signal at the input of the first flip-flop time slot. FLG <0> The signal remains at a high logic value because the corresponding time slot continues to hold valid data. Also at time T1, when Data3 transitions to the output of the second flip-flop time slot, FLG... <1> The signal transitions to a high logic value. Between times T1 and T2, based on the CLKW signal, Data3 begins to transition to the output of the second flip-flop time slot / input of the third flip-flop time slot (e.g., DATAFF2), and Data2 begins to transition to the output of the first flip-flop time slot / input of the second flip-flop time slot (e.g., DATAFF1).

[0070] At time T2, in response to the CLKW signal, the third address ADD1 and the third write data Data1 are received on the DATAX signal at the input of the first flip-flop time slot. FLG <0> Signals and FLG <1> The signals remain at high logic values ​​because the corresponding time slots continue to hold valid data. Also at time T2, when Data3 transitions to the output of the third flip-flop time slot, FLG... <2> The signal transitions to a high logic value. Between times T2 and T3, based on the CLKW signal, Data3 begins to transition to the output of the third flip-flop time slot / input of the fourth flip-flop time slot (e.g., DATAFF3), Data2 begins to transition to the output of the second flip-flop time slot / input of the third flip-flop time slot, and Data1 begins to transition to the output of the first flip-flop time slot / input of the second flip-flop time slot.

[0071] At time T3, in response to the CLKW signal, the fourth address ADD0 and the fourth write data Data0 are received on the DATAX signal at the input of the first flip-flop time slot. FLG <0> Signal, FLG <1> Signals and FLG <2> The signals remain at high logic values ​​because the corresponding time slots continue to hold valid data. Also at time T3, when Data3 data transitions to the output of the fourth flip-flop time slot, FLG... <3> The signal transitions to a high logic value. Between times T3 and T4, based on the CLKW signal, Data3 begins to transition to the output of the fourth flip-flop time slot, Data2 begins to transition to the output of the third flip-flop time slot / input of the fourth flip-flop time slot, Data1 begins to transition to the output of the second flip-flop time slot / input of the third flip-flop time slot, and Data0 begins to transition to the output of the first flip-flop time slot / input of the second flip-flop time slot.

[0072] At time T4, during the read operation and in response to the RdCLK signal, the ADD1 address is received on the ADDX signal. The ADD1 address is compared with the addresses stored in the first, second, third, and fourth time slots. In response to detecting that the ADD1 address is stored in the second time slot, FLG... <1> The signal transitions to a low logic value, and the Data1 data is read.

[0073] At time T5, during the second read operation and in response to the RdCLK signal, the ADD3 address is received on the ADDX signal. The ADD3 address is compared with the addresses stored in the first, second, third, and fourth time slots. In response to detecting that the ADD3 address is stored in the fourth time slot, FLG... <3> The signal is converted to a low logic value, and Data3 is read. In this phase after time T5, two bubbles burst; one in the second time slot and one in the fourth time slot.

[0074] At time T6, in response to the CLKW signal, the fifth address ADD4 and the fifth write data Data4 are received on the DATAX signal at the input of the first flip-flop time slot. FLG <0> Signals and FLG <2> The signals remain at high logic values ​​because the corresponding time slots continue to hold valid data. Also at time T6, when Data0 data transitions to the output of the second flip-flop time slot, FLG... <1> The signal transitions to a high logic value. Between times T6 and T7, based on the CLKW signal, Data2 begins to transition to the output of the fourth flip-flop time slot / input of the third flip-flop time slot (e.g., DATAFF2), and Data0 begins to transition to the output of the second flip-flop time slot / input of the third flip-flop time slot.

[0075] At time T7, in response to the CLKW signal, the sixth address ADD5 and the sixth write data Data5 are received on the DATAX signal at the input of the first flip-flop time slot. FLG <0> The signal can remain at a high logic value because the corresponding time slot continues to hold valid data. Also at time T7, when Data2 data transitions to the output of the fourth flip-flop time slot, FLG... <3> The signal transitions to a high logic value. After time T7, based on the CLKW signal, Data4 begins to transition to the output of the second flip-flop time slot / input of the third flip-flop time slot, and Data5 begins to transition to the output of the first flip-flop time slot / input of the second flip-flop time slot.

[0076] As previously stated, timing diagram 700 is exemplary. The timing relationships are not intended to be drawn to scale, and it should be understood that other timing relationships can be implemented without departing from the scope of this disclosure.

[0077] Although the “Detailed Description” describes certain preferred embodiments and examples, those skilled in the art will understand that the scope of this disclosure extends beyond the specifically disclosed embodiments to other alternative embodiments and / or uses of embodiments, as well as their obvious modifications and equivalents. Furthermore, other modifications within the scope of this disclosure will be apparent to those skilled in the art. Various combinations or sub-combinations of specific features and aspects of the embodiments can also be made with careful consideration and still fall within the scope of this disclosure. It should be understood that various features and aspects of the disclosed embodiments can be combined or substituted with each other to form various modes of the disclosed embodiments. Therefore, the scope of at least some portions of this disclosure should not be limited to the specific embodiments specifically disclosed above.

Claims

1. A device having a bubble bursting register, comprising: A memory device comprising; The register circuit contains multiple time slots to store corresponding address and data pairs, wherein... During a write operation, each of the plurality of time slots preceding a specific time slot among a plurality of time slots that is indicated to be empty is shifted by one time slot to fill the specific time slot, such that a first end time slot among the plurality of time slots is available to receive a new write address and data pair received from the memory controller via the address and data bus, wherein each of the plurality of time slots following the specific time slot retains an existing address and data pair; and A memory array configured to store write data during a write operation, wherein, during the write operation, the new write address and data pair are stored at the register circuitry in a low-latency operation mode, and the write data of the new write address and data pair are stored at a plurality of memory cells of the memory array determined by the write address of the new write address and data pair in a normal operation mode, wherein the memory circuitry is decoupled from the memory array; and A control circuit is configured to determine, based on a bit in a received command corresponding to the write operation, whether the write operation is associated with the low latency operation mode or the normal operation mode. The control circuit is configured to store the new write address and data pair in the register circuit when the write operation is determined to be associated with the low latency operation mode, and to store the write data in the memory array when the write operation is determined to be associated with the normal operation mode. The low latency operation mode refers to a mode with a lower latency than the normal operation mode.

2. The device of claim 1, wherein the register includes a corresponding flag signal for each of the plurality of time slots, wherein a particular time slot is indicated as empty based on the corresponding flag signal corresponding to the particular time slot.

3. The device of claim 1, wherein during a read operation prior to the write operation, in response to detecting that the read address matches the address of the address and data pair stored in the specific time slot, the specific time slot is converted to the empty indication.

4. The device of claim 3, wherein during a read operation, the register is configured to perform an XOR comparison between the read address and the address of the read address and data pair stored in the specific time slot.

5. The device of claim 3, wherein during a read operation, the register is configured to clear a flag signal to provide the empty indication associated with the specific time slot.

6. The device of claim 1, wherein during the write operation, in response to detecting that the second time slot includes a previously stored address that matches the write address in the write address and data pair, an empty indication corresponding to the second time slot among a plurality of time slots is set.

7. The device of claim 1, wherein the memory array is a dynamic random access memory (DRAM) array.

8. A device having a bubble bursting register, comprising: A memory device comprising; A flag path circuit is configured to maintain a first flag signal corresponding to a first time slot of a register, a second flag signal corresponding to a second time slot of the register, and a third flag signal corresponding to a third time slot of the register located between the first and second time slots, wherein the first, second, and third flag signals are configured to indicate whether the first, second, and third time slots are empty, respectively. The address path circuit includes: a first latch circuit corresponding to a first time slot and configured to store a first address; and a second latch circuit corresponding to a second time slot and configured to store a second address. And a third latch circuit, which corresponds to the third time slot and is configured to store the third address; An address matching logic circuit is coupled to the flag path circuit and the first, second, and third latch circuits of the address path circuit. The address matching logic circuit is configured to compare the stored first, second, and third addresses with the received address, and to reset one of the first, second, and third flag signals respectively when the received address matches the stored first, second, or third address. in, During a write operation, and in response to the first and second flag signals indicating that the first and second time slots have valid data and the third flag signal indicating that the third time slot is empty, in response to the third flag signal indicating that the third time slot is empty, the first address is shifted to the third latch circuit to store the first address as the third address, and a new write address received from the memory controller via the address bus is shifted to the first latch circuit as the first address, wherein, during the write operation, based on the shift of the first address to the third latch circuit, the third flag signal is changed to indicate that the third time slot contains valid data. A memory array configured to, during a write operation, store new write data received from a memory controller via a data bus and corresponding to the new write address, wherein, during the write operation, the new write address and the new write data are stored respectively at a first latch circuit and a first data latch circuit in a low latency operation mode, and the write data at the new write address is stored at a plurality of memory cells of the memory array determined by the new write address in a normal operation mode, wherein the first latch circuit and the first data latch circuit are separate from the memory array; and A control circuit is configured to determine whether the write operation is associated with the low latency operation mode or the normal operation mode based on a bit in a received command corresponding to the write operation. The control circuit is configured to, when it is determined that the write operation is associated with the low latency operation mode, store the new write address and the new write data in the first latch circuit and the first data latch circuit, respectively; and when it is determined that the write operation is associated with the normal operation mode, store the write data in the memory cell of the memory array. The low latency operation mode refers to a mode with a latency lower than the normal operation mode.

9. The device of claim 8, wherein during the write operation, the second address is held stored at the second latch circuit.

10. The device of claim 8, wherein during a read operation prior to the write operation, in response to detecting that the read address matches the address stored in the third latch circuit of the third time slot, the third flag signal is switched to indicate that the third time slot is an empty indication.

11. The device of claim 10, further comprising address latching logic configured to compare the read address with the address stored in the third latching circuit.

12. The apparatus of claim 8, further comprising: a first data latch circuit corresponding to the first time slot and configured to store first write data; a second data latch circuit corresponding to the second time slot and configured to store second write data; and a third data latch circuit corresponding to the third time slot and configured to store third write data, wherein during the write operation, in response to a third flag signal indicating that the third time slot is empty, the first write data is shifted to the third data latch circuit to store the first write data as the third write data, and new write data is shifted to the first data latch circuit as the first write data.

13. A method for operating an apparatus having a bubble bursting register, comprising: Receive commands and related new write address and data pairs; Based on a specific bit in the command, the operation is executed in either normal operation mode or low latency operation mode, wherein the latency of low latency operation mode is lower than that of normal operation mode; and During a write operation associated with a new write address and data pair of the memory device received from the memory controller via the address and data buses respectively: Shift each of the multiple time slots of the shift register by one time slot before the specific time slot that is indicated to be empty in the multiple time slots to fill the specific time slot, so that the first end time slot of the multiple time slots is available; Move the new write address and data pair into the first end time slot; and The existing address and data pairs are retained in the time slots following the specific time slot. in, In the low latency operation mode, the new write address and data pair is stored in a shift register. In the normal operation mode, the write data of the new write address and data pair is stored in multiple memory cells of a memory array of a memory device determined based on the write address of the new write address and data pair, and the shift register is separate from the memory array.

14. The method of claim 13, further comprising detecting that the particular time slot is empty based on a flag signal having a value indicating that the particular time slot is empty.

15. The method of claim 13, further comprising, during a read operation prior to the write operation, converting the specific timeslot to have the empty indication in response to detecting that the read address matches an address stored in the specific timeslot.

16. The method of claim 13, further comprising, during the write operation, in response to detecting that the second time slot includes a previously stored address that matches the write address in the write address and data pair, setting an empty indicator corresponding to the second time slot among a plurality of time slots.

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