A method of patterning a semiconductor and a method of manufacturing a memory

Abstract

The application discloses a semiconductor pattern preparation method, which comprises the following steps: forming a sacrificial layer on a target layer to be prepared with a pattern, and forming a honeycomb-shaped interval pattern on the sacrificial layer by using a photoetching process; forming a side wall material layer which uniformly covers the surface of the interval pattern; etching the side wall material layer to form a side wall; removing the sacrificial layer, and etching the target layer with the side wall material layer as a mask to form a hole with an interval smaller than that of the interval pattern. The method provided by the application solves the technical problems of difficult preparation, high cost and long time consumption of a small-interval pattern in the prior art, and achieves the technical effects of saving the cost and time of small-interval pattern preparation.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more particularly to a method for patterning a semiconductor and a method for manufacturing a memory. Background Technology

[0002] To form the structure of semiconductor devices on a wafer, photolithography is used to create patterns for each layer. A typical photolithography process involves applying photoresist, forming patterns on the photoresist, and then etching. However, as semiconductor device dimensions shrink, when using photolithography to generate small-pitch patterns, it becomes increasingly difficult to obtain patterns smaller than the resolution limit due to photolithographic resolution limitations. Fabricating small-pitch patterns using photolithography is becoming increasingly challenging.

[0003] Currently, multiple photolithography techniques are mainly used to solve the problem of fabricating small-pitch patterns. Specifically, for example... Figure 1 As shown, a wide-spacing pattern is first generated by the first photolithography, and then another pattern is generated at the interval by the second photolithography, and so on, so that a small-spacing pattern is prepared by multiple photolithography processes.

[0004] However, photolithography is a high-cost and time-consuming process in semiconductor manufacturing. Performing photolithography multiple times will increase production costs and process time, resulting in significant cost and time consumption. Summary of the Invention

[0005] The purpose of this disclosure is at least in part to solve the technical problem of increased production costs and processing time in the fabrication of small-interval patterns due to multiple photolithography steps in the prior art.

[0006] The embodiments of this disclosure provide the following technical solutions:

[0007] In a first aspect, a method for fabricating patterns on a semiconductor is provided, comprising:

[0008] A sacrificial layer is formed on the target layer of the pattern to be prepared, and a honeycomb-shaped spaced pattern is formed on the sacrificial layer using a photolithography process;

[0009] A sidewall material layer is formed that uniformly covers the surface of the spaced pattern;

[0010] Etching the sidewall material layer forms the sidewall;

[0011] The sacrificial layer is removed, and the target layer is etched using the sidewall material layer as a mask to form holes with a spacing smaller than the spacing pattern.

[0012] Optionally, the spacing pattern is a spacing cylinder; the spacing cylinder is distributed at six fixed points of a regular hexagon and at its center.

[0013] Optionally, the thickness of the sidewall material layer is greater than or equal to half the spacing between the spaced cylinders to form a honeycomb arrangement of side-connected cylinders, with recessed holes formed between the side-connected cylinders.

[0014] Optionally, the etching of the sidewall material layer to form a sidewall includes: anisotropically etching the sidewall material layer to expose the top surface of the spacer cylinder and the surface of the target layer located below the recessed hole, thereby forming a sidewall.

[0015] Optionally, the step of etching the target layer using the sidewall material layer as a mask to form holes with a spacing smaller than the spacing pattern includes: etching the target layer using the sidewall material layer as a mask to form holes with a spacing smaller than the spacing pattern below the recessed holes and below the position before the removal of the spacer cylinder.

[0016] Optionally, the method is used to fabricate a capacitor aperture pattern for a dynamic random access memory, or the method is used to fabricate a channel aperture pattern for a vertical MOSFET.

[0017] Optionally, the anisotropic etching is performed using dry etching technology.

[0018] Optionally, the sacrificial layer is made of polycrystalline silicon, silicon nitride, amorphous carbon layer, or SOH spin-coated hard mask.

[0019] Optionally, the sidewall material layer is made of silicon dioxide, polycrystalline silicon, or silicon nitride.

[0020] Optionally, after etching the target layer using the sidewall material layer as a mask to form holes with a spacing smaller than the spacing pattern, the method further includes: removing the sidewall material layer.

[0021] Secondly, a method for manufacturing dynamic random access memory is provided, comprising:

[0022] Provide semiconductor substrates;

[0023] A target layer is formed on the semiconductor substrate;

[0024] The pore is prepared in the target layer according to any of the methods described in the first aspect;

[0025] A lower electrode, a dielectric layer, and an upper electrode are formed within the hole.

[0026] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

[0027] The semiconductor patterning method and memory manufacturing method provided in this application first prepare a sacrificial layer with an interstitial pattern using photolithography, and uniformly cover the surface of the interstitial pattern with a sidewall material layer. Then, a downward directional etching technique is used to etch the sidewall material layer until the top surface of the interstitial pattern and the surface of the target layer below the recessed area of ​​the sidewall material layer are exposed. In this way, the sidewall material layer covering the sidewalls of the interstitial pattern is preserved through directional etching, and small gaps are formed in the recessed area of ​​the sidewall material layer. Then, the interstitial pattern of the sacrificial layer is removed, and small gaps are formed at the original interstitial pattern. The target layer is then etched using the remaining sidewall material layer as a mask, which can form holes with a spacing equal to the thickness of the sidewall material layer of the interstitial pattern sidewalls. This allows the hole spacing to be less than the minimum resolution of photolithography, and photolithography only needs to be performed when forming the interstitial pattern. Subsequent deposition and etching can replace photolithography, effectively reducing the number of photolithography steps and saving costs and time. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of an existing method for preparing small-pitch graphics.

[0030] Figure 2 A flowchart illustrating a method for fabricating a patterned semiconductor according to one or more embodiments of this disclosure;

[0031] Figure 3 This is a process schematic diagram of a semiconductor patterning method according to one or more embodiments of the present disclosure;

[0032] Figure 4 The process for fabricating honeycomb-shaped porous patterns according to one or more embodiments of this disclosure Figure 1 ;

[0033] Figure 5 The process for fabricating honeycomb-shaped porous patterns according to one or more embodiments of this disclosure Figure 2 ;

[0034] Figure 6 The process for fabricating honeycomb-shaped porous patterns according to one or more embodiments of this disclosure Figure 3 ;

[0035] Figure 7 The process for fabricating honeycomb-shaped porous patterns according to one or more embodiments of this disclosure Figure 4 ;

[0036] Figure 8 The process for fabricating honeycomb-shaped porous patterns according to one or more embodiments of this disclosure Figure 5 ;

[0037] Figure 9 The process for fabricating honeycomb-shaped porous patterns according to one or more embodiments of this disclosure Figure 6 ;

[0038] Figure 10 This is a flowchart of a method for manufacturing a dynamic random access memory according to one or more embodiments of the present disclosure. Detailed Implementation

[0039] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0040] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0041] In the context of this disclosure, when a layer / component is referred to as being "above" another layer / component, that layer / component may be directly above the other layer / component, or there may be an intermediate layer / component between them. Additionally, if a layer / component is "above" another layer / component in one orientation, then when the orientation is reversed, that layer / component may be "below" the other layer / component. In the context of this disclosure, similar or identical components may be denoted by the same or similar reference numerals.

[0042] To better understand the above technical solutions, the following will describe the above technical solutions in detail with reference to specific implementation methods. It should be understood that the embodiments of this disclosure and the specific features in the embodiments are detailed descriptions of the technical solutions of this application, rather than limitations on the technical solutions of this application. In the absence of conflict, the embodiments of this application and the technical features in the embodiments can be combined with each other.

[0043] According to one aspect of this disclosure, a method for fabricating patterns in a semiconductor is provided, such as... Figure 2 As shown, it includes:

[0044] Step S201: A sacrificial layer is formed on the target layer of the pattern to be prepared, and a honeycomb-shaped spacer pattern is formed on the sacrificial layer using a photolithography process.

[0045] Step S202: Form a sidewall material layer that uniformly covers the surface of the spaced pattern;

[0046] Step S203: Etch the sidewall material layer to form a sidewall;

[0047] Step S204: Remove the sacrificial layer and etch the target layer using the sidewall material layer as a mask to form holes with a spacing smaller than the spacing pattern.

[0048] It should be noted that the semiconductor patterning method can be used to fabricate capacitor hole patterns for dynamic random access memory (DRAM), or to fabricate channel hole patterns for vertical NAND gates. Of course, it can also be used for other devices that require the fabrication of small-interval patterns.

[0049] Below, in conjunction with Figure 3-9 This application details the implementation steps of the semiconductor patterning method provided, wherein... Figure 4-9 The upper part is a top view, and the lower part is a cross-sectional view cut along the dashed line of the top view:

[0050] First, a sacrificial layer 2 is formed on the target layer 1 of the pattern to be prepared. In specific implementation, the target layer 1 can be as follows: Figure 3 The diagram shows a multi-layered material structure, which can also be represented as shown below. Figure 4 The diagram shows a single-layer material, and no restrictions are imposed here. The material of the sacrificial layer 2 can be polysilicon, silicon nitride, amorphous carbon layer ACL, or spin-coated hard mask SOH, etc., and the thickness of the sacrificial layer is not limited.

[0051] Then, a spacer pattern is formed on the sacrificial layer 2 using photolithography. In practice, the spacer pattern corresponds to the image to be formed on the target layer 1, and can be fabricated using conventional photolithography.

[0052] For example, such as Figure 3 As shown in (a), when etching the spaced hole pattern on the target layer 1, the spaced pattern on the sacrificial layer 2 is a spacer wall. Preferably, the gap of the spacer wall is the smallest spaced size that the photolithography process can achieve.

[0053] For example, such as Figure 4As shown, when fabricating capacitor hole patterns for DRAM or channel hole patterns for Vertical MOSFET, dense honeycomb-shaped holes need to be etched in the target layer 1. Therefore, the spacing pattern on the sacrificial layer 2 is a honeycomb-shaped arrangement of spacer cylinders. Preferably, the gap between these spacer cylinders is the smallest spacing size that the photolithography process can achieve, so as to meet the density requirements of the pattern to be fabricated.

[0054] Next, a sidewall material layer 3 is formed that uniformly covers the surface of the spacer pattern. Specifically, the sidewall material layer 3 can be prepared on the surface of the spacer pattern using deposition processes such as sputtering deposition or vapor deposition. Due to the unevenness of the spacer pattern, the prepared sidewall material layer 3... Figure 3 (b) and Figure 5 The surface is uneven. The sidewall material layer 3 can be made of silicon dioxide, polycrystalline silicon, or silicon nitride, etc., and the specific thickness of the deposited sidewall material layer 3 is determined according to the required pattern size.

[0055] For example, such as Figure 3 As shown in (b), when the pattern to be prepared in the target layer 1 is a spaced hole pattern, the thickness of the sidewall material layer 3 is the gap width of the spaced holes to be prepared.

[0056] For example, such as Figure 5 As shown, dense honeycomb-like pores need to be etched in the target layer 1. Therefore, the spacing pattern of the sacrificial layer 2 is as follows: a cylinder at the center, surrounded by six hexagonal cylinders. The thickness of the deposited sidewall material layer 3 is greater than or equal to half the spacing between the cylinders, so that the resulting sidewall material layer 3 consists of honeycomb-shaped cylinders with interconnected sides. That is, the thickness of the sidewall material layer is such that the cylinders of the sidewall material layer 3 covering the cylinders of each sacrificial layer 2 can contact and connect. This creates recessed holes 31 between the cylinders connected on the sides of the sidewall material layer 3.

[0057] Next, the sidewall material layer 3 is etched to form the sidewalls. That is, the sidewall material layer 3 is anisotropically etched downwards until the top surface of the spacer pattern and the surface of the target layer 1 located below the recessed area of ​​the sidewall material layer 3 are exposed, while retaining the sidewall material layer 3 covering the sidewalls of the spacer pattern.

[0058] In the specific implementation process, since the sidewall material layer 3 is deposited uniformly in all directions, the exposed surfaces of the sacrificial layer 2 and the target layer 1 will be covered by the sidewall material layer 3. Since the sidewall material layer 3 is etched downwards, the sacrificial layer 2, i.e., the sidewall material layer 3 covering the side of the spacer pattern, will not be etched away. Figure 3As shown in (c), only the top of the protruding area of ​​the sidewall material layer 3 is etched downwards to reveal the top surface of the spaced pattern, and the bottom of the recessed area of ​​the sidewall material layer 3 is etched to reveal the surface of the target layer 1 located below the recessed area of ​​the sidewall material layer 3.

[0059] If it is necessary to etch dense honeycomb-like holes in target layer 1, then as follows Figure 6 As shown, the sidewall material layer 3 is etched downwards to expose the top surface of the spacer cylinder and the surface of the target layer 1 located below the recessed hole 21.

[0060] The specific anisotropic etching process can employ conventional anisotropic etching processes such as physical dry etching or chemical dry etching, and no restrictions are imposed here.

[0061] Then, remove the sacrificial layer 2, as follows: Figure 3 (d) and Figure 7 As shown, only the sidewall material layer 3 remains on the target layer 1. Small gaps are formed in the recessed areas (or recessed hole 31 areas) of the sidewall material layer 3 and the original area where the sacrificial layer 2 was located. The surface of the target layer 1 is exposed below the small gaps. The specific method for removing the sacrificial layer 2 can be based on the materials of the sacrificial layer 2 and the sidewall material layer 3, by selecting a corresponding cleaning agent (etching agent) with an appropriate selection ratio.

[0062] Next, using the sidewall material layer 3 as a mask, the target layer 1 is etched to form holes with a spacing smaller than the spacing pattern.

[0063] The hole can be like Figure 3 (e) shows a spacer hole, which can also be shown as... Figure 8 The image shows a densely honeycomb-like distribution of pores. Figure 8 The final hole pattern can include those located in Figure 4 The hexagon has six vertices and seven circular holes at its center, and is located at... Figure 4 The holes are located at the twelve vertices of two other hexagons concentric with the central hexagon, and the vertices of these two other hexagons are fitted into... Figure 4 Between the vertices of the hexagon. And one of the other two hexagons has a size greater than [missing information]. Figure 4 One of the hexagons is smaller than the other hexagon. Figure 4 The hexagon in the middle. Thus, the number of holes generated using this application is almost three times that of directly pressing... Figure 4 The number of holes formed by photolithography at specific locations significantly increases the density of the formed holes.

[0064] Specifically, by using the method provided in this application, Figure 3 (d) shows the sidewall material layer 3 as a mask, used to etch the target layer 1. Figure 3The spacing between the spacers shown in (e) is reduced by at least half compared to spacers fabricated in a single photolithography step. This effectively reduces the number of photolithography steps, saving both cost and time.

[0065] And using the method provided in this application to Figure 7 The sidewall material layer shown is the mask etching target layer 1. Below the recessed hole 31 and below the position before the spacer cylinder is removed, a pattern with a smaller interval than the spacer pattern can be formed, such as... Figure 8 The honeycomb-like porous pattern shown has a density more than twice that of honeycomb-like patterns prepared using a single photolithography step. This effectively reduces the number of photolithography steps, saving costs and time.

[0066] After etching the target layer 1 to form the hole, the process also includes removing the remaining sidewall material layer 3. If... Figure 3 As shown, the target layer is a multi-layered material. After removing the sidewall material layer 3, other layers above the functional layer 32 can also be removed.

[0067] Based on the same inventive concept, this application also provides a method for manufacturing a dynamic random access memory, such as... Figure 10 As shown, it includes:

[0068] Step S1001: Provide a semiconductor substrate. A preliminary structure for forming a DRAM product can be formed on the semiconductor substrate, including active regions, sub-lines (gates), bit lines and contacts, memory node contacts, and capacitor landing pads, etc.

[0069] Step S1002: Continue forming the target layer on the semiconductor substrate. This target layer can be a molded oxide layer with pre-formed capacitor holes. A support layer can be formed in the molded oxide layer, and a hard mask layer can be formed on top of the molded oxide layer for protection.

[0070] Step S1003: Prepare a hole in the target layer according to the semiconductor patterning method provided in this application;

[0071] Step S1004: A lower electrode, a dielectric layer, and an upper electrode are formed inside the hole.

[0072] Since the method for preparing pores in the target layer has been described in detail in the foregoing embodiments, it will not be repeated here.

[0073] Specifically, the semiconductor patterning method and memory manufacturing method provided in this application first prepare a sacrificial layer with an interstitial pattern using photolithography, and uniformly cover the surface of the interstitial pattern with a sidewall material layer. Then, a downward directional etching technique is used to etch the sidewall material layer until the top surface of the interstitial pattern and the surface of the target layer below the recessed area of ​​the sidewall material layer are exposed. In this way, the sidewall material layer covering the sidewalls of the interstitial pattern is preserved through directional etching, and small gaps are formed in the recessed area of ​​the sidewall material layer. Then, the interstitial pattern of the sacrificial layer is removed, and small gaps are formed at the original interstitial pattern. The target layer is then etched using the remaining sidewall material layer as a mask, which can form holes with a spacing equal to the thickness of the sidewall material layer of the interstitial pattern sidewalls. This allows the hole spacing to be less than the minimum resolution of photolithography, and photolithography only needs to be performed when forming the interstitial pattern. Subsequent deposition and etching can replace photolithography, effectively reducing the number of photolithography steps and saving costs and time.

[0074] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0075] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from the spirit and scope of this disclosure. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A method for fabricating patterns on a semiconductor, characterized in that, include: A sacrificial layer is formed on the target layer of the pattern to be prepared, and the sacrificial layer is formed into a honeycomb-shaped spacer pattern using a photolithography process. The spacer pattern is a spacer cylinder, which is distributed at the six vertices and the center of a regular hexagon. The material of the sacrificial layer is polycrystalline silicon, silicon nitride, amorphous carbon layer ACL, or spin-coated hard mask SOH. A sidewall material layer is formed to uniformly cover the surface of the spaced cylinders, wherein the thickness of the sidewall material layer is greater than or equal to half the distance between the spaced cylinders, so as to form a honeycomb-shaped arrangement of side-connected cylinders, and recessed holes are formed between the side-connected cylinders. Etching the sidewall material layer forms the sidewall; The etching of the sidewall material layer to form a sidewall includes: anisotropically etching the sidewall material layer to expose the top surface of the spacer cylinder and the surface of the target layer located below the recessed hole, thereby forming a sidewall. The anisotropic etching is performed using a dry etching technique. The sidewall material layer is uneven. The sidewall material layer covering the side of the spacer cylinder is not etched away. Only the top of the protruding area of ​​the sidewall material layer is etched away to expose the top surface of the spacer cylinder, and the bottom of the recessed area of ​​the sidewall material layer is etched away to expose the surface of the target layer located below the recessed area of ​​the sidewall material layer. Remove the sacrificial layer and etch the target layer using the sidewall as a mask to form holes with a spacing smaller than the spacing cylinder; The process of etching the target layer using the sidewall as a mask to form holes with a spacing smaller than the spacing cylinder includes: Using the sidewall as a mask, the target layer is etched to form holes with a spacing smaller than that of the spacer cylinder below the recessed hole and below the position before the spacer cylinder is removed, wherein the holes are a densely honeycomb-shaped pattern.

2. The method as described in claim 1, characterized in that, The method is used to prepare a capacitor hole pattern for a dynamic random access memory, or the method is used to prepare a channel hole pattern for a vertical MOSFET.

3. The method as described in claim 1, characterized in that, The material of the sidewall material layer is silicon dioxide, polycrystalline silicon, or silicon nitride.

4. The method as described in claim 1, characterized in that, After etching the target layer using the sidewall as a mask to form holes spaced smaller than the spacing cylinders, the process further includes: Remove the sidewall.

5. A method for manufacturing a dynamic random access memory, characterized in that, include: Provide semiconductor substrates; A target layer is formed on the semiconductor substrate; The method according to any one of claims 1-4 forms the pore in the target layer; A lower electrode, a dielectric layer, and an upper electrode are formed within the hole.

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