Method for manufacturing trench semiconductor device

Abstract

A method for manufacturing a trench semiconductor device includes the following steps: first, forming an epitaxial layer on a substrate, then forming a trench in the epitaxial layer, and forming a gate structure in the trench, wherein the gate structure includes an upper gate, a lower gate, and an intermediate insulating portion, and the intermediate insulating portion is located in the upper gate. Therefore, the gate capacitance characteristics are effectively improved and the reaction speed of the gate is increased.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor component, and more particularly to a method for manufacturing a trench semiconductor component. Background Art

[0002] Power Metal Oxide Semiconductor Field Effect Transistor (Power MOSFET), referred to as power transistor, is a field effect transistor currently widely used in analog circuits and digital circuits. Power Metal Oxide Semiconductor Field Effect Transistor has very low on-resistance and has the advantage of very fast switching speed, so it has become the mainstream of power components.

[0003] The structure of power MOSFET can be classified according to the current flow path. The current flowing parallel to the surface of the component is called horizontal type, and the current flowing vertically is called vertical type. The drain terminal of the vertical power MOSFET is made at the bottom of the component, so the resistance per unit chip area can be reduced.

[0004] In addition, trench gate power MOSFETs can reduce on-resistance and become the mainstream of high-frequency and low-voltage power components. For electronic power, reducing on-resistance and gate capacitance can help improve the response speed of power components and improve product quality. Summary of the invention

[0005] The invention summary is intended to provide a simplified summary of the present disclosure so that readers can have a basic understanding of the present disclosure. This invention summary is not a complete overview of the present disclosure, and it is not intended to point out the important / critical components of the embodiments of the present invention or to define the scope of the present invention.

[0006] One of the purposes of the present invention is to provide a method for manufacturing a trench semiconductor component, which can further reduce the input capacitance and reverse transfer capacitance of the semiconductor component and increase the output capacitance, thereby effectively improving the switching speed of the semiconductor component.

[0007] To achieve the above-mentioned purpose, the technical aspects of the present invention are about a method for manufacturing a trench semiconductor component, which includes the following steps: first, an epitaxial layer is formed on a substrate, then a trench is formed in the epitaxial layer, and a gate structure is formed in the trench, wherein the gate structure includes an upper gate, a lower gate and an intermediate insulating portion, and the intermediate insulating portion is located in the upper gate.

[0008] In some embodiments, the method for manufacturing a trench semiconductor device further includes depositing a first oxide layer in the trench, and depositing a first polysilicon layer on the first oxide layer and in the trench.

[0009] In some embodiments, the thickness of the first oxide layer is about 5000 angstroms. The thickness of the first polysilicon layer is between 6000 angstroms and 10000 angstroms, and the first polysilicon layer is between 6000 angstroms and 10000 angstroms, and fills the trench.

[0010] In some embodiments, the method for manufacturing a trench semiconductor device further includes etching back the first polysilicon layer to a position approximately 1.5 micrometers to 2 micrometers below the upper surface of the first oxide layer.

[0011] In some embodiments, the method for manufacturing a trench semiconductor device further includes oxidizing a surface of the first polysilicon layer to form a second oxide layer, and using the second oxide layer and the first oxide layer to cover the lower gate.

[0012] In some embodiments, the trench semiconductor component manufacturing method also includes depositing a silicon nitride layer in the trench, etching back the silicon nitride layer to form an intermediate insulating portion, and etching back the first oxide layer to remove a portion of the first oxide layer to form a first dielectric layer and expose a portion of the surface of the epitaxial layer, and the first dielectric layer and the second oxide layer cover the lower gate.

[0013] In some embodiments, the method for manufacturing a trench semiconductor device further includes oxidizing a surface of the epitaxial layer to form a gate oxide layer.

[0014] In some embodiments, the method for manufacturing a trench semiconductor device further includes depositing a second polysilicon layer to fill the trench, and etching back the second polysilicon layer to a position approximately 200 angstroms to 500 angstroms below the upper surface of the gate oxide layer.

[0015] In some embodiments, the method for manufacturing a trench semiconductor device further includes performing ion implantation in the epitaxial layer, heating to drive the ions in, and using a source photomask to define a source region.

[0016] In some embodiments, the trench semiconductor device manufacturing method further includes forming a second dielectric layer on the gate oxide layer, etching the second dielectric layer and the gate oxide layer using a contact area mask to form an opening, and depositing a metal layer on the second dielectric layer and in the opening.

[0017] Therefore, the trench semiconductor component manufacturing method disclosed in the present invention can manufacture power metal oxide semiconductor transistors, and effectively reduce the size of the upper gate by using the intermediate insulating part, and make the upper gate accurately formed between the intermediate insulating part and the gate oxide layer. At the same time, the first dielectric layer and the second oxide layer are used to cover the lower gate, which effectively improves the gate capacitance characteristics and increases the response speed of the gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more clearly understood, the accompanying drawings are described as follows:

[0019] Figures 1 to 8 It is a partial cross-sectional schematic diagram of a manufacturing process step of a trench semiconductor component according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The following examples are described in detail with reference to the accompanying drawings, but the examples provided are not intended to limit the scope of the present disclosure, and the description of the structural operation is not intended to limit the order of its execution. Any device with equal functions produced by recombining the components is within the scope of the present disclosure. In addition, the drawings are for illustrative purposes only and are not drawn in their original size. For ease of understanding, the same or similar components in the following description will be indicated by the same symbols.

[0021] In addition, the terms used throughout the specification and claims generally have the ordinary meaning of each term used in the field, in the context of this disclosure, and in the specific context, unless otherwise noted. Certain terms used to describe the present disclosure will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art on the description of the present disclosure.

[0022] In the embodiments and claims, unless otherwise specified in the context, "a", "an" and "the" may refer to a single or multiple number. The numbers used in the steps are only used to mark the steps for ease of description, and are not used to limit the order and implementation methods.

[0023] Secondly, the words "include", "including", "have", "contain" and the like used in this article are all open terms, which mean including but not limited to.

[0024] Figures 1 to 8 A partial cross-sectional schematic diagram of a manufacturing process of a trench semiconductor device according to an embodiment of the present invention is shown. Figures 1 to 8 , to illustrate the trench semiconductor device manufacturing method. The trench semiconductor device manufacturing method includes the following steps. First, refer to Figure 1 , an epitaxial layer 120 is formed on the substrate 110, and a trench 122 is formed in the epitaxial layer 120. In some embodiments, the substrate 110 is an N-type semiconductor substrate or a P-type semiconductor substrate, taking a silicon substrate as an example, the N-type conductive impurities are pentavalent element ions, such as phosphorus ions or arsenic ions, and the P-type conductive impurities are trivalent element ions, such as boron ions, aluminum ions, or gallium ions.

[0025] In addition, the epitaxial layer 120 has the same conductivity type as the substrate 110, but the doping concentration of the epitaxial layer 120 is generally lower than the doping concentration of the substrate 110. When the substrate 110 has a high concentration of N-type doping, the epitaxial layer 120 may have a low concentration of N-type doping, but the present invention is not limited thereto.

[0026] In some embodiments, the width of the trench 122 is approximately between 1 micrometer and 2 micrometers, and the depth of the trench 122 is approximately between 5 micrometers and 7 micrometers.

[0027] Next, see Figure 2 , depositing a first oxide layer 130 in the trench 122, and then depositing a first polysilicon layer 140 on the first oxide layer 130 and in the trench 122. In some embodiments, the thickness of the first oxide layer 130 is about 5000 angstroms. The thickness of the first polysilicon layer 140 is between about 6000 angstroms and 10000 angstroms and is used to fill the trench 122 .

[0028] See also Figure 3 , the first polysilicon layer 140 is etched back to make its upper surface lower than the upper surface of the first oxide layer 130. Then, the surface of the first polysilicon layer 140 is oxidized to form a second oxide layer 144, and the second oxide layer 144 and the first oxide layer 130 are used to cover the lower gate 142, so that the lower gate 142 is sealed between the first oxide layer 130 and the second oxide layer 144. In some embodiments, the first polysilicon layer 140 is etched back to make its upper surface lower than the upper surface of the first oxide layer 130 by about 1.5 micrometers to 2 micrometers, and the thickness of the second oxide layer 144 is about 100 angstroms to 200 angstroms.

[0029] Then, see Figure 4 , depositing a silicon nitride layer 150 in the trench 122, see Figure 5 , the silicon nitride layer 150 is etched back to form an intermediate insulating portion 152, and the first oxide layer 130 is etched back to remove a portion of the first oxide layer 130, thereby forming a first dielectric layer 132, and exposing a portion of the surface of the epitaxial layer 120, and the first dielectric layer 132 and the second oxide layer 144 cover the lower gate 142.

[0030] In some embodiments, the thickness of the silicon nitride layer 150 is about 3000 angstroms to 8000 angstroms. After etching, the height of the upper surface of the intermediate insulating portion 152 is about 200 angstroms to 500 angstroms lower than the height of the upper surface of the epitaxial layer 120. After the first oxide layer 130 is etched back, the height of the upper surface of the formed first dielectric layer 132 is about 1.0 microns to 1.5 microns lower than the height of the upper surface of the epitaxial layer 120.

[0031] See also Figure 6 The method for manufacturing a trench semiconductor device further includes oxidizing the exposed surface of the epitaxial layer 120 to form a gate oxide layer 160. Next, a second polysilicon layer 170 is deposited to fill the space of the trench 122. In some embodiments, the gate oxide layer 160 has a thickness of about 500 angstroms to 1000 angstroms. The second polysilicon layer 170 has a thickness of about 3000 angstroms to 5000 angstroms and fills the space of the trench 122.

[0032] See also Figure 7 , and then the second polysilicon layer 170 is etched back to a position about 200 angstroms to 500 angstroms below the upper surface of the gate oxide layer 160. Next, ion implantation is performed to implant ions into the epitaxial layer 120 next to the gate structure 210, and further heating is performed to drive in the ions. In some embodiments, a trivalent element such as boron is used to perform P-type ion implantation, and then heating is performed to drive in trivalent elements such as boron. Next, a source aurora mask is used to define the source region 180. In some embodiments, a source aurora mask is used to implant ions into the source region 180, and further heating is performed to drive in the ions, for example, pentavalent elements such as arsenic, phosphorous, and antimony are shielded by the source aurora mask to implant N-type ions, and heated to drive in the ions.

[0033] See also Figure 8 As shown in the figure, a second dielectric layer 190 is then formed on the gate oxide layer 160 and the gate structure 210, and a contact mask is used to etch the second dielectric layer 190 and the gate oxide layer 160 to form the required opening 162, and then a metal layer 200 is deposited on the second dielectric layer 190 and in the opening 162, and then a mask and etching process are used to form the required metal line. In some embodiments, the second dielectric layer 190 includes boro-phospho-silicate glass (BPSG) as a dielectric layer, and its thickness is about 6000 angstroms to 10000 angstroms. The metal layer 200 can be an aluminum metal layer, and its thickness is about 3.0 microns to 5.0 microns, however, the present invention is not limited thereto.

[0034] In some embodiments, the upper gate 172 of the gate structure 210 is formed between the middle insulating portion 152 and the gate oxide layer 160 , so that the middle insulating portion 152 is located in the upper gate 172 , and the lower gate 142 is enclosed in the first dielectric layer 132 and the second oxide layer 144 .

[0035] In summary, the trench semiconductor component manufacturing method disclosed in the present invention can produce power metal oxide semiconductor transistors. The volume of the upper gate is effectively reduced by the intermediate insulating part, and the upper gate is accurately formed between the intermediate insulating part and the gate oxide layer. At the same time, the first dielectric layer and the second oxide layer are used to cover the lower gate. Therefore, the drain-source breakdown voltage (BVDSS) is effectively increased and the input capacitance (Ciss) and reverse transfer capacitance (Crss) are reduced, the output capacitance (Coss) is increased, the gate capacitance characteristics are improved, and the response speed of the gate is increased.

[0036] Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the present disclosure. Anyone with ordinary knowledge in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.

[0037]

Explanation of symbols

[0038] 110: Base material

[0039] 120: epitaxial layer

[0040] 122: Groove

[0041] 130: First oxide layer

[0042] 132: first dielectric layer

[0043] 140: first polysilicon layer

[0044] 142: Lower gate

[0045] 144: Second oxide layer

[0046] 150: Silicon nitride layer

[0047] 152: Middle insulation part

[0048] 160: Gate oxide layer

[0049] 162: Opening

[0050] 170: second polysilicon layer

[0051] 172: Upper gate

[0052] 180: Source region

[0053] 190: Second dielectric layer

[0054] 200:Metal layer

[0055] 210: Gate structure.

Claims

1. A method for manufacturing a trench semiconductor component, characterized in that: Include: forming an epitaxial layer on a substrate; forming a trench in the epitaxial layer; as well as Forming a gate structure in the trench, wherein the gate structure includes an upper gate, a lower gate and an intermediate insulating portion, and the intermediate insulating portion is located in the upper gate; depositing a first oxide layer in the trench; Depositing a first polysilicon layer on the first oxide layer and in the trench; Etching back the first polysilicon layer to below the upper surface of the first oxide layer; Oxidizing the surface of the first polysilicon layer to form a second oxide layer, and using the second oxide layer and the first oxide layer to cover the lower gate; depositing a silicon nitride layer in the trench; Etching back the silicon nitride layer to form the middle insulating portion; Etching back the first oxide layer to remove a portion of the first oxide layer, thereby forming a first dielectric layer and exposing a portion of the surface of the epitaxial layer, wherein the first dielectric layer and the second oxide layer cover the lower gate; Oxidizing the surface of the epitaxial layer to form a gate oxide layer; depositing a second polysilicon layer to fill the trench; as well as The second polysilicon layer is etched back to expose the intermediate insulating portion.

2. The method for manufacturing a trench semiconductor device as claimed in claim 1, wherein the thickness of the first oxide layer is between 5000 angstroms and 10000 angstroms, and the thickness of the first polysilicon layer is between 6000 angstroms and 10000 angstroms, and fills the trench.

3. The method for manufacturing a trench semiconductor device according to claim 2, further comprising: The first polysilicon layer is etched back to a position 1.5 microns to 2 microns below the upper surface of the first oxide layer.

4. The method for manufacturing a trench semiconductor device according to claim 1, further comprising: The second polysilicon layer is etched back to a position 200 angstroms to 500 angstroms below the upper surface of the gate oxide layer.

5. The method for manufacturing a trench semiconductor device according to claim 4, further comprising: Performing ion implantation on the epitaxial layer and heating the layer to facilitate ion penetration; and Use a source mask to define the source region.

6. The method for manufacturing a trench semiconductor device according to claim 5, further comprising: forming a second dielectric layer on the gate oxide layer; Using a contact region mask, etching the second dielectric layer and the gate oxide layer to form a plurality of openings; and A metal layer is deposited on the second dielectric layer and in the openings.

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