Semiconductor structure fabrication methods and semiconductor structures

Abstract

This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself. The method for fabricating the semiconductor structure includes: providing a substrate having first trenches aligned in the same direction; forming a protective layer on the sidewalls of the first trenches; forming a second trench at the bottom of the first trenches, the width of the second trench being greater than the width of the first trench; forming a first isolation layer on the sidewalls of the second trenches to reduce the opening size of the second trenches; filling the first and second trenches to form a second isolation layer and forming voids within the second trenches; forming a third trench on the substrate, the third trench being perpendicular to the first trenches; and forming bit lines within the third trenches. This disclosure improves the electrical stability of the semiconductor structure by introducing an isolation layer with a void structure inside the bit line trenches, thereby reducing the parasitic capacitance of the bit lines.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and more particularly to a method for preparing a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used and important module in electronic devices, typically used for data storage and retrieval. Due to its advantages of low power consumption and high integration, DRAM is frequently used as the main memory in computers. DRAM can only retain data for a short time; to maintain data, DRAM must be refreshed periodically. The basic unit of DRAM consists of a transistor and a capacitor. If the capacitor leaks current, insufficient charge will lead to data errors. To replenish the lost charge and prevent information loss, the gate capacitor must be periodically recharged; therefore, the capacitor must be periodically refreshed. If a memory cell is not refreshed, the data will be lost.

[0003] Data retention time in Dynamic Random Access Memory (DRAM) is limited by leakage current. There are two main leakage mechanisms affecting DRAM data retention time: one is transistor cell leakage, primarily due to gate-induced drain leakage current, caused by the high electric field effect at the drain junction. Under negative gate bias, a depletion region is generated at the gate, which in turn generates an enhanced electric field. This field causes band bending, leading to interband tunneling. Electrons and minority carriers moving at the gate can tunnel through this region into the drain, resulting in unwanted leakage current. The other is dielectric leakage between the bit line contact structure and the memory node contact structure. Dielectric leakage typically occurs inside the capacitor, where electrons flow through the metal and dielectric regions. Dielectric leakage occurs when electrons tunnel through the dielectric layer from one electrode to another. As process nodes shrink, the distance between the bit line contact structure and the memory node contact structure is also decreasing, thus exacerbating this problem. Manufacturing process variations in these structural components also negatively impact dielectric leakage between the bit line contact structure and the memory node contact structure. Another important factor affecting the performance of dynamic random access memory (DRAM) is the device's parasitic capacitance. AC analysis should be performed during DRAM development because bit line coupling can cause write recovery time delays and other performance failures. Since doped polysilicon is used not only for transistor gates but also for bit line contacts and memory node contacts, this results in multiple potential parasitic capacitances.

[0004] In existing technologies, for semiconductor memories such as dynamic random access memory (DRAM), the mainstream bit line structure is formed by sequentially filling oxide layers after bit line channel etching. After the bit line pattern is formed, the oxide structure between the bit lines determines the inter-bit line capacitance. Bit line parasitic capacitance, as an important electrical parameter, affects the stability of DRAM.

[0005] As dynamic random access memory (DRAM) has evolved, improving its stability and performance has become a major obstacle to its further development. Summary of the Invention

[0006] The technical problem to be solved by this disclosure is to reduce the parasitic capacitance of the bit line and improve the electrical stability of the semiconductor structure by introducing an isolation layer with a void structure inside the bit line trench, thereby providing a method for fabricating a semiconductor structure and a semiconductor structure.

[0007] This disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate having first trenches arranged in the same direction; forming a protective layer on the sidewalls of the first trenches; forming a second trench at the bottom of the first trenches, the width of the second trench being greater than the width of the first trench; forming a first isolation layer on the sidewalls of the second trenches to reduce the opening size of the second trenches; filling the first trenches and the second trenches to form a second isolation layer and forming a void within the second trenches; forming a third trench on the substrate, the third trench being perpendicular to the first trenches; and forming bit lines within the third trenches.

[0008] In some embodiments, in the method for fabricating the semiconductor structure, the bit line formation step includes: depositing a metal layer in the third trench and forming a metal silicide by isotropic diffusion into contact with the substrate; removing the unreacted metal layer to form the bit line.

[0009] In some embodiments, in the method for fabricating the semiconductor structure, the formation of the third trench involves a secondary expansion.

[0010] In some embodiments, in the method for fabricating the semiconductor structure, the protective layer, the first isolation layer, and the second isolation layer are each formed independently using physical vapor deposition and / or chemical vapor deposition.

[0011] In some embodiments, in the method for fabricating the semiconductor structure, the second trench is formed by isotropic etching.

[0012] In some embodiments, in the method for fabricating the semiconductor structure, the second trench is located below the first trench, and the second trench is in the shape of an inverted teardrop.

[0013] In some embodiments, the method for fabricating the semiconductor structure further includes a cleaning step in forming the second trench.

[0014] In some embodiments, the cleaning step in the method for fabricating the semiconductor structure uses HF.

[0015] In some embodiments, in the method of fabricating the semiconductor structure, the filling of the first trench and the second trench is carried out by a stepped coverage method, in which the first trench is filled and a void is formed in the second trench.

[0016] In some embodiments, in the method for preparing the semiconductor structure, the materials of the protective layer, the first isolation layer, and the second isolation layer are each independently selected from silicon oxide, silicon nitride, and silicon oxynitride.

[0017] In some embodiments, in the method for fabricating the semiconductor structure, the step of forming a protective layer on the sidewall of the first trench further comprises: growing a protective layer in the first trench, the protective layer covering the sidewall and bottom of the first trench; removing the protective layer located at the bottom of the first trench, and retaining the protective layer on the sidewall of the first trench.

[0018] To address the aforementioned issues, this disclosure provides a semiconductor structure comprising: a substrate having bit line trenches arranged in the same direction, the bit line trenches including a first trench and a second trench, the second trench being located below the first trench and communicating with the first trench; an isolation layer filling the interior of the bit line trenches, the isolation layer having voids; and bit lines disposed between the bit line trenches and spaced apart by the isolation layer.

[0019] In some embodiments, the bit line trenches in the semiconductor structure are formed using isotropic etching.

[0020] In some embodiments, in the semiconductor structure, the second trench is in the shape of an inverted teardrop.

[0021] In some embodiments, in the semiconductor structure, the void is disposed in the isolation layer of the second trench portion.

[0022] In some embodiments of the semiconductor structure, the bit line is made of metal silicide.

[0023] In some embodiments, in the semiconductor structure, the isolation layer is formed using one or more of physical vapor deposition, chemical vapor deposition, and step-over deposition methods.

[0024] In some embodiments, in the semiconductor structure, the material of the isolation layer is selected from silicon oxide, silicon nitride, and silicon oxynitride.

[0025] This disclosure improves the electrical stability of semiconductor structures by introducing an isolation layer with a void structure inside the bit line trench to reduce bit line parasitic capacitance. Attached Figure Description

[0026] Appendix Figure 1 The diagram shows a step-by-step illustration of a method for fabricating a semiconductor structure according to a specific embodiment of this disclosure.

[0027] Appendix Figure 2A-2G The attached image shows... Figure 1 Process diagram of steps S10-S16.

[0028] Appendix Figure 3 The diagram shows a step of forming a protective layer on the sidewall of the first trench in a method for fabricating a semiconductor structure according to a specific embodiment of this disclosure.

[0029] Appendix Figures 4A-4B The attached image shows... Figure 3 A schematic diagram of the process steps S31-S32.

[0030] Appendix Figures 5A-5B The diagram shown is a schematic representation of the secondary expansion process of the third trench in a specific embodiment of the semiconductor structure fabrication method described in this disclosure.

[0031] Appendix Figure 6 The diagram shown is a schematic diagram of a semiconductor structure according to a specific embodiment of this disclosure.

[0032] Appendix Figures 7A-7G The attached image shows... Figure 1 Process diagram of steps S10-S16.

[0033] Appendix Figures 8A-8B The attached image shows... Figure 3 A schematic diagram of the process steps S31-S32.

[0034] Appendix Figure 9 The diagram shown is a schematic diagram of a semiconductor structure according to a specific embodiment of this disclosure. Detailed Implementation

[0035] The following detailed description, in conjunction with the accompanying drawings, illustrates the method for fabricating the semiconductor structure and specific embodiments thereof.

[0036] Appendix Figure 1The diagram illustrates the steps of a method for fabricating a semiconductor structure according to a specific embodiment of this disclosure, including: Step S10, providing a substrate having first trenches arranged in the same direction; Step S11, forming a protective layer on the sidewalls of the first trenches; Step S12, forming a second trench at the bottom of the first trenches, the width of the second trench being greater than the width of the first trench; Step S13, forming a first isolation layer on the sidewalls of the second trenches to reduce the opening size of the second trenches; Step S14, filling the first trenches and the second trenches to form a second isolation layer, and forming a void within the second trenches; Step S15, forming a third trench on the substrate, the third trench intersecting with the first trenches; Step S16, forming bit lines within the third trenches.

[0037] Appendix Figure 2A-2G The attached image shows... Figure 1 Process diagram of steps S10-S16.

[0038] Appendix Figure 2A As shown, referring to step S10, a substrate 201 is provided, the substrate 201 having first trenches 202 arranged in the same direction. In one specific embodiment of this disclosure, the substrate 201 is a Si substrate; in other specific embodiments of this disclosure, the material of the substrate 201 can also be sapphire, silicon carbide, gallium nitride, and other substrate materials commonly used in the semiconductor field. In one specific embodiment of this disclosure, the first trenches 202 are obtained using dry etching and / or wet etching processes.

[0039] Appendix Figure 2B As shown, referring to step S11, a protective layer 203 is formed on the sidewall of the first trench 202. In one specific embodiment of this disclosure, the material of the protective layer 203 is selected from, but is not limited to, silicon oxide, silicon nitride, and silicon oxynitride materials, and the protective layer 203 is formed by physical vapor deposition and / or chemical vapor deposition.

[0040] In one specific embodiment of this disclosure, the method for forming the protective layer 203 is described in the appendix. Figure 3 and appendix Figures 4A-4B .

[0041] Appendix Figure 3 The diagram shows a step of forming a protective layer 203 on the sidewall of the first trench 202 in a method for fabricating a semiconductor structure according to a specific embodiment of the present disclosure. The steps include: step S31, growing a protective layer in the first trench, the protective layer covering the sidewall and bottom of the first trench; and step S32, removing the protective layer located at the bottom of the first trench, while retaining the protective layer on the sidewall of the first trench.

[0042] Appendix Figures 4A-4BThe attached image shows... Figure 3 A schematic diagram of the process steps S31-S32.

[0043] Appendix Figure 4A As shown, referring to step S31, a protective layer 21 is grown within the first trench 202, the protective layer 21 covering the sidewalls and bottom of the first trench 202. In one specific embodiment of this disclosure, the material of the protective layer 21 is selected from, but is not limited to, silicon oxide, silicon nitride, and silicon oxynitride materials, and the protective layer 21 is formed using physical vapor deposition and / or chemical vapor deposition methods.

[0044] Appendix Figure 4B As shown, referring to step S32, the protective layer 21 located at the bottom of the first trench 202 is removed, while the protective layer 21 on the sidewall of the first trench 202 is retained, thus forming an attached layer. Figure 2B The protective layer 203 is shown. This is so that the bottom of the first trench 202 can be etched in a subsequent step.

[0045] Received Figure 2B After seeing the structure shown, continue with the following steps.

[0046] Appendix Figure 2C As shown, referring to step S12, a second trench 204 is formed at the bottom 202 of the first trench, and the width of the second trench 204 is greater than the width of the first trench 202. In one specific embodiment of this disclosure, the second trench 204 is located below the first trench 202, and the second trench 204 is teardrop-shaped. The width of the widest part of the second trench 204 is greater than the width of the first trench 202. In one specific embodiment of this disclosure, the second trench 204 is formed by isotropic etching. The formation of the second trench 204 also includes a cleaning step. In one specific embodiment of this disclosure, after the isotropic etching is completed to form the second trench 204, a cleaning step is performed, and the cleaning step uses HF. In other specific embodiments of this disclosure, the second trench 204 may have other shapes.

[0047] Appendix Figure 2DAs shown, referring to step S13, a first isolation layer 205 is formed on the sidewall of the second trench 204 to reduce the opening size of the second trench 204. In one specific embodiment of this disclosure, the material of the first isolation layer 205 is selected from, but is not limited to, silicon oxide, silicon nitride, and silicon oxynitride, and the first isolation layer 205 is formed by physical vapor deposition and / or chemical vapor deposition. In other specific embodiments of this disclosure, the materials of the protective layer 203 and the first isolation layer 205 are each independently selected from silicon oxide, silicon nitride, and silicon oxynitride; the protective layer 203 and the first isolation layer 205 are each independently formed by physical vapor deposition and / or chemical vapor deposition.

[0048] Appendix Figure 2E As shown, referring to step S14, the first trench 202 and the second trench 204 are filled to form a second isolation layer 206, and voids 207 are formed within the second trench 204. The filling of the first trench 202 and the second trench 204 employs a stepped coverage method, filling the first trench 202 completely and forming voids 207 within the second trench 204. In one specific embodiment of this disclosure, the material of the second isolation layer 206 is selected from, but is not limited to, silicon oxide, silicon nitride, and silicon oxynitride materials, and the second isolation layer 206 is formed using physical vapor deposition and / or chemical vapor deposition. In other specific embodiments of this disclosure, the materials of the protective layer 203, the first isolation layer 205, and the second isolation layer 206 are each independently selected from silicon oxide, silicon nitride, and silicon oxynitride materials. The protective layer 203, the first isolation layer 205, and the second isolation layer 206 are each independently formed using physical vapor deposition and / or chemical vapor deposition. In this specific embodiment, the second isolation layer 206 is made of the same material and is fused together with the protective layer 203 and the first isolation layer 205. In other specific embodiments of this disclosure, the second isolation layer 206 may also be made of a different material than the protective layer 203 and the first isolation layer 205, and present a layered effect.

[0049] Appendix Figure 2F As shown, referring to step S15, a third trench 208 is formed on the substrate 201, the third trench 208 being perpendicular to the first trench 202. In one specific embodiment of this disclosure, the formation of the third trench 208 employs dry etching and / or wet etching processes. In subsequent steps, the third trench 208 is used to form bit lines.

[0050] In one specific embodiment of this disclosure, the formation of the third trench 208 involves a secondary enlargement. In another specific embodiment of this disclosure, the secondary enlargement employs dry etching and / or wet etching processes. (See attached document.) Figures 5A-5BThe diagram shown is a schematic representation of the secondary expansion process of the third trench in a specific embodiment of the semiconductor structure fabrication method described in this disclosure. Figure 5A The diagram shown is a schematic diagram of the third trench 208 before its secondary enlargement. To better form the bit line in subsequent processes, the prepared third trench 22 needs to be enlarged secondaryly. Figure 5B The diagram shown is a schematic of the second expansion of the third trench 208.

[0051] Received Figure 2F After seeing the structure shown, continue with the following steps.

[0052] Appendix Figure 2G As shown, referring to step S16, a bit line 209 is formed within the third trench 208. The bit line 209 is made of a metal silicide material. In one specific embodiment of this disclosure, the bit line 209 is made of cobalt silicide material.

[0053] The step of forming bit line 209 further includes: depositing a metal layer in the third trench 208 and forming a metal silicide by isotropic diffusion into contact with the substrate 201; removing the unreacted metal layer to form bit line 209. In a specific embodiment of this disclosure, the step of forming bit line 209 further includes: depositing a cobalt layer in the third trench 208 and forming cobalt silicide by isotropic diffusion into contact with the substrate 201; removing the unreacted cobalt layer to form bit line 209, wherein bit line 209 is formed using cobalt silicide material.

[0054] Appendix Figure 6 The diagram shown is a schematic representation of the semiconductor structure obtained after the above steps are completed, according to a specific embodiment of this disclosure. The semiconductor structure includes: a substrate 601, on which bit line trenches 61 are arranged in the same direction. Each bit line trench 61 includes a first trench 611 and a second trench 612, the second trench 612 being located below and communicating with the first trench 611; an isolation layer 602, filling the interior of the bit line trenches 61, and having gaps 603 within the isolation layer 602; and bit lines 604, disposed between the bit line trenches 61 and spaced apart by the isolation layer 602.

[0055] In one embodiment of this disclosure, the bit line trench 61 is formed by isotropic etching. The second trench 612 is teardrop-shaped, and the width of the widest part of the second trench 612 is greater than the width of the first trench 611. In other embodiments of this disclosure, the second trench 612 may have other shapes. In one embodiment of this disclosure, the second trench 612 is formed by isotropic etching. In one embodiment of this disclosure, the first trench 611 is obtained by dry etching and / or wet etching processes. After completing the bit line trench 61 etching step, a cleaning step is required, wherein the cleaning step uses HF.

[0056] In one specific embodiment of this disclosure, the void 603 is disposed in the isolation layer 602 of the second trench 612 portion. The material of the isolation layer 602 is selected from silicon oxide, silicon nitride, and silicon oxynitride. The isolation layer 602 is formed by one or more methods selected from physical vapor deposition, chemical vapor deposition, and step-capture method. In this specific embodiment, the isolation layer 602 is formed using one material; in other specific embodiments of this disclosure, the isolation layer 602 may also be formed using multiple different materials, exhibiting a layered effect. By providing the void 603 in the isolation layer 602, the bit line parasitic capacitance is reduced, and the electrical stability of the semiconductor structure is improved.

[0057] The bit line 604 is made of metal silicide. In one specific embodiment of this disclosure, the bit line 604 is made of cobalt silicide.

[0058] The above technical solution introduces an isolation layer 602 with gaps 603 inside the bit line trench 61 to reduce the parasitic capacitance of the bit line and improve the electrical stability of the semiconductor structure.

[0059] In another specific embodiment of this disclosure, the second groove may take a shape other than the inverted teardrop shape. (See attached image) Figures 7A-7G The attached diagram shows another specific implementation. Figure 1 Process diagram of steps S10-S16.

[0060] Appendix Figure 7A As shown, referring to step S10, a substrate 701 is provided, the substrate 701 having first trenches 702 arranged in the same direction. In one specific embodiment of this disclosure, the substrate 701 is a Si substrate; in other specific embodiments of this disclosure, the material of the substrate 701 can also be sapphire, silicon carbide, gallium nitride, and other substrate materials commonly used in the semiconductor field. In one specific embodiment of this disclosure, the first trenches 702 are obtained using dry etching and / or wet etching processes.

[0061] Appendix Figure 7B As shown, referring to step S11, a protective layer 703 is formed on the sidewall of the first trench 702. In one specific embodiment of this disclosure, the material of the protective layer 703 is selected from, but is not limited to, silicon oxide, silicon nitride, and silicon oxynitride materials, and the protective layer 703 is formed by physical vapor deposition and / or chemical vapor deposition.

[0062] Appendix Figure 7C As shown, referring to step S12, a second trench 704 is formed at the bottom 702 of the first trench, and the width of the second trench 704 is greater than the width of the first trench 702. In one specific embodiment of this disclosure, the second trench 704 is located below the first trench 702, and the second trench 704 is elliptical. The width of the widest part of the second trench 704 is greater than the width of the first trench 702, that is, the minor axis of the ellipse is greater than the width of the first trench 702. In one specific embodiment of this disclosure, the second trench 704 is formed by isotropic etching. The formation of the second trench 704 also includes a cleaning step. In one specific embodiment of this disclosure, after the isotropic etching is completed to form the second trench 704, a cleaning step is performed, and the cleaning step uses HF. In other specific embodiments of this disclosure, the second trench 704 may have other shapes.

[0063] Appendix Figure 7D As shown, referring to step S13, a first isolation layer 705 is formed on the sidewall of the second trench 704 to reduce the opening size of the second trench 204. In one specific embodiment of this disclosure, the material of the first isolation layer 205 is selected from, but is not limited to, silicon oxide, silicon nitride, and silicon oxynitride, and the first isolation layer 705 is formed by physical vapor deposition and / or chemical vapor deposition. In other specific embodiments of this disclosure, the materials of the protective layer 703 and the first isolation layer 705 are each independently selected from silicon oxide, silicon nitride, and silicon oxynitride; the protective layer 703 and the first isolation layer 705 are each independently formed by physical vapor deposition and / or chemical vapor deposition.

[0064] Appendix Figure 7EAs shown, referring to step S14, the first trench 702 and the second trench 704 are filled to form a second isolation layer 706, and voids 707 are formed within the second trench 704. The filling of the first trench 702 and the second trench 704 employs a stepped coverage method, filling the first trench 702 completely and forming voids 707 within the second trench 704. In one specific embodiment of this disclosure, the material of the second isolation layer 706 is selected from, but is not limited to, silicon oxide, silicon nitride, and silicon oxynitride materials, and the second isolation layer 706 is formed using physical vapor deposition and / or chemical vapor deposition. In other specific embodiments of this disclosure, the materials of the protective layer 703, the first isolation layer 705, and the second isolation layer 706 are each independently selected from silicon oxide, silicon nitride, and silicon oxynitride materials. The protective layer 703, the first isolation layer 705, and the second isolation layer 706 are each independently formed using physical vapor deposition and / or chemical vapor deposition. In this specific embodiment, the second isolation layer 706 is made of the same material and is fused with the protective layer 703 and the first isolation layer 705. In other specific embodiments of this disclosure, the second isolation layer 706 may also be made of a different material than the protective layer 703 and the first isolation layer 705, and present a layered effect.

[0065] Appendix Figure 7F As shown, referring to step S15, a third trench 708 is formed on the substrate 701, the third trench 708 being perpendicular to the first trench 702. In one specific embodiment of this disclosure, the formation of the third trench 708 employs a dry etching and / or wet etching process. In subsequent steps, the third trench 708 is used to form bit lines.

[0066] In one specific embodiment of this disclosure, the formation of the third trench 708 involves a secondary enlargement. In another specific embodiment of this disclosure, the secondary enlargement employs dry etching and / or wet etching processes. (See attached document.) Figures 8A-8B The diagram shown is a schematic representation of the secondary expansion process of the third trench in a specific embodiment of the semiconductor structure fabrication method described in this disclosure. Figure 8A The diagram shown is a schematic of the third trench 708 before secondary enlargement. To better form the bit line in subsequent processes, the prepared third trench 72 needs to be enlarged secondary. (See attached diagram.) Figure 8B The diagram shown is a schematic of the third groove after its secondary expansion (708).

[0067] Received Figure 7F After seeing the structure shown, continue with the following steps.

[0068] Appendix Figure 7GAs shown, referring to step S16, a bit line 709 is formed within the third trench 708. The bit line 709 is made of a metal silicide material. In one specific embodiment of this disclosure, the bit line 709 is made of cobalt silicide material.

[0069] The step of forming bit line 709 further includes: depositing a metal layer in the third trench 708 and forming a metal silicide by isotropic diffusion into contact with the substrate 701; removing the unreacted metal layer to form bit line 709. In a specific embodiment of this disclosure, the step of forming bit line 709 further includes: depositing a cobalt layer in the third trench 708 and forming cobalt silicide by isotropic diffusion into contact with the substrate 701; removing the unreacted cobalt layer to form bit line 709, wherein bit line 709 is formed using cobalt silicide material.

[0070] Appendix Figure 9 The diagram shown is a schematic representation of the semiconductor structure obtained after the above steps are completed, according to a specific embodiment of this disclosure. The semiconductor structure includes: a substrate 901, on which bit line trenches 91 are arranged in the same direction. Each bit line trench 91 includes a first trench 911 and a second trench 912, the second trench 912 being located below and communicating with the first trench 911; an isolation layer 902, filling the interior of the bit line trenches 91, the isolation layer 902 having gaps 903; and bit lines 904, disposed between the bit line trenches 91 and spaced apart by the isolation layer 902.

[0071] In one embodiment of this disclosure, the bit line trench 91 is formed by isotropic etching. The second trench 912 is elliptical, and the width of the widest part of the second trench 912 is greater than the width of the first trench 911, that is, the minor axis of the ellipse is greater than the width of the first trench 911. In other embodiments of this disclosure, the second trench 912 may have other shapes. In one embodiment of this disclosure, the second trench 912 is formed by isotropic etching. In one embodiment of this disclosure, the first trench 911 is obtained by dry etching and / or wet etching processes. After completing the bit line trench 91 etching step, a cleaning step is required, wherein the cleaning step uses HF.

[0072] In one specific embodiment of this disclosure, the void 903 is disposed in the isolation layer 902 of the second trench 912 portion. The material of the isolation layer 902 is selected from silicon oxide, silicon nitride, and silicon oxynitride. The isolation layer 902 is formed by one or more methods selected from physical vapor deposition, chemical vapor deposition, and step-capture method. In this specific embodiment, the isolation layer 902 is formed using one material; in other specific embodiments of this disclosure, the isolation layer 902 may also be formed using multiple different materials, exhibiting a layered effect. By providing the void 903 in the isolation layer 902, the parasitic capacitance of the bit lines is reduced, and the electrical stability of the semiconductor structure is improved.

[0073] The bit line 904 is made of metal silicide. In one specific embodiment of this disclosure, the bit line 904 is made of cobalt silicide.

[0074] The above technical solution introduces an isolation layer 902 with gaps 903 inside the bit line trench 91 to reduce the parasitic capacitance of the bit line and improve the electrical stability of the semiconductor structure.

[0075] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided having first trenches arranged in the same direction; A protective layer is formed on the sidewall of the first trench; A second groove is formed at the bottom of the first groove, and the width of the second groove is greater than the width of the first groove; A first isolation layer is formed on the sidewall of the second trench to reduce the opening size of the second trench; The first and second trenches are filled to form a second isolation layer, and a void is formed in the second trench; A third trench is formed on the substrate, the third trench being located between adjacent second trenches and perpendicular to the first trench; Bit lines are formed in the third trench. The bit lines are made of metal silicide material. The bit lines are in contact with the first isolation layer. The gaps are located between adjacent bit lines.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of forming bit lines includes: A metal layer is deposited in the third trench and the metal silicide is formed by isotropic diffusion into contact with the substrate. Remove the unreacted metal layer to form bit lines.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of the third trench involved a second expansion.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The protective layer, the first isolation layer, and the second isolation layer are each formed independently using physical vapor deposition and / or chemical vapor deposition methods.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, The second trench is formed by isotropic etching.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, The second groove is located below the first groove, and the second groove is in the shape of an inverted teardrop.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, The process of forming the second trench also includes a cleaning step.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The cleaning step uses HF.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that, The filling of the first and second trenches is carried out using a stepped covering method, which fills the first trench and creates gaps in the second trench.

10. The method for preparing a semiconductor structure according to claim 1, characterized in that, The materials of the protective layer, the first isolation layer, and the second isolation layer are each independently selected from silicon oxide, silicon nitride, and silicon oxynitride.

11. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of forming a protective layer on the sidewall of the first trench further includes: A protective layer is grown within the first trench, the protective layer covering the sidewalls and bottom of the first trench; Remove the protective layer located at the bottom of the first trench, and retain the protective layer on the sidewall of the first trench.

12. A semiconductor structure, characterized in that, include: A substrate having bit line trenches arranged in the same direction, the bit line trenches including a first trench and a second trench, the second trench being located below the first trench and communicating with the first trench, the width of the second trench being greater than the width of the first trench. An isolation layer that fills the interior of the bit line trench and has voids within it; Bit lines are disposed between the bit line grooves and spaced apart by the isolation layer; The isolation layer includes a protective layer formed on the sidewall of the first trench, a first isolation layer formed on the sidewall of the second trench, and a second isolation layer filling the first trench and the second trench. The gap is disposed in the second isolation layer within the second trench. The bit line is made of metal silicide material. The bit line is in contact with the first isolation layer. The gap is located between adjacent bit lines.

13. The semiconductor structure according to claim 12, characterized in that, The bit line trenches are formed by isotropic etching.

14. The semiconductor structure according to claim 12, characterized in that, The second groove is shaped like an inverted teardrop.

15. The semiconductor structure according to claim 12, characterized in that, The isolation layer is formed using one or more of the following methods: physical vapor deposition, chemical vapor deposition, and step-over method.

16. The semiconductor structure according to claim 12, characterized in that, The material of the isolation layer is selected from silicon oxide, silicon nitride, and silicon oxynitride.

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