Integrated circuit and method of manufacturing the same

Abstract

An integrated circuit includes a power rail set, an active area set, a first wire set, and a first via set and a second via set. The power rail set is configured to provide a first supply voltage or a second supply voltage and is located on a first level of a backside of a substrate. The active area set is a second level of a frontside of the substrate. The first wire set extends in a second direction and overlaps the active area set. The first via set is located between the active area set and the first wire set and electrically couples the active area set and the first wire set together. The second via set is located between the first wire set and the power rail set and electrically couples the first wire set and the power rail set together. Embodiments of the present application also relate to methods of manufacturing an integrated circuit.

Description

Technical Field

[0001] Embodiments of this application relate to integrated circuits and methods of manufacturing the same. Background Technology

[0002] Recent trends in miniaturized integrated circuits (ICs) have resulted in smaller devices that consume less power but deliver more functionality at higher speeds. Miniaturization processes have also created more stringent design and manufacturing specifications and reliability challenges. Various electronic design automation (EDA) tools generate, optimize, and verify standard cell layout designs for integrated circuits, while ensuring compliance with standard cell layout design and manufacturing specifications. Summary of the Invention

[0003] Some embodiments of this application provide an integrated circuit, including: a power rail group extending in a first direction, configured to provide a first supply voltage or a second supply voltage, and located on a first layer on the back side of a substrate; an active region group extending in the first direction and located on a second layer on the front side of the substrate opposite to the back side, the second layer being different from the first layer, and the active region group overlapping the power rail group; a first conductor group extending in a second direction different from the first direction, located on a third layer on the back side of the substrate, the third layer being different from the first layer and the second layer, and overlapping the active region group; a first via group located between the active region group and the first conductor group, the first via group electrically coupling the active region group to the first conductor group; and a second via group located between the first conductor group and the power rail group, the second via group electrically coupling the first conductor group and the power rail group.

[0004] Other embodiments of this application provide an integrated circuit including: a first power rail extending in a first direction, configured to provide a first supply voltage and located on a first layer on the back side of a substrate; a second power rail extending in the first direction, configured to provide a second supply voltage different from the first supply voltage, and the second power rail being located on the first layer and separated from the first power rail in a second direction different from the first direction; a first signal line extending in the first direction, located on the first layer, and located between the first power rail and the second power rail; and a first active region extending in the first direction and located on the front side of the substrate opposite to the back side. On the second layer, the second layer is different from the first layer, and the first active region overlaps with and is electrically coupled to the first power rail; the second active region extends in the first direction, is located on the second layer, is separated from the first active region in the second direction, overlaps with and is electrically coupled to the second power rail; and the first conductor extends in the second direction, is located on the third layer on the back side of the substrate, the third layer is different from the first and second layers, overlaps with the first and second active regions, and electrically couples the first and second active regions to the first signal line.

[0005] Some embodiments of this application provide a method for manufacturing an integrated circuit, the method comprising: fabricating a transistor group and pseudo-vias in a front side of a substrate; thinning a back side of the substrate opposite to the front side; fabricating a first via group and a first conductor group on the back side of the thinned substrate at a first level, the first conductor group being electrically coupled to the transistor group through the first via group; fabricating a second via group on the back side of the thinned substrate; and depositing a conductive material on the back side of the thinned substrate at a second level to form a second conductor group, the second conductor group being electrically coupled to the first conductor group through the second via group. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figures 1A to 1B This is a layout design diagram of an integrated circuit according to some embodiments.

[0008] Figures 2A to 2C This is a diagram of an integrated circuit according to some embodiments.

[0009] Figures 3A to 3F This is a diagram of a corresponding integrated circuit according to some embodiments.

[0010] Figures 4A to 4B This is a layout design diagram of an integrated circuit according to some embodiments.

[0011] Figures 5A to 5E This is a diagram of an integrated circuit according to some embodiments.

[0012] Figures 6A to 6B This is a layout design diagram of an integrated circuit according to some embodiments.

[0013] Figures 7A to 7C This is a diagram of an integrated circuit according to some embodiments.

[0014] Figures 8A to 8B This is a diagram of a corresponding integrated circuit according to some embodiments.

[0015] Figure 9 These are circuit diagrams of integrated circuits according to some embodiments.

[0016] Figures 10A to 10C This is a top view of a corresponding portion of an integrated circuit according to some embodiments.

[0017] Figure 11 These are circuit diagrams of integrated circuits according to some embodiments.

[0018] Figures 12A to 12C This is a top view of a corresponding portion of an integrated circuit according to some embodiments.

[0019] Figure 13 These are circuit diagrams of integrated circuits according to some embodiments.

[0020] Figures 14A to 14C This is a top view of a corresponding portion of an integrated circuit according to some embodiments.

[0021] Figure 15 These are circuit diagrams of integrated circuits according to some embodiments.

[0022] Figures 16A to 16C This is a top view of a corresponding portion of an integrated circuit according to some embodiments.

[0023] Figure 17A This is a flowchart of a method for forming or manufacturing an integrated circuit according to some embodiments.

[0024] Figure 17B This is a flowchart of a method for manufacturing a back-side wiring track and a back-side through-hole connector according to some embodiments.

[0025] Figures 18A to 18F This is a diagram of an intermediate version of an integrated circuit according to some embodiments.

[0026] Figure 19 This is a flowchart of a method for manufacturing an IC device according to some embodiments.

[0027] Figure 20 This is a flowchart of a method for generating a layout design of an integrated circuit according to some embodiments.

[0028] Figure 21 This is a schematic diagram of a system for designing IC layout and manufacturing IC circuits according to some embodiments.

[0029] Figure 22 This is a block diagram of an IC manufacturing system and an associated IC manufacturing process according to at least one embodiment of the present invention. Detailed Implementation

[0030] The following disclosure provides numerous different embodiments or instances for implementing the features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements, etc., are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. Other components, materials, values, steps, arrangements, etc., may be contemplated. For example, in the following description, forming a first component on or above a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0031] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0032] According to some embodiments, the integrated circuit includes a first power rail, a second power rail, a first signal line, a first active region, a second active region, and a first conductor.

[0033] In some embodiments, a first power rail and a second power rail extend in a first direction and are located on a first layer on the back side of the substrate. In some embodiments, the first power rail is configured to provide a first supply voltage, and the second power rail is configured to provide a second supply voltage different from the first supply voltage.

[0034] In some embodiments, the first signal line extends in a first direction and is also located on a first layer on the back side of the substrate. In some embodiments, the first signal line is located between a first power rail and a second power rail.

[0035] In some embodiments, the first active region and the second active region are located on a second layer on the front side of the substrate opposite to the back side.

[0036] In some embodiments, the first conductor extends in a second direction and is located on a third layer on the back side of the substrate. In some embodiments, the first conductor electrically couples a first active region and a second active region to a first signal line.

[0037] In some embodiments, by electrically coupling the first active region and the second active region to the first signal line, the integrated circuit of the present invention provides greater wiring flexibility and more via locations, thus increasing wiring resources compared to other methods.

[0038] Figures 1A to 1B This is a diagram of an integrated circuit layout design 100 according to some embodiments. Layout design 100 is... Figures 2A to 2C The layout diagram of integrated circuit 200.

[0039] Figure 1A yes Figure 1B The layout design of 100 is shown in the diagram of the corresponding part 100A, which is simplified for ease of explanation. Figure 1B This is a diagram of layout design 100, including part 100A, which has been simplified for ease of explanation.

[0040] For ease of explanation, Figures 1A to 1B , Figures 2A to 2C , Figures 3A to 3E , Figures 4A to 4B , Figures 5A to 5E , Figures 6A to 6B , Figures 7A to 7C , Figures 8A to 8B , Figure 9 , Figures 10A to 10C , Figure 11 , Figures 12A to 12C , Figure 13 , 14A to Figure 14C , Figure 15 , Figures 16A to 16C and Figures 18A to 18F One or more of the marked elements were not in Figures 1A to 1B, Figures 2A to 2C , Figures 3A to 3E , Figures 4A to 4B , Figures 5A to 5E , Figures 6A to 6B , Figures 7A to 7C , Figures 8A to 8B , Figure 9 , Figures 10A to 10C , Figure 11 , Figures 12A to 12C , Figure 13 , Figures 14A to 14C , Figure 15 , Figures 16A to 16C and Figures 18A to 18F One or more markers in the layout design. In some embodiments, the layout design 100 includes Figures 1A to 1B Additional elements not shown in the diagram.

[0041] Part 100A includes an oxide diffusion (OD) layer or active layer, a gate (POLY) layer, a back metal 0 (BM0) layer, a back metal 1 (BM1) layer, a back via 0 (VB0) layer, and a via back signal / power (VBS / P) layer of layout design 100. Figure 1B The layout design of 100 is one or more components.

[0042] The layout design 100 includes one or more components from the OD level, POLY level, BM0 level, BM1 level, VB0 level, VBS / P level and metal 0 (M0) level of the layout design 100.

[0043] Layout design 100 can be used for manufacturing Figures 2A to 2C Integrated circuit 200.

[0044] Layout design 100 has cell boundaries 101a and 101b extending in a first direction X, and a midpoint 101c. Midpoint 101c is equidistant from cell boundaries 101a and 101b. Layout design 100 has a height CH1a in a second direction Y, from cell boundary 101b to cell boundary 101a. In some embodiments, the second direction Y is different from the first direction X. In some embodiments, layout design 100 is adjacent to other cell layout designs (not shown) along cell boundaries 101a and 101b and along cell boundaries (not labeled) extending in the second direction Y. In some embodiments, layout design 100 is a single height standard cell.

[0045] In some embodiments, at least 100, 400 ( ) are laid out in the design. Figures 4A to 4B ) or 600 ( Figures 6A to 6B ) is a standard cell layout design. In some embodiments, layout designs 100, 400 ( Figures 4A to 4B ) or 600 ( Figures 6A to 6BOne or more of these are layout designs for logic gate cells. In some embodiments, the logic gate cells include AND, OR, NAND, NOR, XOR, inverting, AND-OR-inverting (AOI), OR-AND-inverting (OAI), multiplexers, flip-flops, buffers, latches, delays, or clock cells. In some embodiments, layout designs 100, 400 (… Figures 4A to 4B ) or 600 ( Figures 6A to 6B One or more of these are layout designs for memory cells. In some embodiments, the memory cells include static random access memory (SRAM), dynamic RAM (DRAM), resistive RAM (RRAM), magnetoresistive RAM (MRAM), or read-only memory (ROM). In some embodiments, layout designs 100, 400 ( Figures 4A to 4B ) or 600 ( Figures 6A to 6B One or more of the following includes a layout design comprising one or more active or passive components. Examples of active components include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel and / or n-channel field-effect transistors (PFETs / NFETs), FinFETs, nanosheet transistors, nanowire transistors, complementary FETs (CFETs), and planar MOS transistors with raised source / drain electrodes. Examples of passive components include, but are not limited to, capacitors, inductors, fuses, and resistors.

[0046] The layout design 100 includes one or more active region layout patterns 102a or 102b extending in the first direction X (collectively referred to as “active region pattern group 102”).

[0047] The embodiments of the present invention use the term "layout pattern," and for the sake of brevity, the term will also be referred to as "pattern" in the remainder of the present invention.

[0048] The active region patterns 102a and 102b of the active region pattern group 102 are separated from each other in the second direction Y. The active region pattern group 102 can be used to manufacture integrated circuits 200, 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600, or 1800. Figures 2A to 2C , Figures 3A to 3F , Figures 5A to 5E , Figures 7A to 7C , Figures 8A to 8B , Figures 10A to 10C , Figures 12A to 12C , Figures 14A to 14C , Figures 16A to 16C or Figures 18A to 18F The corresponding active region group is 202 or 1602.

[0049] In some embodiments, the active region group 202 is located on the front side 203a of the integrated circuit 200, 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600, or 1800. In some embodiments, the active region patterns 102a, 102b of the active region pattern group 102 can be used to manufacture the corresponding active regions 202a, 202b of the active region group 202 of the integrated circuit 200, 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600, or 1800.

[0050] In some embodiments, the active region pattern group 102 is referred to as an oxide diffusion (OD) region, which defines at least integrated circuits 200, 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600 or 1800 or layout designs 100, 400 (…). Figures 4A to 4B ) or 600 ( Figures 6A to 6B The source diffusion region or drain diffusion region.

[0051] In some embodiments, the active region pattern 102a of the active region pattern group 102 can be used to manufacture the source and drain regions of n-type metal-oxide-semiconductor (NMOS) transistors of integrated circuits 200, 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600 or 1800, and the active region pattern 102b of the active region pattern group 102 can be used to manufacture the source and drain regions of p-type metal-oxide-semiconductor (PMOS) transistors of integrated circuits 200, 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600 or 1800.

[0052] In some embodiments, the active region pattern 102a of the active region pattern group 102 can be used to manufacture the source and drain regions of PMOS transistors of integrated circuits 200, 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600 or 1800, and the active region patterns 102b, 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600 or 1800 of the active region pattern group 102 can be used to manufacture the source and drain regions of NMOS transistors of integrated circuit 200.

[0053] In some embodiments, the active region pattern group 102 is located on a first layout level. In some embodiments, the first layout level corresponds to layout design 100, 300, or 500. Figures 1A to 1B , Figures 3A to 3B or Figures 5A to 5B An active layer or OD layer of one or more of the following integrated circuits: 200, 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600, or 1800. In some embodiments, the OD layer is located above the BM1 and BM0 layers.

[0054] In some embodiments, the active region pattern 102a can be used to fabricate the source and drain regions of one or more n-type finFET transistors, n-type nanosheet transistors, or n-type nanowire transistors, and the active region layout pattern 102b can be used to fabricate the source and drain regions of one or more p-type finFET transistors, p-type nanosheet transistors, or p-type nanowire transistors.

[0055] In some embodiments, the active region pattern 102a can be used to fabricate the source and drain regions of one or more p-type finFET transistors, p-type nanosheet transistors, or p-type nanowire transistors, and the active region layout pattern 102b can be used to fabricate the source and drain regions of one or more n-type finFET transistors, n-type nanosheet transistors, or n-type nanowire transistors.

[0056] Other widths for the active region pattern group 102 or other numbers of active region patterns in the active region pattern group 102 are within the scope of this invention.

[0057] Other configurations, arrangements, or the number of patterns in the active area pattern group 102 are within the scope of this invention.

[0058] The layout design 100 also includes one or more gate patterns 104a, 104b, 104c, 104d, 104e, or 104f (collectively referred to as "gate pattern group 104") extending in the second direction Y. Each of the gate patterns in the gate pattern group 104 is separated from the adjacent gate pattern of the gate pattern group 104 by a first spacing (not shown) in the first direction X.

[0059] Gate pattern group 104 can be used to manufacture integrated circuits 200, 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600 or 1800. Figures 2A to 2C , Figures 3A to 3F , Figures 5A to 5E , Figures 7A to 7C , Figures 8A to 8B , Figures 10A to 10C , Figures 12A to 12C , Figures 14A to 14C , Figures 16A to 16C or Figures 18A to 18F The corresponding gate group 204.

[0060] In some embodiments, the gate patterns 104a, 104b, 104c, 104d, 104e, and 104f of the gate pattern group 104 can be used to manufacture integrated circuits 200, 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600, or 1800. Figures 2A to 2C , Figures 3A to 3F , Figures 5A to 5E , Figures 7A to 7C , Figures 8A to 8B , Figures 10A to 10C , Figures 12A to 12C , Figures 14A to 14C , Figures 16A to 16C or Figures 18A to 18F The corresponding gates 204a, 204b, 204c, 204d, 204e, and 204f of the gate group 204.

[0061] In some embodiments, at least a portion of the gate patterns 104a, 104b, 104c, 104d, 104e, or 104f of the gate pattern group 104 can be used to manufacture the gates of NMOS transistors of integrated circuits 1000, 1200, 1400, or 1600 and integrated circuit 1800, and at least a portion of the gate patterns 104a, 104b, 104c, 104d, 104e, or 104f of the gate pattern group 104 can be used to manufacture the gates of PMOS transistors of integrated circuits 1000, 1200, 1400, or 1600 and integrated circuit 1800.

[0062] Gate pattern group 104 is located above active region pattern group 102, conductive component pattern group 106, conductive component pattern group 110, and conductive component pattern group 120. Gate pattern group 104 is located on a second layout level different from the first layout level. In some embodiments, the second layout level is different from the first layout level. In some embodiments, the second layout level corresponds to layout design 100, 300, or 500. Figures 1A to 1B , Figures 3A to 3B or Figures 5A to 5B ) or one or more of the integrated circuits 200, 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600 or 1800, at the POLY level. In some embodiments, the POLY level is located above the OD level, BM1 level and BM0 level.

[0063] Other configurations in gate pattern group 104, arrangements or the number of patterns at other layout levels are within the scope of this invention.

[0064] The layout design 100 also includes one or more conductive component patterns 106a, 106b, or 106c (collectively referred to as "conductive component pattern group 106") extending in the second direction Y and located on a third layout level. In some embodiments, the third layout level is different from the first and second layout levels.

[0065] In some embodiments, the third layout level corresponds to layout design 100, 300, or 500. Figures 1A to 1B , Figures 3A to 3B or Figures 5A to 5B The back-side metal 0 (BM0) layer of one or more of the following integrated circuits: 200, 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600, or 1800. In some embodiments, the BM0 layer is located above the BM1 layer and below the POLY and OD layers.

[0066] The conductive component pattern group 106 can be used to manufacture integrated circuit 200. Figures 2A to 2C ) or integrated circuits 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600 or 1800 ( Figures 3A to 3F , Figures 5A to 5E , Figures 7A to 7C , Figures 8A to 8B , Figures 10A to 10C , Figures 12A to 12C , Figures 14A to 14C , Figures 16A to 16C or Figures 18A to 18F The corresponding conductor group 206.

[0067] In some embodiments, conductive component patterns 106a, 106b, or 106c can be used to fabricate conductor group 206 of integrated circuit 200. Figures 2A to 2C The corresponding conductors 206a, 206b, or 206c are respectively. In some embodiments, the conductor group 206 is located on the back side 203b of the integrated circuit 200. The conductive component pattern group 106 overlaps with the gate pattern group 104 and the active region pattern group 102.

[0068] Each of the conductive component patterns 106a, 106b and 106c in the conductive component pattern group 106 is separated from each other in the first direction X.

[0069] In some embodiments, at least one conductive component pattern 106a, 106b, or 106c of the conductive component pattern group 106 has a length (not labeled) in the second direction Y that is greater than the width of the active region pattern group 102 in the second direction Y. In some embodiments, at least one conductive component pattern 106a, 106b, or 106c of the conductive component pattern group 106 has a length (not labeled) in the second direction Y that is the same as the width of the active region pattern group 102 in the second direction Y.

[0070] Other lengths or widths for conductive component pattern group 106, or other numbers of conductive component patterns in conductive component pattern group 106, are within the scope of this invention. In some embodiments, at least one of conductive component patterns 106a, 106b, or 106c has a different width than the other of conductive component patterns 106a, 106b, or 106c.

[0071] Other configurations, arrangements, or number of patterns in the conductive component pattern group 106 are within the scope of this invention.

[0072] The layout design 100 also includes at least one conductive component pattern 110a (collectively referred to as “conductive component pattern group 110”) that extends at least in the first or second direction Y and is located at the third layout level.

[0073] The conductive component pattern group 110 can be used to manufacture integrated circuit 200. Figures 2A to 2C ) or integrated circuits 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600 or 1800 ( Figures 3A to 3F , Figures 5A to 5E , Figures 7A to 7C , Figures 8A to 8B , Figures 10A to 10C , Figures 12A to 12C , Figures 14A to 14C , Figures 16A to 16C or Figures 18A to 18F The corresponding conductor group 210.

[0074] In some embodiments, the conductive component pattern 110a can be used to fabricate the conductor group 210 of the integrated circuit 200. Figures 2A to 2C The corresponding conductor 210a. In some embodiments, the conductor group 210 is located on the back side 203b of the integrated circuit 200. The conductive component pattern group 110 overlaps with the gate pattern group 104 and the active region pattern group 102.

[0075] In some embodiments, at least the width (not marked) of the conductive component pattern group 110 in the first direction X or the length in the second direction Y is greater than the length (in the second direction Y) or the width (in the first direction X) of the conductive component pattern group 106.

[0076] Other widths of the conductive component pattern group 110 or other numbers of conductive component patterns in the conductive component pattern group 110 are within the scope of this invention.

[0077] Other configurations, arrangements, or number of patterns in the conductive component pattern group 110 are within the scope of this invention.

[0078] The layout design 100 also includes one or more through-hole patterns 108a, 108b or 108c (collectively referred to as “through-hole pattern group 108”) or one or more through-hole patterns 112a or 112b (collectively referred to as “through-hole pattern group 112”).

[0079] Through-hole pattern group 108 can be used to manufacture corresponding through-hole group 208. Figures 2A to 2C In some embodiments, the through-hole patterns 108a, 108b, or 108c of the through-hole pattern group 108 can be used to manufacture the corresponding through holes 208a, 208b, or 208c of the through-hole group 208. Figures 2A to 2C ).

[0080] Through-hole pattern group 112 can be used to manufacture corresponding through-hole group 212 ( Figures 2A to 2C In some embodiments, the through-hole patterns 112a or 112b of the through-hole pattern group 112 can be used to manufacture the corresponding through-holes 212a or 212b of the through-hole group 212. Figures 2A to 2C ).

[0081] In some embodiments, the via pattern group 108 is located between the active region pattern group 102 and the conductive component pattern group 106.

[0082] In some embodiments, the via pattern group 112 is located between the active region pattern group 102 and the conductive component pattern group 110.

[0083] At least through-hole pattern group 108 or through-hole pattern group 112 is located in layout design 100, 300 or 500 ( Figures 1A to 1B , Figures 3A to 3B or Figures 5A to 5B This can be located at the via-side signal / power (VBS / P) level of one or more of the following integrated circuits: 200, 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600, or 1800. In some embodiments, the VBO level is located between the BMO level and the OD level. In some embodiments, the VBO level is located between a first layout level and a third layout level. Other layout levels are within the scope of this invention.

[0084] At least via pattern 108a or 108c is located between active region pattern 102b and corresponding conductive component pattern 106a or 106c. Via pattern 108b is located between active region pattern 102a and conductive component pattern 106b. In some embodiments, each via pattern of via pattern group 108 is located at the location of the corresponding source or drain region of an NMOS or PMOS transistor manufactured by layout design 100.

[0085] Via pattern 112a is located between active region pattern 102b and conductive component pattern 110a. Via pattern 112b is located between active region pattern 102a and conductive component pattern 110a. In some embodiments, each via pattern in via pattern group 108 is located at the location of the corresponding source or drain region of an NMOS or PMOS transistor manufactured by layout design 100.

[0086] In some embodiments, at least the via pattern 108a, 108c, or 112a overlaps with the active region pattern 102b. In some embodiments, at least the via pattern 108b or 112b overlaps with the active region pattern 102b.

[0087] In some embodiments, each through-hole pattern of through-hole pattern group 108 is separated from its adjacent through-hole patterns in the first direction X by a spacing (not marked). In some embodiments, each through-hole pattern of through-hole pattern group 112 is separated from its adjacent through-hole patterns in the first direction X by a spacing (not marked).

[0088] The number of other configurations, arrangements, or patterns at other layout levels in at least the through-hole pattern group 108 or 112 is within the scope of this invention.

[0089] The layout design 100 includes one or more conductive component layout patterns 120a or 120b (collectively referred to as "conductive component pattern group 120") extending in a first direction X and located on a fourth layout level. In some embodiments, the fourth layout level is different from the first, second, and third layout levels.

[0090] In some embodiments, the fourth layout level corresponds to layout design 100, 300, or 500. Figures 1A to 1B , Figures 3A to 3B or Figures 5A to 5B The back-side metal 1 (BM1) layer of one or more of the following integrated circuits: 200, 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600, or 1800. In some embodiments, the BM1 layer is located below the BM1 layer, the POLY layer, and the OD layer.

[0091] In some embodiments, the conductive component pattern group 120 is referred to as the "power rail pattern group 120". In some embodiments, the conductive component pattern 120a or 120b is referred to as the corresponding power rail pattern 120a or 120b.

[0092] The conductive component pattern group 120 can be used to manufacture integrated circuit 200. Figures 2A to 2C The corresponding conductive component group 220. In some embodiments, the conductive component group 220 is located on the back side 203b of the integrated circuit 200. In some embodiments, the conductive component patterns 120a, 120b of the conductive component pattern group 120 can be used to manufacture the conductive component group 220 of the integrated circuit 200. Figures 2A to 2C The corresponding conductive components 220a and 220b are as follows.

[0093] The conductive component patterns 120a and 120b of the conductive component pattern group 120 are separated from each other in the second direction Y.

[0094] In some embodiments, when viewed from the bottom / back side (e.g., in the positive Z direction) of layout design 100, the conductive component patterns 120a and 120b of conductive component pattern group 120 overlap with the corresponding active region patterns 102a and 102b of layout design 100, and are therefore referred to as “introduced power rail” designs.

[0095] In some embodiments, the centers of conductive component patterns 120a and 120b in the first direction X are aligned with the corresponding centers of corresponding active region patterns 102a and 102b in the first direction X.

[0096] At least the conductive component pattern 120a or 120b has a width BM1 in the second direction Y. PW1a In some embodiments, the width BM1 PW1a The width (not marked) of the conductive component pattern group 106 in the second direction Y is the same. In some embodiments, the width BM1 PW1a The width (not marked) of the conductive component pattern group 106 in the second direction Y is different.

[0097] Other widths for conductive component pattern group 120 or other numbers of conductive component patterns in conductive component pattern group 120 are within the scope of the invention. In some embodiments, at least conductive component pattern 120a has a different width than conductive component pattern 120b.

[0098] Other configurations, arrangements, or number of patterns in the conductive component pattern group 120 are within the scope of this invention.

[0099] The layout design 100 also includes one or more through-hole patterns 130a, 130b or 130c (collectively referred to as “through-hole pattern group 130”).

[0100] Through-hole pattern group 130 can be used to manufacture corresponding through-hole group 230 ( Figures 2A to 2C In some embodiments, the through-hole patterns 130a, 130b, or 130c of the through-hole pattern group 130 can be used to manufacture the corresponding through holes 230a, 230b, or 230c of the through-hole group 230. Figures 2A to 2C ).

[0101] At least through-hole pattern group 130 is located in layout design 100, 300 or 500 ( Figures 1A to 1B , Figures 3A to 3B or Figures 5A to 5B This can be located at the back-side metal 0 (VB0) level of a via in one or more of the following integrated circuits: 200, 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600, or 1800. In some embodiments, the VB0 level is located between the BM0 and BM1 levels. In some embodiments, the VB0 level is located between a third layout level and a fourth layout level. Other layout levels are within the scope of this invention.

[0102] In some embodiments, the via pattern group 130 is located between the conductive component pattern group 106 and the conductive component pattern group 120. In some embodiments, at least the via patterns 130a, 130b or 130c overlap with the corresponding conductive component patterns 106a, 106b or 106c.

[0103] At least via pattern 130a or 130c is located between the corresponding conductive component pattern 106a or 106c and conductive component pattern 120b. Via pattern 130b is located between conductive component pattern 106b and conductive component pattern 120a. In some embodiments, each via pattern of via pattern group 130 is located at the location of the corresponding source or drain region of an NMOS or PMOS transistor manufactured by layout design 100.

[0104] In some embodiments, each through-hole pattern of the through-hole pattern group 130 is separated from the adjacent through-hole patterns of the through-hole pattern group 130 by a spacing (not marked) in the first direction X.

[0105] At least the number of other configurations, arrangements or patterns at other layout levels in the through-hole pattern group 130 is within the scope of this invention.

[0106] Layout design 100 also includes one or more conductive component patterns 160a, 160b, 160c, 160d, or 160e (collectively, “conductive component pattern group 160”) extending in the first direction X and located on a fifth layout level. In some embodiments, the fifth layout level differs from the first, second, third, and fourth layout levels. In some embodiments, the fifth layout layer corresponds to layout design 100, 300, or 500 (…). Figures 1A to 1B , Figures 3A to 3B or Figures 5A to 5B The MO layer is a metal 0 (MO) layer of one or more of the following integrated circuits: 200, 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600, or 1800. In some embodiments, the MO layer is located above the OD layer, POLY layer, MD layer, VG layer, VD layer, BM1 layer, and BM0 layer.

[0107] The conductive component pattern group 160 can be used to manufacture the corresponding conductive structure group 260 of the integrated circuit 200. Figures 2A to 2C The conductive component patterns 160a, 160b, 160c, 160d, and 160e can be used to manufacture the corresponding conductive structures 260a, 260b, 260c, 260d, and 260e. Figures 2A to 2B , Figures 5A to 5C , Figures 7A to 7C , Figure 10A , Figure 12A , Figure 14A and Figure 16A ).

[0108] Although each of the conductive component patterns 160a, 160b, 160c, 160d, or 160e is shown as a continuous pattern, in some embodiments, one or more of the conductive component patterns 160a, 160b, 160c, 160d, or 160e are divided into one or more discontinuous patterns.

[0109] The conductive component pattern group 160 overlaps at least with the gate pattern group 104, the active region pattern group 102, the conductive component pattern group 106, the conductive component pattern group 110, or the conductive component pattern group 120. In some embodiments, the conductive component pattern group 160 overlaps with other lower-level patterns (not shown for illustration) of other layout levels of the layout design 100. For example, for illustration purposes, the layout design does not show via patterns (e.g., diffusion-over-via (VD) or gate-over-via (VG)) located between the conductive component pattern group 160 and the contact pattern group (not labeled), but VD, VG, and MD are present in... Figures 10A to 10B , Figures 12A to 12B , Figures 14A to 14B and Figures 16A to 16B As shown in the image.

[0110] At least one pattern 160a, 160b, 160c, 160d, or 160e of the conductive component pattern group 160 has a width (not marked) in the second direction Y. Other widths for the conductive component pattern group 160 are within the scope of this invention. In some embodiments, at least one conductive component pattern of the conductive component pattern group 160 has a width in the second direction Y that is different from the width of at least one other conductive component pattern of the conductive component pattern group 160.

[0111] In some embodiments, the conductive component patterns 160a, 160b, 160c, 160d, and 160e of the conductive component pattern group 160 correspond to five M0 wiring tracks in the layout design 100. Other numbers of M0 wiring tracks are within the scope of this invention.

[0112] Other configurations, arrangements, or number of patterns in the conductive component pattern group 160 are within the scope of this invention.

[0113] Figures 2A to 2C This is a diagram of an integrated circuit 200 according to some embodiments.

[0114] Figure 2A This is a top view of an integrated circuit 200 according to some embodiments. Figure 2B yes Figure 2A The diagram of the corresponding part 200B of the integrated circuit 200 is simplified for ease of explanation. Figure 2A This is a diagram of integrated circuit 200, including part 200B, which has been simplified for ease of explanation.

[0115] Figures 2B to 2C This is a corresponding cross-sectional view of an integrated circuit 200 according to some embodiments. Figure 2B This is a cross-sectional view of an integrated circuit 200 intersecting with plane A-A' according to some embodiments. Figure 2C This is a cross-sectional view of an integrated circuit 200 intersecting plane B-B' according to some embodiments. Figures 2A to 2C , Figures 3A to 3E , Figures 4A to 4B , Figures 5A to 5E , Figures 6A to 6B , Figures 7A to 7C , Figures 8A to 8B , Figure 9 , Figures 10A to 10C , Figure 11 , Figures 12A to 12C , Figure 13 , Figures 14A to 14C , Figure 15 , Figures 16A to 16C and Figures 18A to 18FThose identical or similar components in one or more of (shown below) are given the same reference numerals, and therefore their detailed descriptions are omitted.

[0116] Integrated circuit 200 is manufactured through layout design 100. The structural relationships of integrated circuit 200, including alignment, length and width, as well as configuration and layers, are similar to those of integrated circuit 200. Figures 1A to 1B The layout design includes the structural relationships, configurations, and layers of 100, and for simplicity, at least in Figures 2A to 2C The lieutenant general will not provide a similar detailed description. For example, in some embodiments, the layout design 100 has a minimum width BM1. PW1a Or the cell height CH1a is similar to the corresponding width BM1 of integrated circuit 200. PW1b Or cell height CH1b, and for brevity, similar detailed descriptions are omitted. For example, in some embodiments, at least one or more widths, lengths, or spacings of layout design 100 are similar to the corresponding widths, lengths, or spacings of integrated circuit 200, and for brevity, similar detailed descriptions are omitted. For example, in some embodiments, at least cell boundaries 101a or 101b or midpoint 101c of layout design 100 are similar to at least corresponding cell boundaries 201a or 201b or midpoint 201c of integrated circuit 200, and for brevity, similar detailed descriptions are omitted.

[0117] The integrated circuit 200 includes at least an active region group 202, a gate group 204, an insulating region 205, a conductor group 206, a conductor group 210, a via group 208, a via group 212, a conductor group 220 (also referred to as a power rail group 220), a via group 230, and a conductor group 260.

[0118] The active region group 202 includes one or more active regions 202a or 202b embedded in the substrate 290.

[0119] The substrate has a front side 203a and a back side 203b opposite to the front side 203a. In some embodiments, at least an active region group 202, a gate group 204, or a conductor group 260 are formed in the front side 203a of the substrate 290.

[0120] In some embodiments, the active region group 202 corresponds to the nanosheet structure (not labeled) of a nanosheet transistor. In some embodiments, the active region group 202 includes a drain region and a source region grown by an epitaxial growth process. In some embodiments, the active region group 202 includes drain regions and source regions grown with epitaxial material at corresponding drain regions and source regions.

[0121] Other transistor types are within the scope of this invention. For example, in some embodiments, the active region group 202 corresponds to the nanowire structure (not shown) of a nanowire transistor. In some embodiments, the active region group 202 corresponds to the planar structure (not shown) of a planar transistor. In some embodiments, the active region group 202 corresponds to the fin structure (not shown) of a finFET.

[0122] In some embodiments, active region 202a corresponds to the source and drain regions of the NMOS transistor of integrated circuit 200, 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600 or 1800, and active region 202b corresponds to the source and drain regions of the PMOS transistor of integrated circuit 200, 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600 or 1800.

[0123] In some embodiments, active region 202a corresponds to the source and drain regions of the PMOS transistor of integrated circuit 200, 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600 or 1800, and active region 202b corresponds to the source and drain regions of the NMOS transistor of integrated circuit 200, 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600 or 1800.

[0124] In some embodiments, at least the active region 202a is an N-type doped S / D region, and the active region 202b is a P-type doped S / D region embedded in the dielectric material of the substrate 290. In some embodiments, at least the active region 202a is a P-type doped S / D region, and the active region 202b is an N-type doped S / D region embedded in the dielectric material of the substrate 290.

[0125] The number of other configurations, arrangements or structures at other layout levels in the active region group 202 is within the scope of this invention.

[0126] Gate group 204 includes one or more of gates 204a, 204b, 204c, 204d, 204e, or 204f. In some embodiments, at least a portion of gates 204a, 204b, 204c, 204d, 204e, or 204f is the gate of an NMOS transistor of integrated circuit 1000, 1200, 1400, or 1600 and integrated circuit 1800, and at least a portion of gates 204a, 204b, 204c, 204d, 204e, or 204f is the gate of a PMOS transistor of integrated circuit 1000, 1200, 1400, or 1600 and integrated circuit 1800.

[0127] In some embodiments, at least gate 204a or 204b corresponds to a dummy gate. In some embodiments, the dummy gate is the gate of a non-functional transistor. In some embodiments, at least gate 204a or 204b corresponds to a continuous polycrystalline (CPODE) region on the OD edge or a polycrystalline (PODE) region on the OD edge.

[0128] Other configurations in gate group 204, arrangements at other layout levels, or the number of gates are within the scope of this invention.

[0129] Insulating region 205 is configured to electrically isolate one or more elements from active region group 202, gate group 204, conductor group 206, conductor group 210, via group 208, via group 212, conductor group 220, via group 230, or conductor group 260. In some embodiments, insulating region 205 includes elements from methods 1700A to 1700B. Figures 17A to 17B Multiple insulating regions are deposited at different times during the process. In some embodiments, the insulating regions are dielectric materials. In some embodiments, the dielectric materials include silicon dioxide, silicon oxynitride, etc.

[0130] Other configurations, arrangements at other layout levels, or other quantities of portions in the insulating region 205 are within the scope of this invention.

[0131] Conductor group 206 includes one or more of conductors 206a, 206b, or 206c. Conductor group 206 is located on the back side 203b of integrated circuit 200.

[0132] In some embodiments, when viewed from the top / front side 203a of the integrated circuit 200 (e.g., in the positive Z direction), the conductor group 206 overlaps with the gate group 204 and the active region group 202. In some embodiments, when viewed from the bottom / back side 203b of the integrated circuit 200 (e.g., in the positive Z direction), conductors 206a and 206c overlap with the active region 202b, and conductor 206b overlaps with the active region 202a.

[0133] Other lengths or widths of conductor group 206 are within the scope of this invention. Other configurations, arrangements at other layout levels, or the number of conductors in conductor group 206 are within the scope of this invention.

[0134] The via group 208 includes one or more of vias 208a, 208b, or 208c. In some embodiments, the via group 208 is located between the active region group 202 and the conductor group 206. The via group 208 is embedded in the insulating region 205. The via group 208 is located at the overlap between the active region group 202 and the conductor group 206.

[0135] At least via 208a or 208c is configured to electrically couple the active region 202b and the corresponding conductor 206a or 206c together. Via 208b is configured to electrically couple the active region 202a and the conductive component pattern 206b together.

[0136] In some embodiments, via group 208 is configured to electrically couple the corresponding source or drain region of active region group 202 to conductor group 206.

[0137] Other configurations, arrangements at other layout levels, or the number of through holes in the through hole group 208 are within the scope of this invention.

[0138] Conductor group 210 includes conductor 210a. Conductor group 210 is embedded in insulating region 205. Other numbers of structures in conductor group 210 are within the scope of this invention.

[0139] Conductor group 210 is configured to provide signal routing between lower layers. For example, in some embodiments, conductor group 210 is configured to provide signal routing between active regions of active region group 202.

[0140] In some embodiments, conductor 210a is configured to electrically couple the drain or source of a PMOS or NMOS transistor to the drain or source of another PMOS or NMOS transistor.

[0141] In some embodiments, conductor group 210 and via group 212 are configured to electrically couple active region group 210 of integrated circuit 200, generating additional wiring resources compared to other methods. In some embodiments, conductor group 210 is configured to electrically couple gate group 204 of integrated circuit 200, generating additional wiring resources compared to other methods. In some embodiments, conductor group 210 is configured to electrically couple active region group 210 and gate group 204 to each other, generating additional wiring resources compared to other methods.

[0142] In some embodiments, conductor group 210 corresponds to conductive structure group. In some embodiments, when viewed from the top / front side 203a of integrated circuit 200 (e.g., in the positive Z direction), conductor group 210 overlaps with gate group 204 and active region group 202. In some embodiments, when viewed from the bottom / back side 203b of integrated circuit 200 (e.g., in the positive Z direction), conductor group 210 overlaps with at least one gate of active region group 202 and gate group 204. Conductor group 210 is located between gate pairs of gate group 204.

[0143] In some embodiments, the bottom surface of conductor 210a is located above the top surface of conductor group 230. In some embodiments, the top surface of conductor 210a is located below the bottom surface of at least the back side 203b of active region group 210 or substrate 290.

[0144] Other configurations, arrangements at other layout levels, or the number of conductors in conductor group 210 are within the scope of this invention.

[0145] The via group 212 includes one or more of vias 212a or 212b. The via group 212 is embedded in the insulating region 205. In some embodiments, the via group 212 is located between the active region group 202 and the conductor group 210. In some embodiments, the via group 212 is configured to electrically couple a corresponding source or drain region of the active region group 202 to the conductor group 210. The via group 212 is located at the overlap between the active region group 202 and the conductor group 210.

[0146] Through-hole 212a is configured to electrically couple active region 202b and conductor 210a. Through-hole 212b is configured to electrically couple active region 202a and conductor 210a.

[0147] In some embodiments, the active region 202b (e.g., the drain / source of an NMOS / PMOS transistor) is electrically coupled to the conductor 210a through a via 212a, and the conductor 210a is electrically coupled to the active region 202a (e.g., the drain / source of a PMOS / NMOS transistor) through a via 212b.

[0148] Other lengths or widths for conductor group 212 are within the scope of this invention. Other configurations in via group 212, arrangements at other layout levels, or the number of vias are within the scope of this invention.

[0149] The conductor group 220 (also referred to as "power rail 220") includes one or more conductors (also referred to as "power rails") 220a or 220b. At least conductor 220a or 220b has a width BM1 in the second direction Y. PW1b In some embodiments, conductor group 220 corresponds to conductive structure group. Conductor group 220 is embedded in insulating region 205.

[0150] In some embodiments, when viewed from the bottom / back side of the integrated circuit 200 (e.g., in the positive Z direction), conductors 220a and 220b overlap with corresponding active regions 202a and 202b, and are therefore referred to as “introduced power rails”.

[0151] In some embodiments, conductor group 220 is configured to supply power from the back side 203b of integrated circuit 200 to active region group 202. In some embodiments, conductor group 220 is configured to supply a first supply voltage of voltage source VDD or a second supply voltage of reference voltage source VSS to an integrated circuit such as integrated circuit 200. In some embodiments, the first supply voltage is different from the second supply voltage.

[0152] In some embodiments, at least conductor 220b is configured to provide a second supply voltage of reference voltage source VSS to the corresponding active region 202b, and conductor 220a is configured to provide a first supply voltage of voltage source VDD to the active region 202a.

[0153] In some embodiments, at least conductor 220b is configured to provide a first supply voltage of voltage source VDD to the corresponding active region 202b, and conductor 220a is configured to provide a second supply voltage of reference voltage source VSS to the active region 202a.

[0154] Conductor group 220 is configured to supply power from the back side 203b of integrated circuit 200 to one or more devices formed on the front side 203a of integrated circuit 200. In some embodiments, conductor group 220 is electrically coupled to active region group 202 of integrated circuit 200, thereby supplying power from the back side 203b of integrated circuit 200 to active region group 202, thereby freeing up resources on the front side 203a of integrated circuit 200 and resulting in greater wiring flexibility and additional wiring resources compared to other methods.

[0155] In some embodiments, conductor 220b is electrically coupled to conductors 206a and 206c through corresponding vias 230a and 230c, and conductors 206a and 206c are further electrically coupled to active region 202b through corresponding vias 208a and 208c, thereby providing a first supply voltage of voltage source VDD or a second supply voltage of reference voltage source VSS to the source or drain of the corresponding active region 202b.

[0156] In some embodiments, conductor 220a is electrically coupled to conductor 206b through via 230b, and conductor 206b is further electrically coupled to active region 202a through via 208b, thereby providing a first supply voltage of voltage source VDD or a second supply voltage of reference voltage source VSS to the source or drain of the corresponding active region 202a.

[0157] Other configurations, arrangements at other layout levels, or the number of conductors in conductor group 220 are within the scope of this invention.

[0158] The via group 230 includes one or more of vias 230a, 230b, or 230c. In some embodiments, the via group 230 is located between conductor group 206 and conductor group 220. The via group 230 is located at the overlap between conductor group 206 and conductor group 220.

[0159] In some embodiments, via group 230 is configured to electrically couple conductor group 206 and conductor group 220 together.

[0160] In some embodiments, at least one via of via group 230 is configured to electrically couple a corresponding conductor of conductor group 206 to a corresponding conductor of conductor group 220.

[0161] Through-hole 230a or 230c is configured to electrically couple conductor 220b and corresponding conductor 206a or 206c together. Through-hole 230b is configured to electrically couple conductor 220a and conductor 206b together.

[0162] In some embodiments, one or more of the through holes in the through hole group 208, 212, or 230 have a square shape, a rectangular shape, a circular shape, or a polygonal shape. Other lengths, widths, and shapes for one or more of the through holes in the through hole group 208, 212, or 230 are within the scope of this invention.

[0163] Other configurations, arrangements at other layout levels, or the number of through holes in the through hole group 230 are within the scope of this invention.

[0164] The conductive component group 260 includes one or more of conductive components 260a, 260b, 260c, 260d, or 260e. The conductive component group 260 overlaps with at least one gate of the gate group 204 or at least one active region of the active region group 202.

[0165] In some embodiments, the conductive component group 260 overlaps with other lower components (not shown for ease of illustration) of other layout levels of integrated circuits 200, 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600, or 1800. For example, for ease of illustration, integrated circuit 200 does not show a via (e.g., VD or VG) located between the conductive component group 260 and at least the gate group 204 or contact group (not shown).

[0166] Other configurations, arrangements at other layout levels, or the number of conductive components in the conductive component group 260 are within the scope of this invention.

[0167] In some embodiments, at least one gate region of the gate group 204 is formed using doped or undoped polysilicon (or polysilicon). In some embodiments, at least one gate region of the gate group 204 comprises a metal, such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof.

[0168] In some embodiments, at least one conductor of conductor group 206, at least one conductor of conductor group 210, at least one conductor of conductor group 220, at least one through-hole of through-hole group 208, at least one through-hole of through-hole group 212, at least one through-hole of through-hole group 230, or at least one conductor of conductor group 260 comprises one or more layers of conductive material, metal, metal compound, or doped semiconductor. In some embodiments, the conductive material comprises tungsten, cobalt, ruthenium, copper, or combinations thereof. In some embodiments, the metal comprises at least Cu (copper), Co, W, Ru, Al, etc. In some embodiments, the metal compound comprises at least AlCu, W-TiN, TiSi. x NiSi x TiN, TaN, etc. In some embodiments, the doped semiconductor includes at least doped silicon, etc.

[0169] In some embodiments, conductor groups 206, 210, 230 and via groups 208, 212 and 230 are located on the back side 203b of the substrate 290 of the integrated circuit 200.

[0170] In some embodiments, the active region group 202, the gate group 204, and the conductor group 260 are located on the front side 203a of the substrate 290 of the integrated circuit 200, 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600, or 1800. The front side 203a of the integrated circuit 200 is opposite to the back side 203b of the integrated circuit 200, 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600, or 1800 in the second direction Y. In some embodiments, by placing conductor groups 206, conductor groups 210, conductor groups 230 and via groups 208, 212 and 230 on the back side 203b of integrated circuits 200, 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600 or 1800, integrated circuits 200, 300A-300F, 500, 700, 800, 1000, 1200, 1400, 1600 or 1800 occupy less area than other methods.

[0171] Figures 3A to 3F This is a top view of the corresponding integrated circuit 300-300F according to some embodiments.

[0172] Figure 3C This is a top view of the amplification section 300C of the conductor group 310 of the integrated circuit 300A according to some embodiments.

[0173] Figure 3D This is a top view of the amplification section 300D of the conductor group 312 of the integrated circuit 300A according to some embodiments.

[0174] Figure 3E This is a top view of the amplification section 300E of the conductor group 314 of the integrated circuit 300A according to some embodiments.

[0175] Figure 3F This is a top view of the amplification section 300F of the conductor group 316 of the integrated circuit 300B according to some embodiments.

[0176] Integrated circuit 300A includes a cell array 302a arranged in 5 rows and at least 3 columns. Other numbers of rows and columns are within the scope of this invention. In some embodiments, each cell of cell array 302a corresponds to a cell manufactured by layout design 100. In some embodiments, cell array 302a and cell array 302b ( Figure 3B Each unit corresponds to a portion of integrated circuit 200, simplified for ease of explanation. For example, for clarity, the VB0, VBS / P, OD, POLY, and M0 layers are not shown. Figures 3A to 3E As shown in the image.

[0177] Integrated circuits 300A-300B also include conductor group 320. In some embodiments, conductor group 320 in integrated circuits 300A-300B is similar to conductor group 220 in integrated circuit 200; for brevity, a similar detailed description is omitted.

[0178] Conductor group 320 includes one or more of conductors 320a, 320b, ..., 320i or 320j. Conductor group 320 overlaps with cell array 302a and is a power rail. Conductor pairs 320 of conductor group 320 overlap with each row of cell array 302a and are configured to provide power to the corresponding overlapping rows. For example, in some embodiments, conductors 320a and 320b overlap with row 1 of cell array 302a and provide power (VDD / VSS) to the cells in row 1, but not to the cells in rows 2-5. Similarly, in some embodiments, conductors 320c and 320d overlap with row 2 of cell array 302a and provide power (VDD / VSS) to the cells in row 2, but not to the cells in rows 1 and rows 3-5.

[0179] Integrated circuit 300A also includes region 302, region 304 and region 306.

[0180] Region 302 includes conductors 310a and 310b (collectively referred to as “conductor group 310”) and other conductors (unlabeled, but identified by the keyword as part of BMO_b). Conductors 310a and 310b are adjacent to each other. In some embodiments, adjacent elements are elements that are directly close to each other. Conductors 310a and 310b are separated from each other in the second direction Y from one cell to another.

[0181] Conductors 310a and 310b have a length L1 in the second direction Y. Conductors 310a and 310b have a width W1 in the first direction X. Conductors 310a and 310b are separated from each other by a distance BM0 in the second direction Y. ES1 .

[0182] Region 304 includes conductors 312a and 312b (collectively referred to as “conductor group 312”) and other conductors (not labeled, but shown as part of BM0_b). Conductors 312a and 312b are adjacent to each other. Conductors 312a and 312b are separated from each other in the second direction Y from one cell to another.

[0183] Conductors 312a and 312b have a length L1 in the second direction Y. Conductor 312a has a width W1 in the first direction X. Conductor 312b has a width W2 in the first direction X. Conductors 312a and 312b are separated from each other by a distance BM0 in the second direction Y. ES1 .

[0184] Region 306 includes conductors 314a and 314b (collectively referred to as “conductor group 314”) and other conductors (not labeled, but shown as part of BM0_b). Conductors 314a and 314b are adjacent to each other. Conductors 314a and 314b are separated from each other in the second direction Y from one cell to another.

[0185] Conductors 314a and 314b have a length L1 in the second direction Y. Conductors 314a and 314b have a width W2 in the first direction X. Conductors 310a and 310b are separated from each other by a distance BM0 in the second direction Y. ES1 .

[0186] In some embodiments, each conductor of conductor group 310, 312, or 314 is similar to conductor group 210 of integrated circuit 200, and similar detailed descriptions are omitted. In some embodiments, each conductor of conductor group 310, 312, or 314 is configured to carry a signal for one or more transistors.

[0187] In some embodiments, the BMO_b conductor is similar to conductor group 206 of integrated circuit 200, and similar detailed descriptions are omitted. In some embodiments, conductor group 320 is electrically coupled to the BMO_b conductor and configured to supply power to the BMO_b conductor. Other configurations in the BMO_b conductor, arrangements at other layout levels, or the number of conductors are within the scope of this invention.

[0188] In some embodiments, conductors 310a, 310b, and 312a have the same shape.

[0189] In some embodiments, conductors 312a and 312b have different shapes. For example, conductor 312b has a reduced width in the first direction X compared to conductor 312a.

[0190] In some embodiments, at least two of conductors 312b and 314a have the same shape. In some embodiments, at least conductors 312b, 314a and 314b are similar, and similar detailed descriptions are omitted.

[0191] Other configurations in conductor groups 302, 304, 306, or 320, arrangements at other layout levels, or the number of conductors are within the scope of this invention.

[0192] Figure 3B This is a top view of an integrated circuit 300B according to some embodiments.

[0193] Integrated circuit 300B includes a cell array 302b, a conductor group 320, and a region 308. The cell array 302b is arranged in 5 rows and at least 2 columns. Other numbers of rows and columns are within the scope of this invention. In some embodiments, Figure 3B The cell array 302b in the middle is similar to Figure 3A The cell array 302a, and for the sake of brevity, similar detailed descriptions are omitted.

[0194] Region 308 includes conductors 316a and 316b (collectively referred to as “conductor group 316”) and other conductors (unlabeled, but identified by the keyword as part of BMO_b). Conductors 316a and 316b are adjacent to each other. Conductors 316a and 316b are separated from each other from one cell to another in a first direction X. In some embodiments, each conductor of conductor group 316 is similar to conductor groups 210, 310, 312, or 314, and similar detailed descriptions are omitted.

[0195] In some embodiments, at least conductor 316a or 316b is similar to at least conductor 312b, 314a or 314b, and similar detailed descriptions are omitted. In some embodiments, conductors 316a and 316b have the same shape as each other. In some embodiments, at least conductor 316a or 316b has the same shape as at least conductor 312b, 314a or 314b.

[0196] Conductors 316a and 316b have a length L1 in the second direction Y. Conductors 316a and 316b have a width W2 in the first direction X. Conductors 310a and 310b are separated from each other by a distance BM0 in the first direction X. S1 .

[0197] Other configurations of the BM0_b conductor, arrangements at other layout levels, or the number of conductors are within the scope of this invention.

[0198] Other configurations in conductor group 316, arrangements at other layout levels, or the number of conductors are within the scope of this invention.

[0199] Figures 4A to 4B This is a diagram of an integrated circuit layout design 400 according to some embodiments. Layout design 400 is... Figures 5A to 5E The layout diagram of the integrated circuit 500.

[0200] Figure 4A yes Figure 4B The layout design of part 400A is simplified for ease of explanation. Part 400A is... Figure 1A This is a variant of part 100A, and therefore a similar detailed description is omitted.

[0201] Figure 4B This is a diagram of layout design 400 and includes portion 400A, simplified for ease of explanation. In some embodiments, layout design 400 includes... Figures 4A to 4B Additional components not shown. Layout design 400 includes sections 400A and M0 levels.

[0202] Layout design 400 can be used for manufacturing Figures 5A to 5E The integrated circuit 500.

[0203] Layout design 400 is layout design 100 ( Figures 1A to 1B Variations of ). For example, layout design 400 shows an example of conductive component pattern group 420 for additional wiring resources to electrically couple at least active region pairs manufactured by active region pattern group 102.

[0204] and Figures 1A to 1BCompared to layout design 100, layout design 400 replaces conductive component pattern group 120 with conductive component pattern group 420, and therefore similar detailed descriptions are omitted.

[0205] The layout design 400 includes an active region pattern group 102, a gate pattern group 104, a conductive component pattern group 106, a via pattern group 108, a conductive component pattern group 110, a via pattern group 112, a conductive component pattern group 420, and a via pattern group 130.

[0206] The conductive component pattern group 420 includes one or more conductive component patterns 420a, 420b or 420c.

[0207] and Figures 1A to 1B Compared to layout design 100, the conductive component patterns 420a and 420b of layout design 400 replace the corresponding conductive component patterns 120a and 120b, and therefore a similar detailed description is omitted. Figures 1A to 1B Compared to layout design 100, the conductive component pattern 420c of layout design 400 is similar to conductive component patterns 120a and 120b, and therefore a similar detailed description is omitted.

[0208] Conductive component pattern group 420 can be used to manufacture integrated circuit 500 ( Figures 5A to 5E The corresponding conductor group 520. In some embodiments, the conductor group 520 is located on the back side 203b of the integrated circuit 500. In some embodiments, the conductive component patterns 420a, 420b, 420c of the conductive component pattern group 420 can be used to manufacture the corresponding conductors 520a, 520b, 520c of the conductive component group 520 of the integrated circuit 500. Figures 5A to 5E ).

[0209] The conductive component pattern 420c extends in the first direction X and is located between conductive component patterns 420a and 420b. In some embodiments, the conductive component pattern 420c is also referred to as "signal line pattern 420c". For example, in some embodiments, the conductive component pattern 420c can be used to fabricate conductor 520c, and conductor 520c can be used to route one or more signals for the NMOS or PMOS transistors of the active region group 202.

[0210] Each of the conductive component patterns 420a, 420b and 420c in the conductive component pattern group 420 is separated from each other in the second direction Y.

[0211] In some embodiments, when viewed from the bottom / back side (e.g., in the positive Z direction) of the layout design 400, the conductive component patterns 420a and 420b overlap with the corresponding cell boundaries 101a and 101b of the layout design 400, and the conductive component pattern 420c overlaps with the midpoint 101c of the layout design 400.

[0212] The conductive component patterns 420a and 420b have a zigzag shape or are oriented in an alternating manner relative to each other. For example, conductive component pattern 420a includes conductive component patterns 420a1 and 420a2 coupled together, and conductive component pattern 420a includes conductive component patterns 420b1, 420b2 and 420b3 coupled together.

[0213] Conductive component pattern 420a2 is coupled to and corresponds to the extended region of conductive component pattern 420a1, and conductive component patterns 420b2 and 420b3 are coupled to and correspond to the extended region of conductive component pattern 420b1.

[0214] The conductive component pattern 420a2 is offset or interleaved from the conductive component pattern 420b2 or 420b3 at least in the first direction X, and vice versa.

[0215] In some embodiments, when viewed from the bottom / back side (e.g., in the positive Z direction) of the layout design 400, by making conductive component pattern 420a2 an extension of conductive component pattern 420a, and conductive component patterns 420b2 and 420b3 corresponding extensions of conductive component pattern 420b, more overlap is generated with the conductive component patterns 420a2, 420b2, and 420b3 of the underlying patterns (e.g., conductive component pattern groups 108 and 110), thereby increasing the number of via landing points for via pattern group 130.

[0216] In some embodiments, the centers of conductive component patterns 420a1 and 420b1 in the first direction X are aligned with the corresponding unit boundaries 101a and 101b in the first direction X. In some embodiments, the center of conductive component pattern 420c in the first direction X is aligned with the midpoint 101c in the first direction X.

[0217] At least the conductive component pattern 420a1 or 420b1 has a width BM1 in the second direction Y. PW2a At least the conductive component patterns 420a2, 420b2, or 420b3 have a width W1a in the second direction Y. In some embodiments, the width BM1 PW2a It differs from the width W1a.

[0218] At least the conductive component pattern 420c has a width BM1 in the second direction Y. W1a Each conductive component pattern in the conductive component pattern group 106 has a similar shape in the second direction Y. Figures 3C to 3F Length L1 and width BM0 HW1a Each through-hole pattern in the through-hole pattern group 130 has a width BV0 in the second direction Y. W1a .

[0219] Each conductive component pattern in the conductive component pattern group 106 is separated from each other by a distance BM0 in the second direction Y. ES1a Each conductive component pattern 420a1 or 420b1 is separated from the conductive component pattern 420c by a distance BM1 in the second direction Y. S1a .

[0220] The layout design 400 has a cell height CH2a in the second direction. In some embodiments, the cell height CH2a is different from the cell height CH1a. In some embodiments, the cell height CH2a is the same as the cell height CH1a.

[0221] In some embodiments, layout design 400 does not satisfy the first design rule set based on Formula 2 (shown below). For example, in some embodiments, when layout design 400 does not satisfy the first design rule set, an interleaved power delivery layout similar to conductive component pattern set 420 is used. In some embodiments, the first design rule set relates to the cell height CH2a of layout design 400.

[0222] In some embodiments, the cell height CH2a of the layout design 400 is determined according to Formula 1 and expressed as:

[0223] CH2a=BM1 PW2a +2*BM1 S1a +BM1 W1a =2*BM0 HW1a +2*BM0 ES1a (1)

[0224] Among them, BM1 PW2a It is at least the width of the conductive component pattern 420a1 or 420b1, BM1 S1a BM1 is the distance or interval between the conductive component pattern 420c and at least the conductive component pattern 420a1 or 420b1 in the second direction Y. W1a It is the width of the conductive component pattern 420c in the second direction Y, BM0 HW1a It is the width of each conductive component pattern in the conductive component pattern group 106 in the second direction Y, and BMO ES1aIt is the distance between each conductive component pattern in the conductive component pattern group 106 and each other in the second direction Y.

[0225] In some embodiments, the first design rule group includes the width BV0 of each via pattern in the via pattern group 130 of the layout design 400. W1a Does it satisfy Formula 2?

[0226] For example, Formula 2 is expressed as:

[0227] BV0 W1a <0.5*BM1 PW2a –0.5*BM0 ES1a (2)

[0228] In some embodiments, when the width BV0 of each through-hole pattern in the through-hole pattern group 130 of the layout design 400 is... W1a When the width is less than Formula 2, an interleaved power delivery network layout is used to the conductive component pattern group 420. In some embodiments, when the width BV0 of each via pattern in the via pattern group 130 of the layout design 400 is... W1a When the value is greater than or equal to Formula 2, the interleaved power supply network layout to the conductive component pattern group 420 is not used. In some embodiments, if the interleaved power supply network layout to the conductive component pattern group 420 is not used, a layout similar to the conductive component pattern group 620 is used. Figures 6A to 6B The power supply network layout.

[0229] Other widths for conductive component pattern group 420 or other numbers of conductive component patterns in conductive component pattern group 420 are within the scope of the invention. In some embodiments, at least conductive component pattern 420a has a different width than conductive component pattern 420b.

[0230] Other configurations, arrangements, or number of patterns in the conductive component pattern group 420 are within the scope of this invention.

[0231] In some embodiments, the signal line patterns and power rails of at least the conductive component pattern group 103 are moved from the front side of the layout design 400 or 600 to the back side of the layout design 400 or 600, resulting in a layout design 400 or 600 that uses at least one fewer upper metal layer rail in the conductive component pattern group 160, resulting in a layout design with smaller height, smaller area, greater wiring flexibility and additional wiring resources compared to other methods.

[0232] Figures 5A to 5E This is a diagram of an integrated circuit 500 according to some embodiments.

[0233] Figure 5AThis is a top view of an integrated circuit 500 according to some embodiments. Figure 5B yes Figure 5A A top view of the corresponding portion 500B of the integrated circuit 500, simplified for ease of explanation. Figure 5B This is a diagram of integrated circuit 500, including part 500B, simplified for ease of explanation. Integrated circuit 500 includes part 500B and the M0 level.

[0234] Figure 5C This is a corresponding cross-sectional view of an integrated circuit 500 according to some embodiments. Figure 5C This is a cross-sectional view of an integrated circuit 500 intersecting with plane C-C' according to some embodiments. Figure 5D This is a cross-sectional view of an integrated circuit 500 intersecting with plane D-D' according to some embodiments.

[0235] Integrated circuit 500 is manufactured through layout design 400. The structural relationships of integrated circuit 500, including alignment, length and width, as well as configuration and layers, are similar to those of integrated circuit 500. Figures 4A to 4B The layout design includes the structural relationships, configuration, and layers of 400, and for simplicity, at least in... Figures 5A to 5E The lieutenant general did not provide a similar detailed description.

[0236] Integrated Circuit 500 is Integrated Circuit 200 ( Figures 2A to 2C Variations of ). For example, integrated circuit 500 shows an example of conductor group 520 for additional wiring resources to electrically couple at least active region pairs manufactured by active region group 202.

[0237] and Figures 2A to 2C Compared to integrated circuit 200, the conductor group 520 of integrated circuit 500 replaces the conductor group 220, and therefore a similar detailed description is omitted.

[0238] The integrated circuit 500 includes at least an active region group 202, a gate group 204, an insulating region 205, a conductor group 206, a conductor group 210, a via group 208, a via group 212, a conductor group 520 (also referred to as a power rail group 520), a via group 230, and a conductor group 260.

[0239] The conductor group 520 includes at least conductors 520a, 520b, or 520c. In some embodiments, the conductor group 520 is located on the back side 203b of the integrated circuit 500.

[0240] Conductor 520c extends in a first direction X and is located between conductors 520a and 520b. In some embodiments, conductor 520c is also referred to as "signal line 520c". For example, in some embodiments, conductor 520c can be used to route one or more signals for the NMOS or PMOS transistors of the active region group 202. In some embodiments, by including conductor 520c between conductors 520a and 520b, conductors 520a and 520b are positioned away from each other in a second direction Y when compared to conductors 220a and 220b to accommodate conductor 520c. Therefore, in some embodiments, when viewed from the bottom / back side of integrated circuit 500 (e.g., in the positive Z direction), conductors 520a and 520b overlap with corresponding cell boundaries 201a and 201b of integrated circuit 500, and conductor 520c overlaps with the midpoint 201c of integrated circuit 500.

[0241] In some embodiments, the centers of conductors 520a1 and 520b1 in the first direction X are aligned with the corresponding unit boundaries 201a and 201b in the first direction X. In some embodiments, the center of conductor 520c in the first direction X is aligned with the midpoint 201c in the first direction X.

[0242] Conductors 520a and 520b have a serrated shape or are oriented in an alternating manner relative to each other. For example, conductor 520a includes conductors 520a1 and 520a2 coupled together, and conductor 520a includes conductors 520b1, 520b2 and 520b3 coupled together. Conductor 520a2 is offset or interleaved from or at least interleaved with conductors 520b2 or 520b3 in a first direction X, and vice versa.

[0243] Conductor 520a2 is coupled to and corresponds to the extended region of conductor 520a1, and conductors 520b2 and 520b3 are coupled to and correspond to the extended region of conductor 520b1.

[0244] In some embodiments, when viewed from the bottom / back side (e.g., in the positive Z direction) of the integrated circuit 500, by making conductor 520a2 an extension of conductor 520a, and conductors 520b2 and 520b3 corresponding extensions of conductor 520b, more overlap is created with conductors 520a2, 520b2, and 520b3 of the underlying structure (e.g., conductor groups 208 and 210), thereby increasing the via landing points for via group 230, even with... Figures 2A to 2C Compared to conductors 220a and 220b, conductors 520a and 520b are already far apart from each other.

[0245] At least conductor 520a1 or 520b1 has a width BM1 in the second direction Y.PW2b At least conductors 520a2, 520b2, or 520b3 have a width W1b in the second direction Y. In some embodiments, the width BM1 PW2b Unlike the width W1b, at least conductors 520a2, 520b2, or 520b3 have a length L2a in the first direction X.

[0246] At least conductor 520c has a width BM1 in the second direction Y. W1b Each conductor in conductor group 206 has a corresponding [specific feature] in the second direction Y. Figures 3C to 3F Length L1 and width BM0 HW1b Each through-hole in the through-hole group 230 has a width BV0 in the second direction Y. W1b .

[0247] Each conductor of conductor group 206 is separated from each other by a distance BM0 in the second direction Y. ES1b Each conductor 520a1 or 520b1 is separated from conductor 520c by a distance BM1 in the second direction Y. S1b .

[0248] The integrated circuit 500 has a cell height CH2a in the second direction.

[0249] In some embodiments, integrated circuit 500 does not satisfy the second design rule set based on Formula 4 (shown below). For example, in some embodiments, when integrated circuit 500 does not satisfy the second design rule set, an interleaved power delivery network similar to conductor group 520 is used. In some embodiments, the second design rule set relates to the cell height CH2b of integrated circuit 500.

[0250] In some embodiments, the cell height CH2b of the integrated circuit 500 is determined according to Formula 3 and is expressed as:

[0251] CH2b=BM1 PW2b +2*BM1 S1b +BM1 W1b =2*BM0 HW1b +2*BM0 ES1b (3)

[0252] Among them BM1 PW2b It is at least the width of conductor 520a1 or 520b1, BM1 S1b BM1 is the distance or spacing between conductor 520c and at least conductor 520a1 or 520b1 in the second direction Y. W1b It is the width of conductor 520c in the second direction Y, BM0 HW1b It is the width of each conductor in conductor group 206 in the second direction Y, and BM0 ES1bIt is the distance between each conductor of conductor group 206 in the second direction Y.

[0253] In some embodiments, the second design rule set includes the width BV0 of each via of the via group 230 of the integrated circuit 500. W1b Does it satisfy Formula 4?

[0254] For example, Formula 4 is expressed as:

[0255] BV0 W1b <0.5*BM1 PW2b –0.5*BM0 ES1b (4)

[0256] In some embodiments, when the width BV0 of each via of the via group 230 of the integrated circuit 500 is... W1b When the width is less than that of Formula 4, an interleaved power delivery network similar to conductor group 520 is used. In some embodiments, when the width BV0 of each via of via group 230 of integrated circuit 500 is... W1b When the value is greater than or equal to Formula 4, the interleaved power supply network to conductor group 520 is not used. In some embodiments, if the interleaved power supply network to conductor group 520 is not used, a network similar to conductor group 720 is used. Figures 7A to 7C ) power supply network.

[0257] Other widths or lengths for conductor group 520 or other numbers of conductors in conductor group 520 are within the scope of this invention. In some embodiments, at least conductor 520a has a different width than conductor 520b.

[0258] Other configurations in conductor group 520, arrangements at other levels, or the number of conductors are within the scope of this invention.

[0259] In some embodiments, conductor 520b is electrically coupled to conductors 206a and 206c through corresponding vias 230a and 230c, and conductors 206a and 206c are further electrically coupled to active region 202b through corresponding vias 208a and 208c, thereby providing a first supply voltage of voltage source VDD or a second supply voltage of reference voltage source VSS to the source or drain of the corresponding active region 202b.

[0260] In some embodiments, conductor 520a is electrically coupled to conductor 206b through via 230b, and conductor 206b is further electrically coupled to active region 202a through via 208b, thereby providing a first supply voltage of voltage source VDD or a second supply voltage of reference voltage source VSS to the source or drain of the corresponding active region 202a.

[0261] In some embodiments, by moving at least the signal lines and power rails of the conductor group 520 from the front side 203a of the integrated circuit 500 or 700 to the back side 203b of the integrated circuit 500 or 700, an integrated circuit 500 or 700 using at least one fewer upper metal layer rail in the conductor group 260 is produced, resulting in an integrated circuit with a smaller height, smaller area, greater wiring flexibility and additional wiring resources compared to other methods.

[0262] Figures 6A to 6B This is a diagram of an integrated circuit layout design 600 according to some embodiments. Layout design 600 is... Figures 7A to 7C The layout diagram of the integrated circuit 700.

[0263] Figure 6A yes Figure 6B The layout design of 600 is shown in the diagram corresponding to the 600A part, which has been simplified for ease of explanation.

[0264] Figure 6B This is a layout design diagram of 600, including a portion of 600A, simplified for ease of explanation. For example, Figure 6B The layout design 600 also includes M0. In other words, for ease of explanation, Figure 6A Part 600A does not include M0. In some embodiments, layout design 600 includes Figures 6A to 6B Additional components not shown. Layout design 600 includes sections 600A and M0 levels.

[0265] Layout design 600 can be used for manufacturing Figures 7A to 7C The integrated circuit 700.

[0266] Layout design 600 is layout design 400 ( Figures 4A to 4B A variant of ). Part 600A is Figure 4A Variations of part 400A are shown, and therefore similar detailed descriptions are omitted. For example, layout design 600 shows an instance where the conductive component pattern group 620 does not have a zigzag shape. In other words, the conductive component pattern group 620 does not include extended regions 520a2, 520b2, or 520b3 that are oriented in an alternating manner with respect to each other.

[0267] and Figures 1A to 1B Compared to layout design 100, layout design 600 replaces conductive component pattern group 420 with conductive component pattern group 620, and therefore similar detailed descriptions are omitted.

[0268] The layout design 600 includes an active region pattern group 102, a gate pattern group 104, a conductive component pattern group 106, a via pattern group 108, a conductive component pattern group 110, a via pattern group 112, a conductive component pattern group 620, and a via pattern group 130. The conductive component pattern group 620 includes one or more conductive component patterns 620a, 620b, or 420c.

[0269] and Figures 4A to 4B Compared to layout design 400, the conductive component patterns 620a and 620b of layout design 600 replace the corresponding conductive component patterns 420a and 420b, and therefore similar detailed descriptions are omitted.

[0270] Conductive component pattern group 620 can be used to manufacture integrated circuit 700 ( Figures 7A to 7C The corresponding conductor group 720. In some embodiments, the conductive component patterns 620a, 620b, and 420c of the conductive component pattern group 620 can be used to manufacture the conductive component group 720 of the integrated circuit 700. Figures 7A to 7C The corresponding conductors are 720a, 720b, and 520c.

[0271] and Figures 4A to 4B Compared to conductive component patterns 420a and 420b, conductive component patterns 620a and 620b do not have a serrated shape or an interleaved orientation relative to each other. For example, conductive component pattern 620a does not include conductive component pattern 420a2, and conductive component pattern 620b does not include conductive component patterns 620b2 and 620b3.

[0272] At least the conductive component pattern 620a or 620b has a width BM1 in the second direction Y. PW2a Each conductive component pattern 620a or 620b is separated from the conductive component pattern 620c by a distance BM1 in the second direction Y. S1a The layout design 600 has a cell height CH2a in the second direction. In some embodiments, the cell height of the layout design 600 is greater than the cell height of the layout design 400, and therefore, the spacing BM1 between the conductive component pattern 620c and the conductive component patterns 620a and 620b is... SW1b It is sufficient to avoid using a serrated shape.

[0273] In some embodiments, layout design 600 satisfies a first set of design rules. For example, in some embodiments, when a layout design (e.g., layout design 600) satisfies the first set of design rules, a non-interleaved power delivery layout similar to conductive component pattern group 620 is used. In some embodiments, the first set of design rules relates to the cell height CH2a of layout design 600.

[0274] In some embodiments, the cell height CH2a of the layout design 600 is determined according to Formula 1 (described above). In some embodiments, the first design rule group includes the width BV0 of each via pattern in the via pattern group 130 of the layout design 600. W1a Does it satisfy Formula 2 (described above)?

[0275] In some embodiments, when the width BV0 of each through-hole pattern in the through-hole pattern group 130 of the layout design 400 is... W1a When the value is greater than or equal to Formula 2, a non-interleaved power delivery network layout is used for the conductive component pattern group 620. In other words, if the width BV0 of each via pattern in the via pattern group 130 of the layout design (e.g., layout design 600) is greater than or equal to Formula 2, a non-interleaved power delivery network layout is used for the conductive component pattern group 620. W1a If the value is equal to or greater than that of Formula 2, then the first design rule group is satisfied, but Formula 2 is not satisfied. In some embodiments, if Formula 2 is not satisfied, then a pattern similar to conductive component pattern group 420 is used. Figures 4A to 4B The power supply network layout.

[0276] Other widths for conductive component pattern group 620 or other numbers of conductive component patterns in conductive component pattern group 620 are within the scope of the invention. In some embodiments, at least conductive component pattern 620a has a different width than conductive component pattern 620b.

[0277] Other configurations, arrangements, or number of patterns in the conductive component pattern group 620 are within the scope of this invention.

[0278] In some embodiments, the layout design 600, which includes a conductive component pattern group 620, achieves the above-mentioned... Figures 1A to 5E One or more benefits discussed in the text.

[0279] Figures 7A to 7C This is a diagram of an integrated circuit 700 according to some embodiments.

[0280] Figure 7A This is a top view of an integrated circuit 700 according to some embodiments. Figure 7B yes Figure 7A A top view of the corresponding portion 700B of the integrated circuit 700, simplified for ease of explanation. Figure 7B This is a diagram of integrated circuit 700, including part 700B, simplified for ease of explanation. Integrated circuit 700 includes part 700B and the M0 level.

[0281] Figure 7C This is a cross-sectional view of an integrated circuit 700 intersecting with plane E-E' according to some embodiments.

[0282] Integrated circuit 700 is manufactured through layout design 600. The structural relationships of integrated circuit 700, including alignment, length and width, as well as configuration and layers, are similar to those of integrated circuit 700. Figures 6A to 6B The layout design includes the structural relationships, configuration, and layers of the 600, and for simplicity, at least in... Figures 7A to 7C The lieutenant general did not provide a similar detailed description.

[0283] Integrated circuit 700 is an improvement on integrated circuit 500. Figures 5A to 5C Variations of ) are omitted, and therefore similar detailed descriptions are omitted. For example, integrated circuit 700 shows an instance where conductor group 720 does not have a serrated shape. In other words, conductor group 720 does not include extended regions 720a2, 720b2, or 720b3 that are oriented in an alternating manner with respect to each other.

[0284] and Figures 5A to 5B Compared to integrated circuit 500, the conductor group 720 of integrated circuit 700 replaces the conductor group 520, and therefore a similar detailed description is omitted.

[0285] The integrated circuit 700 includes at least an active region group 202, a gate group 204, an insulating region 205, a conductor group 206, a conductor group 210, a via group 208, a via group 212, a conductor group 720 (also referred to as a power rail group 720), a via group 230, and a conductor group 260.

[0286] The conductor group 720 includes one or more conductors 720a, 720b or 520c.

[0287] and Figures 5A to 5B Compared to integrated circuit 500, conductors 720a and 720b of integrated circuit 700 replace the corresponding conductors 520a and 520b, and therefore a similar detailed description is omitted.

[0288] Conductor group 720 can be used to manufacture integrated circuit 700 ( Figures 7A to 7C The corresponding conductor group 720. In some embodiments, conductors 720a, 720b, and 520c of conductor group 720 can be used to manufacture conductor group 720 of integrated circuit 700. Figures 7A to 7C The corresponding conductors are 720a, 720b, and 520c.

[0289] and Figures 5A to 5C Compared to conductors 520a and 520b, conductors 720a and 720b do not have a serrated shape or an interleaved orientation relative to each other. For example, conductor 720a does not include conductor 520a2, and conductor 720b does not include conductors 720b2 and 720b3.

[0290] At least conductor 720a or 720b has a width BM1 in the second direction Y. PW2bEach conductor 720a or 720b is separated from conductor 720c by a distance BM1 in the second direction Y. S1b Integrated circuit 700 has a cell height CH2b in the second direction. In some embodiments, the cell height of integrated circuit 700 is greater than the cell height of integrated circuit 500, and therefore, the spacing BM1 between conductor 720c and conductors 720a and 720b is... SW1b It is sufficient to avoid using a serrated shape.

[0291] In some embodiments, integrated circuit 700 satisfies a second set of design rules. For example, in some embodiments, when an integrated circuit (e.g., integrated circuit 700) satisfies the second set of design rules, a non-interleaved power supply similar to conductor group 720 is used. In some embodiments, the second set of design rules relates to the cell height CH2b of integrated circuit 700.

[0292] In some embodiments, the cell height CH2b of integrated circuit 700 is determined according to Formula 1 (described above). In some embodiments, the second design rule set includes the width BV0 of each via of via group 230 of integrated circuit 700. W1b Does it satisfy Formula 2 (described above)?

[0293] In some embodiments, when the width BV0 of each via of the via group 230 of the integrated circuit 500 is... W1b When the value is greater than or equal to Formula 2, a non-interleaved power supply network is used to the conductor group 720. In other words, if the width BV0 of each via of the via group 230 of the integrated circuit (e.g., integrated circuit 700) is... W1b If the value is equal to or greater than that of Formula 2, then the second design rule group is satisfied, but Formula 2 is not satisfied. In some embodiments, if Formula 2 is not satisfied, then a conductor group similar to 520 is used. Figures 4A to 4B ) power supply network.

[0294] Other widths of conductor group 720 or other numbers of conductors in conductor group 720 are within the scope of this invention. In some embodiments, at least conductor 720a has a different width than conductor 720b.

[0295] Other configurations in conductor group 720, arrangements at other levels, or the number of conductors are within the scope of this invention.

[0296] In some embodiments, the integrated circuit 700, including the conductor group 720, implements the above-mentioned... Figures 1A to 5E One or more benefits discussed in the text.

[0297] Figures 8A to 8B These are diagrams of corresponding integrated circuits 800A-800B according to some embodiments.

[0298] Figure 8A This is a top view of an integrated circuit 800A according to some embodiments.

[0299] Figure 8B This is a top view of a portion 800B of the conductor group 820 of an integrated circuit 800A according to some embodiments.

[0300] Integrated circuit 800 is integrated circuit 300A ( Figure 3A Variations of ), and therefore similar detailed descriptions are omitted. For example, integrated circuit 800 shows conductor group 820 replaced. Figure 3A An example of conductor group 320 is given, and therefore a similar detailed description is omitted. In other words, conductor group 820 has a serrated shape and also includes signal lines (e.g., conductor 826).

[0301] Integrated circuit 800A includes Figure 3A The arrangement is a cell array 302a with 3 rows and at least 2 columns. Other numbers of rows and columns are within the scope of this invention. In some embodiments, each cell of the cell array 302a corresponds to a cell manufactured by layout design 400. In some embodiments, each cell of the cell array 302a corresponds to a portion of integrated circuit 500, for simplicity of illustration.

[0302] Conductor group 820 includes one or more of conductors 822, 824, or 826. In some embodiments, conductor group 820 includes more than conductors 822, 824, and 826 (similar to...). Figures 3A to 3B The conductors are shown, but for simplicity, they are simplified. In some embodiments, each row of the cells overlaps with three conductors similar to conductors 822, 824, or 826.

[0303] In some embodiments, the conductor group 820 in integrated circuits 800A-800B is similar to the conductor group 520 of integrated circuit 500, and similar detailed descriptions are omitted for brevity.

[0304] In some embodiments, conductors 822 and 824 are not power rails. In some embodiments, each cell in the cell array shares a VSS power rail (e.g., conductor 824) with an adjacent cell row and shares a VDD power rail (e.g., conductor 822) with another adjacent cell row. For example, in some embodiments, cell 802 shares a VSS power rail (e.g., conductor 824) with cells in row 1 and shares a VDD power rail (e.g., conductor 822) with cells in row 3.

[0305] Conductor 822 overlaps with row 2-3 of cell array 302a and provides voltage VDD to the cells in row 2-3. Conductor 824 overlaps with row 1-2 of cell array 302a and provides reference voltage VSS to the cells in row 1-2.

[0306] Conductor 822 includes conductor 822a coupled to extended conductor portions 822a1, 822a2, ..., 822a6 and extended conductor portions 822b1, 822b2, ..., 822b5. Conductor 822a and extended conductor portions 822a1, 822a2, ..., 822a6 and extended conductor portions 822b1, 822b2, ..., 822b5 are similar to conductors 520a1 and 520a2 and conductors 520b1, 520b2 and 520b3, and similar detailed descriptions are omitted.

[0307] Conductor 824 includes conductor 824a coupled to extended conductor portions 824a1, 824a2, ..., 824a6 and extended conductor portions 824b1, 824b2, ..., 824b6. Conductor 824a and extended conductor portions 824a1, 824a2, ..., 824a6 and extended conductor portions 824b1, 824b2, ..., 824b6 are similar to conductors 520a1 and 520a2 and conductors 520b1, 520b2 and 520b3, and similar detailed descriptions are omitted.

[0308] In some embodiments, when viewed from the bottom / back side (e.g., in the positive Z direction) of the integrated circuit 800, each extended conductor portion 822a1, 822a2, ..., 822a6, each extended conductor portion 822b1, 822b2, ..., 822b5, each extended conductor portion 824a1, 824a2, ..., 824a6, and each extended conductor portion 824b1, 824b2, ..., 824b6 overlaps with the BMO_b conductor to provide power (VDD / VSS) through vias in the BVO layer.

[0309] In some embodiments, the integrated circuit 800, including a conductor group 820, implements the above-mentioned... Figures 1A to 5E One or more benefits discussed in the text.

[0310] Other configurations, arrangements on other levels, or the number of conductors in integrated circuits 800A-800B are within the scope of this invention.

[0311] Figure 9 This is a circuit diagram of an integrated circuit 900 according to some embodiments. In some embodiments, the integrated circuit 900 is a complementary metal-oxide-semiconductor (CMOS) inverter circuit. The CMOS inverter circuit is used for illustration; other types of circuits are also within the scope of this invention.

[0312] Integrated circuit 900 includes a P-type metal-oxide-semiconductor (PMOS) transistor P9-1 coupled to an N-type metal-oxide-semiconductor (NMOS) transistor N9-1.

[0313] The gate terminal of PMOS transistor P9-1 is coupled to the gate terminal of NMOS transistor N9-1 and configured as input node IN. The drain terminal of PMOS transistor P9-1 is coupled to the drain terminal of NMOS transistor N9-1 and configured as output node OUT. The source terminal of PMOS transistor P9-1 is coupled to voltage source VDD. The source terminal of NMOS transistor N9-1 is coupled to reference voltage source VSS.

[0314] Figures 10A to 10C This is a top view of corresponding portions 1000A-1000C of an integrated circuit 1000 according to some embodiments.

[0315] Integrated circuit 1000 is manufactured using a corresponding layout design similar to that of integrated circuit 1000. For simplicity, Figures 10A to 10C , Figures 12A to 12C , Figures 14A to 14C and Figures 16A to 16C The description corresponds to integrated circuits 1000, 1200, 1400, and 1600, but in some embodiments, Figures 10A to 10C , Figures 12A to 12C , Figures 14A to 14C and Figures 16A to 16C Also corresponding to layout designs similar to layout designs 100, 400, and 600, the structural elements of integrated circuits 1000, 1200, 1400, and 1600 also correspond to layout patterns, and the structural relationships of integrated circuits 1000, 1200, 1400, and 1600, including alignment, length and width, as well as configuration and layers, are similar to the structural relationships, configuration, and layers of integrated circuits 1000, 1200, 1400, and 1600. For the sake of brevity, similar detailed descriptions will not be described.

[0316] Integrated circuit 1000 is an embodiment of integrated circuit 900.

[0317] Figure 10A This is a top view of portion 1000A of integrated circuit 1000, simplified for ease of explanation. Portion 1000A includes one or more components of integrated circuit 1000 at the OD layer, POLY layer, diffusion-over-metal (MD) layer, MO layer, gate-over-via (VG) layer, and diffusion-over-via (VD) layer of integrated circuit 1000.

[0318] Figure 10BThis is a top view of part 1000B of integrated circuit 1000, simplified for ease of explanation. Part 1000B includes one or more components of integrated circuit 1000 at the OD layer, POLY layer, MD layer, BMO layer, and VBS / P layer of integrated circuit 1000.

[0319] Figure 10C This is a top view of part 1000C of integrated circuit 1000, simplified for ease of explanation. Part 1000C includes one or more components of integrated circuit 1000 at the POLY, BM0, BM1, and VB0 levels.

[0320] In some embodiments, integrated circuits 1000, 1200, 1400, and 1600 include Figures 10A to 10C , Figures 12A to 12C , Figures 14A to 14C and Figures 16A to 16C Additional elements not shown in the diagram.

[0321] Integrated Circuit 1000 is Integrated Circuit 500 ( Figures 5A to 5E Variations of ) are shown, and therefore similar detailed descriptions are omitted. For example, integrated circuit 1000 is shown using Figures 5A to 5E The detailed implementation of the integrated circuit 500 Figure 9 An example of a CMOS inverter from the integrated circuit 900.

[0322] Integrated circuit 1000 includes at least an active region group 202, a gate group 1004, a conductor group 1006, a via group 1008, a conductor group 1020, a via group 1030, a contact group 1040, a conductor group 1060, and vias in a VG layer and a via in a VD layer. In some embodiments, for simplicity, the via VD between the contact group 1040 and the conductor group 1060 and the via VG between the gate group 1004 and the conductor group 1060 are not described, but... Figures 10A to 10C As shown in the image.

[0323] and Figures 5A to 5E Compared to integrated circuit 500, gate group 1004 replaces gate group 204, conductor group 1006 replaces conductor group 206, via group 1008 replaces via group 208, conductor group 1020 replaces conductor group 520, via group 1030 replaces via group 230, and conductor group 1060 replaces conductor group 260, and thus similar detailed descriptions of each group and each individual component within each corresponding group are omitted.

[0324] exist Figures 10A to 10CIn the above, active region 202a corresponds to the active region (e.g., source / drain) of PMOS transistor P9-1, and active region 202b corresponds to the active region (e.g., source / drain) of NMOS transistor N9-1.

[0325] Gate group 1004 includes at least gates 1004a, 1004b, or 1004c. Figures 10A to 10C In this configuration, gate 1004b corresponds to the gates of PMOS transistor P9-1 and NMOS transistor N9-1. In some embodiments, gates 1004a and 1004c are dummy gates.

[0326] The contact group 1040 includes one or more contacts 1040a, 1040b, or 1040c. In some embodiments, the contact group is located on the MD layer of the integrated circuit 1000. In some embodiments, the MD layer is located between the OD layer and the MO layer.

[0327] In some embodiments, contact 1040a corresponds to the drain terminals of PMOS transistor P9-1 and NMOS transistor N9-1, and electrically couples the drain terminals of PMOS transistor P9-1 and NMOS transistor N9-1 together. In some embodiments, contact 1040b corresponds to the source terminal of PMOS transistor P9-1 and is electrically coupled to the source terminal of PMOS transistor P9-1. In some embodiments, contact 1040c corresponds to the source terminal of NMOS transistor N9-1 and is electrically coupled to the source terminal of NMOS transistor N9-1.

[0328] The conductor group 1006 includes at least conductor 1006a or 1006b.

[0329] The through-hole group 1008 includes at least through-hole 1008a or 1008b.

[0330] Conductor group 1020 includes at least conductors 1020a, 1020b, or 1020c. Conductor 1020a is the VDD power rail, and conductor 1020b is the VSS power rail.

[0331] The through-hole group 1030 includes at least through-hole 1030a or 1030b.

[0332] Conductor 1020a is electrically coupled to the source of PMOS transistor P9-1 and configured to provide a voltage VDD to the source of PMOS transistor P9-1. For example, conductor 1020a is electrically coupled to conductor 1006a through via 1030a, and conductor 1006a is electrically coupled to the source of PMOS transistor P9-1 through via 1008a.

[0333] Conductor 1020b is electrically coupled to the source of NMOS transistor N9-1 and configured to provide a reference voltage VSS to the source of NMOS transistor N9-1. For example, conductor 1020b is electrically coupled to conductor 1006b through via 1030b, and conductor 1006b is electrically coupled to the source of NMOS transistor N9-1 through via 1008b.

[0334] Conductor group 1060 includes at least conductors 1060a, 1060b, 1060c, 1060d, or 1060e. In some embodiments, conductor group 1060 is configured as an input node IN and an output node OUT of integrated circuit 900. For example, in some embodiments, conductor 1060b is an input node IN and conductor 1060d is an output node OUT. In some embodiments, integrated circuit 1000 implements the above... Figures 1A to 5E One or more benefits discussed herein. In some embodiments, one or more of the drain or source electrodes are flipped with the other.

[0335] Other configurations, arrangements at other levels, or the number of conductors in integrated circuit 1000 are within the scope of this invention.

[0336] Figure 11 This is a circuit diagram of an integrated circuit 1100 according to some embodiments. In some embodiments, the integrated circuit 1100 is a NAND gate. NAND gates are used to illustrate that other types of circuits are within the scope of this invention.

[0337] Integrated circuit 1100 includes PMOS transistors P11-1 and P11-2 coupled to NMOS transistors N11-1 and N11-2.

[0338] The gate terminals of PMOS transistor P11-1 and NMOS transistor N11-1 are coupled together and configured as input node IN1a. The gate terminals of PMOS transistor P11-2 and NMOS transistor N11-2 are coupled together and configured as input node IN2a.

[0339] The source terminals of PMOS transistor P11-1 and PMOS transistor P11-2 are coupled to the voltage source VDD. The source terminal of NMOS transistor N11-1 is coupled to the reference voltage source VSS. The source terminal of NMOS transistor N11-2 and the drain terminal of NMOS transistor N11-1 are coupled to each other.

[0340] The drain terminals of PMOS transistor P11-1, PMOS transistor P11-2, and NMOS transistor N11-2 are coupled to each other and configured as output node OUT1. For example... Figure 11As shown, the drain terminals of PMOS transistor P11-2 and PMOS transistor N11-2 are connected at least through conductor 1206c. Figures 12A to 12C (As described in the text) Electrical coupling. In some embodiments, one or more of the drain or source terminals are flipped with the other.

[0341] Figures 12A to 12C This is a top view of corresponding portions 1200A-1200C of an integrated circuit 1200 according to some embodiments.

[0342] Integrated circuit 1200 is manufactured using a layout design similar to that of integrated circuit 1200.

[0343] Integrated circuit 1200 is an embodiment of integrated circuit 1100.

[0344] Figure 12A This is a top view of portion 1200A of integrated circuit 1200, simplified for ease of explanation. Portion 1200A includes one or more components of integrated circuit 1200 at the OD, POLY, MD, M0, VG, and VD layers.

[0345] Figure 12B This is a top view of portion 1200B of integrated circuit 1200, simplified for ease of explanation. Portion 1200B includes one or more components of integrated circuit 1200 at the OD layer, POLY layer, MD layer, BMO layer, and VBS / P layer of integrated circuit 1200.

[0346] Figure 12C This is a top view of portion 1200C of integrated circuit 1200, simplified for ease of explanation. Portion 1200C includes one or more components of integrated circuit 1200 at the POLY, BM0, BM1, and VB0 levels.

[0347] Integrated Circuit 1200 is Integrated Circuit 500 ( Figures 5A to 5E ) or Integrated Circuit 1000 ( Figures 10A to 10C Variations of () are shown, and therefore similar detailed descriptions are omitted. For example, integrated circuit 1200 is shown as implemented in detail using integrated circuit 500 or 1000. Figure 11 An example of a NAND gate in the integrated circuit 1100.

[0348] Integrated circuit 1200 includes at least an active region group 202, a gate group 1204, a conductor group 1206, a via group 1208, a conductor group 1220, a via group 1230, a contact group 1240, a conductor group 1260, and vias in a VG layer and a via group 1270 in a VD layer. In some embodiments, for simplicity, the via VD between the contact group 1240 and the conductor group 1260, and the via VG between the gate group 1204 and the conductor group 1260 are not described. However, in Figures 12A to 12C As shown in the image.

[0349] and Figures 5A to 5E Compared to integrated circuit 500, gate group 1204 replaces gate group 204, conductor group 1206 replaces conductor group 206, via group 1208 replaces via group 208, conductor group 1220 replaces conductor group 520, via group 1230 replaces via group 230, and conductor group 1260 replaces conductor group 260, and thus similar detailed descriptions of each group and each individual component within each corresponding group are omitted.

[0350] exist Figures 12A to 12C In the above, active region 202a corresponds to the active regions (e.g., source / drain) of PMOS transistors P11-1 and P11-2, and active region 202b corresponds to the active regions (e.g., source / drain) of NMOS transistors N11-1 and N11-2.

[0351] Gate group 1204 includes at least gates 1204a, 1204b, 1204c, or 1204d. Figures 12A to 12C In the diagram, gate 1204b corresponds to the gates of PMOS transistor P11-1 and NMOS transistor N11-1. Figures 12A to 12C In this configuration, gate 1204c corresponds to the gates of PMOS transistor P11-2 and NMOS transistor N11-2. In some embodiments, gates 1204a and 1204d are dummy gates.

[0352] The contact group 1240 includes one or more contacts 1240a, 1240b, 1240c, 1240d, or 1240e. In some embodiments, the contact group 1240 is located on the MD layer of the integrated circuit 1200.

[0353] In some embodiments, contact 1240a corresponds to the drain terminals of PMOS transistor P11-2 and NMOS transistor N11-2, and electrically couples the drain terminals of PMOS transistor P11-2 and NMOS transistor N11-2 together.

[0354] In some embodiments, contact 1240b corresponds to the source terminal of PMOS transistor P11-1 or the source terminal of PMOS transistor P11-2, and is electrically coupled to the source of PMOS transistor P11-1 and the source of PMOS transistor P11-2.

[0355] In some embodiments, the contact 1240c corresponds to the drain terminal of NMOS transistor N11-1 or the source terminal of NMOS transistor N11-2, and is electrically coupled to the drain of NMOS transistor N11-1 and the source of NMOS transistor N11-2.

[0356] In some embodiments, contact 1240d corresponds to the drain terminal of PMOS transistor P11-1 and is electrically coupled to the drain of PMOS transistor P11-1.

[0357] In some embodiments, contact 1240e corresponds to the source terminal of NMOS transistor N11-1 and is electrically coupled to the source of NMOS transistor N11-1.

[0358] The conductor group 1206 includes at least conductors 1206a, 1206b or 1206c.

[0359] The through-hole group 1208 includes at least through holes 1208a, 1208b, 1208c or 1208d.

[0360] Conductor group 1220 includes at least conductors 1220a, 1220b, or 1220c. Conductor 1220a is the VDD power rail, and conductor 1220b is the VSS power rail.

[0361] The through-hole group 1230 includes at least through-hole 1230a or 1230b.

[0362] Conductor 1220a is electrically coupled to the sources of PMOS transistors P11-1 and P11-2 and configured to provide a voltage VDD to the sources of PMOS transistors P11-1 and P11-2. For example, conductor 1220a is electrically coupled to conductor 1206a through via 1230a, and conductor 1206a is electrically coupled to the sources of PMOS transistors P11-1 and P11-2 through via 1208a.

[0363] Conductor 1220b is electrically coupled to the source of NMOS transistor N11-1 and configured to provide a reference voltage VSS to the source of NMOS transistor N11-1. For example, conductor 1220b is electrically coupled to conductor 1206b through via 1230b, and conductor 1206b is electrically coupled to the source of NMOS transistor N11-1 through via 1208b.

[0364] Conductor 1206c electrically couples the drain of PMOS transistor P11-2 and the drain of NMOS transistor N11-2 together. For example, the drain of PMOS transistor P11-2 is electrically coupled to conductor 1206c through via 1208c, and conductor 1206c is electrically coupled to the drain of NMOS transistor N11-2 through via 1208d.

[0365] Conductor group 1260 includes at least conductors 1260a, 1260b, 1260c, 1260d, or 1260e. In some embodiments, conductor group 1260 is configured as input node IN1a, input node IN2a, and output node OUT1 of integrated circuit 1200. For example, in some embodiments, conductor 1260b is output node OUT1, conductor 1260c is input node IN1a, and conductor 1260d is input node IN2a.

[0366] Conductor 1260b electrically couples the drain of PMOS transistor P11-1 and the drain of PMOS transistor P11-2 together. For example, the drain of PMOS transistor P11-1 is electrically coupled to contact 1240d, contact 1240d is electrically coupled to conductor 1206c through via 1270a, conductor 1206c is electrically coupled to contact 1240a through via 1270b, and contact 1240a is electrically coupled to the drain of PMOS transistor P11-2.

[0367] Vias 1270a and 1270b are part of via group 1270. Via group 1270 is similar to via group 1208, but is located at the VD level, and therefore a similar detailed description is omitted. In some embodiments, one or more of the drain or source electrodes are flipped with the other.

[0368] In some embodiments, integrated circuit 1200 implements the above-mentioned... Figures 1A to 5E One or more benefits discussed in the text.

[0369] Other configurations, arrangements at other levels, or the number of conductors in integrated circuit 1200 are within the scope of this invention.

[0370] Figure 13 This is a circuit diagram of an integrated circuit 1300 according to some embodiments. In some embodiments, the integrated circuit 1300 is a 2-2 AND / OR inverting (AOI) circuit. The 2-2 AOI circuit is used for illustration; other types of circuits, including other types of AOI circuits, are within the scope of this invention.

[0371] Integrated circuit 1300 includes PMOS transistors P13-1, P13-2, P13-3, and P13-4 coupled to NMOS transistors N13-1, N13-2, N13-3, and N13-4.

[0372] The gate terminals of PMOS transistor P13-1 and NMOS transistor N13-1 are coupled together and configured as input node IN1b. The gate terminals of PMOS transistor P13-2 and NMOS transistor N13-2 are coupled together and configured as input node IN2b. The gate terminals of PMOS transistor P13-3 and NMOS transistor N13-3 are coupled together and configured as input node IN3b. The gate terminals of PMOS transistor P13-4 and NMOS transistor N13-4 are coupled together and configured as input node IN4b.

[0373] The source terminals of PMOS transistor P13-1 and PMOS transistor P13-2 are coupled to the voltage source VDD. The source terminals of NMOS transistor N13-1 and NMOS transistor N13-4 are each coupled to the reference voltage source VSS.

[0374] The source terminal of NMOS transistor N13-2 and the drain terminal of NMOS transistor N13-1 are coupled to each other. The source terminal of NMOS transistor N13-3 and the drain terminal of NMOS transistor N13-4 are coupled to each other.

[0375] The source terminal of PMOS transistor P13-4, the source terminal of PMOS transistor P13-3, the drain terminal of PMOS transistor P13-2, and the drain terminal of PMOS transistor P13-1 are coupled to each other.

[0376] The drain terminals of PMOS transistor P13-4, PMOS transistor P13-3, NMOS transistor N13-2, and NMOS transistor N13-3 are coupled to each other and configured as output node OUT2. For example... Figures 14A to 14C As shown, the drain terminals of PMOS transistors P13-3 and P13-4 and the drain terminals of NMOS transistors N13-2 and N13-3 are connected at least through conductor 1410a. Figures 14A to 14C (As described in the text) Electrically coupled together. In some embodiments, one or more of the drain or source terminals are flipped with the other.

[0377] Other configurations, arrangements, or other circuits in integrated circuit 1300 are within the scope of this invention.

[0378] Figures 14A to 14C This is a top view of corresponding portions 1400A-1400C of an integrated circuit 1400 according to some embodiments.

[0379] Integrated circuit 1400 is manufactured using a corresponding layout design similar to that of integrated circuit 1100. Integrated circuit 1400 is an embodiment of integrated circuit 1100.

[0380] Figure 14A This is a top view of portion 1400A of integrated circuit 1400, simplified for ease of explanation. Portion 1400A includes one or more components of integrated circuit 1400 at the OD layer, POLY layer, MD layer, M0 layer, VG layer, and VD layer of integrated circuit 1400.

[0381] Figure 14B This is a top view of portion 1400B of integrated circuit 1400, simplified for ease of explanation. Portion 1400B includes one or more components of integrated circuit 1400 at the OD layer, POLY layer, MD layer, BMO layer, and VBS / P layer of integrated circuit 1400.

[0382] Figure 14C This is a top view of portion 1400C of integrated circuit 1400, simplified for ease of explanation. Portion 1400C includes one or more components of integrated circuit 1400 at the POLY, BM0, BM1, and VB0 levels.

[0383] Integrated Circuit 1400 is an integral part of Integrated Circuit 500 ( Figures 5A to 5E ) or Integrated Circuit 1000 ( Figures 10A to 10C ) or integrated circuit 1200 ( Figures 12A to 12C Variations of () are shown, and therefore similar detailed descriptions are omitted. For example, integrated circuit 1400 is shown as implemented in detail using integrated circuit 500 or 1000. Figure 13 An example of the AOI logic gates of the integrated circuit 1300.

[0384] Integrated circuit 1400 includes at least an active region group 202, a gate group 1404, a conductor group 1406, a via group 1408, a conductor group 1410, a via group 1412, a conductor group 1420, a via group 1430, a contact group 1440, a conductor group 1460, and vias in a VG layer and via groups in a VD layer 1470. In some embodiments, for simplicity, the via VD between the contact group 1440 and the conductor group 1460 and the via VG between the gate group 1404 and the conductor group 1460 are not described, but... Figures 14A to 14C As shown in the image.

[0385] and Figures 5A to 5ECompared to integrated circuit 500, gate group 1404 replaces gate group 204, conductor group 1406 replaces conductor group 206, via group 1408 replaces via group 208, conductor group 1410 replaces conductor group 210, via group 1408 replaces via group 212, conductor group 1420 replaces conductor group 520, via group 1430 replaces via group 230, conductor group 1460 replaces conductor group 260, and thus similar detailed descriptions of each group and each individual component within each corresponding group are omitted.

[0386] exist Figures 14A to 14C In the PMOS transistors P13-1, P13-2, P13-3 and P13-4, the active region 202a corresponds to the active region (e.g., source / drain) of the PMOS transistors P13-1, P13-2, P13-3 and P13-4, and the active region 202b corresponds to the active region (e.g., source / drain) of the NMOS transistors N13-1, N13-2, N13-3 and N13-4.

[0387] Gate group 1404 includes at least gates 1404a, 1404b, ..., 1404e or 1404f. Figures 14A to 14C In the diagram, gate 1404b corresponds to the gates of PMOS transistor P13-1 and NMOS transistor N13-1. Figures 14A to 14C In the diagram, gate 1404c corresponds to the gate of both PMOS transistor P13-2 and NMOS transistor N13-2. Figures 14A to 14C In the diagram, gate 1404d corresponds to the gate of PMOS transistor P13-3 and NMOS transistor N13-3. Figures 14A to 14C In this context, gate 1404e corresponds to the gates of PMOS transistor P13-4 and NMOS transistor N13-4. In some embodiments, gates 1404a and 1404f are dummy gates.

[0388] The contact group 1440 includes one or more contacts 1440a, 1440b, 1440c, ..., 1440i or 1440j. In some embodiments, the contact group 1440 is located on the MD layer of the integrated circuit 1400.

[0389] In some embodiments, contact 1440a corresponds to the source terminal of PMOS transistor P13-4 and is electrically coupled to the source of PMOS transistor P13-4.

[0390] In some embodiments, contact 1440b corresponds to the drain terminal of PMOS transistor P13-4 or the drain terminal of PMOS transistor P13-3, and is electrically coupled to the drain of PMOS transistor P13-4 and the drain of PMOS transistor P13-3.

[0391] In some embodiments, contact 1440c corresponds to the source terminal of PMOS transistor P13-3 or the drain terminal of PMOS transistor P13-2, and is electrically coupled to the source of PMOS transistor P13-3 and the drain of PMOS transistor P13-2.

[0392] In some embodiments, contact 1440d corresponds to the source terminal of PMOS transistor P13-2 or the source terminal of PMOS transistor P13-1, and is electrically coupled to the source of PMOS transistor P13-2 and the source of PMOS transistor P13-1.

[0393] In some embodiments, contact 1440e corresponds to the drain terminal of PMOS transistor P13-1 and is electrically coupled to the drain of PMOS transistor P13-1.

[0394] In some embodiments, contact 1440f corresponds to the source terminal of NMOS transistor P13-1 and is electrically coupled to the source of NMOS transistor P13-1.

[0395] In some embodiments, the contact 1440g corresponds to the drain terminal of NMOS transistor N13-1 or the source terminal of NMOS transistor N13-2, and is electrically coupled to the drain of NMOS transistor N13-1 and the source of NMOS transistor N13-2.

[0396] In some embodiments, the contact 1440h corresponds to the drain terminal of NMOS transistor N13-2 or the drain terminal of NMOS transistor N13-3, and is electrically coupled to the drain of NMOS transistor N13-2 and the drain of NMOS transistor N13-3.

[0397] In some embodiments, contact 1440i corresponds to the source terminal of NMOS transistor N13-3 or the drain terminal of NMOS transistor N13-4, and is electrically coupled to the source of NMOS transistor N13-3 and the drain of NMOS transistor N13-4.

[0398] In some embodiments, contact 1440j corresponds to the source terminal of NMOS transistor N13-4 and is electrically coupled to the source of NMOS transistor N13-4.

[0399] The conductor group 1406 includes at least conductors 1406a, 1406b or 1406c.

[0400] The through-hole group 1408 includes at least through holes 1408a, 1408b or 1408c.

[0401] The conductor group 1410 includes at least conductor 1410a.

[0402] The through-hole group 1412 includes at least through-holes 1412a or 1412b.

[0403] Conductor group 1420 includes at least conductors 1420a, 1420b, or 1420c. Conductor 1420a is the VDD power rail, and conductor 1420b is the VSS power rail.

[0404] The through-hole group 1430 includes at least through holes 1430a, 1430b or 1430c.

[0405] Conductor 1420a is electrically coupled to the sources of PMOS transistors P13-1 and P13-2 and configured to provide a voltage VDD to the sources of PMOS transistors P13-1 and P13-2. For example, conductor 1420a is electrically coupled to conductor 1406a through via 1430a, and conductor 1406a is electrically coupled to the sources of PMOS transistors P13-1 and P13-2 through via 1408a.

[0406] Conductor 1420b is electrically coupled to the source of NMOS transistor N13-1 and the source of NMOS transistor N13-4 and configured to provide a reference voltage VSS to the source of NMOS transistor N13-1 and the source of NMOS transistor N13-4. For example, conductor 1420b is electrically coupled to conductor 1406b through via 1430b, and conductor 1406b is electrically coupled to the source of NMOS transistor N13-1 through via 1408b. Furthermore, conductor 1420b is electrically coupled to conductor 1406c through via 1430c, and conductor 1406c is electrically coupled to the source of NMOS transistor N13-4 through via 1408c.

[0407] Conductor 1410a electrically couples the drains of PMOS transistors P13-3 and P13-4 and the drains of NMOS transistors N13-2 and N13-3 together. For example, the drains of PMOS transistors P13-3 and P13-4 are electrically coupled to conductor 1410a through via 1412a, and conductor 1410a is electrically coupled to the drains of NMOS transistors N13-2 and NMOS transistors N13-3 through via 1412b.

[0408] Conductor group 1460 includes at least conductors 1460a, 1460b, 1460c, 1460d, 1460e, 1460f, 1460g, or 1460h. In some embodiments, conductor group 1460 is configured as input node IN1b, input node IN2b, input node IN1c, input node IN2d, and output node OUT2 of integrated circuit 1400. For example, in some embodiments, conductor 1460c is input node IN3b, conductor 1460d is input node IN4b, conductor 1460f is input node IN2b, conductor 1460g is input node IN1b, and conductor 1460h is output node OUT2.

[0409] Conductor 1460b electrically couples together the drain of PMOS transistor P13-1, the drain of PMOS transistor P13-2, the source of PMOS transistor P13-3, and the source of PMOS transistor P13-4. For example, conductor 1460b is electrically coupled to contacts 1440e, 1440c, and 1440a through corresponding vias 1470a, 1470b, and 1470c. Contact 1440a is electrically coupled to the drain of PMOS transistor P13-4. Contact 1440c is electrically coupled to the drain of PMOS transistor P13-2 and the source of PMOS transistor P13-3. Contact 1440e is electrically coupled to the source of PMOS transistor P13-1.

[0410] Vias 1470a, 1470b, and 1470c are part of via group 1470. Via group 1470 is similar to via group 1408, but is located at the VD level, and therefore a similar detailed description is omitted. In some embodiments, one or more of the drain or source electrodes are flipped with the other.

[0411] In some embodiments, integrated circuit 1400 implements the above-mentioned... Figures 1A to 5E One or more benefits discussed in the text.

[0412] Other configurations, arrangements at other levels, or the number of conductors in integrated circuit 1400 are within the scope of this invention.

[0413] Figure 15 This is a circuit diagram of an integrated circuit 1500 according to some embodiments.

[0414] In some embodiments, integrated circuit 1500 is a trigger circuit. In some embodiments, integrated circuit 1500 is a multi-bit trigger (MBFF) circuit.

[0415] Integrated circuit 1500 is configured to receive at least a data signal D or a scan input signal SI, and is configured to output an output signal Q. In some embodiments, the data signal D is a data input signal. In some embodiments, the scan input signal SI is a scan input signal. In some embodiments, the output signal Q is at least a stored state of the data signal D or the scan input signal SI. The trigger circuit is used for illustration; other types of circuits are within the scope of this invention.

[0416] Integrated circuit 1500 includes PMOS transistors P15-1, P15-2, P15-3, P15-4, P15-5, P15-6, P15-7, P15-8, P15-9 and P15-10, NMOS transistors N15-1, N15-2, N15-3, N15-4, N15-5, N15-6, N15-7, N15-8, N15-9 and N15-10, and inverters I15-1, I15-2, I15-3, I15-4, I15-5 and I15-6.

[0417] In some embodiments, the signal sl_a is a latched version of the signal SI or Ml_ax.

[0418] In some embodiments, NMOS transistor N15-1, PMOS transistor P15-1, NMOS transistors N15-2 and N15-3, and PMOS transistors P15-2 and P15-3 form a first latch (not labeled).

[0419] The gate terminal of PMOS transistor P15-1 is configured to receive clock signal CLKBB. The gate terminal of NMOS transistor N15-1 is configured to receive clock signal CLKB.

[0420] The source terminal of PMOS transistor P15-1, the drain terminal of PMOS transistor P15-7, the drain terminal of PMOS transistor P15-9, and each of node mx1 are coupled together.

[0421] The source terminal of NMOS transistor N15-1, the drain terminal of NMOS transistor N15-7, the drain terminal of NMOS transistor N15-9, and each of node mx2 are coupled together.

[0422] The drain terminals of PMOS transistor P15-1, NMOS transistor N15-1, NMOS transistor N15-3, PMOS transistor P15-3, and the input terminal of inverter I15-1 are all coupled together.

[0423] The gate terminal of PMOS transistor P15-2 and the gate terminal of NMOS transistor N15-2 are coupled together and further coupled to at least node mx3.

[0424] The source terminal of PMOS transistor P15-2 is coupled to the voltage source VDD. The drain terminal of PMOS transistor P15-2 is coupled to the source terminal of PMOS transistor P15-3.

[0425] The gate terminal of PMOS transistor P15-3 is configured to receive clock signal CLKB. In some embodiments, the gate terminal of PMOS transistor P15-3 is coupled to at least the output terminal of inverter I15-5.

[0426] The gate terminal of NMOS transistor N15-3 is configured to receive clock signal CLKBB. In some embodiments, the gate terminal of NMOS transistor N15-3 is coupled to at least the output terminal of inverter I15-6.

[0427] The source terminal of NMOS transistor N15-3 is coupled to the drain terminal of NMOS transistor N15-2. The source terminal of transistor N15-2 is coupled to the reference voltage source VSS.

[0428] In some embodiments, inverter I15-1, transmission gate TG2, NMOS transistors N15-5 and N15-6, and PMOS transistors P15-5 and P15-6 form a second latch (not labeled).

[0429] The input terminal of inverter I15-1 is configured to receive signal Ml_ax. The output terminal of inverter I15-1 is coupled to at least node mx3 and configured to output signal M1_b to the gate of PMOS transistor P15-2, the gate of NMOS transistor N15-2, and transmission gate TG2.

[0430] Transmission gate TG2 is coupled between nodes mx3 and mx4. Transmission gate TG2 is configured to receive signal Ml_b, clock signal CLKB, and clock signal CLRBB. Transmission gate TG2 is configured to output signal S1_a to inverter I15-2, PMOS transistor P15-5, and NMOS transistor N15-5. Transmission gate TG2 includes NMOS transistor N15-4 ​​and PMOS transistor P15-4 coupled together.

[0431] The gate terminal of the PMOS transistor P15-4 is configured to receive the clock signal CLKB. The gate terminal of the NMOS transistor N15-4 ​​is configured to receive the clock signal CLRBB.

[0432] The source terminals of PMOS transistor P15-4, NMOS transistor N15-4, node mx3, the output terminal of inverter I15-1, the gate terminal of PMOS transistor P15-2, and the gate terminal of NMOS transistor N15-2 are each coupled together. In some embodiments, the drain terminals of PMOS transistor P15-4 and NMOS transistor N15-4 ​​are coupled to node mx3, the output terminal of inverter I15-1, the gate terminal of PMOS transistor P15-2, and the gate terminal of NMOS transistor N15-2.

[0433] The drain terminals of PMOS transistor P15-4, NMOS transistor N15-4, node mx4, the input terminal of inverter I15-2, and the drain terminals of NMOS transistor N15-5 and PMOS transistor P15-5 are each coupled together. In some embodiments, the source terminals of PMOS transistor P15-4 and NMOS transistor N15-4 ​​are coupled to node mx4, the input terminal of inverter I15-2, the drain terminals of NMOS transistor N15-5 and PMOS transistor P15-5.

[0434] The gate terminal of PMOS transistor P15-6 and the gate terminal of NMOS transistor N15-6 are coupled together, and further coupled to at least node mx5.

[0435] The source terminal of PMOS transistor P15-6 is coupled to the voltage source VDD. The drain terminal of PMOS transistor P15-6 is coupled to the source terminal of PMOS transistor P15-5.

[0436] The gate terminal of PMOS transistor P15-5 is configured to receive clock signal CLKBB. In some embodiments, the gate terminal of PMOS transistor P15-5 is at least coupled to the output terminal of inverter I15-6. Each of the drain terminals of PMOS transistor P15-5 and NMOS transistor N15-5 is coupled to each other and further coupled to at least node mx4.

[0437] The gate terminal of NMOS transistor N15-5 is configured to receive clock signal CLKB. In some embodiments, the gate terminal of NMOS transistor N15-5 is at least coupled to the output terminal of inverter I15-5.

[0438] The source terminal of NMOS transistor N15-5 is coupled to the drain terminal of NMOS transistor N15-6. The source terminal of transistor N15-6 is coupled to the reference voltage source VSS.

[0439] The input terminal of inverter I15-2 is coupled to at least node mx4 and configured to receive signal S1_a. The output terminal of inverter I15-2 is coupled to at least the input terminal of inverter I15-3, the gate of PMOS transistor P15-6, the gate of NMOS transistor N15-6, or node mx5 and configured to output signal Sl_bx to at least the input terminal of inverter I15-3, the gate of PMOS transistor P15-6, the gate of NMOS transistor N15-6, or node mx5.

[0440] The input terminals of inverter I15-3 are coupled to at least node mx5 and configured to receive the signal S1_bx from inverter I15-2. The output terminals of inverter I15-3 are configured to output the output signal Q.

[0441] The input terminal of inverter I15-4 is configured to receive a scan enable signal SE. The output terminal of inverter I15-4 is configured to output an inverted scan enable signal SEB. In some embodiments, the output terminal of inverter I15-4 is coupled to at least the gate terminal of PMOS transistor P15-8 or the gate terminal of NMOS transistor N15-9.

[0442] The input terminal of inverter I15-5 is configured to receive a clock signal CP. The output terminal of inverter I15-5 is configured to output a clock signal CLKB to at least the input terminal of inverter I15-6. In some embodiments, the output terminal of inverter I15-5 is coupled to at least the gate terminal of PMOS transistor P15-3, the gate terminal of NMOS transistor N15-5, the gate terminal of PMOS transistor P15-4, or the gate terminal of NMOS transistor N15-1.

[0443] The input terminal of inverter I15-6 is at least coupled to the output terminal of inverter I15-5 and configured to receive the clock signal CLKB. The output terminal of inverter I15-6 is configured to output the clock signal CLKBB. In some embodiments, the output terminal of inverter I15-6 is at least coupled to the gate terminal of PMOS transistor P15-5, the gate terminal of NMOS transistor N15-3, the gate terminal of PMOS transistor P15-1, or the gate terminal of NMOS transistor N15-4 ​​and outputs the clock signal CLKBB to at least the gate terminals of PMOS transistor P15-5, NMOS transistor N15-3, PMOS transistor P15-1, or NMOS transistor N15-4.

[0444] In some embodiments, NMOS transistors N15-7, N15-8, N15-9, and N15-10, and PMOS transistors P15-7, P15-8, P15-9, and P15-10 form a multiplexer (not labeled). In some embodiments, the positions of PMOS transistor P15-8 and signal SEB are interchanged with the positions of PMOS transistor P15-7 and signal SI, and vice versa. In some embodiments, the positions of NMOS transistor N15-8 and signal SE are interchanged with the positions of NMOS transistor N15-7 and signal SI, and vice versa.

[0445] The gate terminal of PMOS transistor P15-7 is configured to receive scan input signal SI. The gate terminal of NMOS transistor N15-7 is configured to receive scan input signal SI. In some embodiments, the gate terminal of PMOS transistor P15-7 is coupled to the gate terminal of NMOS transistor N15-7.

[0446] The source terminal of PMOS transistor P15-8 is coupled to the voltage source VDD. The drain terminal of PMOS transistor P15-8 is coupled to the source terminal of PMOS transistor P15-7.

[0447] The gate terminal of PMOS transistor P15-8 is configured to receive the inverted scan enable signal SEB.

[0448] The gate terminal of PMOS transistor P15-9 is configured to receive the scan enable signal SE. The source terminal of PMOS transistor P15-9 is coupled to the drain terminal of PMOS transistor P15-10.

[0449] The source terminal of PMOS transistor P15-10 is coupled to a voltage source VDD. The gate terminal of PMOS transistor P15-10 is configured to receive a data signal D. The gate terminal of NMOS transistor N15-10 is configured to receive a data signal D. In some embodiments, the gate terminal of PMOS transistor P15-10 is coupled to the gate terminal of NMOS transistor N15-10.

[0450] The source terminal of NMOS transistor N15-8 is coupled to the reference voltage source VSS. The drain terminal of NMOS transistor N15-8 is coupled to the source terminal of NMOS transistor N15-7.

[0451] The gate terminal of NMOS transistor N15-8 is configured to receive a scan enable signal SE. In some embodiments, the gate terminal of NMOS transistor N15-8 is coupled to the gate terminal of PMOS transistor P15-9.

[0452] The gate terminal of NMOS transistor N15-9 is configured to receive the inverted scan enable signal SEB. In some embodiments, the gate terminal of NMOS transistor N15-9 is coupled to the gate terminal of PMOS transistor P15-8. The source terminal of NMOS transistor N15-9 is coupled to the drain terminal of NMOS transistor N15-10.

[0453] The source terminal of the NMOS transistor N15-10 is coupled to the reference voltage source VSS.

[0454] In some embodiments, inverter I15-1 includes NMOS transistor N15-11 and PMOS transistor P15-11 ( Figure 15 (Not shown in the image). Inverter I15-2 includes an NMOS transistor N15-12 and a PMOS transistor P15-12 (not shown in the image). Figure 15 (Not shown in the image). Inverter I15-3 includes NMOS transistor N15-13 and PMOS transistor P15-13 (not shown in the image). Figure 15 (Not shown in the image). Inverter I15-5 includes NMOS transistor N14 and PMOS transistor P14 (…). Figure 15 (Not shown in the image). Inverter I15-6 includes an NMOS transistor N15 and a PMOS transistor P15 (not shown in the image). Figure 15 (Not shown in the image). Inverter I15-4 includes NMOS transistor N16 and PMOS transistor P16 (…). Figure 15 (Not shown in the image). In some embodiments, one or more of the drain or source electrodes are flipped with the other.

[0455] Other configurations, arrangements, or other circuits in integrated circuit 1500 are within the scope of this invention.

[0456] Figures 16A to 16C This is a top view of corresponding portions 1600A-1600C of an integrated circuit 1600 according to some embodiments.

[0457] Integrated circuit 1600 is manufactured using a corresponding layout design similar to that of integrated circuit 1600. Integrated circuit 1600 is an embodiment of integrated circuit 1500.

[0458] Figure 16A This is a top view of portion 1600A of integrated circuit 1600, simplified for ease of explanation. Portion 1600A includes one or more components of integrated circuit 1600 at the POLY, MD, M0, VG, and VD layers.

[0459] Figure 16BThis is a top view of portion 1600B of integrated circuit 1600, simplified for ease of explanation. Portion 1600B includes one or more components of integrated circuit 1600 at the OD layer, POLY layer, BM0 layer, BM1 layer, VB0 layer, and VBS / P layer of integrated circuit 1600.

[0460] Figure 16C This is a top view of portion 1600C of integrated circuit 1600, simplified for ease of illustration. Portion 1600C includes one or more components of integrated circuit 1600, including the OD layer, POLY layer, metal 1 (M1) layer, and via 0 (V0) layer. In some embodiments, the V0 layer is located between the M1 layer and the M0 layer.

[0461] Integrated Circuit 1600 is an integral part of Integrated Circuit 500 ( Figures 5A to 5E ) or Integrated Circuit 1000 ( Figures 10A to 10C ), Integrated Circuit 1200 ( Figures 12A to 12C ) or integrated circuit 1400 ( Figures 14A to 14C Variations of ), and therefore similar detailed descriptions are omitted. For example, integrated circuit 1600 shows a detailed implementation using integrated circuit 500. Figure 15 An example of a flip-flop in the integrated circuit 1500.

[0462] Integrated circuit 1600 includes at least active region groups 202 and 1602, gate groups 1604 and 1606, conductor group 1610, via group 1612, conductor group 1620, via group 1630, contact groups 1640 and 1642, conductor group 1660, via group 1670, via group 1672, conductor group 1680, and conductor group 1682. Integrated circuit 1600 is similar to integrated circuit 1400, and therefore similar detailed descriptions are omitted. In some embodiments, for brevity, items in layers similar to those of integrated circuit 1400 are not described.

[0463] exist Figures 16A to 16CIn the active region 202a, the active region corresponds to the active region (e.g., source / drain) of PMOS transistors P15-1, P15-2, P15-3, P15-7, P15-8, P15-9, P15-10 and inverter I15-6, and the active region 202b corresponds to the active region (e.g., source / drain) of NMOS transistors N15-1, N15-2, N15-3, N15-7, N15-8, N15-9, N15-10 and inverter I15-6. The active region group 1602... Active region 1602a corresponds to the active regions (e.g., source / drain) of PMOS transistors P15-4, P15-5 and P15-6 and inverters I15-1, I15-2, I15-3, I15-4 and I15-5, and active region 1602b of active region group 1602 corresponds to the active regions (e.g., source / drain) of NMOS transistors N15-4, N15-5 and N15-6 and inverters I15-1, I15-2, I15-3, I15-4 and I15-5.

[0464] Gate group 1604 includes one or more of gates 1604a, ..., 1604j. Gate group 1606 includes one or more of gates 1606a, ..., 1606i. In some embodiments, gate groups 1606 and 1608 are located on the POLY layer of integrated circuit 1600.

[0465] The conductor group 1610 includes at least conductors 1610a, 1610b, ..., 1610n. In some embodiments, the conductor group 1610 is located on the BMO layer of the integrated circuit 1600.

[0466] The via group 1612 includes one or more of vias 1612a, ..., 1612n. In some embodiments, the via group 1612 is located on the VBSP layer of the integrated circuit 1600.

[0467] Conductor group 1620 includes at least conductors 1620a, 1620b, ..., 1620e. In some embodiments, conductor group 1610 is located on the BM1 layer of integrated circuit 1600.

[0468] The via group 1630 includes one or more of vias 1630a, ..., 1630n. In some embodiments, the via group 1630 is located on the VB0 layer of the integrated circuit 1600.

[0469] Contact group 1640 includes one or more contacts 1640a, ..., 1640r. Contact group 1642 includes one or more contacts 1642a, ..., 1642n. In some embodiments, contact group 1640 or 1642 is located on the MD layer of integrated circuit 1600.

[0470] Conductor group 1660 includes one or more of 1660a, 1660b, ..., 1660u. In some embodiments, conductor group 1660 is located on the M0 layer of integrated circuit 1600.

[0471] The via group 1670 includes one or more of vias 1670a, ..., 1670j. In some embodiments, the via group 1670 is located on the VD layer of the integrated circuit 1600. In some embodiments, the via group 1670 is configured to electrically couple one or more conductors from the conductor group 1660 to the contact group 1640 or 1642, or vice versa.

[0472] Via group 1672 includes one or more of vias 1672a, ..., 1672s. In some embodiments, via group 1672 is located on the VG layer of integrated circuit 1600. In some embodiments, via group 1672 is configured to electrically couple one or more conductors in conductor group 1660 to gate group 1604 or 1606, or vice versa.

[0473] Conductor group 1680 includes one or more of 1680a, 1680b, ..., 1680u. In some embodiments, conductor group 1680 is located on the M1 layer of integrated circuit 1600. Conductor group 1680 is an M1 wiring track extending in a second direction Y. In some embodiments, conductor group 1680 is a wiring track in other metal layers. In some embodiments, one or more conductors in conductor group 1680 are configured to receive a corresponding signal (e.g., such as...). Figure 16C The input pins marked in the middle.

[0474] Via group 1682 includes one or more of vias 1682a, ..., 1682t. In some embodiments, via group 1682 is located on the V0 layer of integrated circuit 1600. Via group 1682 is configured to electrically couple one or more conductors in conductor group 1680 to conductor group 1660 and vice versa. Via group 1682 is located between conductor group 1680 and conductor group 1660.

[0475] Gate groups 1604 and 1606 correspond to one or more gates of PMOS transistors P15-1 to P15-10, NMOS transistors N15-1 to N15-10, and inverters I15-1 to I15-6 of integrated circuit 1500. In some embodiments, each gate in gate groups 1604 and 1606 is in Figures 16A to 16C Chinese identification Figure 15 Having Figures 16A to 16C The corresponding gate and corresponding transistor are shown in the diagram, and are omitted for brevity.

[0476] Conductors 1620a and 1620d are the VDD power rail, and conductor 1620b is the VSS power rail. Conductors 1620c and 1620e are signal lines.

[0477] Conductor 1620a is electrically coupled to the sources of PMOS transistors P15-10, P15-8, and P15-2, and to the source of the PMOS transistor in inverter I15-6, and is configured to provide a voltage VDD to the sources of PMOS transistors P15-10, P15-8, and P15-2, and to the source of the PMOS transistor in inverter I15-6. For example, conductor 1620a is electrically coupled to conductors 1610c, 1610d, and 1610e through corresponding vias 1630c, 1630d, and 1630e. Conductors 1610c and 1610d are coupled to the corresponding sources of PMOS transistors P15-10 and P15-8 through corresponding vias 1612c and 1612d. Conductor 1610e is coupled to the source of PMOS transistor P15-2 and the source of PMOS transistor of inverter I15-6 through via 1612e.

[0478] Conductor 1620b is electrically coupled to the sources of NMOS transistors N15-10, N15-8, and N15-2, the source of the NMOS transistor in inverter I15-6, the source of the NMOS transistors in inverters I15-3 and I15-2, the source of the NMOS transistor in inverter I15-4, the source of NMOS transistor N15-6, and the source of the NMOS transistors in inverters I15-1 and I15-5, and is configured to provide a voltage VSS to the sources of NMOS transistors N15-10, N15-8, and N15-2, the source of the NMOS transistor in inverter I15-6, the source of the NMOS transistors in inverters I15-3 and I15-2, the source of the NMOS transistor in inverter I15-4, the source of NMOS transistor N15-6, and the source of the NMOS transistors in inverters I15-1 and I15-5. For example, conductor 1620b is electrically coupled to conductors 1610f, 1610g, 1610h, 1610i, 1630j, and 1630k through corresponding vias 1630f, 1630g, 1630h, 1630i, 1630j, and 1610k. Conductors 1610f and 1610g are coupled to the corresponding sources of NMOS transistors N15-10 and N15-8 through corresponding vias 1630f and 1630g. Conductor 1610h is coupled to the source of NMOS transistor N15-2 and the source of the NMOS transistor in inverter I15-6 through via 1612h. Conductor 1610i is coupled to the source of the NMOS transistor in inverter I15-3 and the source of the NMOS transistor in inverter I15-2 through via 1612i. Conductor 1610j is coupled to the source of the NMOS transistor in inverter I15-4 and the source of NMOS transistor N15-6 through via 1612j. Conductor 1610k is coupled to the source of the NMOS transistor in inverter I15-1 and the source of the NMOS transistor in inverter I15-5 through via 1612k.

[0479] Conductor 1620d is electrically coupled to the source of the PMOS transistors in inverters I15-3, I15-2, I15-4, I15-1, and I15-5, and to the source of PMOS transistor P15-6, and provides voltage VDD to the source of the PMOS transistors in inverters I15-3, I15-2, I15-4, I15-1, and I15-5, and to the source of PMOS transistor P15-6. For example, conductor 1620d is electrically coupled to conductors 1610l, 1610m, and 1610n through corresponding vias 1630l, 1630m, and 1630n. Conductor 1610l is coupled to the source of the PMOS transistor in inverter I15-3 and the source of the PMOS transistor in inverter I15-2 through via 1612l. Conductor 1610m is coupled to the source of the PMOS transistor in inverter I15-4 and the source of the PMOS transistor in inverter I15-6 through via 1612m. Conductor 1610n is coupled to the source of the PMOS transistor in inverter I15-1 and the source of the PMOS transistor in inverter I15-5 through via 1612n.

[0480] Conductor 1620e electrically couples the drains of PMOS transistors P15-7 and P15-9 and the source of PMOS transistor P15-1 together. For example, the drains of PMOS transistors P15-7 and P15-9 are electrically coupled to conductor 1610a through via 1612a, conductor 1610a is electrically coupled to conductor 1620e through via 1630a, conductor 1620e is electrically coupled to conductor 1610b through via 1630b, and conductor 1610b is electrically coupled to the source of PMOS transistor P15-1 through via 1612b.

[0481] Conductor 1660a electrically couples the source of NMOS transistor N15-1, the drain of NMOS transistor N15-7, and the drain of NMOS transistor N15-9 together. For example, conductor 1660a is electrically coupled to contacts 1640a and 1640b through corresponding vias 1670a and 1670b. Contact 1640a is electrically coupled to the drains of NMOS transistors N15-7 and NMOS transistor N15-9. Contact 1640b is electrically coupled to the source of NMOS transistor N15-1.

[0482] In some embodiments, integrated circuit 1600 implements the above-mentioned... Figures 1A to 5E One or more benefits discussed in the text.

[0483] Other configurations, arrangements on other levels, or the number of conductors in the integrated circuit 1600 are within the scope of this invention.

[0484] Figure 17AThis is a functional flowchart of a method for manufacturing an IC device according to some embodiments. It should be understood that... Figure 17A Additional operations are performed before, during, and / or after the method described in the text 1700A, and some other processes may be described only briefly here.

[0485] In some embodiments, other orders of operation of methods 1700A-1700B are within the scope of the invention. Methods 1700A-1700B include exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be appropriately added, substituted, changed in order, and / or eliminated according to the spirit and scope of the disclosed embodiments. In some embodiments, at least one or more of the operations of methods 1700A, 1700B, 1900, or 2000 are not performed.

[0486] In some embodiments, methods 1700A-1700B are embodiments of operation 1904 of method 1900. In some embodiments, methods 1700A-1700B can be used to manufacture or produce at least integrated circuits 200, 300A-300F, 500, 700-1600, or 1800, or integrated circuits having components similar to at least layout designs 100, 400, or 600. In some embodiments, other sequences of operations of methods 1700A-1700B are within the scope of this invention. Methods 1700A-1700B include exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be appropriately added, substituted, altered in order, and / or eliminated according to the spirit and scope of the disclosed embodiments.

[0487] Figures 18A to 18F This is a cross-sectional view of an intermediate device structure obtained during the fabrication of a back-side wiring track and a back-side via connector for connecting the back-side wiring track to the source / drain terminals of a transistor, according to some embodiments. Figures 18A to 18E This is a cross-sectional view of the intermediate device structure of integrated circuit 200.

[0488] Figures 18A to 18C The device structure in the diagram corresponds to the edge of integrated circuit 200. Figure 2A The intermediate version of line A1-A1'. Figures 18D to 18F The device structure in the diagram corresponds to the edge of integrated circuit 200. Figure 2A The intermediate version of line A2-A2'.

[0489] In operation 1702 of method 1700A, a transistor array and a pseudo-via are fabricated on the front side 203a of a semiconductor wafer or substrate. In some embodiments, the transistor array of method 1700A includes one or more transistors from active region groups 202, 1602, or 1802.

[0490] In some embodiments, the device structure prepared in operation 1702 includes Figure 18A The device structure.

[0491] In some embodiments, operation 1702 includes fabricating source and drain regions of a transistor array in a first well. In some embodiments, the first well includes a p-type dopant. In some embodiments, the p-type dopant includes boron, aluminum, or other suitable p-type dopant. In some embodiments, the first well includes an epitaxial layer grown over a substrate. In some embodiments, the epitaxial layer is doped by adding a dopant during the epitaxial process. In some embodiments, the epitaxial layer is doped by ion implantation after its formation. In some embodiments, the first well is formed by doping a substrate. In some embodiments, doping is performed by ion implantation. In some embodiments, the first well has a range from 1 × 10⁻⁶. 12 atoms / cm 3 Up to 1×10 14 atoms / cm 3 The dopant concentration.

[0492] In some embodiments, the first well comprises an n-type dopant. In some embodiments, the n-type dopant comprises phosphorus, arsenic, or other suitable n-type dopant. In some embodiments, the concentration of the n-type dopant ranges from about 1 × 10⁻⁶. 12 atoms / cm 3 To approximately 1×10 14 atoms / cm 3 .

[0493] In some embodiments, the formation of the source / drain components includes: removing a portion of the substrate to form a groove at the edge of the spacer; and then performing a filling process by filling the groove in the substrate. In some embodiments, the groove is etched after removing the pad oxide layer or sacrificial oxide layer, for example, wet etching or dry etching. In some embodiments, an etching process is performed to remove the top surface portion of the active region adjacent to the isolation region (such as an STI region). In some embodiments, the filling process is performed by epitaxy or epitaxial (epi) process. In some embodiments, the groove is filled using a growth process performed concurrently with the etching process, wherein the growth rate of the growth process is greater than the etching rate of the etching process. In some embodiments, a combination of a growth process and an etching process is used to fill the groove. For example, a material layer is grown in the groove, and then the grown material is subjected to an etching process to remove a portion of the material. The etched material is then subjected to a subsequent growth process until the desired material thickness is achieved in the groove. In some embodiments, the growth process continues until the top surface of the material is above the top surface of the substrate. In some embodiments, the growth process continues until the top surface of the material is coplanar with the top surface of the substrate.

[0494] In some embodiments, a portion of the first well is removed by an isotropic or anisotropic etching process. The etching process selectively etches the first well without etching the gate structure and any spacers. In some embodiments, the etching process is performed using reactive ion etching (RIE), wet etching, or other suitable techniques.

[0495] In some embodiments, semiconductor material is deposited in a trench to form source / drain components. In some embodiments, an epitaxial process is performed to deposit semiconductor material in the trench. In some embodiments, the epitaxial process includes selective epitaxial growth (SEG), CVD, molecular beam epitaxy (MBE), other suitable processes, and / or combinations thereof. The epitaxial process uses gaseous and / or liquid precursors that interact with the composition of the substrate. In some embodiments, the source / drain components include epitaxially grown silicon (epiSi), silicon carbide, or silicon-germanium. In some cases, during the epitaxial process, the source / drain components of the IC device associated with the gate structure are in-situ doped or undoped. When the source / drain components are undoped during the epitaxial process, in some cases, the source / drain components are doped during subsequent processes. Subsequent doping processes are implemented by ion implantation, plasma immersion ion implantation, gas and / or solid source diffusion, other suitable processes, and / or combinations thereof. In some embodiments, the source / drain components are further exposed to an annealing process after the source / drain components are formed and / or after a subsequent doping process.

[0496] In some embodiments, operation 1702 further includes contacts forming a transistor group (e.g., contact group 1040, 1240, 1440, or 1640). In some embodiments, operation 1702 further includes a gate region 1804 forming a transistor group. In some embodiments, the gate region is located between a drain region and a source region. In some embodiments, the gate region is located over a first well and a substrate. In some embodiments, fabricating the gate region of operation 1702 includes performing one or more deposition processes to form one or more dielectric material layers. In some embodiments, the deposition processes include chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other processes suitable for depositing one or more material layers. In some embodiments, fabricating the gate region includes performing one or more deposition processes to form one or more conductive material layers. In some embodiments, fabricating the gate region includes forming a gate electrode or a dummy gate electrode. In some embodiments, fabricating the gate region includes depositing or growing at least one dielectric layer, such as a gate dielectric. In some embodiments, the gate region is formed using doped or undoped polysilicon (or polysilicon). In some embodiments, the gate region comprises a metal, such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof.

[0497] exist Figure 18A In the cross-sectional view, source region 1802a and drain region 1802b are part of the active region 1802 of an n-type or p-type transistor and are formed on the front side 203a of substrate 1890. The front side 203a of substrate 1890 is located above a portion 1890b of substrate 1890. A pseudo-via structure 1894 is formed in the portion 1890b of substrate 1890 located below the active region 1802. Gate structures 1804a, 1804b, and 1804c are formed above the active region 1802 on the front side 203a of substrate 1890. In some embodiments, pseudo-via 1894 is an insulating layer. In some embodiments, pseudo-via 1894 is photoresist and is deposited in a groove of the wafer during a spin-coating process.

[0498] In operation 1704 of method 1700A, thinning is performed on the back side 203b of the wafer or substrate 1890. In some embodiments, operation 1704 includes a thinning process performed on the back side 203b of the semiconductor wafer or substrate 1890. In some embodiments, the thinning process includes grinding operations and polishing operations (such as chemical mechanical polishing (CMP)) or other suitable processes. In some embodiments, after the thinning process, a wet etching operation is performed to remove defects formed on the back side 203b of the semiconductor wafer or substrate 1890.

[0499] exist Figure 18B In the cross-sectional view, a portion of 1890a is removed through thinning operation 1704, thereby exposing the top surface 1894a of the pseudo-through hole 1894. Figure 18C In the cross-sectional view, a portion of 1890b is also removed by the thinning operation 1704, thereby exposing the back side of the wafer or substrate 1890.

[0500] In operation 1706 of method 1700A, a first group of conductors and a first group of vias are formed on the back side 203b of a wafer or substrate on a first level (e.g., BMO). In some embodiments, operation 1706 includes depositing a first group of conductive regions at least above the back side of the integrated circuit. In some embodiments, method 1700B is an embodiment of operation 1706.

[0501] In some embodiments, the first conductor group of method 1700A includes one or more portions of at least conductor groups 206, 210, 310, 312, 314, 316, 1006, 1206, 1406, 1410, 1606, 1610, or 1810. In some embodiments, the first via group of method 1700A includes one or more portions of at least via groups 208, 212, 1008, 1208, 1408, 1412, 1608, 1612, or 1812. In some embodiments, operation 1706 includes forming a first self-aligned contact (SAC) group in an insulating layer above the wafer back side 203b.

[0502] In operation 1708 of method 1700A, a second via group is formed on the back side 203b of the wafer or substrate opposite the front side 203a. In some embodiments, the second via group of method 1700A includes portions of at least one or more of via groups 230, 1030, 1230, 1430, or 1630. In some embodiments, operation 1708 includes forming a second SAC group in an insulating layer above the back side of the wafer.

[0503] In operation 1710 of method 1700A, conductive material is deposited on the back side 203b of a wafer or substrate on a second level (e.g., BM1) of the integrated circuit to form a second set of conductive structures. In some embodiments, operation 1710 further includes forming at least a set of power rails and a set of signal lines.

[0504] In some embodiments, the second conductive structure group of method 1700A includes portions of at least one or more of conductor groups 120, 420, 320, 620, 820, 1020, 1220, 1420, or 1620.

[0505] In some embodiments, one or more of operations 1706, 1708, or 1710 of method 1700A include using a combination of photolithography and material removal processes to form an opening in an insulating layer (not shown) above a substrate. In some embodiments, the photolithography process includes patterning a photoresist, such as a positive or negative photoresist. In some embodiments, the photolithography process includes forming a hard mask, an anti-reflective structure, or another suitable photolithographic structure. In some embodiments, the material removal process includes a wet etching process, a dry etching process, a RIE process, laser drilling, or another suitable etching process. The opening is then filled with a conductive material, such as copper, aluminum, titanium, nickel, tungsten, or other suitable conductive materials. In some embodiments, CVD, PVD, sputtering, ALD, or other suitable formation processes are used to fill the opening.

[0506] In some embodiments, at least one or more operations of method 1700A or 1700B are performed via Figure 22 The system 2200 is used for implementation. In some embodiments, at least one method (such as method 1700A discussed above or method 1700B discussed below) is implemented wholly or partially by at least one manufacturing system including system 2200. One or more of the operations of method 1700A or 1700B are carried out by IC manufacturing plant 2240 ( Figure 22 The process is implemented to manufacture IC device 2260. In some embodiments, one or more of the operations of method 1700A are implemented using manufacturing tool 2252 to manufacture wafer 2242.

[0507] Figure 17B This is a flowchart illustrating a method 1700B for fabricating a first conductor group and a first via on the back side of an integrated circuit according to some embodiments.

[0508] In some embodiments, the first conductor group of method 1700A includes one or more portions of at least conductor groups 206, 210, 310, 312, 314, 316, 1006, 1206, 1406, 1410, 1606, 1610, or 1810. In some embodiments, the first via group of method 1700A includes one or more portions of at least via groups 208, 212, 1008, 1208, 1408, 1412, 1608, 1612, or 1812.

[0509] In some embodiments, method 1700B is an embodiment of operation 1706 of method 1700A.

[0510] In operation 1720 of method 1700B, an insulating layer 1840 is deposited on the back side 203b of the wafer or substrate. In some embodiments, the insulating layer 1840 electrically isolates the underlying layer from one or more upper layers deposited in at least one or more of operations 1708, 1710, 1722, 1724, or 1726. In some embodiments, the insulating layer 1840 covers the back side 203b of the substrate but exposes the top surface 1894a of the pseudo-via 1864.

[0511] In some embodiments, the insulating layer 1840 is a dielectric material. In some embodiments, the dielectric material includes silicon dioxide, silicon oxynitride, etc.

[0512] exist Figure 18C In the cross-sectional view, the insulating layer 1840 covers the back side 203b of the wafer or substrate 1890, but the top surface 1894a of the pseudo-via 1864 is exposed.

[0513] In operation 1722 of method 1700B, a hard mask 1852 is deposited on insulating layer 1840. In some embodiments, operation 1722 further includes removing pseudo vias 1864 to form trenches 1844 in hard mask 1852 and insulating layer 1840. In some embodiments, hard mask 1852 electrically isolates the underlying layer from one or more upper layers deposited in at least one or more of operations 1708, 1710, or 1726.

[0514] In some embodiments, the hard mask 1852 comprises amorphous carbon or silicon. In some embodiments, the hard mask 1852 comprises silicon carbide, silicon nitride, silicon oxynitride, etc. In some embodiments, the hard mask 1852 is deposited by CVD or some other deposition technique compatible with method 1700B. Other hard mask materials compatible with methods 1700A-1700B are also included within the scope of this invention. In some embodiments, after the hard mask is formed, the back side 203b is planarized to provide a layered surface for subsequent steps.

[0515] exist Figure 18D In the cross-sectional view, the trench 1844 is formed in the hard mask 1852 and the insulating layer 1840, and the top surface 1802a1 of the active region 1802a is exposed.

[0516] In operation 1724 of method 1700B, the lateral portion of the hard mask 1852 is removed by directional etching. In some embodiments, operation 1724 causes the hard mask 1852 to have an opening 1846 in the second direction Y that is larger than the trench 1844 formed in the insulating layer 1850. In some embodiments, the directional etching of operation 1724 includes a plasma etching process that includes an etchant gas, such as chlorine, fluorine, etc.

[0517] exist Figure 18D In the cross-sectional view, the opening 1846 formed in the hard mask 1852 has a length L1 or width BM0 in the second direction Y. HW1b .exist Figure 18D In the cross-sectional view, the trench 1844 formed in the insulating layer 1850 has a width BVB in the second direction Y. W1b .

[0518] In operation 1726 of method 1700B, a conductive material is deposited in trenches within insulating layer 1850 and openings 1846 within hard mask 1852. In some embodiments, the conductive material includes copper, aluminum, titanium, nickel, tungsten, or other suitable conductive materials. In some embodiments, CVD, PVD, sputtering, ALD, or other suitable formation processes are used to fill the openings and trenches. In some embodiments, after depositing the conductive material in operation 1726, the conductive material is planarized to provide a layered surface for subsequent steps.

[0519] In some embodiments, one or more of the operations of methods 1700A, 1700B, 1900, or 2000 are not performed.

[0520] One or more of the operations of methods 1900-2000 are implemented by a processing device configured to execute instructions for manufacturing integrated circuits (such as at least integrated circuits 200, 300A-300F, 500, 700-1600, or 1800). In some embodiments, one or more operations of methods 1900-2000 are implemented using the same processing device as that used in one or more different operations of methods 1900-2000. In some embodiments, a processing device different from the processing device used to implement one or more different operations of methods 1900-2000 is used to implement one or more operations of methods 1900-2000. In some embodiments, the order of other operations of methods 1700A, 1700B, 1900, or 2000 is within the scope of this invention. Methods 1700A, 1700B, 1900, or 2000 include exemplary operations, but these operations are not necessarily implemented in the order shown. In accordance with the spirit and scope of the disclosed embodiments, operations in methods 1700A, 1700B, 1900 or 2000 may be appropriately added, replaced, changed in order and / or eliminated.

[0521] Figure 19 This is a flowchart of a method 1900 for forming or manufacturing an integrated circuit according to some embodiments. It should be understood that... Figure 19Additional operations are performed before, during, and / or after the method 1900 described herein, and only a few other operations may be briefly described herein. In some embodiments, method 1900 can be used to form integrated circuits, such as at least integrated circuits 200, 300A-300F, 500, 700-1600, or 1800. In some embodiments, method 1900 can be used to form integrated circuits having similar component and structural relationships to one or more of layout designs 100, 400, or 600.

[0522] In operation 1902 of method 1900, a layout design for an integrated circuit is generated. Operation 1902 is performed by a processing device (e.g., processor 2102) configured to execute instructions for generating the layout design. Figure 21 )) Implementation. In some embodiments, the layout design of method 1900 includes one or more patterns of at least layout design 100, 400, or 600, or one or more components similar to at least integrated circuit 200, 300A-300F, 500, 700-1600, or 1800. In some embodiments, the layout design of this application is a Graphical Database System (GDSII) file format.

[0523] In operation 1904 of method 1900, the integrated circuit is manufactured based on a layout design. In some embodiments, operation 1904 of method 1900 includes manufacturing at least one mask based on a layout design, and manufacturing the integrated circuit based on the at least one mask.

[0524] Figure 20 This is a flowchart of a method 2000 for generating an integrated circuit layout design according to some embodiments. It should be understood that... Figure 20 Additional operations are performed before, during, and / or after method 2000 as depicted herein, and only a few other processes may be briefly described herein. In some embodiments, method 2000 is an embodiment of operation 1902 of method 1900. In some embodiments, method 2000 can be used to generate one or more layout patterns of at least layout designs 100, 400, or 600, or one or more components similar to at least integrated circuits 200, 300A-300F, 500, 700-1600, or 1800.

[0525] In some embodiments, method 2000 can be used to generate one or more layout patterns having structural relationships of configuration and layers including alignment, length and width, and at least layout design 100, 400, or 600, or similar to one or more components of at least integrated circuit 200, 300A-300F, 500, 700-1600, or 1800, and for simplicity, Figure 20 The lieutenant general will no longer provide similar detailed descriptions.

[0526] In operation 2002 of method 2000, an active region pattern group is generated or placed on a layout design. In some embodiments, the active region pattern group of method 2000 includes at least a portion of one or more patterns of active region pattern group 102. In some embodiments, the active region pattern group of method 2000 includes one or more regions similar to active region group 1602.

[0527] In operation 2004 of method 2000, a first gate pattern set is generated or placed in a layout design. In some embodiments, the first gate pattern set of method 2000 includes at least a portion of one or more patterns of gate group 104. In some embodiments, the first gate pattern set of method 2000 includes one or more gates similar to at least gate group 1004, 1204, 1404, or 1604.

[0528] In operation 2006 of method 2000, a first conductive pattern set is generated or placed on a layout design. In some embodiments, the first conductive pattern set of method 2000 includes at least a portion of one or more patterns of at least conductive pattern set 106 or 110.

[0529] In some embodiments, the first conductive pattern group of method 2000 includes one or more conductors similar to at least conductor groups 310, 312, 314, 316, 1006, 1206, 1406, 1410, 1606, or 1610. In some embodiments, the first conductive pattern group of method 2000 includes one or more conductors similar to at least conductors in a BMO layer.

[0530] In some embodiments, the first conductive pattern group of method 2000 includes at least a portion of one or more patterns of at least conductive pattern group 160. In some embodiments, the first conductive pattern group of method 2000 includes one or more conductors similar to at least conductor group 1060, 1260, 1460 or 1660.

[0531] In some embodiments, the first conductive pattern group of method 2000 includes one or more contacts similar to at least contact groups 1040, 1240, 1440, or 1640. In some embodiments, the first conductive pattern group of method 2000 includes one or more conductors similar to at least contacts in an MD layer.

[0532] In operation 2008 of method 2000, a first via pattern group is generated or placed on a layout design. In some embodiments, the first via pattern group of method 2000 includes at least a portion of one or more patterns of via pattern group 108 or 112. In some embodiments, the first via pattern group of method 2000 includes one or more patterns similar to at least via group 1008, 1208, 1408, 1412, 1608 or 1612.

[0533] In some embodiments, the first via pattern group of method 2000 includes one or more patterns similar to at least via group 1270, 1470, or 1670. In some embodiments, the first via pattern group of method 2000 includes one or more vias similar to at least vias in a VG or VD layer.

[0534] In operation 2010 of method 2000, a power rail pattern group is generated or placed in the layout design.

[0535] In some embodiments, the power rail pattern set of method 2000 includes at least a portion of one or more patterns of conductive pattern sets 120, 420, or 620. In some embodiments, the power rail pattern set of method 2000 includes at least a portion of one or more patterns of conductive patterns 120a, 120b, 420a, 420b, 620a, or 620b.

[0536] In some embodiments, the power rail pattern set of method 2000 includes one or more patterns similar to at least conductor groups 320, 820, 1020, 1220, 1420, or 1620. In some embodiments, the power rail pattern set of method 2000 includes one or more patterns similar to at least conductors 320a, 320b, 820a, 820b, 1020a, 1020b, 1220a, 1220b, 1420a, 1420b, 1620b, or 1620b.

[0537] In operation 2012 of method 2000, a group of signal line patterns is generated or placed on a layout design. In some embodiments, the group of signal line patterns in method 2000 includes at least a portion of one or more patterns of conductive pattern groups 120, 420, or 620. In some embodiments, the group of signal line patterns in method 2000 includes at least a portion of one or more patterns of conductive patterns 120c, 420c, or 620c.

[0538] In some embodiments, the signal line pattern set of method 2000 includes one or more patterns similar to at least conductor groups 320, 820, 1020, 1220, 1420, or 1620. In some embodiments, the signal line pattern set of method 2000 includes one or more patterns similar to at least conductors 320c, 820c, 1020c, 1220c, 1420c, 1620c, or 1620e.

[0539] In operation 2014 of method 2000, a second via pattern group is generated or placed on a layout design. In some embodiments, the second via pattern group of method 2000 includes at least a portion of one or more patterns of via pattern group 130.

[0540] In some embodiments, the second via pattern group of method 2000 includes one or more patterns similar to at least via group 1030, 1230, 1430, or 1630. In some embodiments, the second via pattern group of method 2000 includes one or more vias similar to at least vias in a VB0 layer.

[0541] Figure 21 This is a schematic diagram of a system 2100 for designing IC layout and manufacturing IC circuits according to some embodiments.

[0542] In some embodiments, system 2100 generates or places one or more IC layout designs described herein. System 2100 includes a hardware processor 2102 and a non-transitory computer-readable storage medium 2104 (e.g., memory 2104) encoded with, i.e., storing computer program code 2106, i.e., a set of executable instructions 2106. Computer-readable storage medium 2104 is configured to interface with a manufacturing machine for producing integrated circuits. Processor 2102 is electrically coupled to computer-readable storage medium 2104 via bus 2108. Processor 2102 is also electrically coupled to I / O interface 2110 via bus 2108. Network interface 2112 is also electrically connected to processor 2102 via bus 2108. Network interface 2112 is connected to network 2114, enabling processor 2102 and computer-readable storage medium 2104 to be connected to external components via network 2114. Processor 2102 is configured to execute computer program code 2106 encoded in computer-readable storage medium 2104 so that system 2100 can be used to perform some or all of the operations as described in methods 1900-2000.

[0543] In some embodiments, processor 2102 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0544] In some embodiments, the computer-readable storage medium 2104 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 2104 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In some embodiments using optical disk, the computer-readable storage medium 2104 includes optical disk-read-only memory (CD-ROM), optical disk-read / write device (CD-R / W), and / or digital video optical disk (DVD).

[0545] In some embodiments, storage medium 2104 stores computer program code 2106 configured to cause system 2100 to implement methods 1900-2000. In some embodiments, storage medium 2104 also stores information required to implement methods 1900-2000, as well as information generated during the implementation of methods 1900-2000, such as layout design 2116, user interface 2118, and manufacturing unit 2120 and / or executable instruction sets to implement the operation of methods 1900-2000. In some embodiments, layout design 2116 includes a layout pattern of at least layout design 100, 400, or 600, or one or more components similar to at least integrated circuit 200, 300A-300F, 500, 700-1600, or 1800.

[0546] In some embodiments, storage medium 2104 stores instructions (e.g., computer program code 2106) for interfacing with a manufacturing machine. The instructions (e.g., computer program code 2106) enable processor 2102 to generate manufacturing instructions readable by the manufacturing machine to efficiently implement methods 1900-2000 during the manufacturing process.

[0547] System 2100 includes an I / O interface 2110. The I / O interface 2110 is coupled to external circuitry. In some embodiments, the I / O interface 2110 includes a keyboard, keypad, mouse, trackball, touchpad, and / or cursor arrow keys for transmitting information and commands to processor 2102.

[0548] System 2100 also includes a network interface 2112 coupled to processor 2102. Network interface 2112 allows system 2100 to communicate with network 2114, where one or more other computer systems are connected. Network interface 2112 includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-2094. In some embodiments, methods 1900-2000 are implemented in two or more systems 2100, and information such as layout design and user interface is exchanged between different systems 2100 via network 2114.

[0549] System 2100 is configured to receive information related to a layout design via I / O interface 2110 or network interface 2112. The information is transmitted via bus 2108 to processor 2102 to determine a layout design for manufacturing at least integrated circuits 200, 300A-300F, 500, 700-1600, or 1800. The layout design is then stored as layout design 2116 in computer-readable medium 2104. System 2100 is configured to receive information related to a user interface via I / O interface 2110 or network interface 2112. The information is stored as user interface 2118 in computer-readable medium 2104. System 2100 is configured to receive information related to a manufacturing unit 2120 via I / O interface 2110 or network interface 2112. The information is stored as manufacturing unit 2120 in computer-readable medium 2104. In some embodiments, manufacturing unit 2120 includes manufacturing information utilized by system 2100. In some embodiments, manufacturing unit 2120 corresponds to... Figure 22 Mask manufacturing 2234.

[0550] In some embodiments, methods 1900-2000 are implemented as a standalone software application executed by a processor. In some embodiments, methods 1900-2000 are implemented as a software application as part of an additional software application. In some embodiments, methods 1900-2000 are implemented as a plug-in to a software application. In some embodiments, methods 1900-2000 are implemented as a software application as part of an EDA tool. In some embodiments, methods 1900-2000 are implemented as a software application used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout of an integrated circuit device. In some embodiments, the layout is stored on a non-transitory computer-readable medium. In some embodiments, a method such as that available from CADENCE DESIGN SYSTEMS, Inc. is used. Tools or other suitable layout generation tools are used to generate the layout. In some embodiments, the layout is generated based on a netlist created from a schematic design. In some embodiments, methods 1900-2000 are implemented by manufacturing a device to manufacture an integrated circuit using a mask set manufactured based on one or more layout designs generated by system 2100. In some embodiments, system 2100 is a manufacturing device configured to manufacture an integrated circuit using a mask set manufactured based on one or more layout designs of the present invention. Figure 21 The system 2100 generates a layout design for an integrated circuit that is smaller than other methods. In some embodiments, Figure 21 The System 2100 generates a layout design for integrated circuit structures that, compared to other methods, occupies less area and provides better routing resources.

[0551] Figure 22 This is a block diagram of an integrated circuit (IC) manufacturing system 2200 and its associated IC manufacturing process according to at least one embodiment of the present invention. In some embodiments, based on the layout diagram, the manufacturing system 2200 is used to manufacture (A) one or more semiconductor masks or (B) at least one component in a semiconductor integrated circuit layer.

[0552] exist Figure 22 In this system, IC manufacturing system 2200 (hereinafter referred to as "System 2200") includes entities that interact with each other throughout the design, development, and manufacturing cycles, such as design room 2220, mask room 2230, and IC manufacturing plant / manufacturer ("fab") 2240 and / or services related to the manufacture of IC devices 2260. Entities in System 2200 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, one or more of design room 2220, mask room 2230, and IC manufacturing plant 2240 are owned by a single, larger company. In some embodiments, one or more of design room 2220, mask room 2230, and IC manufacturing plant 2240 coexist in a shared facility and use shared resources.

[0553] Design studio (or design team) 2220 generates IC design layout 2222. IC design layout 2222 includes various geometric patterns designed for IC device 2260. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 2260 to be manufactured. The layers combine to form various IC components. For example, portions of IC design layout 2222 include various IC components formed in a semiconductor substrate (such as a silicon wafer), such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads, as well as various material layers disposed on the semiconductor substrate. Design studio 2220 implements appropriate design procedures to form IC design layout 2222. Design procedures include one or more of logic design, physical design, or place-and-route. IC design layout 2222 is presented in one or more data files containing information about the geometric patterns. For example, IC design layout 2222 may be represented in GDSII or DFII file format.

[0554] Mask chamber 2230 includes data preparation 2232 and mask fabrication 2234. Mask chamber 2230 uses an IC design layout 2222 to fabricate one or more masks 2245 for fabricating various layers of an IC device 2260 according to the IC design layout 2222. Mask chamber 2230 performs mask data preparation 2232, in which the IC design layout 2222 is converted into a representative data file (RDF). Mask data preparation 2232 provides the RDF to mask fabrication 2234. Mask fabrication 2234 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (intermediate mask) 2245 or a semiconductor wafer 2242. Mask data preparation 2232 manipulates the design layout 2222 to conform to the specific characteristics of the mask writer and / or the requirements of IC fabrication 2240. Figure 22 In this diagram, mask data preparation 2232 and mask manufacturing 2234 are shown as separate elements. In some embodiments, mask data preparation 2232 and mask manufacturing 2234 may be collectively referred to as mask data preparation.

[0555] In some embodiments, mask data preparation 2232 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors such as those that may be caused by diffraction, interference, or other process effects. OPC adjusts the IC design layout 2222. In some embodiments, mask data preparation 2232 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution aids, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as a reverse imaging problem.

[0556] In some embodiments, mask data preparation 2232 includes a mask rule checker (MRC) that checks the IC design layout that has undergone processes in the OPC using a set of mask creation rules that include specific geometric and / or connectivity constraints to ensure sufficient margin to address variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout to compensate for constraints during mask fabrication 2234, which may eliminate some modifications implemented in the OPC to meet the mask creation rules.

[0557] In some embodiments, mask data preparation 2232 includes a lithography process check (LPC), which simulates the process performed by IC fabrication plant 2240 to manufacture IC device 2260. The LPC simulates this process based on IC design layout 2222 to create a simulated manufactured device such as IC device 2260. Processing parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, or combinations thereof. In some embodiments, after creating a simulated manufactured device via LPC, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC will be repeated to further improve IC design layout 2222.

[0558] It should be understood that, for clarity, the above description of mask data preparation 2232 has been simplified. In some embodiments, data preparation 2232 includes additional features such as logic operations (LOPs) to modify the IC design layout according to manufacturing rules. Furthermore, the processes applied to the IC design layout 2222 during data preparation 2232 can be performed in various different sequences.

[0559] Following mask data preparation 2232 and during mask fabrication 2234, a mask 2245 or mask set 2245 is fabricated based on a modified IC design layout 2222. In some embodiments, mask fabrication 2234 includes performing one or more photolithographic exposures based on the IC design 2222. In some embodiments, a mechanism of electron beams (e-beams) or multiple electron beams is used to pattern the mask (photomask or intermediate mask) 2245 based on the modified IC design layout 2222. Various techniques can be employed to form the mask 2245. In some embodiments, a binary technique is used to form the mask 2245. In some embodiments, the mask pattern includes opaque regions and transparent regions. Radiation beams (such as ultraviolet (UV) beams) used to expose an image-sensitive material layer (e.g., photoresist) already coated on the wafer are blocked by the opaque regions and pass through the transparent regions. In one example, a binary mask version of the mask 2245 includes a transparent substrate (e.g., quartz glass) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, a phase-shifting technique is used to form mask 2245. In the phase-shifting mask (PSM) version of mask 2245, the individual components in the pattern formed on the phase-shifting mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase-shifting mask can be an attenuation-type PSM or an alternating-type PSM. The mask generated by mask fabrication 2234 is used in various processes. For example, such a mask is used in ion implantation processes to form various doped regions in a semiconductor wafer, in etching processes to form various etched regions in a semiconductor wafer, and / or in other suitable processes.

[0560] IC manufacturing plant 2240 is an IC manufacturing entity that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC manufacturing plant 2240 is a semiconductor foundry. For example, there may be manufacturing facilities for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility may provide back-end manufacturing (back-end process (BEOL) manufacturing) for interconnecting and packaging IC products, and a third manufacturing facility may provide other services for the foundry entity.

[0561] IC manufacturing plant 2240 includes wafer fabrication tool 2252 (hereinafter referred to as "manufacturing tool 2252") configured to perform various manufacturing operations on semiconductor wafer 2242, thereby enabling IC device 2260 to be manufactured according to a mask (e.g., mask 2245). In various embodiments, manufacturing tool 2252 includes one or more of the following: wafer stepper, ion implanter, photoresist coater, process chamber, such as a CVD chamber or LPCVD furnace, CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of implementing one or more suitable manufacturing processes as discussed herein.

[0562] IC manufacturing plant 2240 uses masks (or multiple masks) 2245 manufactured by mask chamber 2230 to manufacture IC devices 2260. Therefore, IC manufacturing plant 2240 at least indirectly uses IC design layout 2222 to manufacture IC devices 2260. In some embodiments, semiconductor wafers 2242 are manufactured by IC manufacturing plant 2240 using masks (or multiple masks) 2245 to form IC devices 2260. In some embodiments, IC manufacturing includes performing one or more photolithographic exposures at least indirectly based on IC design 2222. Semiconductor wafer 2242 includes a silicon substrate or other suitable substrate on which material layers are formed. Semiconductor wafer 2242 also includes one or more of various doped regions, dielectric components, multilayer interconnects, etc. (formed in subsequent manufacturing steps).

[0563] System 2200 is shown as having a design room 2220, a mask room 2230, or an IC manufacturing plant 2240 as different components or entities. However, it should be understood that one or more of the design room 2220, mask room 2230, or IC manufacturing plant 2240 are part of the same component or entity.

[0564] For example, the following patents contain information about integrated circuit (IC) manufacturing systems (e.g., Figure 22 The details of System 2200 and its related IC manufacturing processes are incorporated herein by reference in the entirety of U.S. Patent No. 9,256,709, granted February 9, 2016; U.S. Patent Pre-Publication No. 20150278429, published October 1, 2015; U.S. Patent Pre-Publication No. 20100040838, published February 6, 2014; and U.S. Patent No. 7,260,442, granted August 21, 2007.

[0565] One aspect of this specification relates to integrated circuits. In some embodiments, the integrated circuit includes a power rail group, an active region group, a first conductor group, and a first via group and a second via group. In some embodiments, the power rail group extends in a first direction, is configured to provide a first supply voltage or a second supply voltage, and is located on a first layer on the back side of a substrate. In some embodiments, the active region group extends in the first direction and is located on a second layer on the front side of the substrate opposite to the back side, the second layer being different from the first layer, and the active region group overlapping the power rail group. In some embodiments, the first conductor group extends in a second direction different from the first direction, is located on a third layer on the back side of the substrate, the third layer being different from the first and second layers, and overlapping the active region group. In some embodiments, the first via group is located between the active region group and the first conductor group, electrically coupling the active region group to the first conductor group. In some embodiments, the second via group is located between the first conductor group and the power rail group, electrically coupling the first conductor group and the power rail group.

[0566] Another aspect of this specification relates to integrated circuits. In some embodiments, the integrated circuit includes a first power rail, a second power rail, a first signal line, a first active region, a second active region, and a first conductive line. In some embodiments, the first power rail extends in a first direction, is configured to provide a first supply voltage, and is located on a first layer on the back side of a substrate. In some embodiments, the second power rail extends in the first direction, is configured to provide a second supply voltage different from the first supply voltage, and is located on the first layer and separated from the first power rail in a second direction different from the first direction. In some embodiments, the first signal line extends in the first direction, is located on the first layer, and is located between the first and second power rails. In some embodiments, the first active region extends in the first direction and is located on a second layer on the front side of the substrate opposite to the back side, the second layer being different from the first layer, and the first active region overlaps with and is electrically coupled to the first power rail. In some embodiments, the second active region extends in the first direction, is located on the second layer, is separated from the first active region in the second direction, and overlaps with and is electrically coupled to the second power rail. In some embodiments, the first conductor extends in a second direction and is located on a third layer on the back side of the substrate. The third layer is different from the first and second layers, overlaps with the first and second active regions, and electrically couples the first and second active regions to the first signal line.

[0567] Another aspect of this specification relates to a method of manufacturing an integrated circuit. In some embodiments, the method includes: fabricating a transistor group and pseudo-vias in a front side of a substrate; thinning a back side of the substrate opposite to the front side; fabricating a first via group and a first conductor group on the back side of the thinned substrate at a first level, the first conductor group being electrically coupled to the transistor group through the first via group; fabricating a second via group on the back side of the thinned substrate; and depositing a conductive material on the back side of the thinned substrate at a second level to form a second conductor group, the second conductor group being electrically coupled to the first conductor group through the second via group.

[0568] Some embodiments of this application provide an integrated circuit, including: a power rail group extending in a first direction, configured to provide a first supply voltage or a second supply voltage, and located on a first layer on the back side of a substrate; an active region group extending in the first direction and located on a second layer on the front side of the substrate opposite to the back side, the second layer being different from the first layer, and the active region group overlapping the power rail group; a first conductor group extending in a second direction different from the first direction, located on a third layer on the back side of the substrate, the third layer being different from the first layer and the second layer, and overlapping the active region group; a first via group located between the active region group and the first conductor group, the first via group electrically coupling the active region group to the first conductor group; and a second via group located between the first conductor group and the power rail group, the second via group electrically coupling the first conductor group and the power rail group.

[0569] In some embodiments, the active region group includes: a first active region extending in the first direction; and a second active region extending in the first direction and spaced apart from the first active region in the second direction. In some embodiments, the power rail group includes: a first power rail extending in the first direction, configured to provide the first supply voltage to the first active region and overlapping the first active region; and a second power rail extending in the first direction, configured to provide the second supply voltage to the second active region, overlapping the second active region and spaced apart from the first power rail in the second direction. In some embodiments, the first conductor group includes: a first conductor extending in the second direction, overlapping the first active region and the first power rail; and a second conductor extending in the second direction, overlapping the second active region and the second power rail. In some embodiments, the first via group includes: a first via located between the first active region and the first conductor, the first via electrically coupling the first active region to the first conductor; and a second via located between the second active region and the second conductor, the second via electrically coupling the second active region to the second conductor. In some embodiments, the second via group includes: a third via located between the first conductor and the first power rail, the third via electrically coupling the first conductor to the first power rail; and a fourth via located between the second conductor and the second power rail, the fourth via electrically coupling the second conductor to the second power rail. In some embodiments, the integrated circuit further includes: a first conductor extending at least in the first direction or the second direction, located on the third layer on the back side of the substrate, overlapping the first active region and the second active region. In some embodiments, the integrated circuit further includes: a third via located between the first drain / source of the first active region and the first conductor, the third via electrically coupling the first drain / source of the first active region to the first conductor; and a fourth via located between the second drain / source of the second active region and the first conductor, the fourth via electrically coupling the second drain / source of the second active region to the first conductor. In some embodiments, the integrated circuit further includes: a gate group extending in the second direction on a fourth level on the front side of the substrate, the fourth level being different from the first level, the second level and the third level, and overlapping the active region group.

[0570] Other embodiments of this application provide an integrated circuit including: a first power rail extending in a first direction, configured to provide a first supply voltage and located on a first layer on the back side of a substrate; a second power rail extending in the first direction, configured to provide a second supply voltage different from the first supply voltage, and the second power rail being located on the first layer and separated from the first power rail in a second direction different from the first direction; a first signal line extending in the first direction, located on the first layer, and located between the first power rail and the second power rail; and a first active region extending in the first direction and located on the front side of the substrate opposite to the back side. On the second layer, the second layer is different from the first layer, and the first active region overlaps with and is electrically coupled to the first power rail; the second active region extends in the first direction, is located on the second layer, is separated from the first active region in the second direction, overlaps with and is electrically coupled to the second power rail; and the first conductor extends in the second direction, is located on the third layer on the back side of the substrate, the third layer is different from the first and second layers, overlaps with the first and second active regions, and electrically couples the first and second active regions to the first signal line.

[0571] In some embodiments, the integrated circuit further includes: a second conductor extending in the second direction, located on the third layer, overlapping the first active region and the second active region, separated from the first conductor in the first direction, and further electrically coupling the first active region and the second active region to the first signal line. In some embodiments, the integrated circuit further includes: a first via located between a first drain / source of the first active region and the first conductor, the first via electrically coupling the first drain / source of the first active region to the first conductor; and a second via located between a second drain / source of the first active region and the second conductor, the second via electrically coupling the second drain / source of the second active region to the second conductor. In some embodiments, the integrated circuit further includes: a third via located between the first conductor and the first signal line, the third via electrically coupling the first conductor to the first signal line; and a fourth via located between the second conductor and the first signal line, the fourth via electrically coupling the second conductor to the first signal line. In some embodiments, the integrated circuit further includes: a first conductor extending at least in the first direction or the second direction, located on the third level on the back side of the substrate, overlapping the first active region and the second active region. In some embodiments, the integrated circuit further includes: a first via located between a first drain / source of the first active region and the first conductor, the first via electrically coupling the first drain / source of the first active region to the first conductor; and a second via located between a second drain / source of the second active region and the first conductor, the second via electrically coupling the second drain / source of the second active region to the first conductor. In some embodiments, the integrated circuit further includes: a second wire extending in the second direction, located on the third level, overlapping the first active region, and separated from the first wire in the first direction; and a third wire extending in the second direction, located on the third level, overlapping the second active region, and separated from the first wire in the first direction. In some embodiments, the integrated circuit further includes: a first via located between the first active region and the second conductor, the first via electrically coupling the first active region to the second conductor; a second via located between the second active region and the third conductor, the second via electrically coupling the second active region to the third conductor; a third via located between the second conductor and the first power rail, the third via electrically coupling the second conductor to the first power rail; and a fourth via located between the third conductor and the second power rail, the fourth via electrically coupling the third conductor to the second power rail.In some embodiments, the first power rail or the second power rail includes: a center conductor extending in the first direction and having a first side and a second side opposite to the first side; a first conductive portion group coupled to the first side of the center conductor extending in the second direction, and each conductive portion of the first conductive portion group being spaced apart from each other in the first direction; and a second conductive portion group coupled to the second side of the center conductor extending in the second direction, each conductive portion of the second conductive portion group being spaced apart from each other in the first direction, wherein the first conductive portion group alternates with the second conductive portion group in the first direction.

[0572] Some embodiments of this application provide a method for manufacturing an integrated circuit, the method comprising: fabricating a transistor group and pseudo-vias in a front side of a substrate; thinning a back side of the substrate opposite to the front side; fabricating a first via group and a first conductor group on the back side of the thinned substrate at a first level, the first conductor group being electrically coupled to the transistor group through the first via group; fabricating a second via group on the back side of the thinned substrate; and depositing a conductive material on the back side of the thinned substrate at a second level to form a second conductor group, the second conductor group being electrically coupled to the first conductor group through the second via group.

[0573] In some embodiments, fabricating the first via group and the first conductor group includes: depositing an insulating layer on the back side of the thinned substrate; depositing a hard mask on the insulating layer and removing the pseudo vias to form trenches in the hard mask and the insulating layer; removing lateral portions of the hard mask by directional etching to form additional openings in the hard mask; and depositing conductive material in the trenches in the insulating layer and the additional openings in the hard mask.

[0574] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. An integrated circuit, comprising: A power rail assembly extends in a first direction, is configured to provide a first supply voltage or a second supply voltage, and is located on a first level on the back side of a substrate, wherein the power rail assembly includes a first power rail and a second power rail. An active region group extends in the first direction and is located on a second level on the front side of the substrate opposite to the back side, the second level being different from the first level, and the active region group overlapping the power rail group; A first conductor group extends in a second direction different from the first direction and is located on a third level on the back side of the substrate. The third level is different from the first level and the second level and overlaps with the active region group. The first conductor group includes a first conductor and a second conductor. The first conductor overlaps with the first power rail, and the second conductor overlaps with the second power rail. The first conductor and the second conductor are arranged along the second direction and are separated from each other in the second direction. A first via group is located between the active region group and the first conductor group, the first via group electrically coupling the active region group to the first conductor group; and The second through-hole group is located between the first wire group and the power rail group, and the second through-hole group is electrically coupled to the first wire group and the power rail group.

2. The integrated circuit according to claim 1, wherein, The active region group includes: A first active region extends in the first direction; and The second active region extends in the first direction and is separated from the first active region in the second direction.

3. The integrated circuit according to claim 2, wherein, The first power rail extends in the first direction, is configured to provide the first supply voltage to the first active region, and overlaps with the first active region; as well as The second power rail extends in the first direction, is configured to provide the second supply voltage to the second active region, overlaps with the second active region, and is separated from the first power rail in the second direction.

4. The integrated circuit according to claim 3, wherein, The first conductor overlaps with the first active region; and The second conductor overlaps with the second active region.

5. The integrated circuit according to claim 4, wherein, The first through-hole group includes: A first via is located between the first active region and the first conductor, the first via electrically coupling the first active region to the first conductor; and A second via is located between the second active region and the second conductor, and the second via electrically couples the second active region to the second conductor.

6. The integrated circuit according to claim 5, wherein, The second through-hole group includes: A third through-hole is located between the first conductor and the first power rail, the third through-hole electrically coupling the first conductor to the first power rail; and A fourth through hole is located between the second conductor and the second power rail, and the fourth through hole electrically couples the second conductor to the second power rail.

7. The integrated circuit according to claim 5, further comprising: A first conductor, extending at least in the first or second direction, is located on the third layer on the back side of the substrate, overlapping the first active region and the second active region.

8. The integrated circuit according to claim 7, further comprising: The third via is located between the first drain / source of the first active region and the first conductor, and the third via electrically couples the first drain / source of the first active region to the first conductor. as well as A fourth via is located between the second drain / source of the second active region and the first conductor, wherein the fourth via electrically couples the second drain / source of the second active region to the first conductor.

9. The integrated circuit according to claim 1, further comprising: A gate group, extending in the second direction, is located on a fourth layer on the front side of the substrate, the fourth layer being different from the first layer, the second layer and the third layer, and overlapping with the active region group.

10. An integrated circuit, comprising: A first power rail extends in a first direction, is configured to provide a first supply voltage, and is located on a first level on the back side of the substrate; A second power rail extends in the first direction and is configured to provide a second supply voltage different from the first supply voltage. The second power rail is located on the first level and is separated from the first power rail in a second direction different from the first direction. The first power rail has a first sidewall facing away from the second power rail, and the second power rail has a second sidewall facing away from the first power rail. A first signal line extends in the first direction, is located on the first level, and is located between the first power rail and the second power rail; A first active region extends in the first direction and is located on a second level on the front side of the substrate opposite to the back side, the second level being different from the first level, and the first active region overlaps with and is electrically coupled to the first power rail. The second active region extends in the first direction, is located on the second level, is separated from the first active region in the second direction, overlaps with the second power rail, and is electrically coupled to the second power rail. as well as A first conductor extends in the second direction and is located on a third layer on the back side of the substrate. The third layer is different from the first layer and the second layer, overlaps with the first active region and the second active region, and electrically couples the first active region and the second active region to the first signal line. The first conductor is higher than the first power rail, the second power rail, and the first signal line. Viewed from top to bottom, the first conductor is entirely located between the first sidewall and the second sidewall.

11. The integrated circuit according to claim 10, further comprising: The second conductor extends in the second direction, is located on the third level, overlaps with the first active region and the second active region, is separated from the first conductor in the first direction, and further electrically couples the first active region and the second active region to the first signal line.

12. The integrated circuit according to claim 11, further comprising: The first via is located between the first drain / source of the first active region and the first wire, and the first via electrically couples the first drain / source of the first active region to the first wire. as well as The second via is located between the second drain / source of the first active region and the second wire, and the second via electrically couples the second drain / source of the second active region to the second wire.

13. The integrated circuit according to claim 12, further comprising: A third through hole is located between the first conductor and the first signal line, and the third through hole electrically couples the first conductor to the first signal line. as well as A fourth through hole is located between the second conductor and the first signal line, and the fourth through hole electrically couples the second conductor to the first signal line.

14. The integrated circuit according to claim 10, further comprising: A first conductor, extending at least in the first or second direction, is located on the third layer on the back side of the substrate, overlapping the first active region and the second active region.

15. The integrated circuit of claim 14, further comprising: The first via is located between the first drain / source of the first active region and the first conductor, and the first via electrically couples the first drain / source of the first active region to the first conductor. as well as The second via is located between the second drain / source of the second active region and the first conductor, and the second via electrically couples the second drain / source of the second active region to the first conductor.

16. The integrated circuit of claim 10, further comprising: The second conductor extends in the second direction, is located on the third level, overlaps with the first active region, and is separated from the first conductor in the first direction; as well as A third conductor extends in the second direction, is located on the third level, overlaps with the second active region, and is separated from the first conductor in the first direction.

17. The integrated circuit according to claim 16, further comprising: A first via is located between the first active region and the second conductor, and the first via electrically couples the first active region to the second conductor. The second via is located between the second active region and the third conductor, and the second via electrically couples the second active region to the third conductor; A third through hole is located between the second wire and the first power rail, and the third through hole electrically couples the second wire to the first power rail. as well as A fourth through hole is located between the third conductor and the second power rail, and the fourth through hole electrically couples the third conductor to the second power rail.

18. The integrated circuit according to claim 10, wherein, The first power rail or the second power rail includes: A central conductor extends in the first direction and has a first side and a second side opposite to the first side; A first conductive portion group, coupled to the first side of the central conductor, extends in the second direction, and each conductive portion of the first conductive portion group is spaced apart from each other in the first direction; and A second conductive portion group is coupled to a second side of the central conductor, the second conductive portion group extending in a second direction, and each conductive portion of the second conductive portion group being spaced apart from each other in the first direction. The first conductive portion group alternates with the second conductive portion group in the first direction.

19. A method for manufacturing an integrated circuit, the method comprising: Transistor arrays and pseudo-vias are fabricated on the front side of the substrate; Thinning is performed on the back side of the substrate opposite to the front side; A first via group and a first conductor group are formed on the back side of the thinned substrate at the first level, the first conductor group being electrically coupled to the transistor group through the first via group, wherein the first conductor group includes a first conductor and a second conductor; A second set of vias is formed on the back side of the thinned substrate; and Conductive material is deposited on the back side of the thinned substrate at the second level to form a power rail assembly, which is electrically coupled to the first conductor assembly through the second via assembly. The power rail assembly includes a first power rail and a second power rail, the first conductor overlaps with the first power rail, the second conductor overlaps with the second power rail, the first conductor and the second conductor are arranged along a first direction, and the first conductor and the second conductor are separated from each other in the first direction.

20. The method according to claim 19, wherein, Manufacturing the first through-hole assembly and the first wire assembly includes: An insulating layer is deposited on the back side of the thinned substrate; A hard mask is deposited on the insulating layer, and the pseudo vias are removed to form trenches in the hard mask and the insulating layer; Additional openings are formed in the hard mask by removing the lateral portion of the mask through directional etching; and Conductive material is deposited in the trenches within the insulating layer and in the additional openings within the hard mask.

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