Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate, the substrate including a base, dummy gates located on the substrate, and sidewalls located on both sides of the dummy gates; the substrate including an isolation region intersecting with a plurality of dummy gates in its extending direction; removing the dummy gates within the isolation region to expose the sidewalls on both sides of the dummy gates; thinning the exposed sidewalls within the isolation region along the sidewalls away from the dummy gates to form a transverse isolation trench; and forming a transverse isolation structure filling the transverse isolation trench. The method improves the performance of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits, the feature size of integrated circuits continues to shrink. As the feature size decreases, the traditional gate dielectric layer becomes thinner and thinner, which increases the leakage current of transistors and causes excessive power consumption of semiconductor devices.

[0003] To address the aforementioned issues, existing technologies employ a method of replacing the polysilicon gate with a metal gate to form the gate. In this gate replacement process, a polysilicon dummy gate is first formed, followed by the formation of the corresponding device structure. After the device structure is formed, the polysilicon dummy gate is etched away to form a gate trench. A suitable metal material is then used to fill the gate trench to form the metal gate. This allows the metal gate to avoid the high-temperature processing required during device structure formation, preventing threshold voltage drift in the transistor and thus minimizing its performance impact.

[0004] However, devices manufactured using existing semiconductor processes do not perform well. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby optimizing the performance of the semiconductor structure.

[0006] To address the above problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising:

[0007] A substrate is provided, the substrate including a substrate, dummy gates located on the substrate, and sidewalls located on both sides of the dummy gates; the substrate includes an isolation region intersecting with a plurality of dummy gates in its extending direction;

[0008] Remove the dummy gate within the isolation region to expose the sidewalls on both sides of the dummy gate;

[0009] Along the sidewall away from the dummy gate direction, the exposed sidewall in the isolation region is thinned to form a transverse isolation trench;

[0010] A transverse isolation structure is formed that fills the transverse isolation trench.

[0011] Accordingly, embodiments of the present invention also provide a semiconductor structure, comprising:

[0012] The substrate includes a substrate, a gate located on the substrate, and sidewalls located on both sides of the gate, wherein the substrate includes an isolation region that intersects with a plurality of gates in its extending direction;

[0013] The transverse isolation structure located within the isolation zone;

[0014] The sidewall extends below the transverse isolation structure, and the thickness of the sidewall located below the transverse isolation structure along the direction away from the gate is less than that of the sidewalls on both sides of the gate.

[0015] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0016] In this embodiment of the invention, when forming the transverse isolation trench, after removing the dummy gate in the isolation region and exposing the sidewalls on both sides of the dummy gate, the exposed sidewalls in the isolation region are thinned along the sidewalls away from the dummy gate to remove protrusions that may be located between the dummy gates, thereby avoiding damage to the metal gate caused by the protrusions in subsequent processes and improving the performance of the device. Attached Figure Description

[0017] Figures 1 to 9 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0018] Figures 10 to 23 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention;

[0019] Figures 24 to 26 This is a schematic diagram of the semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0020] As the background technology shows, devices formed by existing processes still have performance issues. This paper analyzes the reasons for these poor device performance using a semiconductor structure formation method.

[0021] refer to Figures 1 to 9 The diagram shows a schematic representation of each step in a method for forming a semiconductor structure.

[0022] like Figures 1 to 2 As shown, a substrate is provided, the substrate including a substrate 101, a plurality of parallel dummy gates 120 located on the substrate, and an interlayer dielectric layer 130 filling the spaces between the dummy gates 120, wherein the substrate includes an isolation region 10A, the extension direction of the isolation region 10A intersecting the plurality of parallel dummy gates 120. Figure 2 for Figure 1 A cross-sectional view along the AA' direction.

[0023] like Figure 3 As shown, a portion of the dummy gate and interlayer dielectric layer within the isolation region 10A are removed.

[0024] like Figure 4 As shown, an anisotropic etching process is used to etch and remove the dummy gates in the isolation region 10A, forming a transverse isolation trench 121 that crosses the plurality of parallel dummy gates.

[0025] like Figure 5 As shown, a transverse isolation structure 140 is formed by deposition in the transverse isolation trench.

[0026] like Figure 6 As shown, a metal gate 150 is formed at the remaining dummy gate location.

[0027] like Figures 6 to 8 As shown, wet etching removes the isolation gate 151 from the metal gate 150, forming a cut-off isolation trench 161. Wherein, Figure 8 for Figure 7 A cross-sectional view along the BB' direction.

[0028] like Figure 9 As shown, a cut-off isolation structure 160 is formed that fills the cut-off isolation trench 161.

[0029] The inventors discovered that the devices formed by the above method have poor performance because, during or after the formation of the dummy gate structure, environmental factors (such as temperature and pressure) may cause the dummy gate structure to form protrusions. Figures 2-5 The black shaded area shown, for example, when the dummy gate is polycrystalline silicon, is prone to crystallization under high-temperature environments (such as the high-temperature environment during sidewall deposition processes), thus protruding from the original process space and intruding into the sidewalls on both sides of the dummy gate. Furthermore, during the formation of the transverse isolation trench, the anisotropic etching process only etches in the direction perpendicular to the substrate surface, avoiding etching in other directions to prevent damage to other parts of the dummy gate. This results in the inability to remove the protruding portion from the original process space. If this unremovable protrusion connects with the remaining dummy gate, the metal gate subsequently formed in the dummy gate process space will simultaneously extend to the protrusion location. Therefore, during the wet etching step to remove the isolation gate in the metal gate, the etching solution easily etches the material at the protrusion location and passes through this protrusion location (e.g., Figure 8 As shown in the figure), it is immersed into the metal gate that does not need to be etched (such as...). Figure 7 (As shown by the dashed arrow in the middle), this causes damage to the gate structure of the device.

[0030] The inventors further researched and concluded that completely removing the sidewalls on the side of the dummy gate could solve this technical problem. However, due to the excessive depth of the sidewalls, and the fact that the etching process for completely removing the sidewalls is usually along the direction from the top surface to the bottom surface of the sidewalls, it is difficult to completely remove the sidewalls and it is easy to cause etching residues. As a result, the dummy gate protrusions cannot be completely removed, which affects the performance of the device. Moreover, at the same depth of the semiconductor structure, there are other complex device structures. The etching process for completely removing the sidewalls is very likely to damage other device structures, resulting in a decrease in device performance.

[0031] Based on this, embodiments of the present invention provide a semiconductor structure and a method for forming the same. The method includes: providing a substrate, the substrate including a substrate, a dummy gate located on the substrate, and sidewalls located on both sides of the dummy gate; the substrate including an isolation region intersecting with a plurality of dummy gates in its extending direction; removing the dummy gates in the isolation region to expose the sidewalls on both sides of the dummy gates; thinning the exposed sidewalls in the isolation region along the sidewalls away from the dummy gates to form a transverse isolation trench; and forming a transverse isolation structure filling the transverse isolation trench.

[0032] In this embodiment of the invention, when forming the transverse isolation trench, after removing the dummy gate in the isolation region and exposing the sidewalls on both sides of the dummy gate, the exposed sidewalls in the isolation region are thinned along the sidewalls away from the dummy gate to remove protrusions that may be located between the dummy gates, thereby avoiding damage to the metal gate caused by the protrusions in subsequent processes and thus improving the performance of the device.

[0033] Furthermore, in this embodiment of the invention, the exposed sidewalls in the isolation region are thinned along the direction away from the dummy gate, which is easy to implement and can completely remove the protrusion of the dummy gate without damaging other device structures of the same depth in the semiconductor structure. Compared with completely removing the sidewalls, this embodiment of the invention improves the performance of the device.

[0034] To make the above-mentioned objectives, features and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0035] Figures 10 to 23 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0036] refer to Figures 10-11 A substrate 200 is provided, the substrate including a substrate 201, a plurality of dummy gates 220 located on the substrate, and sidewalls located on both sides of the dummy gates.

[0037] in, Figure 11 It is along Figure 10A cross-sectional view along the CC' direction.

[0038] The substrate includes an isolation region 20A, which intersects with a plurality of dummy gates 220 in its extending direction. Optionally, the extending direction of the isolation region is perpendicular to the extending direction of the dummy gates. The isolation region 20A is the area of ​​the substrate 200 used to form a transverse isolation trench. This region covers a portion of the plurality of dummy gates and a portion of the area between the plurality of dummy gates, so that a transverse isolation trench can be formed by subsequent etching of the isolation region.

[0039] The width of the isolation region should not be too large or too small. If the isolation region is too large, the width of the subsequent cross-cut isolation trench will also be too large, occupying too much space and hindering the reduction of the semiconductor structure size. If the width of the isolation region is too small, the width of the subsequent cross-cut isolation trench will also be too small, which is not conducive to the function of the isolation device. Accordingly, the width of the isolation region can be 20 nanometers to 30 nanometers.

[0040] The substrate 201 is used to provide support for other structures. In this embodiment of the invention, the substrate 201 may be made of silicon. In other embodiments, the substrate may also be made of germanium, silicon carbide, gallium arsenide, or indium gallium nitride, and may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The substrate material may be suitable for process requirements or easy to integrate. An interface layer may also be formed on the surface of the substrate 201, and the interface layer may be made of silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0041] The dummy gate 220 occupies space for the metal gate structure formed in subsequent processes. The dummy gate 220 can be polycrystalline silicon. In other embodiments, the material of the dummy gate 220 can also be monocrystalline silicon, amorphous silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, or amorphous carbon.

[0042] In the process of forming device structures, in order to facilitate the simultaneous formation of multiple device structures, multiple parallel dummy gates are usually formed on the substrate at the same time, which facilitates the corresponding processing in the device formation process and simplifies the process flow.

[0043] Sidewalls 230 are formed on both sides of the dummy gate 220, and the sidewalls 230 can define the formation regions of the source and drain doped layers. Further, in this embodiment of the invention, the substrate also includes an interlayer dielectric layer 240 filled on the sidewall facing away from the dummy gate. The interlayer dielectric layer 240 is used to isolate different device structures and further define the process space for the device.

[0044] The sidewall can be made of silicon nitride. In other embodiments of the invention, the sidewall can also be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride.

[0045] The interlayer dielectric layer 240 is made of an insulating material. In this embodiment, the interlayer dielectric layer 240 is made of silicon oxide. In other embodiments, the interlayer dielectric layer 240 may also be made of other dielectric materials such as silicon nitride or silicon oxynitride.

[0046] In this embodiment of the invention, a hard mask layer 250 may also be formed on the dummy gate 220, and the sidewalls 230 and the interlayer dielectric layer 240 are flush with the hard mask layer 250. The hard mask layer 250 is used to protect the dummy gate, and the material of the hard mask layer 250 may be silicon nitride. In other embodiments, the material of the hard mask layer may also be silicon oxynitride.

[0047] In this embodiment of the invention, the substrate further includes fins protruding from the substrate, and the dummy gate spans the fins. The material of the fins may be the same as or different from the material of the substrate. The dummy gate spans the discrete fins, thereby enabling device control using the fins as a channel structure.

[0048] refer to Figures 12 to 14 Remove the dummy gate 220 within the isolation region to expose the sidewalls 230 on both sides of the dummy gate 220.

[0049] By removing the dummy gate 220 within the isolation region, the sidewalls 230 on both sides of the dummy gate 220 are exposed. This allows for the thinning of the sidewalls 230 along the direction away from the dummy gate 220, thereby completely removing any protrusions that may appear on the dummy gate 220.

[0050] In this embodiment, considering that the structure below the top surface of the dummy gate in the substrate structure is relatively simple and the corresponding device structure is relatively small, the removal of the dummy gate in the isolation region can first remove the semiconductor structure of a portion of the isolation region, and then remove the remaining dummy gate, thereby reducing the etching depth of the remaining dummy gate and thus reducing the difficulty of the etching process.

[0051] Specifically, in this embodiment, the semiconductor structure further includes an interlayer dielectric layer, and correspondingly, removing the dummy gate within the isolation region includes:

[0052] refer to Figures 12 to 13 ,in, Figure 13 for Figure 12A cross-sectional view along the CC' direction, with a portion of the thickness of the dummy gate 220, sidewall 230, and interlayer dielectric layer 240 removed along a direction perpendicular to the substrate surface;

[0053] In this embodiment, when the substrate further includes a fin, there are fewer device structures on the top surface of the fin and more and more complex device structures below the top surface of the fin. Therefore, in this embodiment, the top surface of the remaining interlayer dielectric layer is higher than the top surface of the fin.

[0054] In this embodiment of the invention, a hard mask layer is also formed on the dummy gate. Correspondingly, the hard mask layer in the isolation region 20A is further removed in this step.

[0055] Specifically, the hard mask layer, dummy gate, sidewalls, and interlayer dielectric layer within the isolation region can be removed through a series of semiconductor processes such as photolithography and etching. For example, a patterned first mask layer (e.g., Figure 12 As shown in 260), the first mask layer has an opening that exposes the isolation region, and further uses the first mask layer 260 as a mask to remove the hard mask layer 250, dummy gate, sidewall, and interlayer dielectric layer (e.g., ...) in the corresponding region. Figure 13 (As shown).

[0056] refer to Figure 14 Remove the remaining dummy gate and expose the surface of the remaining sidewall 230 facing the dummy gate.

[0057] Optionally, the remaining dummy gates can be removed using a series of semiconductor processes such as photolithography and etching. For example, a patterned second mask layer can be formed, having an opening that exposes the isolation region, and the corresponding portion of the dummy gate can be removed using this second mask layer as a mask.

[0058] It is understandable that, during the removal of the dummy gate, since the material of the dummy gate is different from the materials of other parts, an etching process with a higher etching ratio for the dummy gate material can be selected based on the characteristics of the material to etch the dummy gate, thereby reducing damage to other parts of the device structure.

[0059] In this embodiment of the invention, an anisotropic etching process, such as plasma etching, can be used to remove the dummy gate, thereby avoiding damage to other areas of the device.

[0060] It is understandable that when using an anisotropic etching process to remove the dummy gate, only the dummy gate structure perpendicular to the exposed top surface of the dummy gate can be removed, making it easy for protrusions intruding into both sides of the dummy gate to remain unremoved. Therefore, in this embodiment, the protrusions are completely removed by further thinning the sidewalls.

[0061] In this embodiment of the invention, a first cleaning process is further included on the exposed sidewall surface of the substrate to remove polymer residues that may have occurred during the etched dummy gate step.

[0062] Specifically, the first cleaning process may include: cleaning with HF solution at a temperature of 10°C to 30°C; then cleaning with HPM (a mixed solution of H2SO4 and H2O2) solution at a temperature of 80°C to 160°C; and then cleaning with an alkaline solution (such as a mixed solution of NH4OH, H2O2, and H2O) at a temperature of 20°C to 90°C.

[0063] Next, refer to Figure 15 Along the sidewall away from the dummy gate direction ( Figure 15 (As indicated by the arrow), the exposed sidewalls within the isolation zone are thinned to form a transverse isolation trench.

[0064] The transverse isolation trench is used to cut off the dummy gates in the dummy gate extension direction, thereby isolating multiple corresponding device structures in the dummy gate extension direction. It should be noted that, to facilitate semiconductor integration processes, the transverse isolation trench simultaneously cuts off multiple dummy gates along a direction perpendicular to the dummy gate extension direction, thereby simultaneously isolating multiple device structures. Correspondingly, the extension direction of the isolation region is perpendicular to the extension direction of the multiple dummy gates and intersects with the dummy gates.

[0065] In this embodiment of the invention, by removing the exposed sidewalls within the isolation zone, protrusions that may remain within the sidewalls can be removed, avoiding damage to the metal gate caused by the protrusions in subsequent processes, thereby improving the performance of the device.

[0066] It should be noted that the protrusions of the dummy gate are usually very small. Therefore, the protrusions can be removed simply by thinning the sidewall away from the direction of the dummy gate along the sidewall.

[0067] In this embodiment of the invention, the etching direction of the sidewall is along the sidewall away from the dummy gate direction, thereby enabling the removal of the sidewall from a larger surface area, resulting in a high etching rate and good etching effect. Optionally, based on the high etching rate of the sidewall in this embodiment, a larger thickness of the sidewall can also be removed during the sidewall thinning step. For example, a sidewall of a preset thickness can be removed, which can be 20% to 100% of the sidewall thickness. That is, the sidewall can be completely removed during the sidewall thinning step, thereby completely removing the protrusion.

[0068] In this embodiment of the invention, atomic layer etching (ALE) can be used to thin the sidewall. Specifically, thinning the sidewall within the isolation region along the direction away from the dummy gate can include: modifying the surface of the sidewall facing the dummy gate using a first process; and etching the modified sidewall surface using a second process. The modification of the sidewall surface using the first process, combined with the etching of the modified sidewall surface using the second process, effectively thins the surface of the sidewall facing the dummy gate.

[0069] The first and second processes can be performed cyclically to repeat the thinning process until a sidewall of a predetermined thickness is removed along the direction away from the dummy gate. Optionally, the process can be repeated 10 to 30 times to achieve the thinning of the sidewall.

[0070] In this embodiment of the invention, the first and second processes can be plasma processes, whereby the sidewalls within the isolation region are thinned by cyclically performing modification and etching processes within a plasma chamber. It is understood that using both the first and second processes as plasma processes simplifies the process flow and avoids device contamination caused by changes in different process environments.

[0071] Specifically, in the first process, the reactant gas can be one or more of hydrogen (H2) and helium (He), and in the second process, the reactant gas can be a mixture of fluorine (F) gas and ammonia (NH3). For example, in the first process, the reactant gas can be hydrogen and helium, wherein the hydrogen flow rate is 100 sccm to 500 sccm, the helium flow rate is 100 sccm to 500 sccm, the reaction pressure is 5 mT to 20 mT, the source power is 500 W to 1500 W, and the bias power is 200 W to 500 W; in the second process, the reactant gas is nitrogen trifluoride (NF3) and ammonia, wherein the nitrogen trifluoride flow rate is 5 sccm to 50 sccm, the ammonia flow rate is 10 sccm to 100 sccm, the reaction pressure is 100 mT to 500 mT, and the source power is 300 W to 700 W. In the second process, argon gas (Ar) with a flow rate of 300 sccm to 700 sccm can be further introduced into the reaction chamber.

[0072] It should be noted that in the first process, the pressure is slightly lower to allow the plasma in the cavity to react fully in the horizontal direction (the surface of the sidewall facing the dummy gate is horizontal). In the second process, the plasma tends to react with the modified sidewall surface, and the pressure is slightly higher to fully press the plasma into the bottom of the sidewall, thereby achieving overall thinning of the sidewall surface facing the dummy gate.

[0073] Furthermore, in the second process, the source power can be 300W to 700W, and the bias power can be slightly lower (e.g., 0W to 10W) ​​or not set (i.e., 0W).

[0074] In this embodiment of the invention, after thinning the exposed sidewall in the isolation region along the sidewall away from the dummy gate direction, the method further includes: performing a second cleaning process on the exposed sidewall surface of the substrate to remove polymer residues that may have occurred during the sidewall etching step.

[0075] Specifically, the second cleaning process may include: cleaning with HF solution at a temperature of 10°C to 30°C; then cleaning with HPM (a mixed solution of H2SO4 and H2O2) solution at a temperature of 80°C to 160°C; and then cleaning with an alkaline solution (such as a mixed solution of NH4OH, H2O2, and H2O) at a temperature of 20°C to 90°C.

[0076] Furthermore, in this embodiment of the invention, after forming the transverse isolation trench and before forming the transverse isolation structure that fills the transverse isolation trench, the surface of the transverse isolation trench is surface-treated to form a transition layer (not shown in the figure) on the surface of the transverse isolation trench. The material of the transition layer matches the crystal lattice of the material of the transverse isolation structure, so that the transition layer can fill the vacancies and dangling valences on the surface of the transverse isolation trench, making the subsequently formed transverse isolation structure fit the surface of the transverse isolation trench better, improving the isolation performance of the transverse isolation structure, thereby improving the performance of the device.

[0077] In this embodiment of the invention, the transverse isolation structure can be a nitrided material, and the surface treatment of the transverse isolation trench includes: nitriding the surface of the transverse isolation trench.

[0078] Specifically, the surface of the transverse isolation trench can be nitrided using a plasma process, wherein the reaction gas can be nitrogen (N2), the flow rate can be 100 sccm to 1000 sccm, the reaction pressure can be 10 mT to 100 mT, the source power can be 100 W to 1000 W, and the reaction time can be 5 s to 30 s.

[0079] Next, refer to Figure 16-17 This forms a transverse isolation structure 270 that fills the transverse isolation trench. Wherein, Figure 17 for Figure 16 A sectional view along the CC' direction.

[0080] Isolation of device structures is achieved by forming a cross-cut isolation structure 270 that fills the cross-cut isolation trench. The cross-cut isolation structure 270 can be made of an insulating material to provide electrical isolation between device structures.

[0081] The material of the transverse isolation structure 270 can be one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment of the invention, the material of the transverse isolation structure 270 can be silicon nitride.

[0082] In an embodiment of the present invention, the process of forming a transverse isolation structure that fills the transverse isolation trench may include: forming a transverse isolation material that completely covers the side of the substrate having the transverse isolation trench; grinding away the transverse isolation material on the surface of the substrate, and retaining the transverse isolation material in the transverse isolation trench as the transverse isolation structure 270.

[0083] The process for forming the transverse isolation material can be flowable chemical vapor deposition (FCVD). The grinding process can be chemical mechanical polishing to give the transverse isolation structure good morphological characteristics. It should be noted that the first mask layer can be removed simultaneously during the grinding process of the transverse isolation material.

[0084] In this embodiment of the invention, after forming the transverse isolation structure that fills the transverse isolation trench, the following process may also be included:

[0085] refer to Figure 18 The remaining dummy gate on the substrate is removed by a wet etching process to form a gate trench 281.

[0086] The dummy gate is removed to form a gate trench 281, which provides process space for the subsequent formation of a metal gate.

[0087] To completely remove the remaining dummy gate and isolation mask layer on the substrate, this step employs a wet etching process to remove the dummy gate and isolation mask layer. Specifically, an acidic oxidizing etchant, such as a mixture of nitric acid (HNO3) and hydrofluoric acid (HF), can be used to etch the dummy gate.

[0088] It should be noted that during the removal of the dummy gate, a hard mask layer is also formed on the dummy gate. Correspondingly, in this step, the hard mask layer is removed first to expose the dummy gate, and then the dummy gate is removed.

[0089] In this embodiment of the invention, the sidewalls that may have protrusions have been thinned, so that the process of forming the gate trench in this step will not form a gap corresponding to the protrusion portion based on the protrusions in the sidewalls.

[0090] refer to Figures 19-20 A metal gate 280 is formed in the gate trench 281; wherein, Figure 20 for Figure 19 A cross-sectional view along the DD' direction.

[0091] Specifically, after the gate trench 281 is formed, processes such as deposition and electroplating can be used to form a metal material in the gate trench 281, and the metal material outside the gate trench can be removed by a grinding process to form a metal gate 280 in the gate trench 281.

[0092] It should be noted that, in the formation process of this embodiment of the invention, the metal gate 280 formed includes not only a metal conductive gate for use as a gate structure in the device structure, but also an isolation gate 282 for use as an isolation gate. The isolation gate 282 is used to be etched away in subsequent steps, and a truncated isolation structure is formed at the corresponding spatial location, thereby achieving isolation between device structures.

[0093] In this embodiment of the invention, the process of forming the gate trench does not create a gap in the corresponding protrusion based on the protrusion in the sidewall, and therefore no metal material is formed in the gap during this step.

[0094] Furthermore, in combination Figure 20 refer to Figures 21-22 The isolation gate 282 in the metal gate 280 is removed using a wet etching process, forming a cut-off isolation trench 291. Figure 22 It is along Figure 21 A cross-sectional view obtained by cutting along the DD' direction.

[0095] Correspondingly, in this step, the isolation gate can be removed by wet etching or a combination of wet etching and dry etching, which will not be elaborated here.

[0096] In this embodiment of the invention, the sidewalls that may have protrusions have been thinned, so the process of forming the gate trench will not create gaps in the corresponding protrusions in the sidewalls. Consequently, no metal material will be formed in the gaps during the formation of the metal gate. This prevents the etching solution from seeping into the metal gate that does not need to be etched through the corresponding gaps, or from the etching solution removing the metal material in the gaps and then further seeping into the metal gate that does not need to be etched, thus avoiding damage to the gate structure of the device.

[0097] Further reference Figure 23 This forms a cut-off isolation structure 290 that fills the cut-off isolation trench.

[0098] Isolation of device structures is achieved by forming a cut-off isolation structure 290 that fills the cut-off isolation trench. The material of the cut-off isolation structure 290 can be an insulating material to provide electrical isolation between device structures.

[0099] The cut-off isolation structure 290 can be one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment of the invention, the cut-off isolation structure 290 can be silicon nitride.

[0100] In an embodiment of the present invention, the process of forming the cut-off isolation structure 290 that fills the cut-off isolation trench may include: forming a cut-off isolation material that completely covers the side of the substrate having the cut-off isolation trench; grinding away the cut-off isolation material on the surface of the substrate, and retaining the cut-off isolation material in the cut-off isolation trench as the cut-off isolation structure 290.

[0101] The process for forming the truncated isolation material can be flowable chemical vapor deposition (FCVD). The grinding process can be chemical mechanical polishing to give the truncated isolation structure good morphological characteristics.

[0102] In this embodiment of the invention, when forming the transverse isolation trench, after removing the dummy gate within the isolation region and exposing the sidewalls on both sides of the dummy gate, the exposed sidewalls within the isolation region are further thinned along the sidewalls away from the dummy gate direction to remove any protrusions that may be located between the dummy gates. This avoids damage to the metal gate caused by the protrusions in subsequent processes, thereby improving the device performance.

[0103] This invention also provides a semiconductor structure, see [link to previous document]. Figures 24-26 ,in, Figure 25 for Figure 24 Cross-sectional view along the EE' direction. Figure 26Bit Figure 24 A cross-sectional view along the FF' direction, including:

[0104] The substrate 300 includes a substrate 301, a gate 380 located on the substrate, and sidewalls 330 located on both sides of the gate 380. The substrate 300 includes an isolation region 30A, which intersects with a plurality of gates 380 in its extending direction.

[0105] The transverse isolation structure 370 is located within the isolation zone 30A;

[0106] Wherein, the sidewall 330 extends below the transverse isolation structure 370, and the sidewall located below the transverse isolation structure 370 (e.g.) Figure 26 The thickness of the sidewall (as shown in 330) along the direction away from the gate is smaller than that of the sidewalls on both sides of the gate 380 (e.g., Figure 25 330 shown).

[0107] Optionally, the substrate 300 further includes a fin protruding from the substrate, with the gate spanning the fin.

[0108] Optionally, the substrate 300 further includes a cut-off isolation structure 390, which is parallel to the gate 380 and connected to the transverse isolation structure 370.

[0109] The isolation region 30A is the area of ​​the substrate 300 in which a transverse isolation structure is provided. This region transversely cuts a portion of the structure of multiple parallel gates 380, as well as a portion of the structure between the multiple gates.

[0110] It should be noted that the transverse isolation structure 370 is used to transversely cut the gate in the gate extension direction to isolate multiple corresponding device structures in the gate extension direction. It should also be noted that, to facilitate semiconductor integration processes, the transverse isolation structure 370 simultaneously cuts multiple parallel gates along a direction perpendicular to the gate extension direction to simultaneously isolate multiple device structures. Correspondingly, the extension direction of the isolation region is perpendicular to the extension direction of the multiple parallel gates and intersects with the gate.

[0111] The width of the transverse isolation structure 370 should not be too large or too small. If the width of the transverse isolation structure 370 is too large, it will occupy too much space, which is not conducive to reducing the size of the semiconductor structure; if the width of the transverse isolation structure 370 is too small, it will not be conducive to playing the role of an isolation device. Accordingly, the width of the transverse isolation structure 370 can be from 10 nanometers to 30 nanometers.

[0112] The substrate 301 is used to provide support for other structures. In this embodiment of the invention, the material of the substrate 301 may be silicon.

[0113] In this embodiment of the invention, the substrate further includes fins protruding from the substrate and spanning the fins. The fins may be made of the same material as the substrate or a different material. The fins spanning the discrete fins allow for device control using the fins as a channel structure.

[0114] Sidewalls 330 are provided on both sides of the gate 380, and the sidewalls 330 can define the formation regions of the source and drain doped layers. The material of the sidewalls 330 can be silicon nitride. In other embodiments of the present invention, the sidewalls can also be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride.

[0115] The interlayer dielectric layer 340 is made of an insulating material. In this embodiment, the interlayer dielectric layer 340 is made of silicon oxide. In other embodiments, the interlayer dielectric layer 340 may also be made of other dielectric materials such as silicon nitride or silicon oxynitride.

[0116] The material of the transverse isolation structure 370 can be one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment of the invention, the material of the transverse isolation structure 370 can be silicon nitride.

[0117] The semiconductor structure can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0118] While the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of the present invention. Therefore, the scope of protection of the embodiments of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a substrate, a dummy gate located on the substrate, and sidewalls located on both sides of the dummy gate; The substrate includes an isolation region that intersects with a plurality of dummy gates in its extending direction; Remove the dummy gate within the isolation region to expose the sidewalls on both sides of the dummy gate; Along the sidewall away from the dummy gate direction, the exposed sidewall in the isolation region is thinned to form a transverse isolation trench; A transverse isolation structure is formed that fills the transverse isolation trench.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of thinning the sidewalls within the isolation region along the direction away from the dummy gate includes: The surface of the sidewall facing the dummy gate is modified using a first process; The modified sidewall surface is etched using a second process.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The first process and the second process are repeated until a sidewall of a predetermined thickness is removed along the sidewall in the direction away from the dummy gate.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The preset thickness is 20% to 100% of the sidewall thickness.

5. The method for forming a semiconductor structure as described in claim 2, characterized in that, The first process and the second process are plasma processes.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, In the first process, the reactant gas is one or more of hydrogen and helium; in the second process, the reactant gas is a mixture of fluorine-containing gas and ammonia.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, In the first process, the reaction gases are hydrogen and helium, wherein the hydrogen flow rate is 100 sccm to 500 sccm, the helium flow rate is 100 sccm to 500 sccm, the reaction pressure is 5 mT to 20 mT, the source power is 500 W to 1500 W, and the bias power is 200 W to 500 W.

8. The method for forming a semiconductor structure as described in claim 6, characterized in that, In the second process, the reaction gases are nitrogen trifluoride and ammonia, wherein the flow rate of nitrogen trifluoride is 5 sccm to 50 sccm, the flow rate of ammonia is 10 sccm to 100 sccm, the reaction pressure is 100 mT to 500 mT, and the source power is 300 W to 700 W.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming the transverse isolation trench, and before forming the transverse isolation structure that fills the transverse isolation trench, the method further includes: performing a surface treatment on the surface of the transverse isolation trench to form a transition layer on the surface of the transverse isolation trench, wherein the transition layer material matches the crystal lattice of the material of the transverse isolation structure.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The transverse isolation structure is made of nitrided material, and the surface treatment of the transverse isolation trench includes: nitriding the surface of the transverse isolation trench.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The surface of the transverse isolation trench is nitrided using a plasma process, wherein the reaction gas is nitrogen, the flow rate is 100sccm to 1000sccm, the reaction pressure is 10mT to 100mT, the source power is 100W to 1000W, and the reaction time is 5s to 30s.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate further includes an interlayer dielectric layer filled on the side of the sidewall facing away from the dummy gate; The removal of the dummy gate within the isolation region includes: Along a direction perpendicular to the substrate surface, a portion of the thickness of the dummy gate, sidewalls, and interlayer dielectric layer is removed; Remove the remaining dummy gate, exposing the surface of the remaining sidewall facing the dummy gate.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The substrate further includes a fin protruding from the substrate, and the dummy gate spans the fin; in the step of removing a portion of the thickness of the dummy gate, sidewalls and interlayer dielectric layer, the top surface of the remaining interlayer dielectric layer is higher than the top surface of the fin.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that: After removing the dummy gate in the isolation region and before thinning the sidewalls in the isolation region, the method further includes performing a first cleaning process on the exposed sidewall surface of the substrate. After thinning the sidewalls within the isolation region along the direction away from the dummy gate along the sidewalls, and before forming the transverse isolation structure that fills the transverse isolation trench, the method further includes: performing a second cleaning process on the exposed sidewall surface of the substrate.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming the transverse isolation structure that fills the transverse isolation trench, the method further includes: The remaining dummy gates on the substrate are removed by a wet etching process to form gate trenches; A metal gate is formed in the gate trench; The isolation gate in the metal gate is removed by a wet etching process to form a cut-off isolation trench. A cut-off isolation structure is formed to fill the cut-off isolation trench.

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, The sidewall is made of one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride.

17. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the transverse isolation structure includes one or more of the following: silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride.

18. A semiconductor structure, characterized in that, include: The substrate includes a substrate, a gate located on the substrate, and sidewalls located on both sides of the gate, wherein the substrate includes an isolation region that intersects with a plurality of gates in its extending direction; The transverse isolation structure located within the isolation zone; Wherein, the sidewall extends below the transverse isolation structure, and the thickness of the sidewall located below the transverse isolation structure along the direction away from the gate is less than that of the sidewalls on both sides of the gate. A cut-off isolation structure is provided, which is parallel to the gate and connected to the transverse isolation structure.

19. The semiconductor structure as claimed in claim 18, characterized in that, The substrate also includes a fin protruding from the substrate, and the gate extends across the fin.

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