Method for manufacturing single diffusion region cut-off structure in FinFET

Abstract

The present invention discloses a method for manufacturing a single diffusion region cut-off structure in a FinFET, comprising: step 1, forming a plurality of fin bodies on a semiconductor substrate; step 2, defining a formation region of an SDB structure and etching to form a first groove; step 3, filling a first dielectric layer in the first groove; step 4, performing a fin body truncation process, in which the first dielectric layer protects the fin body material on both sides of the first groove and prevents loss; step 5, forming a shallow trench isolation; step 6, back-etching the shallow trench isolation to expose the top section of each fin body; step 7, forming a first gate dielectric layer and a polysilicon gate in a formation region of a gate structure; step 8, forming an embedded epitaxial layer in the fin body on both sides of the polysilicon gate. The present invention can simplify the formation process of the SDB and prevent the fin body material on both sides of the SDB groove from being lost, thereby ensuring the quality of the embedded epitaxial layer at the same time.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for manufacturing a single diffusion region cut-off structure in a fin field effect transistor (FinFET transistor). Background Art

[0002] In FinFET, a double diffusion break (DDB) structure and a single diffusion break (SDB) structure are usually used to isolate the active area. The width of the active area of ​​a device unit such as a standard logic cell is calculated according to the contacted poly pitch (CPP). The DDB structure includes at least two pseudo gate structures, while the SDB structure only occupies the width of one pseudo gate structure. Therefore, the DDB needs to add an additional CPP width. The SDB can set the width of the active area to the minimum. The device formed by the SDB process has a higher density and a smaller device area. The SDB process technology is usually used in process nodes below 14nm.

[0003] According to different process nodes, SDB manufacturing process is divided into three generations, namely:

[0004] First generation: SDB is manufactured in a fin loop, which is suitable for 16nm and 14nm process nodes.

[0005] Second generation: SDB is manufactured in an interlayer film process loop (ILD loop), which is suitable for the 10nm process node.

[0006] Third generation: SDB is manufactured in a metal gate process ring (MG loop), which is suitable for the 7nm process node.

[0007] This application focuses on the manufacturing process of the first generation SDB. In the first generation SDB process, the SDB is formed together with the fin formation process. In the fin process loop, in addition to forming a global fin pattern on the semiconductor substrate, the fin needs to be truncated, that is, the fin in the area where the device is not required to be formed needs to be removed.

[0008] The truncation of the fin body is divided into the Fin Fine Cut (FFC) process and the Fin Coarse Cut (FCC) process. The FFC process is so fine that it can only cut one fin body, while the FCC process can cut multiple fin bodies, including horizontal cuts parallel to the fin body and vertical cuts perpendicular to the fin body. Usually, FFC is performed first, followed by FCC.

[0009] According to the different process sequences of FFC and FCC, the first generation SDB process is divided into two types. The existing process flow of the first type of SDB is to place the SDB etching process after the FFC and FCC processes; the existing process flow of the second type of SDB is to place the SDB etching process before the FFC and FCC processes.

[0010] The advantage of the existing first SDB process flow is that the etching process in the FFC and FCC processes will not affect the size of the groove formed by SDB etching, that is, the size of the SDB groove. Since the fin material on both sides of the SDB groove will not be lost, the quality of the embedded epitaxial layer subsequently formed adjacent to the SDB groove will be guaranteed. However, the disadvantage of this process is that after the FFC and FCC are completed, the photolithography process that defines the SDB formation area becomes complicated, and the planarization process is also more challenging, which will cause large fluctuations in the critical size and depth of the SDB groove.

[0011] The advantages of the existing first SDB process flow are that the photolithography process is simple, planarization is easier to achieve, and the fluctuations in the critical dimensions and depth of the SDB groove are small. The disadvantage is that after the SDB groove is formed, the FFC and FCC processes will be carried out. The fin material will be etched in the FFC and FCC processes and wet cleaned after the etching is completed. These processes will cause loss of the fin material on the side of the SDB groove. Since the embedded epitaxial layer is formed by etching the fin body to form a groove and then filling the epitaxial layer in the groove, the epitaxial layer can only be formed on the single crystal surface of the fin material exposed in the groove. On both sides of the SDB groove, due to the loss of fin material, the fin material on the side of the groove of the embedded epitaxial layer close to the SDB side is easily consumed, so that the epitaxial layer cannot be formed on this side, and finally the volume of the embedded epitaxial layer is reduced, which will affect the quality of the embedded epitaxial layer. Summary of the invention

[0012] The technical problem to be solved by the present invention is to provide a method for manufacturing a single diffusion region cut-off structure in FinFET, which can simplify the SDB formation process and prevent the fin body material on both sides of the SDB groove from being lost, thereby ensuring the quality of the embedded epitaxial layer at the same time.

[0013] In order to solve the above technical problems, the present invention provides a method for manufacturing a single diffusion region cut-off structure in FinFET, comprising the following steps:

[0014] Step 1: forming a plurality of fins on a semiconductor substrate, wherein a spacer region is provided between each of the fins.

[0015] Step 2: defining a formation area of ​​a single diffusion region cut-off structure, and etching the fin body in the formation area of ​​the single diffusion region cut-off structure to form a first groove.

[0016] Step three: filling the first groove with a first dielectric layer.

[0017] Step 4: Perform a fin body truncation process to remove the fin body in the fin body truncation area. In the fin body truncation process, the first dielectric layer protects the fin body material on both sides of the first groove and prevents the loss of the fin body material on both sides of the first groove.

[0018] Step 5: forming shallow trench isolation to completely fill the remaining spacing areas between the fin bodies.

[0019] Step 6: etching back the shallow trench isolation to expose the top section of each fin.

[0020] The top surface of the first dielectric layer in the first groove is also etched back to below the top surface of the fin body, and the first dielectric layer filled in the first groove after the back etching forms the single diffusion region cut-off structure.

[0021] Step seven: forming a stacked structure of a first gate dielectric layer and a polysilicon gate in the gate structure formation area, and also forming a corresponding polysilicon gate in the single diffusion area cut-off structure; the polysilicon gate between the single diffusion area cut-off structures covers the top surface and side surfaces of the fin body.

[0022] Step eight: forming an embedded epitaxial layer in the fin body on both sides of the polysilicon gate, and utilizing the characteristic that the fin body material on both sides of the first groove is not consumed to improve the quality of the embedded epitaxial layer formed on both sides of the first groove.

[0023] A further improvement is that in step three, the first dielectric layer also completely fills the spacing areas between the fins.

[0024] A further improvement is that the material of the first dielectric layer includes an oxide layer.

[0025] A further improvement is that in step five, the shallow trench isolation completely fills the spacing area formed in each of the fin body truncation areas in step four.

[0026] A further improvement is that the oxide layer of the shallow trench isolation is formed by deposition using a FCVD process.

[0027] A further improvement is that in step five, the shallow trench isolation oxide layer is first deposited using the FCVD process to completely fill the retained spacing areas between the fin bodies and extend to outside the retained spacing areas between the fin bodies, and then a chemical mechanical polishing process is performed to make the top surface of the shallow trench isolation oxide layer level with the top surface of the fin body.

[0028] A further improvement is that in step one, each of the fin bodies is in a strip-shaped structure and each of the fin bodies is arranged in parallel.

[0029] A further improvement is that the fin body cutting process in step four is divided into two steps, the first step is a fin body fine cutting process, and the second step is a fin body rough cutting process.

[0030] A further improvement is that the fin body fine truncation process performs truncation on a fin body as a unit, and the fin body truncation area corresponding to the fin body fine truncation process includes multiple first fin body truncation sub-areas, each of the first fin body truncation sub-areas corresponds to a formation area of ​​the fin body.

[0031] A further improvement is that the corresponding fin body truncation area of ​​the fin body rough truncation process includes multiple second fin body truncation sub-areas and multiple third fin body truncation sub-areas, each of the second fin body truncation sub-areas is perpendicular to each of the fin bodies, and each of the third fin body truncation sub-areas is parallel to the fin body and includes multiple formation areas of the fin bodies.

[0032] A further improvement is that in step one, a first hard mask layer is used in the process of forming the fin body. The hard mask layer is first formed on the semiconductor substrate, and then the formation area of ​​the fin body is defined by photolithography. Then, the first hard mask layer is etched, and then the semiconductor substrate is etched using the first hard mask layer as a mask to form the fin body.

[0033] A further improvement is that after the growth of the first dielectric layer is completed, a chemical mechanical polishing process is further performed to make the top surface of the first dielectric layer and the top surface of the first hard mask layer flush.

[0034] A further improvement is that the first gate dielectric layer is a gate oxide layer.

[0035] A further improvement is that in step seven, each of the polysilicon gates is in a strip structure perpendicular to the fin body.

[0036] A further improvement is that, in the NMOS formation region, the material of the embedded epitaxial layer includes SiP; and in the PMOS formation region, the material of the embedded epitaxial layer includes SiGe.

[0037] The present invention places the etching process of the SDB structure before the fin body truncation process, which can simplify the SDB structure formation process, including the SDB formation area definition process such as the photolithography definition process and the planarization process.

[0038] After forming the first groove, i.e., the SDB groove, the present invention does not directly perform the subsequent fin body truncation process, but adds a step of using the first dielectric layer to completely fill the first groove. In this way, the fin body truncation process will not cause loss of fin body materials on both sides of the first groove; and the fin body materials on both sides of the first groove are not lost, which can ensure the subsequent growth conditions of the embedded epitaxial layer, so that the quality of the embedded epitaxial layer is guaranteed.

[0039] Therefore, the present invention can simplify the SDB formation process and prevent the loss of fin material on both sides of the SDB groove, thereby ensuring the quality of the embedded epitaxial layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0041] Figure 1 is a flow chart of a method for manufacturing a single diffusion region cut-off structure in a FinFET according to an embodiment of the present invention;

[0042] Figure 2 The layout structure of the FinFET corresponding to the method for manufacturing the single diffusion region cut-off structure in the FinFET according to the embodiment of the present invention;

[0043] Figure 3A is a cross-sectional view along line AA after the fin body is formed in the method of an embodiment of the present invention;

[0044] Figure 3B is a cross-sectional view along line BB after the fin body is formed in the method of an embodiment of the present invention;

[0045] Figure 4 is a cross-sectional view along line AA after the first groove is formed in the method of an embodiment of the present invention;

[0046] Figure 5A is a cross-sectional view along line AA after the first dielectric layer is filled in the method of the embodiment of the present invention;

[0047] Figure 5B is a cross-sectional view along line BB after the first dielectric layer is filled in the method of the embodiment of the present invention;

[0048] Figure 6 is a cross-sectional view along line BB after the fin body fine truncation process is completed in the method of the embodiment of the present invention;

[0049] Figure 7 is a cross-sectional view along line AA after the fin body rough truncation process is completed in the method of the embodiment of the present invention;

[0050] Fig. 8A is a cross-sectional view along line AA after shallow trench isolation is filled in the method of an embodiment of the present invention;

[0051] Figure 8B is a cross-sectional view along line BB after shallow trench isolation is filled in the method of an embodiment of the present invention;

[0052] Fig.9A is a cross-sectional view along line AA after shallow trench isolation etching back in the method of an embodiment of the present invention;

[0053] Fig. 9B is a cross-sectional view along line BB after the shallow trench isolation is etched back in the method of the embodiment of the present invention;

[0054] Fig. 10A is a cross-sectional view along line AA after the polysilicon gate is formed in the method of an embodiment of the present invention;

[0055] Fig. 10B is a cross-sectional view along line BB after the polysilicon gate is formed in the method of an embodiment of the present invention;

[0056] Fig.11 is a cross-sectional view along line AA after the embedded epitaxial layer is formed in the method of the embodiment of the present invention;

[0057] Figure 12A-12J It is a three-dimensional simulation photograph of the device in each step of the manufacturing method of the single diffusion region cut-off structure in the FinFET in an embodiment of the present invention. DETAILED DESCRIPTION

[0058] like Figure 1 As shown, it is a flow chart of a method for manufacturing a single diffusion region cut-off structure in a FinFET according to an embodiment of the present invention; Figure 2 , which is a layout structure of a FinFET corresponding to a method for manufacturing a single diffusion region cut-off structure in a FinFET according to an embodiment of the present invention; Figure 3A-Figure 11 is a cross-sectional view of a device in each step of a method for manufacturing a single diffusion region cut-off structure in a FinFET according to an embodiment of the present invention; Figure 12A-12J The three-dimensional simulation diagram of the device in each step of the manufacturing method of the single diffusion region cut-off structure in the FinFET of the embodiment of the present invention is provided for a more vivid understanding. Figure 3A-Figure 11The present invention is based on the device cross-sectional view in FIG. 1 , and the same components are marked with the same reference numerals. The method for manufacturing a single diffusion region cut-off structure in a FinFET according to an embodiment of the present invention comprises the following steps:

[0059] Step 1: forming a plurality of fin bodies 101 on a semiconductor substrate 101 a , with a spacing region between each of the fin bodies 101 .

[0060] In the embodiment of the present invention, Figure 2 As shown, each of the fin bodies 101 is in a strip-shaped structure and each of the fin bodies 101 is arranged in parallel.

[0061] Combination Figure 3A , Figure 3B and Fig. 12A As shown, a first hard mask layer 205 is used in the process of forming the fin body 101. The hard mask layer is first formed on the semiconductor substrate 101a, and then the formation area of ​​the fin body 101 is defined by photolithography. Then, the first hard mask layer 205 is etched, and then the semiconductor substrate 101a is etched using the first hard mask layer 205 as a mask to form the fin body 101. Fig. 12A As shown, the first hard mask layer 205 is formed by stacking an oxide layer 205a and a nitride layer 205b.

[0062] Step 2: Define the formation area of ​​the single diffusion region cut-off structure. Usually, a photolithography process is used to define the formation area of ​​the single diffusion region cut-off structure, such as Figure 2 As shown, the formation area of ​​the first groove 301 is marked with a dotted frame 201 .

[0063] Combination Figure 4 and Fig. 12B As shown, the fin body 101 in the formation area of ​​the single diffusion region cut-off structure is etched to form a first groove 301 .

[0064] Step 3: Combination Figure 5A , Figure 5B and Fig. 12C As shown, the first dielectric layer 103 is filled in the first groove 301 .

[0065] In the embodiment of the present invention, the first dielectric layer 103 also completely fills the spacing regions between the fins 101 .

[0066] The material of the first dielectric layer 103 includes an oxide layer.

[0067] After the growth of the first dielectric layer 103 is completed, a chemical mechanical polishing process is further performed to make the top surface of the first dielectric layer 103 and the top surface of the first hard mask layer 205 flush with each other.

[0068] Step 4: Perform a fin body truncation process to remove the fin body 101 in the fin body truncation area. In the fin body truncation process, the first dielectric layer 103 protects the fin body 101 material on both sides of the first groove 301 and prevents the material of the fin body 101 on both sides of the first groove 301 from being lost.

[0069] In the embodiment of the present invention, the fin body cutting process in step four is divided into two steps, the first step is a fin body fine cutting process, and the second step is a fin body rough cutting process.

[0070] The fin body fine truncation process is performed by truncation of one fin body 101 as a unit, and the fin body truncation region corresponding to the fin body fine truncation process includes a plurality of first fin body truncation sub-regions, each of which corresponds to a formation region of one fin body 101. Figure 2 As shown, the dashed box 202 shows the first fin body truncation sub-region. Figure 6 As shown, a groove 302 is formed after the fin body fine cutting process is completed, and the fin body 101 in the groove 302 is removed. Fig.12D A groove 302 is also shown.

[0071] The fin body truncation region corresponding to the fin body rough truncation process includes a plurality of second fin body truncation sub-regions and a plurality of third fin body truncation sub-regions.

[0072] like Figure 2 As shown, the dotted line frame 203 represents the second fin body truncation sub-region, and each of the second fin body truncation sub-regions is perpendicular to each of the fin bodies 101. Figure 7 As shown, a groove 303 is formed in the second fin body truncation sub-region after the fin body rough truncation process is completed, and the fin body 101 in the groove 303 is removed. Fig.12E A groove 303 is also shown.

[0073] like Figure 2 As shown, the dotted frame 204 represents a third fin body truncation sub-region, and each of the third fin body truncation sub-regions is parallel to the fin body 101 and includes a formation region of a plurality of the fin bodies 101 . Fig.12E It is also shown that the groove in the area indicated by the bracket 304 includes both the groove formed by etching the third fin body truncation sub-region and the groove 302 formed by the fin body fine truncation process.

[0074] Step 5: forming shallow trench isolation 105 to completely fill the remaining spacing areas between the fin bodies 101 .

[0075] In step five, the shallow trench isolation 105 completely fills the spacer regions formed in each of the fin body truncation regions in step four.

[0076] In the embodiment of the present invention, the oxide layer of the shallow trench isolation 105 is deposited by a fluid chemical vapor deposition (FCVD) process.

[0077] Preferably, Fig. 8A and Figure 8B As shown, the oxide layer of the shallow trench isolation 105 is first deposited by the FCVD process to completely fill the reserved spacer between the fin bodies 101 and extend outside the reserved spacer between the fin bodies 101. Then, a chemical mechanical polishing process is performed to make the top surface of the oxide layer of the shallow trench isolation 105 flush with the top surface of the fin body 101. Fig.12F The shallow trench isolation 105 is also shown.

[0078] Step 6: Fig.9A and Fig. 9B As shown, the shallow trench isolation 105 is etched back to expose the top section of each fin 101 .

[0079] The top surface of the first dielectric layer 103 in the first groove 301 is also etched back to below the top surface of the fin body 101 , and the first dielectric layer 103 filled in the first groove 301 after the back etching forms the single diffusion region cut-off structure.

[0080] Figure 12G The structure after the shallow trench isolation 105 is etched back is also shown.

[0081] Step 7: Fig. 10A and Fig. 10B As shown, a superimposed structure of a first gate dielectric layer and a polysilicon gate 102 is formed in the formation area of ​​the gate structure, and a corresponding polysilicon gate 102 is also formed in the single diffusion area cut-off structure. The polysilicon gate 102 between the single diffusion area cut-off structures covers the top surface and side surfaces of the fin body 101.

[0082] Fig.12H The structure after the formation of the polysilicon gate 102 is also shown. Generally, the polysilicon gate 102 is formed by first depositing a polysilicon layer all over, then defining a formation area of ​​the gate structure by a photolithography process, and then etching the polysilicon layer. Fig.12H In general, a hard mask layer 206 is also required in the patterning and etching of the polysilicon gate 102. Fig.12H In the embodiment, the hard mask layer 206 is formed by stacking an oxide layer 206a and a nitride layer 206b.

[0083] In the embodiment of the present invention, the first gate dielectric layer is a gate oxide layer.

[0084] like Figure 2As shown, each of the polysilicon gates 102 is in a strip-shaped structure perpendicular to the fin body 101 .

[0085] Step eight, forming an embedded epitaxial layer in the fin 101 on both sides of the polysilicon gate 102 , and utilizing the characteristic that the material of the fin 101 on both sides of the first groove 301 is not consumed to improve the quality of the embedded epitaxial layer formed on both sides of the first groove 301 .

[0086] In the NMOS formation region, the material of the embedded epitaxial layer includes SiP; in the PMOS formation region, the material of the embedded epitaxial layer includes SiGe. Fig.11 As shown, the embedded epitaxial layer composed of SiP is marked with 106a, and the embedded epitaxial layer composed of SiGe is marked with 106b.

[0087] Typically, the SiP layer 106a and the SiGe layer 106b are formed separately. Fig.12I As shown, a mask layer 207 is used to cover the PMOS formation area, and then a SiP layer 106a is formed in the NMOS formation area. During the formation of the SiP layer 106a, a groove is first formed, and then the SiP layer 106a is filled. It can be seen from the area shown by the dotted circle 208 that after the groove of the SiP layer 106a is formed, the spacing between it and the first groove 301 is large enough. This is because there is no fin material loss on both sides of the first groove 301, so the SiP layer 106a can grow completely from all sides, thereby maintaining good quality.

[0088] like Fig.12J As shown, then the SiGe layer 106b is formed in the PMOS formation area. Similarly, during the formation of the SiGe layer 106b, a groove is first formed, and then the SiGe layer 106b is filled. It can be seen from the area shown by the dotted circle 209 that after the groove of the SiGe layer 106b is formed, the spacing between it and the first groove 301 is large enough. This is because there is no fin material loss on both sides of the first groove 301, so the SiGe layer 106b can grow completely from all sides, thereby maintaining good quality.

[0089] In the existing second SDB process described in the background technology, Fig.12I The corresponding dotted circle 208 and Fig.12J At the position of the corresponding dotted circle 209, the fin material on both sides of the first groove 301 will be consumed, so that after the grooves of the SiP layer 106a and the SiGe layer 106b are formed, they are directly connected to the first groove 301, and there is no fin material between the two. Therefore, the epitaxial layer cannot be grown on the side near the first groove 301, resulting in abnormal growth of the SiP layer 106a and the SiGe layer 106b.

[0090] The embodiment of the present invention places the etching process of the SDB structure before the fin body truncation process, which can simplify the SDB structure formation process, including the SDB formation area definition process such as the photolithography definition process and the planarization process.

[0091] After forming the first groove 301, i.e., the SDB groove, the embodiment of the present invention does not directly perform the subsequent fin body truncation process, but adds a step of using the first dielectric layer 103 to completely fill the first groove 301. In this way, the fin body truncation process will not cause loss of the fin body 101 material on both sides of the first groove 301; and the fin body 101 material on both sides of the first groove 301 is not lost, which can ensure the subsequent growth conditions of the embedded epitaxial layer, so that the quality of the embedded epitaxial layer is guaranteed.

[0092] Therefore, the embodiment of the present invention can simplify the SDB formation process while preventing the loss of the fin body 101 material on both sides of the SDB groove, thereby ensuring the quality of the embedded epitaxial layer.

[0093] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A method for manufacturing a single diffusion region cut-off structure in FinFET, characterized in that: The steps include: Step 1: forming a plurality of fins on a semiconductor substrate, wherein a spacer region is provided between each of the fins; Step 2: defining a formation area of ​​a single diffusion region cut-off structure, and etching the fin body in the formation area of ​​the single diffusion region cut-off structure to form a first groove; Step 3: filling the first groove with a first dielectric layer; Step 4: performing a fin body truncation process to remove the fin body in the fin body truncation area. In the fin body truncation process, the first dielectric layer protects the fin body material on both sides of the first groove and prevents the material of the fin body on both sides of the first groove from being lost; Step 5: forming shallow trench isolation to completely fill the remaining spacing areas between the fin bodies; Step 6, etching back the shallow trench isolation to expose the top section of each fin body; The top surface of the first dielectric layer in the first groove is also etched back to be below the top surface of the fin body, and the first dielectric layer filled in the first groove after the back etching forms the single diffusion region cut-off structure; Step 7: forming a stacked structure of a first gate dielectric layer and a polysilicon gate in the gate structure formation area, and forming a corresponding polysilicon gate in the single diffusion region cut-off structure, and the polysilicon gate between the single diffusion region cut-off structures covers the top surface and side surfaces of the fin body; Step eight: forming an embedded epitaxial layer in the fin body on both sides of the polysilicon gate, and utilizing the characteristic that the fin body material on both sides of the first groove is not consumed to improve the quality of the embedded epitaxial layer formed on both sides of the first groove.

2. The method for manufacturing a single diffusion region cut-off structure in FinFET according to claim 1, characterized in that: In step three, the first dielectric layer also completely fills the spacing regions between the fins.

3. The method for manufacturing a single diffusion region cut-off structure in a FinFET according to claim 2, wherein: The material of the first dielectric layer includes an oxide layer.

4. The method for manufacturing a single diffusion region cut-off structure in FinFET according to claim 3, characterized in that: The oxide layer of the shallow trench isolation is deposited by FCVD process.

5. The method for manufacturing a single diffusion region cut-off structure in FinFET according to claim 4, characterized in that: In step five, the shallow trench isolation oxide layer is first deposited using the FCVD process to completely fill the retained spacing areas between the fin bodies and extend to outside the retained spacing areas between the fin bodies, and then a chemical mechanical polishing process is performed to make the top surface of the shallow trench isolation oxide layer level with the top surface of the fin body.

6. The method for manufacturing a single diffusion region cut-off structure in a FinFET according to claim 1, wherein: In step one, each of the fins is in a strip-shaped structure and is arranged in parallel.

7. The method for manufacturing a single diffusion region cut-off structure in a FinFET according to claim 6, characterized in that: The fin body cutting process in step 4 is divided into two steps, the first step is a fin body fine cutting process, and the second step is a fin body rough cutting process.

8. The method for manufacturing a single diffusion region cut-off structure in FinFET according to claim 7, characterized in that: The fin body fine truncation process performs truncation on a fin body as a unit, and a fin body truncation region corresponding to the fin body fine truncation process includes a plurality of first fin body truncation sub-regions, each of which corresponds to a formation region of the fin body.

9. The method for manufacturing a single diffusion region cut-off structure in FinFET according to claim 8, characterized in that: The corresponding fin body truncation area of ​​the fin body rough truncation process includes multiple second fin body truncation sub-areas and multiple third fin body truncation sub-areas, each of the second fin body truncation sub-areas is perpendicular to each of the fin bodies, and each of the third fin body truncation sub-areas is parallel to the fin body and includes multiple formation areas of the fin bodies.

10. The method for manufacturing a single diffusion region cut-off structure in FinFET according to claim 2, characterized in that: In step one, a first hard mask layer is used in the process of forming the fin body. The hard mask layer is first formed on the semiconductor substrate, and then the formation area of ​​the fin body is defined by photolithography. Then, the first hard mask layer is etched, and then the semiconductor substrate is etched using the first hard mask layer as a mask to form the fin body.

11. The method for manufacturing a single diffusion region cut-off structure in FinFET according to claim 10, characterized in that: After the growth of the first dielectric layer is completed, a chemical mechanical polishing process is further included to make the top surface of the first dielectric layer and the top surface of the first hard mask layer flush.

12. The method for manufacturing a single diffusion region cut-off structure in FinFET according to claim 1, characterized in that: The first gate dielectric layer is a gate oxide layer.

13. The method for manufacturing a single diffusion region cut-off structure in FinFET according to claim 6, characterized in that: In step seven, each of the polysilicon gates is in a strip structure perpendicular to the fin body.

14. The method for manufacturing a single diffusion region cut-off structure in FinFET according to claim 1, characterized in that: In the NMOS formation region, the material of the embedded epitaxial layer includes SiP; in the PMOS formation region, the material of the embedded epitaxial layer includes SiGe.

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