Semiconductor structure

Abstract

The embodiment of the present application provides a semiconductor structure, which comprises: a semiconductor substrate, the semiconductor substrate having a first surface and a second surface opposite to the first surface; a pad, the pad being located on the first surface; a heat transfer layer, the heat transfer layer being located on the first surface, and the heat transfer layer being in contact with the pad; and a groove, the groove being located in the semiconductor substrate, and the groove being in communication with the heat transfer layer. The semiconductor structure provided by the embodiment of the present application is beneficial to solve the problems of poor heat dissipation capacity of the semiconductor structure and local high temperature of the pad in the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit packaging technology, and in particular to a semiconductor structure. Background Technology

[0002] As integrated circuits continue to improve and develop, their size continues to shrink while their functionality continues to increase. However, this functional improvement also requires an increasing number of chips and a gradual increase in the integration and consolidation of semiconductor packaging. Therefore, heat dissipation management has become a crucial design focus in integrated circuit and semiconductor packaging processes. Because chips are embedded within organic materials with poor heat dissipation capabilities, the inability to quickly dissipate heat can lead to decreased system performance or even complete failure.

[0003] In stacked semiconductor packaging structures, heat dissipation performance is particularly important. Because current heat dissipation technologies are unable to effectively conduct or dissipate heat from the pads, excessively high local temperature peaks occur within the semiconductor package structure, negatively impacting the overall reliability of the semiconductor package. Summary of the Invention

[0004] This invention provides a semiconductor structure to solve the problems of poor heat dissipation and excessively high local temperature of pads in semiconductor structures.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a semiconductor substrate having a first surface and a second surface opposite to the first surface; a pad located on the first surface; a heat transfer layer located on the first surface and in contact with the pad; and a groove located within the semiconductor substrate and communicating with the heat transfer layer.

[0006] Alternatively, the groove extends through the semiconductor substrate in a direction perpendicular to the semiconductor substrate; or, the groove is a blind hole located within the semiconductor substrate.

[0007] In addition, the groove is a blind hole located in the semiconductor substrate, and the semiconductor structure further includes a connecting hole, the connecting hole being located in the semiconductor substrate and the extending direction of the connecting hole being different from the extending direction of the groove, the semiconductor substrate exposing one end of the connecting hole, and the other end of the connecting hole being connected to the groove.

[0008] In addition, the heat transfer layer is in contact with the side of the pad.

[0009] In addition, the heat transfer layer is in contact with the bottom surface of the pad facing the second surface.

[0010] In addition, the material of the heat transfer layer is an insulating material.

[0011] In addition, the materials for the heat transfer layer include: thermally conductive silicone, thermally conductive insulating elastic rubber, or thermally conductive filler.

[0012] Additionally, the heat transfer layer covers one end of the groove.

[0013] In addition, there are multiple grooves, and the same heat transfer layer is connected to multiple grooves.

[0014] Additionally, it includes a thermally conductive layer located within the groove, wherein the volume of the thermally conductive layer is smaller than the volume of the groove.

[0015] In addition, the heat-conducting layer is made of a metallic material.

[0016] Additionally, the semiconductor substrate includes a central region and an edge region surrounding the central region, and the groove includes a first groove located in the central region and a second groove located in the edge region, wherein the first groove penetrates the semiconductor substrate and the second groove is a blind via located within the semiconductor substrate.

[0017] In addition, a semiconductor packaging structure is provided, characterized in that it includes a plurality of semiconductor structures described above that are stacked sequentially.

[0018] In addition, the multiple grooves of the multiple semiconductor structures are interconnected.

[0019] In addition, the plurality of semiconductor structures include a first semiconductor structure and a second semiconductor structure; the second semiconductor structure further includes pads located on a second side of the second semiconductor structure; the pads on the first side of the first semiconductor structure and the pads on the second side of the second semiconductor structure are connected.

[0020] Compared with the prior art, the technical solution provided by the embodiments of the present invention has the following advantages:

[0021] This invention provides a semiconductor structure, comprising: a semiconductor substrate having a first surface and a second surface opposite to the first surface; a pad located on the first surface; a heat transfer layer located on the first surface and in contact with the pad; and a groove located within the semiconductor substrate and communicating with the heat transfer layer.

[0022] The semiconductor substrate includes pads, a heat transfer layer, and a groove. The pads are in contact with the heat transfer layer, and the grooves are connected to the heat transfer layer. Therefore, the heat on the pads can be transferred to the grooves through the heat transfer layer, which helps to prevent the accumulation of heat in the pads from causing excessively high local temperature peaks in the semiconductor structure. This prevents the semiconductor structure system from degrading or even failing completely, and thus solves the problems of poor heat dissipation capacity and excessively high local temperature of the pads in the semiconductor structure.

[0023] The groove is a blind via located within the semiconductor substrate. The semiconductor structure further includes a connecting via located within the semiconductor substrate, wherein the extending direction of the connecting via is different from the extending direction of the groove. One end of the connecting via is exposed on the semiconductor substrate, and the other end of the connecting via is connected to the groove. The semiconductor substrate includes a central region and an edge region surrounding the central region. The groove includes a first groove located in the central region and a second groove located in the edge region. The first groove penetrates the semiconductor substrate, and the second groove is a blind via located within the semiconductor substrate.

[0024] The groove can penetrate the semiconductor substrate or be a blind via within the semiconductor substrate. If the groove is a blind via within the semiconductor substrate, a connecting hole with one end exposed outside the semiconductor substrate communicates with the groove. Alternatively, the groove is located in the edge region of the semiconductor substrate. In this way, after the heat from the pad is transferred to the groove through the heat transfer layer, different grooves can be connected to the system environment or exposed to the air, transferring the heat from the pad to the system environment or the air, preventing heat accumulation within the semiconductor structure, and improving the reliability of the semiconductor structure.

[0025] The semiconductor structure further includes a thermally conductive layer located within the groove, wherein the volume of the thermally conductive layer is smaller than the volume of the groove. The presence of a thermally conductive layer with a volume smaller than the groove's volume enhances the groove's ability to absorb heat, allowing for faster dissipation of heat from the pads, preventing signal interference, and improving the reliability of the semiconductor structure. Attached Figure Description

[0026] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0027] Figure 1 A top view of a semiconductor substrate for a semiconductor structure provided in an embodiment of the present invention;

[0028] Figure 2 for Figure 1 A schematic diagram of a cross-sectional structure cut along the PP1 direction;

[0029] Figure 3 for Figure 1 A schematic diagram of another cross-sectional structure cut along the PP1 direction;

[0030] Figure 4 for Figure 1 A schematic diagram of another cross-sectional structure cut along the PP1 direction;

[0031] Figure 5 for Figure 1 A schematic diagram of another cross-sectional structure cut along the PP1 direction;

[0032] Figure 6 This is a cross-sectional schematic diagram of a semiconductor packaging structure provided in an embodiment of the present invention. Detailed Implementation

[0033] As can be seen from the background technology, the heat dissipation performance of existing semiconductor structures needs to be improved.

[0034] In existing technologies, semiconductor packaging heat dissipation often employs cold plates and heat sinks attached to the back of the package structure to transfer heat to the system environment or the air. However, this heat dissipation structure does not directly contact the chip, with the package substrate and casing in between. Due to the low thermal conductivity of the package substrate and the high interfacial thermal resistance between film layers, heat cannot be transferred out efficiently and in a timely manner, resulting in poor overall heat dissipation of the package structure and consequently, poor reliability. Furthermore, existing technologies also incorporate pseudo-connectors within the wafer; however, current heat dissipation technologies cannot effectively conduct or dissipate heat from the pads, leading to excessively high localized temperature peaks within the semiconductor structure and negatively impacting the overall reliability of the semiconductor structure.

[0035] To address the above problems, this invention provides a semiconductor structure that solves the issues of poor heat dissipation and excessively high local temperatures on the pads within the semiconductor structure.

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of the present invention to enable the reader to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0037] Figure 1 A top view of a semiconductor substrate for a semiconductor structure provided in an embodiment of the present invention; Figure 2 for Figure 1 A schematic diagram of a cross-sectional structure cut along the PP1 direction; Figure 3 for Figure 1 A schematic diagram of another cross-sectional structure cut along the PP1 direction; Figure 4 for Figure 1 A schematic diagram of another cross-sectional structure cut along the PP1 direction; Figure 5 for Figure 1 A schematic diagram of another cross-sectional structure cut along the PP1 direction.

[0038] refer to Figure 1 and Figure 2 The semiconductor structure in the first embodiment of the present invention includes: a semiconductor substrate 100 having a first surface 101 and a second surface 105 opposite to the first surface 101; a pad 102 located on the first surface 101; a heat transfer layer 103 located on the first surface 101 and in contact with the pad 102; and a groove 104 located within the semiconductor substrate 100 and communicating with the heat transfer layer 103.

[0039] The semiconductor structure provided in the first embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

[0040] The semiconductor substrate 100 is a wafer or chip.

[0041] like Figure 2 As shown, in this embodiment of the invention, the semiconductor substrate 100 includes a groove 104, a heat transfer layer 103, and a pad 102 located on a first surface 101. The groove 104 communicates with the heat transfer layer 103, and the heat transfer layer 103 contacts the pad 102. In other embodiments, the semiconductor substrate further includes an insulating layer covering the first surface of the semiconductor substrate, and the heat transfer layer and the pad are located on the first surface of the insulating layer.

[0042] In this way, the heat on the pad 102 can be transferred to the groove 104 through the heat transfer layer 103, preventing the local temperature peak of the semiconductor structure caused by the accumulation of heat in the pad 102, thereby preventing the temperature in the semiconductor structure space from rising sharply, and preventing the signal interference, system performance degradation or even complete failure caused by the rapid temperature rise. This solves the problems of poor heat dissipation capacity of the semiconductor structure and excessively high local temperature of the pad 102 in the semiconductor structure.

[0043] The groove 104 is located within the semiconductor substrate 100. Specifically, as shown... Figure 2 As shown, in this embodiment of the invention, the groove 104 penetrates the semiconductor substrate 100 along a direction perpendicular to the semiconductor substrate 100.

[0044] The depth-to-width ratio of the groove 104 can be from 20:1 to 100:1. Specifically, the depth-to-width ratio of the groove 104 can be 40:1, 60:1 or 80:1.

[0045] The width of the groove 104 can be 2 to 10 μm. Specifically, the width of the groove 104 can be 4 μm, 6 μm or 8 μm.

[0046] In another example, such as Figure 3 As shown, the groove 104 is a blind hole located in the semiconductor substrate 100. When the groove 104 is a blind hole located in the semiconductor substrate 100, the semiconductor structure also includes a connecting hole 106. The connecting hole 106 is located in the semiconductor substrate 100 and the extension direction of the connecting hole 106 is opposite to the extension direction of the groove 104. The semiconductor substrate 100 exposes one end of the connecting hole 106, and the other end of the connecting hole 106 is connected to the groove 104.

[0047] It is understood that the groove 104 in the semiconductor substrate 100 can be a through hole penetrating the semiconductor substrate 100 or a blind hole in the semiconductor substrate 100. When the groove 104 is a blind hole in the semiconductor substrate 100, the groove will be connected to a connecting hole 106 with one end exposed outside the semiconductor substrate 100.

[0048] In this way, every groove 104 in the semiconductor substrate 100 is connected to the system environment or air, which can quickly conduct heat from the groove 104 out of the semiconductor structure, improve the reliability of the semiconductor structure, and solve the problems of poor heat dissipation capacity and excessively high local temperature of the pads in the semiconductor structure.

[0049] like Figure 4 As shown, in another example, the semiconductor structure also includes a thermally conductive layer 107 located within a recess 104, and the volume of the thermally conductive layer 107 is smaller than the volume of the recess 104. It is understood that the thermally conductive layer 107 can be made of a metallic material.

[0050] In this embodiment of the invention, a heat-conducting layer 107 with a volume smaller than the volume of the groove 104 is present in the groove 104. The heat-conducting layer 107 enhances the heat absorption capacity of the groove 104, allowing heat to be dissipated from the pads 102 as quickly as possible, preventing signal interference and improving the reliability of the semiconductor structure. This solves the problems of poor heat dissipation capacity of the semiconductor structure and excessively high local temperature of the pads 102 in the semiconductor structure. Furthermore, the smaller volume of the heat-conducting layer 107 compared to the groove 104 prevents the heat-conducting layer 107 from compressing the groove 104 due to thermal expansion and contraction after heating.

[0051] like Figure 5As shown, a semiconductor substrate 100 may include multiple recesses, such as a first recess 1041 and a second recess 1042. It is understood that multiple recesses 104 can improve the heat dissipation rate of the pads 102 and improve the reliability of the semiconductor structure.

[0052] In embodiments of the present invention, such as Figure 3 As shown, the same heat transfer layer 103 is connected to a groove 104. In another example, as... Figure 5 As shown, the same heat transfer layer 103 is connected to multiple grooves (first groove 1041 and second groove 1042). The multiple grooves 104 can improve the heat dissipation rate of the heat transfer layer 103 and improve the reliability of the semiconductor structure.

[0053] In this embodiment of the invention, the heat transfer layer 103 is connected to the groove 104 in such a way that the heat transfer layer 103 covers one end of the groove 104. In another example, such as Figure 5 As shown, the sidewall of the heat transfer layer 103 is flush with the sidewall of the groove 104, and the heat transfer layer 103 covers one end of the groove 104. It can be understood that the heat transfer layer may also cover only one end of the groove or only part of the end face of the groove. The larger the area of ​​communication between the heat transfer layer 103 and the groove 104, the better the heat conduction effect.

[0054] The heat transfer layer 103 is an insulating material, and the materials of the heat transfer layer 103 include: thermally conductive silicone, thermally conductive insulating elastic adhesive, or thermally conductive filler adhesive.

[0055] Among them, the thermally conductive filler has high thermal conductivity and electrical insulation. It can be vulcanized and solidified at room temperature, playing the roles of adhesion, sealing and molding. At the same time, it can quickly conduct the heat of the heating element out, playing the role of cooling the heating element, and has excellent thermal conductivity.

[0056] The thermally conductive and insulating elastic adhesive uses a silicone rubber base material and boron nitride, alumina, and other ceramic particles as fillers. It offers superior thermal conductivity compared to thermally conductive silicone rubber, and under the same conditions, its thermal resistance is lower than other thermally conductive materials.

[0057] Thermal conductive silicone, including thermal grease, thermal conductive silicone tape, and thermal conductive silicone cloth, is the most widely used thermal conductive material.

[0058] In embodiments of the present invention, such as Figure 3 As shown, the heat transfer layer 103 is in contact with the side surface of the pad 102. In another example, the heat transfer layer is in contact with the bottom surface of the pad facing the second side. It is understood that, as... Figure 4 As shown, the heat transfer layer 103 can simultaneously contact the side surface of the pad 102 and the bottom surface facing the second surface 105. The larger the contact area between the heat transfer layer 103 and the pad 102, the better the heat conduction effect.

[0059] The first embodiment of the present invention provides a semiconductor structure in which heat on the pad 102 can be transferred to the groove 104 through the heat transfer layer 103, and the groove 104 then transfers the heat to the system environment or the air. This solves the problem in existing semiconductor structures where, when a large current signal is conducted through the pad 102, there is a lot of heat at the pad 102, the heat dissipation requirements are high, and due to the low thermal conductivity of the substrate and the high thermal resistance of the multilayer material interface, the heat cannot be transferred out in a timely and efficient manner, resulting in poor heat dissipation capacity of the semiconductor structure. This invention prevents local temperature peaks in the semiconductor structure caused by heat accumulation in the pad 102, and thus prevents a sharp rise in temperature within the semiconductor packaging structure space, which could lead to a decrease in system performance or even complete failure. This solves the problems of poor heat dissipation capacity and excessively high local temperature of the pad 102 in the semiconductor structure.

[0060] See Figure 5 The second embodiment of the present invention also provides a semiconductor structure, which is substantially the same as the previous embodiment, with the main difference being that the semiconductor substrate 100 includes a central region 108 and an edge region 109 surrounding the central region 108, and the groove 104 includes a first groove 1041 located in the central region 108 and a second groove 1042 located in the edge region 109. The semiconductor structure provided by the second embodiment of the present invention will be described in detail below with reference to the accompanying drawings. For parts that are the same as or corresponding to those in the previous embodiment, please refer to the description of the foregoing embodiments, which will not be repeated hereafter.

[0061] like Figure 5 As shown, in a semiconductor structure provided by the second embodiment of the present invention, the semiconductor substrate 100 includes a central region 108 and an edge region 109 surrounding the central region 108. The groove 104 includes a first groove 1041 located in the central region 108 and a second groove 1042 located in the edge region 109. The first groove 1041 penetrates the semiconductor substrate 100, and the second groove 1042 is a blind hole located in the semiconductor substrate 100.

[0062] In summary, it can be understood that the groove 104 can penetrate the semiconductor substrate 100 or the groove 104 can be a blind via within the semiconductor substrate 100. If the groove 104 is a blind via within the semiconductor substrate 100, then the groove 104 is located in the edge region 109 of the semiconductor substrate 100. In this way, after the heat from the pad 102 is transferred to the groove 104 through the heat transfer layer 103, different grooves 104 can be connected to the system environment or exposed to the air, transferring the heat from the pad 102 to the system environment or the air.

[0063] Compared with the first embodiment of the present invention, this embodiment can make each groove 104 in the semiconductor structure connected to the system loop or air without adding a connecting hole 106 in the semiconductor structure. Without increasing the complexity of the semiconductor structure, it ensures that the heat of the groove is quickly conducted out of the semiconductor structure, prevents heat from accumulating in the semiconductor structure, improves the reliability of the semiconductor structure, and solves the problems of poor heat dissipation capacity of the semiconductor structure and excessive local temperature of the pad 102 in the semiconductor structure.

[0064] Figure 6 This is a cross-sectional schematic diagram of a semiconductor packaging structure provided in an embodiment of the present invention.

[0065] A third embodiment of the present invention also provides a semiconductor packaging structure, which includes a plurality of the above-described semiconductor structures stacked sequentially. For example... Figure 6 As shown, the semiconductor package structure includes a semiconductor substrate 100, a second semiconductor substrate 200, and a third semiconductor substrate 300, with multiple grooves 104 of the multiple semiconductor structures interconnected. The interconnection of the multiple grooves 104 of the multiple semiconductor structures to form a single groove 104 reduces the complexity of the semiconductor package structure and facilitates its implementation.

[0066] like Figure 6 As shown, multiple interconnected grooves 104 can connect to the outer surface of the semiconductor package structure. Connecting multiple interconnected grooves 104 to the outer surface of the semiconductor package structure allows for the unified transfer of heat from the pads 102 within the semiconductor package structure to the system environment or air, thus reducing the complexity of the semiconductor package structure. It is understood that the grooves 104 of the multiple semiconductor structures can also be independent, each individually connected to the system environment or air.

[0067] In one example, the semiconductor package structure includes a first semiconductor structure and a second semiconductor structure; the second semiconductor structure also includes a pad 102 located on the second surface 105 of the second semiconductor structure, and the pad 102 on the first surface 101 of the first semiconductor structure and the pad 102 on the second surface 105 of the second semiconductor structure are connected.

[0068] The third embodiment of the present invention provides a semiconductor packaging structure, including multiple semiconductor structures stacked sequentially. The heat of the pads 102 of the multiple semiconductor structures is transferred to the interconnected grooves 104 through the heat transfer layer 103, and then uniformly transferred to the system environmental control or air. While reducing the complexity of the semiconductor packaging structure, it solves the problems of poor heat dissipation capacity of the semiconductor packaging structure and excessively high local temperature of the pads 102 in the semiconductor packaging structure.

[0069] This invention provides a semiconductor structure and semiconductor packaging structure. Through a heat transfer layer contacting pads and grooves, heat from the pads is transferred to the grooves, and then the heat from the grooves is transferred to the system environment or the air. This prevents the problems of poor heat dissipation in semiconductor structures and semiconductor packaging structures caused by high heat accumulation at the pads when conducting large current signals, high heat dissipation requirements, low substrate thermal conductivity, and high interfacial thermal resistance of multilayer materials, which prevent timely and efficient heat transfer. It also prevents local temperature peaks in the semiconductor structure caused by heat accumulation in the pads, thereby preventing a rapid temperature rise within the semiconductor packaging structure that could lead to system performance degradation or even complete failure. This solves the problems of poor heat dissipation in semiconductor packaging structures and excessively high local temperatures at the pads in semiconductor structures.

[0070] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of the present invention. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A semiconductor substrate having a first surface and a second surface opposite to the first surface; The pads are located on the first surface; A heat transfer layer is located on the first surface and is in contact with the pad. A groove, wherein the groove is located within the semiconductor substrate and is in communication with the heat transfer layer; Wherein, the sidewall of the heat transfer layer is flush with the sidewall of the groove; The number of grooves is multiple, and the same heat transfer layer is connected to multiple grooves; and The semiconductor structure further includes a thermally conductive layer located within the groove, wherein the volume of the thermally conductive layer is smaller than the volume of the groove.

2. The semiconductor structure according to claim 1, characterized in that, The groove extends through the semiconductor substrate in a direction perpendicular to the semiconductor substrate; or, the groove is a blind hole located within the semiconductor substrate.

3. The semiconductor structure according to claim 2, characterized in that, The groove is a blind hole located within the semiconductor substrate. The semiconductor structure further includes a connecting hole located within the semiconductor substrate, wherein the extending direction of the connecting hole is different from the extending direction of the groove, one end of the connecting hole is exposed on the semiconductor substrate, and the other end of the connecting hole is connected to the groove.

4. The semiconductor structure according to claim 1, characterized in that, The heat transfer layer is in contact with the side of the pad.

5. The semiconductor structure according to claim 1, characterized in that, The heat transfer layer is in contact with the bottom surface of the pad facing the second surface.

6. The semiconductor structure according to claim 1, characterized in that, The material of the heat transfer layer is an insulating material.

7. The semiconductor structure according to claim 6, characterized in that, The materials for the heat transfer layer include: thermally conductive silicone, thermally conductive insulating elastic rubber, or thermally conductive filler.

8. The semiconductor structure according to claim 1, characterized in that, The heat transfer layer covers one end of the groove.

9. The semiconductor structure according to claim 1, characterized in that, The heat-conducting layer is made of a metallic material.

10. The semiconductor structure according to any one of claims 1-9, characterized in that, The semiconductor substrate includes a central region and an edge region surrounding the central region. The groove includes a first groove located in the central region and a second groove located in the edge region, wherein the first groove penetrates the semiconductor substrate and the second groove is a blind via located within the semiconductor substrate.

11. A semiconductor packaging structure, characterized in that, It includes a plurality of semiconductor structures as described in any one of claims 1-10, which are stacked sequentially.

12. The semiconductor packaging structure according to claim 11, characterized in that, The multiple grooves of the multiple semiconductor structures are connected together.

13. The semiconductor packaging structure according to claim 11, characterized in that, The plurality of semiconductor structures include a first semiconductor structure and a second semiconductor structure; the second semiconductor structure further includes pads located on a second side of the second semiconductor structure; the pads on the first side of the first semiconductor structure and the pads on the second side of the second semiconductor structure are connected.

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