Front-end-of-line interconnect structures and associated systems and methods

Abstract

The present disclosure provides front-of-line interconnect structures and associated systems and methods. The semiconductor devices can include a dielectric material having a backside formed on a frontside of a semiconductor substrate material, and a frontside; and an interconnect structure extending through the dielectric material. The interconnect structure can be electrically connected to a semiconductor memory array proximate the frontside of the dielectric material. The semiconductor devices can further have an insulative material enclosing at least a portion of the semiconductor memory array and an opening generated during back-end-of-line processing through which an active contact surface at the backside of the interconnect structure is exposed for electrical connection.

Description

[0001] Cross-reference of related applications

[0002] This application claims the rights of U.S. Provisional Patent Application No. 63 / 175,443, filed April 15, 2021; U.S. Provisional Patent Application No. 63 / 071,969, filed August 28, 2020; and U.S. Provisional Patent Application No. 63 / 071,983, filed August 28, 2020, the entire contents of each of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to semiconductor devices, and in several embodiments, more specifically, to systems and methods for forming pre-positioned front-end process interconnect structures for back-side electrical connections. Background Technology

[0004] Microelectronic devices (such as memory devices, microprocessors, and light-emitting diodes) typically comprise one or more semiconductor dies mounted to a substrate and enclosed in a protective capping layer. The semiconductor dies contain functional features such as memory cells, processor circuitry, interconnect circuitry systems, etc. Semiconductor die manufacturers face increasing pressure to reduce the volume occupied by semiconductor dies while increasing the capacity and / or speed of the resulting encapsulated assemblies. To meet these and other demands, semiconductor die manufacturers typically stack multiple semiconductor dies vertically on top of each other to increase the capacity or performance of microelectronic devices within a limited volume on a circuit board or other components on which the semiconductor dies are mounted. In vertical semiconductor die stack assemblies, through-silicon vias (TSVs) are typically used for electrical connections through the dies.

[0005] In semiconductor device manufacturing, front-end processing (FEOL) is used to form individual devices (transistors, capacitors, resistors, etc.) on the active side of a semiconductor substrate. In conventional semiconductor device assemblies, back-end processing (BEOL) of the substrate is used to form various interconnects for back-side electrical connections, such as through-silicon vias, metallization layers, bonding pads, etc. Conventional BEOL processes for forming interconnects require significant processing time and complex manufacturing operations, and their design options for wiring configurations are limited. BEOL processes typically occur immediately preceding the probe phase, where signals are physically acquired from the internal nodes of the semiconductor device for fault analysis and defect detection. Summary of the Invention

[0006] A semiconductor device is described. In some examples, the semiconductor device includes: a dielectric material having a rear side formed on a front side of a semiconductor substrate material and a front side opposite to the rear side; an interconnect structure extending through at least a portion of the dielectric material, the interconnect structure having a rear side defining an active contact surface and a front side opposite to the rear side; a semiconductor memory array adjacent to the front side of the dielectric material and electrically connected to the front side of the interconnect structure; an insulating material enclosing at least a portion of the semiconductor memory array; and an opening through which the active contact surface at the rear side of the interconnect structure is exposed for electrical connection.

[0007] A semiconductor device is described. In some examples, the semiconductor device includes: a dielectric material having a rear side formed on a front side of a semiconductor substrate material and a front side opposite to the rear side; a semiconductor memory array adjacent to the front side of the dielectric material; an insulating material enclosing at least a portion of the semiconductor memory array; an opening extending through the dielectric material to the semiconductor memory array; and an interconnect structure extending through the opening in the dielectric material, the interconnect structure having a rear side defining an active contact surface and a front side opposite to the rear side and electrically connected to the front side of the semiconductor memory array, wherein the active contact surface at the rear side of the interconnect structure is exposed for electrical connection.

[0008] A method for forming electrical connections on the rear side of a semiconductor device is described. In some examples, the method includes: forming, during a front-end process of the semiconductor device, a dielectric material on a semiconductor substrate material having a rear side on a front side of the substrate material and a front side opposite to the rear side; an interconnect structure extending through the dielectric material to the substrate material, the interconnect structure having a rear side electrically connected to a semiconductor memory array adjacent to the front side of the dielectric material and having a front side opposite to the rear side; and an active contact surface on the rear side of the interconnect structure; and exposing the active contact surface for electrical connection access by removing substrate material adjacent to the active contact surface. Attached Figure Description

[0009] Figures 1A to 1G This is an enlarged cross-sectional view showing various stages of manufacturing a semiconductor device with a front-end process interconnect structure according to embodiments of the present technology.

[0010] Figure 2A and 2B This is an enlarged cross-sectional view showing a semiconductor device with a front-end process interconnect structure according to an embodiment of the present technology.

[0011] Figure 3A and 3B This is an enlarged cross-sectional view showing a semiconductor device with a front-end process interconnect structure according to an embodiment of the present technology.

[0012] Figure 4 This is a schematic diagram of a system including a semiconductor device according to an embodiment of the present technology. Detailed Implementation

[0013] The technologies disclosed herein relate to semiconductor devices, systems having semiconductor devices, and related methods for manufacturing semiconductor devices. The term "semiconductor device" generally refers to a solid-state device comprising one or more semiconductor materials. Examples of semiconductor devices include logic devices, memory devices, and diodes. Furthermore, the term "semiconductor device" may refer to a finished device or an assembly or other structure undergoing various processing stages before becoming a finished device.

[0014] Depending on its context, the term "substrate" can refer to a structure supporting an electronic component (e.g., a die), such as a wafer-level substrate, a single-cut die-level substrate, or another die for die stacking applications. Suitable steps of the methods described herein can be performed at the wafer level or at the die level. Furthermore, unless the context otherwise indicates, the structures disclosed herein can be formed using conventional semiconductor manufacturing techniques. For example, materials can be deposited using chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, electroplating, and / or other suitable techniques. Similarly, materials can be removed using, for example, plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques.

[0015] This technology includes semiconductor devices having interconnect structures for forming (e.g., “pre-positioning”) back-side electrical connections during front-end process (FEOL) processing. FEOL is an integrated circuit manufacturing stage in which individual devices (transistors, capacitors, resistors, etc.) are formed on the active side of semiconductor material. Unlike this technology, the FEOL process occurs before the back-side metal interconnect structures are fabricated. Conventional semiconductor device packaging uses back-end process (BEOL) processing to form contact pads, through-silicon vias, interconnect wires, and / or dielectric structures. During BEOL processing, metal and / or dielectric materials are deposited on the wafer to create contacts, insulating materials, metal layers, and / or bonding sites for chip-to-chip and chip-to-package connections. After BEOL processing, a probe phase is performed to physically acquire signals from the internal nodes of the semiconductor device for fault analysis and defect detection. After the probe phase, post-probe processing is performed, which includes processes on the front and / or back sides, including (e.g.) 3D integration (3DI) processing and other processes.

[0016] This technique typically involves forming interconnect structures on or near the active side of a die during FEOL processing (e.g., gate-level processing), and exposing or otherwise accessing the pre-positioned interconnect structures during BEOL or post-probe processing using ultrathin silicon processing or all-silicon removal. In some embodiments, this technique eliminates the need to form BEOL TSVs, allows direct-to-device wiring, and enables other advantages over conventional processes, such as ultrathin die stacking. In some embodiments, interconnect regions are formed in or on a substrate during a first-stage FEOL process. The FEOL-processed interconnects or interconnect regions have active contact surfaces that are at least partially buried within the substrate material and / or dielectric material during at least a portion of the FEOL process. The FEOL interconnects are then exposed for access from the rear side during BEOL or post-probe processing.

[0017] Various FEOL interconnect configurations are available within the scope of this technology, such as arrays, sacrificial oxide, etc., or any combination thereof. Using this technology to process three-dimensional integration (3DI) promises to reduce costs and provide a high degree of design flexibility for wiring and other structures. For example, back-side wiring assemblies can be formed during FEOL processing and brought close together during BEOL or post-probe processing to make through-substrate electrical connections, as described below. In contrast, conventional processes require forming back-side wiring assemblies by patterning, etching, and filling deep holes in silicon to create through-silicon pathways during BEOL processing, which presents various challenges, such as etching and filling relatively deep holes, processing without damaging thin layers, and limitations in layout design. In these respects, the interconnects of this technology are more directly integrated than conventional device connections. Some embodiments can be applied to bonded microelectronic devices, such as NAND circuits. In these configurations, individual complementary metal-oxide-semiconductor (CMOS) and array chips are bonded face-to-face. During FEOL processing, FEOL interconnects are pre-positioned in the silicon and / or dielectric material of the array chip assembly and brought close together to make electrical connections through the rear side of the array chip assembly. In some embodiments, the CMOS assembly includes peripheral circuitry supporting the array but typically does not include memory cells and access devices; the array assembly includes word lines, bit lines, access devices, and memory cells but typically does not include peripheral circuitry such as drivers, latches, controllers, regulators, etc.

[0018] Figures 1A to 1FEnlarged cross-sectional views of various stages of manufacturing a semiconductor device including an array chip assembly 100 (“array assembly 100”) and a CMOS chip assembly 200 (CMOS 200) according to embodiments of the present technology are shown. The array assembly 100 includes a substrate 110, such as a silicon, silicon dioxide, or silicate substrate, on which various materials and components may be formed. The array assembly 100 also includes a dielectric material 112 on the substrate 110. The dielectric material 112 may be silicon oxide or another non-conductive material grown or deposited on the substrate 110, or the dielectric material 112 may be a non-resin or other inorganic material capable of withstanding temperatures above 600°C. The dielectric material may have FEOL pre-positioned interconnects (“first FEOL interconnect 122a” and “second FEOL interconnect 122b”). In this example, the first and second FEOL interconnects 122a and 122b are at least partially embedded within the dielectric material 112. In other embodiments, the first and / or second FEOL interconnects 122a and 122b extend through the dielectric material 112 and are at least partially embedded within the substrate 110, such that the FEOL interconnects can be exposed from the rear side without completely removing the substrate material.

[0019] The array assembly 100 may further include: a first 3D memory array 120a, which is adjacent to the dielectric material 112 and has a first plurality of stacked memory array layers 121a electrically connected to the first FEOL interconnect 122a; and a second 3D memory array 120b, which is adjacent to the dielectric material 112 and has a second plurality of stacked memory array layers 121b electrically connected to the second FEOL interconnect 122b. The first 3D memory array 120a and the second 3D memory array 120b may be designated for individual memory devices after a subsequent single-cut, and although each is illustrated in this example with ten array layers in a stacked configuration, any number of array layers may be present. The array assembly 100 may also have multi-height pillars 136 defining interconnects that electrically couple the first memory array layer 121a to one or more bonding pads 130 via conductive traces / caps 132 and 134 (e.g., copper, solder, etc.). Although not shown, similar multi-height pillars, bonding pads, traces, and caps may be associated with the second memory array layer 121b. In some embodiments, the array assembly 100 may further include one or more bonding pads 140a, which are electrically connected to the first FEOL interconnect 122a, for example, using TSV 146a connected to the bonding pads 140a via conductive traces / caps 142a and 144a. Similarly, the array assembly 100 may further include one or more bonding pads 140b, which are electrically connected to the second FEOL interconnect 122b, for example, using TSV 146b connected to the bonding pads 140b via conductive traces / caps 142b and 144b. Dielectric material 118 may enclose components of a semiconductor device, such as the first and second 3D memory arrays 120a and 120b, pillars 136, bonding pads 130, 140a, 140b, and 210, etc. Although one configuration of the array assembly 100 is depicted in the figures, any suitable configuration of the array assembly 100 is also within the scope of this technology.

[0020] CMOS 200 can be any suitable CMOS chip and includes a substrate 202, active electrical components 204 (e.g., transistors, etc.), and bonding pads 210 configured to be electrically connected to bonding pads 130, 140a, and 140b of the array assembly 100. Figure 1A As shown, the array assembly 100 and the CMOS 200 are formed separately and prepared for bonding via bonding pads 130, 140a, and 140b of the array assembly 100 and bonding pad 210 of the CMOS 200. Next, in Figure 1BIn this configuration, the array assembly 100 is flipped so that the array assembly 100 and the CMOS 200 face each other to position the bonding pads 130, 140a, and 140b toward the bonding pad 210. As shown, each bonding pad of the array assembly 100 corresponds to a separate bonding pad 210 of the CMOS 200; however, in other embodiments, any bonding pad may be configured to bond to a plurality of other bonding pads in a bridging configuration. Figure 1C In this configuration, the bonding pads 130, 140a, and 140b of the array assembly 100 engage and bond to the bonding pad 210 of the CMOS 200 to form an electrical connection between the array assembly 100 and the CMOS 200.

[0021] Figure 1D The demonstration illustrates a BEOL polishing process configured to remove material and thin the substrate 110; however, polishing is stopped before reaching the depths of the first and second FEOL interconnects 122a and 122b, thus preserving the device and structure. Then, as... Figure 1E The diagram illustrates the removal of a silicon substrate 110 by bulk silicon full etching (e.g., wet etching, dry etching, etc.) to expose the rear side 124a of a first FEOL interconnect 122a and the rear side 124b of a second FEOL interconnect 122b, which are accessible from the rear side of the array assembly 100. During the removal of the silicon substrate 110, a dielectric material 112 may be exposed on the rear side of the array assembly 100. Figure 1F Various backside wiring features (formed during BEOL) are shown for forming electrical connections to components (e.g., first and second 3D memory arrays 120a and 120b) of the array assembly 100 via FEOL interconnects 122a and 122b. The wiring features are formed on the backside of the array assembly 100 using a first patterning process to create first and second conductive traces 152a and 152b in a second dielectric passive insulating material 150, and a second patterning process to create first and second wiring interconnects 156a and 156b in a third dielectric material 154. Figure 1G In this configuration, the first and second conductive wiring interconnects 156a and 156b can be further patterned to create first and second bonding pads 160a and 160b to receive assembly interconnects, solder balls, pillars, 3DI interconnects, etc. A dielectric passivation layer 162 (e.g., a nitride or polyamide material) can be added to form the final pattern and protect the surface of the third dielectric material 154 from impact during bonding. Although one configuration of the FEOL interconnect is as follows... Figures 1A to 1G The configuration shown is shown in the figure, but other configurations are also within the scope of this technology.

[0022] Figure 2A and 2B An enlarged cross-sectional view of a semiconductor device having an FEOL interconnect structure configured according to an additional embodiment of the present technology is shown. Figure 2A and 2B The array chip assembly 300 (“array assembly 300”) is shown. Aside from variations in the FEOL interconnects, the array chip assembly 300 is similar in overall structure and configuration to [other components]. Figures 1A to 1G Array assembly 100. Figure 2A and 2B The configuration of the FEOL interconnects is intended to illustrate a variation of the FEOL interconnects; however, further suitable variations are within the scope of this technology. Figure 2A In the process, a semiconductor device having an array assembly 300 has already been subjected to [interaction / component]. Figures 1A to 1E Steps similar to those in [the text] (e.g., bonding pads, grinding, etching, and substrate removal, etc.) result in exposed FEOL interconnects (e.g., similar to [the text]). Figure 1E (The state of the semiconductor device in the CMOS 200). Figures 1A to 1G Same general configuration as in [the context]. Figures 1A to 1G Similar element symbols in the embodiments refer to Figure 2A and 2B Similar features to those in [the text], but may have variations and / or different shapes and sizes, while Figure 2A and 2B The features in the 300 series correspond to features of array assembly 300 that are different from those of array assembly 100.

[0023] Figure 2A An embodiment of an array chip assembly 300 bonded to a CMOS 200 is shown. The array assembly 300 includes a FEOL interconnect 322b having a rear side 324b, which is generally similar to the FEOL interconnect 122b of the array assembly 100, wherein the FEOL interconnect 322b is formed in a dielectric material 112 during FEOL processing. The FEOL interconnect corresponding to the FEOL interconnect 122a of the array assembly 100 is omitted in the array assembly 300. Instead, as Figure 2B As shown, during BEOL processing, BEOL interconnect 322a is formed to create an electrical connection with the first 3D memory array 120a. After the formation of BEOL interconnect 322a, the remaining operations for forming electrical connections with FEOL interconnect 322b and BEOL interconnect 322a (including backside wiring, final pad patterning, and passivation) are similar to those described above. Figure 1F and 1G The operation.

[0024] Figure 3A and 3B An enlarged cross-sectional view showing a semiconductor device configured according to an additional embodiment of the present technology is presented. Figure 3A and 3BThe array chip assembly 400 (“array assembly 400”) is shown. Aside from the variations in FEOL and BEOL processing demonstrated in the array assembly 400, the array chip assembly 400 is similar in overall structure and configuration to… Figures 1A to 1G Array assembly 100. Figure 3A and 3B The configuration of the FEOL structure in this paper is intended to illustrate a variation in FEOL processing; however, further suitable variations are within the scope of this technology. Figure 3A In the process, a semiconductor device having an array assembly 400 has already been subjected to [interaction / component]. Figures 1A to 1E Similar steps (e.g., bonding pads, grinding, etching, and substrate removal) are performed to remove the substrate to expose the dielectric material (e.g., similar to...). Figure 1E The state of the semiconductor device in the image, with different FEOL structures). CMOS200 is shown as having a state similar to... Figures 1A to 1G The same general configuration as in [the game]. Figures 1A to 1G Similar element symbols in the embodiments refer to Figure 3A and 3B Similar features to those in [the text], but may have variations and / or different shapes and sizes, while Figure 3A and 3B The features in the 400 series correspond to features of array assembly 400 that are different from those of array assembly 100.

[0025] Figure 3A An embodiment of an array chip assembly 400 bonded to a CMOS 200 is shown. The array assembly 400 does not have interconnects formed during FEOL processing (e.g., interconnects 122a and 122b of the array assembly 100). Omitting such interconnects prevents complications during BEOL processing, such as arcing during the etching process, and allows interconnects to be selectively formed with a desired layout pattern. In this regard, the first and second conductive traces 152a and 152b and the third dielectric material 154 may be omitted in some embodiments of the array assembly 400. Figure 3B As shown, first and second BEOL interconnect vias 422a and 422b are formed during BEOL processing for electrical connections to the first and second 3D memory arrays 120a and 120b on the rear side of the array assembly 400. After the formation of BEOL interconnects 422a and 422b, the remaining operations for forming electrical connections with BEOL interconnects 422a and 422b (including rear-side wiring, final pad patterning, and passivation) are similar to those described above. Figure 1F and 1G The operation.

[0026] The interconnects described herein may be formed of a suitable conductive material (e.g., copper (Cu)) and may have solder caps to form electrical connections (e.g., tin-silver (SnAg) solder caps). During assembly, the solder caps may be reflowed using combined reflow, acoustic reflow, or other techniques. The bonding pads may be copper pads and may be bonded using copper-to-copper bonding or other suitable techniques.

[0027] Figure 4 This is a block diagram illustrating a system incorporating a semiconductor device according to an embodiment of the present technology. (Referring to the above reference...) Figures 1A to 3B Any of the semiconductor devices described can be incorporated into any of many larger and / or more complex systems, a representative example of which is... Figure 4 The system 1000 is illustrated schematically. System 1000 may include a processor 1002, a memory 1004 (e.g., SRAM, DRAM, flash memory, and / or other memory devices), an input / output device 1006, and / or other subsystems or components 1008. (See above reference) Figures 1A to 3B The described semiconductor assemblies, devices, and device packages may be included in Figure 4 The resulting system 1000 can be configured to perform any of a variety of suitable computing, processing, storage, sensing, imaging, and / or other functions. Therefore, representative examples of system 1000 include, but are not limited to, computers and / or other data processors, such as desktop computers, laptop computers, internet devices, handheld devices (e.g., PDAs, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablet computers, multiprocessor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Additional representative examples of system 1000 include lamps, cameras, vehicles, etc. In these and other examples, system 1000 can be housed in a single unit or distributed across multiple interconnected units, for example, via a communication network. The components of system 1000 may therefore include any of local and / or remote memory storage devices and various suitable computer-readable media.

[0028] As used in the above description, the terms “vertical,” “lateral,” “up,” and “down” may refer to the relative orientation or position of features in a semiconductor device, given the orientation shown in the figures. For example, “upper” or “topmost” may refer to a feature positioned closer to the top of the page than another feature. However, these terms should be interpreted broadly to include semiconductor devices having other orientations (e.g., inverted or tilted orientations, where top / bottom, up / down, above / below, upward / downward, left / right, and far / near end are interchangeable depending on the orientation). Furthermore, for ease of reference, the same element symbols are used throughout this disclosure to identify similar or analogous components or features, but the use of the same element symbols does not imply that features should be interpreted as identical. Indeed, in many instances described herein, features with the same number have multiple embodiments that differ from each other in structure and / or function. Additionally, the same shading may be used to indicate materials with similar composition in cross-section; however, unless specifically indicated herein, the use of the same shading does not imply that materials should be interpreted as identical.

[0029] The foregoing disclosure may also refer to quantities and numbers. Unless otherwise specified, such quantities and numbers should not be considered limiting, but rather as instances of possible quantities and numbers associated with the new technology. Similarly, in this regard, the term "multiple" may be used to refer to a quantity or number. For this purpose, the term "multiple" means any number exceeding one, such as two, three, four, five, etc. For the purposes of this disclosure, the phrase "at least one of A, B, and C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C), encompassing all other possible permutations when more than three elements are listed.

[0030] As will be understood from the foregoing, although specific embodiments of the new technology have been described herein for illustrative purposes, various modifications may be made without departing from this disclosure. Therefore, this disclosure is limited only to the appended claims. Furthermore, specific aspects of the new technology described in the context of the specific embodiments may be combined or eliminated in other embodiments. Moreover, while advantages associated with the specific embodiments have been described in the context of the specific embodiments of this technology, other embodiments may also exhibit such advantages, and not all embodiments must exhibit such advantages to fall within the scope of this disclosure. Therefore, this disclosure and related technologies may cover other embodiments not explicitly shown or described herein.

Claims

1. A semiconductor device comprising: A dielectric material having a rear side formed on a front side of a semiconductor substrate material and a front side opposite to the rear side; An interconnect structure extending through at least a portion of the dielectric material, the interconnect structure having a rear side defining an active contact surface and a front side opposite the rear side; A semiconductor memory array, which is located near the front side of the dielectric material and electrically connected to the front side of the interconnect structure; An insulating material that encloses at least a portion of the semiconductor memory array; An opening, through which the active contact surface at the rear side of the interconnect structure is exposed for electrical connection; and Conductive traces are formed on the active contact surface and electrically connected to the semiconductor memory array through the interconnect structure.

2. The semiconductor device according to claim 1, wherein the dielectric material comprises silicon dioxide.

3. The semiconductor device of claim 1, further comprising an interconnect formed on the conductive trace and electrically connected to the semiconductor memory array through the conductive trace and the interconnect structure.

4. The semiconductor device of claim 1, further comprising a passivation layer formed on the dielectric material.

5. The semiconductor device of claim 4, wherein the passivation layer comprises a nitride material or a polyamide material.

6. The semiconductor device of claim 1, wherein the dielectric material comprises a non-resin material.

7. The semiconductor device according to claim 1, wherein: The semiconductor memory array includes a substrate array layer and additional array layers stacked on the substrate array layer to define the stacked memory array, and the semiconductor device includes bonding pads electrically connected to the stacked memory array. and A CMOS chip assembly that is electrically connected to the stacked memory array via the bonding pad.

8. The semiconductor device according to claim 7, wherein, When the stacked memory array is coupled to the CMOS chip assembly, the active contact surfaces of the interconnect structure are electrically connected to components of the CMOS chip assembly.

9. A semiconductor device comprising: A dielectric material having a rear side formed on a front side of a semiconductor substrate material and a front side opposite to the rear side; A semiconductor memory array located near the front side of the dielectric material; An insulating material that encloses at least a portion of the semiconductor memory array; An opening that extends through the dielectric material into the semiconductor memory array; An interconnect structure extending through the opening in the dielectric material, the interconnect structure having a rear side defining an active contact surface and a front side opposite the rear side and electrically connected to the semiconductor memory array, wherein the active contact surface at the rear side of the interconnect structure is exposed for electrical connection; and Conductive traces are formed on the active contact surface and electrically connected to the semiconductor memory array through the interconnect structure.

10. The semiconductor device of claim 9, further comprising interconnects formed on the interconnect structure and electrically connected to the semiconductor memory array.

11. The semiconductor device of claim 9, further comprising a passivation layer formed on the dielectric material.

12. The semiconductor device of claim 11, wherein the passivation layer comprises a nitride material or a polyamide material.

13. The semiconductor device according to claim 9, wherein: The semiconductor memory array includes a substrate array layer and additional array layers stacked on the substrate array layer to define the stacked memory array, and the semiconductor device includes bonding pads electrically connected to the stacked memory array. and A CMOS chip assembly that is electrically connected to the stacked memory array via the bonding pad.

14. The semiconductor device according to claim 13, wherein, When the stacked memory array is coupled to the CMOS chip assembly, the active contact surfaces of the interconnect structure are electrically connected to components of the CMOS chip assembly.

15. A method for forming an electrical connection on the rear side of a semiconductor device, the method comprising: Formed during the front-end process of the semiconductor device— A dielectric material on a semiconductor substrate material, the dielectric material having a rear side on a front side of the substrate material and a front side opposite to the rear side; An interconnect structure extending through the dielectric material to the substrate material, the interconnect structure having an electrical connection to a rear side of a semiconductor memory array adjacent to the front side of the dielectric material, and having a front side opposite to the rear side; and An active contact surface on the rear side of the interconnect structure; The active contact surface is exposed for electrical connection access by removing the substrate material adjacent to the active contact surface; and Conductive traces are formed on the active contact surface to electrically connect the conductive traces to the semiconductor memory array via the interconnect structure.

16. The method of claim 15, wherein the interconnect structure includes a first interconnect structure, and the semiconductor memory array includes a first semiconductor memory array, and wherein the method further includes forming a second interconnect structure through the dielectric material during back-end processing of the semiconductor device, the second interconnect structure having an electrical connection to a rear side of the second semiconductor memory array adjacent to the front side of the dielectric material.

17. The method of claim 15, further comprising forming a passive insulating material on the dielectric material after removing the substrate material.

18. The method of claim 15, wherein removing the substrate material comprises forming an opening through the substrate material to expose the active contact surface.

19. The method of claim 15, wherein: The semiconductor device is an array chip assembly; and The array chip assembly is bonded to the CMOS chip assembly before the substrate material adjacent to the active contact surface is removed to expose the active contact surface.

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