Electrostatic protection device and electrostatic protection circuit

Abstract

The embodiment of the present application provides a kind of electrostatic protection device and electrostatic protection circuit, electrostatic protection device includes: discharge transistor, on substrate, for discharging static charge;First pad, in first metal layer, with the drain region of the discharge transistor electrically connected;Wherein, the projection of the first pad on the substrate and the projection of the drain region on the substrate partially overlap.The present application is conducive to reduce the effective chip area of electrostatic protection device, and improve the electrostatic discharge speed and discharge capacity of electrostatic protection device.

Description

Technical Field

[0001] This invention relates to the semiconductor field, and in particular to an electrostatic discharge (ESD) protection device and ESD protection circuit. Background Technology

[0002] Static electricity is everywhere. Without electrostatic discharge (ESD) protection circuits, a chip can be quickly damaged by various types of static electricity, and this damage is often fatal.

[0003] To improve the electrostatic discharge capability of electrostatic protection circuits, discharge transistors typically need to be large in size. In addition, the pulse characteristics of electrostatic protection circuits mean that resistors and capacitors occupy a large chip area. Combined with the large area of ​​the discharge transistors, this results in a large effective area for the electrostatic protection circuits applied to the chip pins.

[0004] As the number of chip pins gradually increases, reducing the effective circuit area of ​​the electrostatic discharge (ESD) protection circuit becomes a worthwhile optimization direction to explore. Summary of the Invention

[0005] This invention provides an electrostatic discharge (ESD) protection device and an ESD protection circuit, which helps to reduce the effective chip area of ​​the ESD protection device and improve the ESD discharge speed and discharge capacity of the ESD protection device.

[0006] To address the aforementioned problems, this invention provides an electrostatic discharge protection device, comprising: a discharge transistor located on a substrate for discharging electrostatic charges; a first pad located on a first metal layer and electrically connected to the drain region of the discharge transistor; wherein the projection of the first pad on the substrate partially overlaps with the projection of the drain region on the substrate.

[0007] In addition, the projection of the first pad on the substrate is called the first projection, and the projection of the drain region on the substrate is called the second projection, with the first projection located within the second projection.

[0008] In addition, the electrostatic protection device further includes: a second metal layer located between the first metal layer and the drain region, the second metal layer being electrically connected to the first metal layer via a conductive plug, and the drain region being electrically connected to the second metal layer via a first contact hole.

[0009] In addition, the projection of the conductive plug on the substrate is referred to as the third projection, and the projection of the first contact hole on the substrate is referred to as the fourth projection. Both the third projection and the fourth projection are located within the second projection.

[0010] In addition, a plurality of the first contact holes form a first contact hole array, and the first contact hole array is centrally symmetrical with respect to the center of the drain region.

[0011] In addition, the first contact hole is a recessed contact hole. This helps to reduce the contact resistance between the first contact hole and the drain region, thereby improving the electrostatic discharge capability of the electrostatic protection device.

[0012] Furthermore, the gate structure of the discharge transistor is annular, and the distance from the outer edge of the first contact hole array to the inner edge of the corresponding gate structure is equal. This facilitates the uniform flow of discharge current in multiple directions from the first contact hole array toward the gate structure, ensuring that the discharge transistor has good current discharge capability.

[0013] Furthermore, the source region of the discharge transistor is connected to a second contact hole, and the distance from the second contact hole to the gate structure of the discharge transistor is less than the distance from the first contact hole to the gate structure of the discharge transistor. This allows the drain region to have a larger exposed area along the discharge current path, resulting in better heat dissipation and preventing overheating damage due to high current, thus extending the service life of the discharge transistor.

[0014] Furthermore, the gate structure of the discharge transistor is ring-shaped, and the drain region is located within the gate structure. This helps to further improve the uniformity of the discharge current.

[0015] In addition, the ring shape includes quadrilaterals, hexagons, and octagons.

[0016] In addition, the internal corners of the annular shape are all greater than 90 degrees. This helps to reduce the current surge intensity at the corners, preventing premature aging and damage due to excessive current surges, and ensuring a longer service life for the discharge transistor.

[0017] In addition, the gate structure of the discharge transistor is centrally symmetrical with respect to the center point of the drain region.

[0018] In addition, the area of ​​the drain region is larger than the area of ​​the source region of the discharge transistor.

[0019] In addition, the electrostatic protection device further includes: a wire bonding pad located on the redistribution metal layer, the wire bonding pad being electrically connected to the first pad, and the redistribution metal layer being located above the first metal layer.

[0020] In addition, the electrostatic protection device further includes a redistribution via for electrically connecting the first metal layer and the redistribution metal layer.

[0021] Furthermore, the projection of the first pad on the substrate is denoted as the first projection, the projection of the drain region on the substrate as the second projection, the projection of the redistribution via on the substrate as the fifth projection, and the projection of the wire bonding pad on the substrate as the sixth projection. The first projection and the fifth projection are both located within the second projection, and the sixth projection is located outside the second projection. This helps to avoid the stress of the wire bonding pad during wire bonding affecting the drain region of the discharge transistor, ensuring that the discharge transistor has good discharge capability. In addition, since the first pad is no longer needed for wire bonding, its size can be reduced.

[0022] In addition, the area of ​​the wire bonding pad is larger than that of the first pad. This helps to reduce the difficulty of wire bonding for ESD protection devices.

[0023] Accordingly, embodiments of the present invention also provide an electrostatic discharge (ESD) protection circuit, comprising: an ESD protection device as described in any of the above claims; a power supply terminal electrically connected to the first pad; and a ground terminal electrically connected to the source region of the discharge transistor.

[0024] In addition, the electrostatic protection circuit also includes an electrostatic pulse sensing circuit connected between the power supply terminal and the ground terminal, used to sense electrostatic pulses at the power supply terminal and output a pulse identification signal, wherein the discharge transistor is turned on or off according to the pulse identification signal.

[0025] In addition, the electrostatic protection circuit also includes a driving circuit connected between the power supply terminal and the ground terminal. The driving circuit receives the pulse identification signal and outputs a driving signal, which is connected to the gate structure of the discharge transistor.

[0026] In addition, the electrostatic pulse sensing circuit includes a resistor and a capacitor. The first end of the resistor is connected to the power supply terminal, the second end of the resistor is connected to the first end of the capacitor, and the second end of the capacitor is connected to the ground terminal. The driving circuit includes an inverter. The input terminal of the inverter is connected to the second end of the resistor, and the output terminal of the inverter is connected to the gate structure of the discharge transistor.

[0027] In addition, the electrostatic pulse sensing circuit includes a resistor and a capacitor. The first end of the capacitor is connected to the power supply terminal, the second end of the capacitor is connected to the first end of the resistor, the second end of the resistor is connected to the ground terminal, and the second end of the capacitor is connected to the gate structure of the discharge transistor.

[0028] Accordingly, embodiments of the present invention also provide an electrostatic discharge (ESD) protection circuit, comprising: an ESD protection device as described in any of the above claims; an input / output terminal electrically connected to the first pad; and a power supply terminal electrically connected to the source region of the discharge transistor.

[0029] In addition, the source region of the discharge transistor is electrically connected to the gate structure of the discharge transistor.

[0030] In addition, the discharge transistor is a P-type transistor.

[0031] Accordingly, embodiments of the present invention also provide an electrostatic discharge (ESD) protection circuit, comprising: an ESD protection device as described in any of the above claims; an input / output terminal electrically connected to the first pad; and a ground terminal electrically connected to the source region of the discharge transistor.

[0032] In addition, the source region of the discharge transistor is electrically connected to the gate structure of the discharge transistor.

[0033] In addition, the discharge transistor is an N-type transistor.

[0034] Compared with the prior art, the technical solution provided by the embodiments of the present invention has the following advantages:

[0035] In the above technical solution, the projection of the first pad overlaps with the projection of the drain region, which helps to reduce the effective chip area of ​​the electrostatic discharge device and thus reserve space for other electronic components in the direction parallel to the substrate surface. In addition, the overlapping projections also help to shorten the wire length between the first pad and the drain region, thereby reducing the parasitic resistance and parasitic capacitance on the electrostatic discharge path, and thus improving the discharge speed and discharge capacity of the electrostatic discharge device. Attached Figure Description

[0036] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0037] Figures 1 to 5 This is a schematic diagram of the structure of an electrostatic protection device provided in an embodiment of the present invention;

[0038] Figure 6 This is a schematic diagram of the structure of an electrostatic protection device provided in another embodiment of the present invention;

[0039] Figure 7 This is a schematic diagram of the structure of an electrostatic protection device provided in another embodiment of the present invention;

[0040] Figures 8 to 13 This is a schematic diagram of the electrostatic protection circuit provided in an embodiment of the present invention. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of the present invention to enable the reader to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0042] refer to Figures 1 to 3 , Figures 1 to 3 This is a schematic diagram of the structure of an electrostatic protection device provided in an embodiment of the present invention; wherein, Figure 1 This is a front view of the electrostatic discharge (ESD) protection device. Figure 2 This is a top view of an electrostatic discharge (ESD) protection device. Figure 3 This is a three-dimensional view of a partial structure of an electrostatic discharge (ESD) protection device.

[0043] The electrostatic discharge protection device includes: a discharge transistor 11 located on a substrate 10 for discharging electrostatic charge; a first pad 12 located on a first metal layer M1 and electrically connected to the drain region 111 of the discharge transistor 11; wherein the projection of the first pad 12 on the substrate 10 partially overlaps with the projection of the drain region 111 on the substrate 10.

[0044] In this embodiment, the projection of the first pad 12 onto the substrate 10 is called the first projection, and the projection of the drain region 111 onto the substrate 10 is called the second projection. The first projection is located within the second projection. This helps to further reduce the effective area of ​​the electrostatic discharge protection device, thereby reserving more space for other electronic components in the direction parallel to the surface of the substrate 10. At the same time, the distance from the first pad 12 to the drain region 111 is the shortest, which helps to improve the electrostatic discharge capability of the electrostatic discharge protection device.

[0045] In this embodiment, the electrostatic protection device further includes: a second metal layer M2 located between the first metal layer M1 and the drain region 111, the second metal layer M2 being electrically connected to the first metal layer M1 via a conductive plug 131, and the drain region 111 being electrically connected to the second metal layer M2 via a first contact hole 132.

[0046] Between the first metal layer M1 and the second metal layer M2, there may be one or more metal layers, and adjacent metal layers may be electrically connected by conductive plugs 131. The conductive plugs 131 and the first contact hole 132 are made of different materials. The conductive plugs 131 are usually made of metal, such as copper, aluminum, cobalt, nickel or an alloy composed of multiple metals, while the first contact hole 132 is usually made of metal semiconductor materials, such as cobalt silicide, nickel silicide, etc.

[0047] In this embodiment, the projection of the conductive plug 131 on the substrate 10 is designated as the third projection, and the projection of the first contact hole 132 on the substrate 10 is designated as the fourth projection. Both the third and fourth projections are located within the second projection. This helps to reduce the effective area of ​​the electrostatic discharge protection device.

[0048] Furthermore, the fourth projection is also located within the first projection. In this way, the first pad 12 can be connected to the drain region 111 by a vertical connection, without increasing the conductive path length of the discharge current in the second metal layer M2 and the conductive plug 131. This helps to reduce the parasitic resistance of the discharge current flow path and improve the discharge capability of the electrostatic protection device.

[0049] In this embodiment, reference Figure 4 Multiple first contact holes 132 form a first contact hole array 132a, which is centrally symmetrical with respect to the center of the drain region 111. This helps ensure that the flow from the first contact holes 132 to the source 112 (see reference). Figure 1 The discharge current has good uniformity, thus ensuring that the discharge transistor 11 has good discharge capability.

[0050] In other embodiments, multiple smaller first contact holes can be combined to form a first contact hole with a larger cross-sectional size, thereby further reducing the parasitic resistance of the first contact hole and further improving the discharge capability of the electrostatic protection device.

[0051] Continue to refer to Figure 1 , Figure 2 and Figure 3 In one embodiment, both the conductive plug 131 and the first contact hole 132 are completely located below the first pad 12. The ESD discharge current flows from the first pad 12 through the conductive plug 131 to the second metal layer M2, and then through the first contact hole 132 to the drain region 111 of the discharge transistor 11. This minimizes the ESD discharge current path, thereby further improving the discharge capability of the electrostatic discharge device. The first contact hole 132 can even be exempted from the DRC rule; for example, by... Figure 2 The first contact hole 132 of the 4x4 structure is made into a large contact hole, so that the parasitic resistance on the current discharge path is smaller, thereby further improving the discharge capability of the electrostatic protection device.

[0052] In this embodiment, the first contact hole 132 is a groove-type contact hole, meaning that part of the first contact hole 132 is located within the drain region 111. This helps to further reduce the contact resistance between the first contact hole 132 and the drain region 111, thereby improving the electrostatic discharge capability of the electrostatic protection device.

[0053] In this embodiment, reference Figure 4 Discharge transistor 11 (reference) Figure 1 The gate structure 113 is annular in shape, and the distance from the outer edge of the first contact hole array 132a to the inner edge of the gate structure 113 is equal. Specifically, in different directions of the first contact hole array 132a toward the gate structure 113, there are a first spacing d1, a second spacing d2, a third spacing d3, and a fourth spacing d4 between the outer edge of the first contact hole array 132a and the inner edge of the gate structure 113, and the first spacing d1, the second spacing d2, the third spacing d3, and the fourth spacing d4 are equal.

[0054] This allows the discharge current to flow uniformly in multiple directions toward the gate structure 113 in the first contact hole array 132a, ensuring that the discharge transistor 11 has good current discharge capability.

[0055] Continue to refer to Figure 1 and Figure 2 In this embodiment, the source region 112 of the discharge transistor 11 is connected to the second contact hole 133. The distance from the second contact hole 133 to the gate structure 113 of the discharge transistor 11 is smaller than the distance from the first contact hole 132 to the gate structure 113 of the discharge transistor 11. This allows the drain region 111 to have a larger exposed area in the discharge current path, thereby giving the drain region 111 better heat dissipation capabilities and preventing overheating damage due to large current. Consequently, the discharge transistor 11 has good discharge capability and strong reliability.

[0056] In this embodiment, an LDD structure may not be provided between the drain region 111 and the source region 112 to further reduce the on-resistance, improve the discharge capability, and reduce heat generation. In addition, a well region may be added below the drain region 111, or the drain region 111 and the source region 112 may be placed in the well region as a whole to alleviate the leakage problem of the discharge transistor 11.

[0057] In this embodiment, the gate structure 113 of the discharge transistor 11 is ring-shaped, and the drain region 111 is located within the gate structure 113. This helps to further improve the uniformity of the discharge current.

[0058] In this embodiment, the ring shape includes regular polygons such as quadrilaterals, hexagons, and octagons, and the number of sides of the regular polygon is even.

[0059] In this embodiment, all internal corners of the annular shape are greater than 90 degrees. (Reference) Figure 5Taking the annular shape of the gate structure 113 as a regular quadrilateral as an example, the inner contour of the annular shape has a first corner θ1, and the outer contour has a second corner θ2. By setting chamfers at the corners of the inner and outer contours of the annular shape, the first corner θ1 and the second corner θ2 of the annular shape are greater than 90 degrees. This helps to reduce the current surge intensity at the corners of the gate structure 113, avoids premature aging and damage to the corners due to excessive current surges, and ensures that the discharge transistor 11 has a longer service life.

[0060] It should be noted that the small side edges formed by the chamfer are not counted in the number of side edges of the annular shape; in addition, in other embodiments, only the first corner of the inner contour or the second corner of the outer contour may be adjusted, that is, the chamfer is only set at the corner of the inner contour or the outer contour.

[0061] In addition, refer to Figure 6 When the gate structure 213 is non-ring-shaped, it is centrally symmetrical with respect to the center point 211a of the drain region 211. Specifically, in different directions from the center point 211a toward the gate structure 213, the center point 211a and the gate structure 213 have a first center distance d21, a second center distance d22, a third center distance d23, and a fourth center distance d24, and these distances are equal. This helps to ensure the uniformity of the discharge current of the discharge transistor.

[0062] In this embodiment, the area of ​​the drain region 111 is larger than the area of ​​the source region 112 of the discharge transistor 11. This helps to ensure that the drain region 111 has better heat dissipation capabilities.

[0063] Continue to refer to Figure 2 In this embodiment, the electrostatic discharge (ESD) protection device further includes a third metal layer 151 and a fourth metal layer 152. The third metal layer 151, the fourth metal layer 152, and the second metal layer M2 are disposed on the same layer. The third metal layer 151 is connected to the second contact hole 133. In one embodiment, for example, the third metal layer 151 is further connected to a ground terminal to discharge the electrostatic current from the power supply terminal to the ground terminal. The fourth metal layer 152 is electrically connected to the second metal layer M2 to draw out the voltage of the drain region 111. In one embodiment, for example, the second metal layer M2 is connected to the power supply terminal, and the fourth metal layer 152 is used to electrically connect the power supply terminal to other circuits.

[0064] In this embodiment, the fourth metal layer 152 is connected to the second metal layer M2 at a corner, thus reserving a larger space for the third metal layer 151; in other embodiments, refer to Figure 7 On one side of the gate structure 213, the third metal layer 251 and the fourth metal layer 252 are arranged at intervals.

[0065] Continue to refer to Figure 2 In this embodiment, the second metal layer M2, the third metal layer 151, and the fourth metal layer 152 can all be chamfered, similar to... Figure 5 The chamfered structure can also reduce the impact of current on the metal layer, thereby improving the life and reliability of the metal layer.

[0066] In this embodiment, the electrostatic protection device further includes: a wire bonding pad 14 located on the redistribution metal layer M3, the wire bonding pad 14 being electrically connected to the first pad 12, and the redistribution metal layer M3 being located above the first metal layer M1, that is, on the side of the first metal layer M1 away from the substrate 10.

[0067] Since the first pad 12 is no longer needed for wire bonding, the space originally reserved for wire bonding in the first pad 12 can be omitted, thereby reducing the size of the first pad 12. For example, the size of the reduced first pad 12 in the direction parallel to the surface of the substrate 10 can be less than or equal to 30μm×30μm, or even smaller.

[0068] In this embodiment, the electrostatic protection device further includes a redistribution via 141 for electrically connecting the first metal layer M1 and the redistribution metal layer M3.

[0069] Continue to refer to Figure 1 , Figure 2 and Figure 3 In this embodiment, the projection of the first pad 12 on the substrate 10 is called the first projection, the projection of the drain region 111 on the substrate 10 is called the second projection, the projection of the redistribution via 141 on the substrate 10 is called the fifth projection, and the projection of the wire bonding pad 14 on the substrate 10 is called the sixth projection. The first and fifth projections are both located within the second projection, and the sixth projection is located outside the second projection. By redefining the position of the pads used for wire bonding through on-die redistribution layer technology (On Die RDL), it is beneficial to avoid the stress of wire bonding of the wire bonding pad 14 from affecting the drain region 111 of the discharge transistor 11, thereby ensuring that the discharge transistor 11 has good discharge capability.

[0070] In this embodiment, the area of ​​the wire bonding pad 14 is larger than the area of ​​the first pad 12. For example, the area of ​​the wire bonding pad 14 is equal to 60μm × 60μm. This helps to reduce the difficulty of wire bonding for ESD protection devices.

[0071] In this embodiment, the projection of the first pad partially overlaps with the projection of the drain region, which helps to reduce the effective chip area of ​​the electrostatic discharge device and thus reserve space for other electronic components in the direction parallel to the substrate surface. In addition, the overlapping projections also help to shorten the wire length between the first pad and the drain region, thereby reducing the parasitic resistance and parasitic capacitance on the electrostatic discharge path, thereby improving the discharge speed and discharge capacity of the electrostatic discharge device.

[0072] Accordingly, embodiments of the present invention also provide an electrostatic discharge (ESD) protection circuit, which includes any of the ESD protection devices described above.

[0073] refer to Figure 1 and Figure 8 The electrostatic discharge (ESD) protection circuit includes: any of the above-mentioned ESD protection devices 31; power supply terminal V DD Electrically connected to the first pad 14; ground terminal V SS It is electrically connected to the source region 112 of the discharge transistor 11.

[0074] In this embodiment, the electrostatic protection circuit further includes: an electrostatic pulse sensing circuit 32, connected to the power supply terminal V. DD and grounding terminal V SS Between, used to sense the power supply terminal V DD The electrostatic pulse is generated and a pulse identification signal is output. The discharge transistor 11 is turned on or off according to the pulse identification signal.

[0075] Specifically, refer to Figure 9 The electrostatic pulse sensing circuit 32 includes a capacitor 321 and a resistor 322. The first end of the capacitor 321 is connected to the power supply terminal V. DD The second terminal of capacitor 321 is connected to the first terminal of resistor 322, and the second terminal of resistor 322 is connected to ground V. SS The second end of capacitor 321 is connected to the gate structure 113 of the discharge transistor 11.

[0076] It should be noted that, Figure 9 For the sake of simplicity, the electrostatic discharge protection device 31 is represented by a discharge transistor 11. The same simplified drawing method used in other subsequent illustrations will not be explained again.

[0077] In other embodiments, reference is made to Figure 10 The electrostatic discharge protection circuit also includes: a drive circuit 43, connected to the power supply terminal V. DD and grounding terminal V SS In between, the driving circuit 43 receives the pulse identification signal output by the electrostatic pulse sensing circuit 42 and outputs a driving signal to the electrostatic protection device 41. The driving signal is connected to the gate structure of the discharge transistor.

[0078] Specifically, refer to Figure 11Electrostatic pulse sensing circuit 42 (reference) Figure 10 This includes resistor 421 and capacitor 422. The first terminal of resistor 421 is connected to the power supply terminal V. DD The second terminal of resistor 421 is connected to the first terminal of capacitor 422, and the second terminal of capacitor 422 is connected to the ground terminal V. SS ;Driver circuit 43 (reference) Figure 10 It includes an inverter 431, the input terminal of which is connected to the second terminal of resistor 421, and the output terminal of inverter 431 is connected to the gate structure of discharge transistor 41.

[0079] In this embodiment, an electrostatic discharge protection circuit applicable between the power supply terminal and the grounding terminal is provided, which is beneficial to improving the electrostatic discharge capability between the power supply terminal and the grounding terminal.

[0080] Accordingly, embodiments of the present invention also provide an electrostatic discharge (ESD) protection circuit, which includes any of the ESD protection devices described above.

[0081] refer to Figure 13 The electrostatic discharge (ESD) protection circuit includes: any of the above-mentioned ESD protection devices; input / output (I / O) terminals electrically connected to the first pad; and a power supply terminal V. DD It is connected to the source region of the discharge transistor 61.

[0082] Specifically, the source region of the discharge transistor 61 is electrically connected to the gate structure of the discharge transistor 61, and the discharge transistor 61 is a P-type transistor.

[0083] In this embodiment, an electrostatic discharge protection circuit applicable between the input / output terminal and the power supply terminal is provided, which is beneficial to improving the electrostatic discharge capability between the input / output terminal and the power supply terminal.

[0084] refer to Figure 12 The electrostatic discharge (ESD) protection circuit includes: any of the above-mentioned ESD protection devices; input / output (I / O) terminals electrically connected to the first pad; and a ground terminal V. SS It is connected to the source region of the discharge transistor 51.

[0085] Specifically, the source region of the discharge transistor 51 is electrically connected to the gate structure of the discharge transistor 51, and the discharge transistor 51 is an N-type transistor.

[0086] In this embodiment, an electrostatic discharge protection circuit applicable between the input / output terminal and the ground terminal is provided, which is beneficial to improving the electrostatic discharge capability between the input / output terminal and the ground terminal.

[0087] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of the present invention. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An electrostatic protection device, characterized by, include: A discharge transistor, located on a substrate, is used to discharge electrostatic charges; The first pad, located on the first metal layer, is electrically connected to the drain region of the discharge transistor; Wherein, the projection of the first pad on the substrate partially overlaps with the projection of the drain region on the substrate; A second metal layer is located between the first metal layer and the drain region. The second metal layer is electrically connected to the first metal layer through a conductive plug, and the drain region is electrically connected to the second metal layer through a first contact hole. A wire bonding pad is located in the redistribution metal layer. The wire bonding pad is electrically connected to the first pad. The redistribution metal layer is located above the first metal layer. A redistribution via is used to electrically connect the first metal layer and the redistribution metal layer; The projection of the first pad on the substrate is denoted as the first projection, and the projection of the drain region on the substrate is denoted as the second projection, wherein the first projection is located within the second projection; The projection of the wire bonding pad on the substrate is referred to as the sixth projection, which is located outside the second projection.

2. The electrostatic protection device of claim 1, wherein, The projection of the conductive plug on the substrate is denoted as the third projection, and the projection of the first contact hole on the substrate is denoted as the fourth projection. Both the third projection and the fourth projection are located within the second projection.

3. The electrostatic discharge protection device according to claim 2, characterized in that, The first contact holes form a first contact hole array, and the first contact hole array is centrally symmetrical with respect to the center of the drain region.

4. The electrostatic discharge protection device according to claim 3, characterized in that, The first contact hole is a groove-type contact hole.

5. The electrostatic discharge protection device according to claim 3, characterized in that, The gate structure of the discharge transistor is ring-shaped, and the distance from the outer edge of the first contact hole array to the inner edge of the corresponding gate structure is equal.

6. The electrostatic discharge protection device according to claim 3, characterized in that, The source region of the discharge transistor is connected to a second contact hole, and the distance from the second contact hole to the gate structure of the discharge transistor is less than the distance from the first contact hole to the gate structure of the discharge transistor.

7. The electrostatic discharge protection device according to claim 1, characterized in that, The gate structure of the discharge transistor is ring-shaped, and the drain region is located within the gate structure.

8. The electrostatic discharge protection device according to claim 7, characterized in that, The ring shape includes quadrilaterals, hexagons, and octagons.

9. The electrostatic discharge protection device according to claim 7, characterized in that, The internal corners of the ring shape are all greater than 90 degrees.

10. The electrostatic discharge protection device according to claim 1, characterized in that, The gate structure of the discharge transistor is centrally symmetrical with respect to the center point of the drain region.

11. The electrostatic discharge protection device according to claim 1, characterized in that, The area of ​​the drain region is larger than the area of ​​the source region of the discharge transistor.

12. The electrostatic discharge protection device according to claim 1, characterized in that, The projection of the first pad on the substrate is called the first projection, the projection of the drain region on the substrate is called the second projection, and the projection of the redistribution via on the substrate is called the fifth projection. The first projection and the fifth projection are both located within the second projection.

13. The electrostatic discharge protection device according to claim 12, characterized in that, The area of ​​the wire bonding pad is larger than the area of ​​the first pad.

14. An electrostatic discharge protection circuit, characterized in that, include: The electrostatic discharge protection device as described in any one of claims 1 to 13; The power supply terminal is electrically connected to the first pad. The ground terminal is electrically connected to the source region of the discharge transistor.

15. The electrostatic discharge protection circuit according to claim 14, characterized in that, Also includes: An electrostatic pulse sensing circuit is connected between the power supply terminal and the ground terminal to sense electrostatic pulses at the power supply terminal and output a pulse identification signal. The discharge transistor is turned on or off according to the pulse identification signal.

16. The electrostatic discharge protection circuit according to claim 15, characterized in that, Also includes: A driving circuit is connected between the power supply terminal and the ground terminal. The driving circuit receives the pulse identification signal and outputs a driving signal, which is connected to the gate structure of the discharge transistor.

17. The electrostatic discharge protection circuit according to claim 16, characterized in that, The electrostatic pulse sensing circuit includes a resistor and a capacitor. The first end of the resistor is connected to the power supply terminal, the second end of the resistor is connected to the first end of the capacitor, and the second end of the capacitor is connected to the ground terminal. The driving circuit includes an inverter, the input terminal of which is connected to the second terminal of the resistor, and the output terminal of which is connected to the gate structure of the discharge transistor.

18. The electrostatic discharge protection circuit according to claim 15, characterized in that, The electrostatic pulse sensing circuit includes a resistor and a capacitor. The first end of the capacitor is connected to the power supply terminal, the second end of the capacitor is connected to the first end of the resistor, the second end of the resistor is connected to the ground terminal, and the second end of the capacitor is connected to the gate structure of the discharge transistor.

19. An electrostatic discharge protection circuit, characterized in that, include: The electrostatic discharge protection device as described in any one of claims 1 to 13; The input / output terminals are electrically connected to the first pad. The power supply terminal is electrically connected to the source region of the discharge transistor.

20. The electrostatic discharge protection circuit according to claim 19, characterized in that, The source region of the discharge transistor is electrically connected to the gate structure of the discharge transistor.

21. The electrostatic discharge protection circuit according to claim 19, characterized in that, The discharge transistor is a P-type transistor.

22. An electrostatic discharge protection circuit, characterized in that, include: The electrostatic discharge protection device as described in any one of claims 1 to 13; The input / output terminals are electrically connected to the first pad. The ground terminal is electrically connected to the source region of the discharge transistor.

23. The electrostatic discharge protection circuit according to claim 22, characterized in that, The source region of the discharge transistor is electrically connected to the gate structure of the discharge transistor.

24. The electrostatic discharge protection circuit according to claim 22, characterized in that, The discharge transistor is an N-type transistor.

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