Storage cell structure, storage array structure and preparation method thereof

Abstract

The present application specifically relates to a memory cell structure, a memory array structure and a preparation method thereof, comprising: a selection switch transistor, a first metal layer, a second metal layer and a columnar capacitor; the selection switch transistor is located on a substrate; the first metal layer is located on the selection switch transistor; the second metal layer is located on the first metal layer; the first metal layer at least includes a bit line, the second metal layer at least includes a plate line, and the columnar capacitor is located between the first metal layer and the second metal layer; or the first metal layer at least includes a plate line, the second metal layer at least includes a bit line, and the columnar capacitor is located between the first metal layer and the source of the selection switch transistor; the plate line is electrically connected to the columnar capacitor; the bit line is electrically connected to the drain of the selection switch transistor. The memory cell structure capacitor of the present application is a columnar capacitor, which can achieve a significant reduction in minimum area under the condition of the same storage capacity compared to a memory cell structure with a planar capacitor.

Description

Technical Field

[0001] The present application belongs to the field of storage technology, and specifically relates to a storage unit structure, a storage array structure and a preparation method thereof. Background Art

[0002] Conventional 1T1C (1 transistor 1 capacitor) memory cells require one transistor and one capacitor, and the capacitor is generally a planar capacitor. As integrated circuits shrink along Moore's Law, conventional 1T1C memory cells will encounter the problem of being unable to shrink. This is because in the case of continuous miniaturization, especially to the technology node below the 0.13μm standard CMOS manufacturing process, as the capacitor needs to continue to shrink in area, the capacitance value of the planar capacitor will decrease in proportion to the area reduction. The charge that can be stored in a capacitor that is too small is limited, and the amount of charge stored in the capacitor is greatly reduced, which reduces the performance of the memory cell in actual work and even makes it difficult to read. In order to ensure that the capacitance is large enough when the unit is miniaturized, it is necessary to maintain a larger capacitor structure, which is contrary to the development direction of the continuous shrinking of integrated circuits. Summary of the invention

[0003] Based on this, it is necessary to provide a memory cell structure, a memory array structure and a preparation method thereof that can solve the problems in the above-mentioned background technology.

[0004] One aspect of the present application provides a memory cell structure, comprising: a selection switch transistor, a first metal layer, a second metal layer and a columnar capacitor; wherein:

[0005] The selection switch transistor is located on the substrate;

[0006] The first metal layer is located on the selection switch transistor and has a distance from the selection switch transistor;

[0007] The second metal layer is located on the first metal layer and has a distance from the first metal layer;

[0008] The columnar capacitor comprises: a columnar inner electrode, a capacitor dielectric layer and an outer electrode; the capacitor dielectric layer is located at the periphery of the columnar inner electrode; the outer electrode is located at the periphery of the capacitor dielectric layer;

[0009] The first metal layer includes at least a bit line, the second metal layer includes at least a plate line, and the columnar capacitor is located between the first metal layer and the second metal layer; or the first metal layer includes at least a plate line, the second metal layer includes at least a bit line, and the columnar capacitor is located between the first metal layer and the source of the selection switch transistor;

[0010] The plate line is electrically connected to the columnar capacitor and has a distance therebetween;

[0011] The bit line is electrically connected to the drain of the selection switch transistor.

[0012] In the memory cell structure in the above embodiment, the capacitor is a columnar capacitor, which can achieve a significant reduction in minimum area under the condition of the same storage capacity compared to a memory cell structure with a planar capacitor; by setting the capacitor between the plate line and the selection switch transistor or between the plate line and the bit line, the capacitor can be annealed before forming the back-end metal layer, and the annealing temperature will not be restricted by the back-end metal process technology, and has a more flexible annealing temperature, which can reach between 450°C and 700°C, so that the preparation process of the memory cell structure is compatible with the traditional CMOS planar integration process and ensures that the memory cell structure has better reliability; at the same time, the memory cell structure in the above embodiment adopts a columnar capacitor, and there will be no parasitic capacitance effect of the adjacent metal layer on the capacitor, the selection of the bit line and the plate line is more flexible, and the process flexibility is higher.

[0013] In one embodiment, the capacitor dielectric layer includes a zirconium-doped hafnium oxide thin film layer; the molar ratio of zirconium, hafnium and oxygen in the capacitor dielectric layer is 0.3:0.3:0.5 to 0.7:0.7:2.5.

[0014] In one embodiment, when the first metal layer includes at least a plate line, the second metal layer includes at least a bit line, and the columnar capacitor is located between the first metal layer and the source of the selection switch transistor, the memory cell structure further includes:

[0015] A first dielectric layer is located on the substrate and covers the selection switch transistor; the columnar capacitor is located in the first dielectric layer;

[0016] A second dielectric layer is located between the first dielectric layer and the plate line,

[0017] a first conductive plug, located in the second dielectric layer, wherein the bottom of the first conductive plug contacts the columnar inner electrode, and the top of the first conductive plug contacts the plate line;

[0018] a second conductive plug, located in the first dielectric layer and the second dielectric layer, and electrically connected to the drain of the selection switch transistor;

[0019] a third dielectric layer, located between the second dielectric layer and the bit line and covering the plate line;

[0020] The third conductive plug is located in the third dielectric layer, the bottom of the third conductive plug is electrically connected to the second conductive plug, and the top of the third conductive plug is in contact with the bit line.

[0021] In one embodiment, a metal silicide is further included, which is located between the columnar capacitor and the source of the selection switch transistor and between the second conductive plug and the drain of the selection switch transistor.

[0022] In one embodiment, when the first metal layer includes at least a bit line, the second metal layer includes at least a plate line, and the columnar capacitor is located between the first metal layer and the second metal layer, the memory cell structure further includes:

[0023] A first dielectric layer is located on the substrate and covers the selection switch transistor; the first metal layer also includes a bit line metal layer, and the bit line and the bit line metal layer are both located on the upper surface of the first dielectric layer;

[0024] A second dielectric layer is located on the upper surface of the first dielectric layer and covers the first metal layer; the columnar capacitor is located in the second dielectric layer;

[0025] A third dielectric layer, located between the second dielectric layer and the plate line;

[0026] a first conductive plug, located in the first dielectric layer, wherein the bottom of the first conductive plug contacts the source of the selection switch transistor, and the top of the first conductive plug contacts the bit line metal layer;

[0027] a second conductive plug, located in the first dielectric layer, wherein the bottom of the second conductive plug contacts the drain of the selection switch transistor, and the top of the second conductive plug contacts the bit line;

[0028] The third conductive plug is located in the third dielectric layer, the bottom of the third conductive plug is in contact with the columnar inner electrode, and the top of the third conductive plug is in contact with the plate line.

[0029] In one embodiment, there are a plurality of the plate lines and a plurality of the columnar capacitors, and the plate lines are electrically connected to the columnar capacitors in a one-to-one correspondence.

[0030] In one embodiment, the extension direction of the columnar capacitor is perpendicular to the upper surface of the substrate.

[0031] The present application also provides a method for preparing a memory cell structure, comprising the following steps:

[0032] Providing a substrate, and preparing a selection switch transistor on the substrate;

[0033] A columnar capacitor, a first metal layer and a second metal layer are formed on the selection switch transistor; wherein the first metal layer is located on the selection switch transistor and has a spacing with the selection switch transistor; the second metal layer is located on the first metal layer and has a spacing with the first metal layer; the first metal layer includes at least a bit line, the second metal layer includes at least a plate line, and the columnar capacitor is located between the first metal layer and the second metal layer; or the first metal layer includes at least a plate line, the second metal layer includes at least a bit line, and the columnar capacitor is located between the first metal layer and the source of the selection switch transistor; the plate line is electrically connected to the columnar capacitor and has a spacing with the columnar capacitor; the bit line is electrically connected to the drain of the selection switch transistor.

[0034] In the preparation method of the memory cell structure in the above embodiment, the prepared capacitor is a columnar capacitor, which can achieve a significant miniaturization of the minimum area under the condition of the same storage capacity compared to the memory cell structure with a planar capacitor; by setting the capacitor between the plate line and the selection switch transistor or between the plate line and the bit line, the capacitor can be annealed before forming the back-end metal layer, and the annealing temperature will not be restricted by the back-end metal process technology, and has a more flexible annealing temperature, which can reach between 450°C and 700°C, so that the preparation process of the memory cell structure is compatible with the traditional CMOS planar integration process and ensures that the memory cell structure has good reliability; at the same time, the memory cell structure in the above embodiment adopts a columnar capacitor, and there will be no parasitic capacitance effect of the adjacent metal layer on the capacitor, the selection of the bit line and the plate line is more flexible, and the process flexibility is higher.

[0035] In one embodiment, forming a columnar capacitor, a first metal layer and a second metal layer on the selection switch transistor comprises the following steps:

[0036] A columnar capacitor is formed on the selection switch transistor, wherein the columnar capacitor comprises a columnar inner electrode, a capacitor dielectric layer and an outer electrode; wherein the columnar inner electrode is located on the source of the selection switch transistor; the capacitor dielectric layer is located on the periphery of the columnar inner electrode; the outer electrode is located on the periphery of the capacitor dielectric layer and is electrically connected to the source of the selection switch transistor;

[0037] forming a plate line on the columnar capacitor, wherein the plate line is electrically connected to the columnar inner electrode;

[0038] A bit line is formed on the plate line, and the bit line is electrically connected to the drain of the selection switch transistor.

[0039] In one embodiment, after forming the selection switch transistor and before forming the columnar capacitor, the following steps are further included:

[0040] forming a first dielectric layer on the upper surface of the substrate, wherein the first dielectric layer covers the selection switch transistor;

[0041] Forming the columnar capacitor comprises the following steps:

[0042] forming a capacitor hole in the first dielectric layer;

[0043] forming external electrodes on the sidewalls and bottom of the columnar capacitor hole;

[0044] forming a capacitor dielectric layer on the surface of the outer electrode;

[0045] forming a columnar inner electrode on the inner side of the capacitor dielectric layer;

[0046] After forming the columnar capacitor and before forming the plate line, the following steps are also included:

[0047] forming a second dielectric layer on the upper surface of the first dielectric layer;

[0048] forming a first interconnection through hole in the second dielectric layer, and forming a second interconnection through hole in the second dielectric layer and the first dielectric layer;

[0049] A first conductive plug is formed in the first interconnection through hole, and a second conductive plug is formed in the second interconnection through hole, wherein the bottom of the first conductive plug contacts the columnar inner electrode, and the top of the first conductive plug contacts the plate line; and the bottom of the second conductive plug is electrically connected to the drain of the selection switch transistor;

[0050] After forming the plate line and before forming the bit line, the method further includes the following steps:

[0051] forming a third dielectric layer on the upper surface of the second dielectric layer, wherein the third dielectric layer covers the plate line;

[0052] A third interconnection through hole is formed in the third dielectric layer, and a third conductive plug is formed in the third interconnection through hole, wherein the bottom of the third conductive plug is electrically connected to the second conductive plug, and the top of the third conductive plug is in contact with the bit line.

[0053] In one embodiment, after forming the second dielectric layer, the method further includes annealing the obtained structure at a temperature of 450° C. to 750° C.

[0054] In one embodiment, before forming the first dielectric layer, the method further includes forming metal silicide on at least the upper surface of the source and the upper surface of the drain; the bottom of the columnar capacitor and the bottom of the second conductive plug are in contact with the metal silicide.

[0055] In one embodiment, forming a columnar capacitor, a first metal layer and a second metal layer on the selection switch transistor comprises the following steps:

[0056] forming a first metal layer on the selection switch transistor, wherein the first metal layer includes a bit line and a bit line metal layer; the bit line is electrically connected to the drain of the selection switch transistor, and the bit line metal layer is electrically connected to the source of the selection switch transistor;

[0057] A columnar capacitor is formed on the upper surface of the bit line metal layer, the columnar capacitor comprises a columnar inner electrode, a capacitor dielectric layer and an outer electrode; wherein the columnar inner electrode is located on the bit line metal layer; the capacitor dielectric layer is located at the periphery of the columnar inner electrode; the outer electrode is located at the periphery of the capacitor dielectric layer and is in contact with the bit line metal layer;

[0058] A plate line is formed on the columnar capacitor, and the plate line is electrically connected to the columnar inner electrode.

[0059] The present application also provides a storage array structure, including:

[0060] A plurality of storage unit structures as described in any of the above schemes; a plurality of the selection switch transistors and a plurality of the columnar capacitors are arranged in multiple rows and columns; and the gates of the selection switch transistors in the same row are electrically connected to the same word line, the capacitors in the same row are electrically connected to the same plate line, and the selection switch transistors in the same column are electrically connected to the same bit line.

[0061] The present application also provides a method for preparing a memory array structure, comprising the step of preparing a plurality of the memory cell structures using the method for preparing a memory cell structure as described in any of the above schemes. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, drawings of other embodiments can be obtained based on these drawings without paying any creative work.

[0063] Figure 1 Flow chart of a method for preparing a memory cell structure provided in one embodiment of the present application.

[0064] Figures 2 to 9 Schematic diagram of the structure obtained in each step of the method for preparing a memory cell structure provided in an embodiment of the present application; wherein: Figures 2 to 8 Schematic diagram of the cross-sectional structure of the structure obtained in each step of the method for preparing the memory cell structure provided in one embodiment of the present application, Fig. 9 for Figure 8 Schematic diagram of the three-dimensional structure.

[0065] Fig.10 A circuit diagram of a storage array structure provided in another embodiment of the present application.

[0066] Figures 11 to 17 This is a schematic diagram of the structure obtained in each step of the method for preparing a memory cell structure provided in another embodiment of the present application; wherein, Figures 11 to 16 Schematic diagram of the cross-sectional structure of the structure obtained in each step of the method for preparing a memory cell structure provided in another embodiment of the present application, Fig.17 for Fig.16 Schematic diagram of the three-dimensional structure.

[0067] Fig.18 A circuit diagram of a storage array structure provided in yet another embodiment of the present application.

[0068] Explanation of the reference numerals: 10, substrate; 11, selection switch transistor; 111, gate structure; 1111, word line gate; 1112, side wall; 112, source; 113, drain; 12, capacitor; 121, columnar inner electrode; 122, capacitor dielectric layer; 123, outer electrode; 13, first dielectric layer; 14, second dielectric layer; 15, first conductive plug; 16, second conductive plug; 17, plate line; 171, plate line metal layer; 18, third dielectric layer; 19, third conductive plug; 20, bit line; 201, bit line metal layer; 21, metal silicide. DETAILED DESCRIPTION

[0069] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0070] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0071] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.

[0072] In one embodiment, please refer to Figure 1 , the present application provides a method for preparing a memory cell structure, comprising the following steps:

[0073] S11: providing a substrate, and preparing a selection switch transistor on the substrate;

[0074] S12: Forming a columnar capacitor, a first metal layer and a second metal layer on the selection switch transistor; wherein the first metal layer is located on the selection switch transistor and has a spacing with the selection switch transistor; the second metal layer is located on the first metal layer and has a spacing with the first metal layer; the first metal layer includes at least a bit line, the second metal layer includes at least a plate line, and the columnar capacitor is located between the first metal layer and the second metal layer; or the first metal layer includes at least a plate line, the second metal layer includes at least a bit line, and the columnar capacitor is located between the first metal layer and the source of the selection switch transistor; the plate line is electrically connected to the columnar capacitor and has a spacing with the columnar capacitor; the bit line is electrically connected to the drain of the selection switch transistor.

[0075] In the preparation method of the memory cell structure in the above embodiment, the prepared capacitor is a columnar capacitor, which can achieve a significant miniaturization of the minimum area under the condition of the same storage capacity compared to the memory cell structure with a planar capacitor; by setting the capacitor between the plate line and the selection switch transistor or between the plate line and the bit line, the capacitor can be annealed before forming the back-end metal layer, and the annealing temperature will not be restricted by the back-end metal process technology, and has a more flexible annealing temperature, which can reach between 450°C and 700°C, so that the preparation process of the memory cell structure is compatible with the traditional CMOS planar integration process and ensures that the memory cell structure has good reliability; at the same time, the memory cell structure in the above embodiment adopts a columnar capacitor, and there will be no parasitic capacitance effect of the adjacent metal layer on the capacitor, the selection of the bit line and the plate line is more flexible, and the process flexibility is higher.

[0076] In step S11, refer to Figure 1 Step S11 in Figure 2 , providing a substrate 10 , and preparing a selection switch transistor 11 on the substrate 10 .

[0077] In one example, the substrate 10 may include, but is not limited to, a silicon substrate.

[0078] In one example, preparing the selection switch transistor 11 on the substrate 10 may include the following steps:

[0079] S111: forming an oxide layer (not shown) on the upper surface of the substrate 10. Specifically, the oxide layer may be formed by, but not limited to, a thermal oxidation process, a physical vapor deposition process, or a chemical vapor deposition process;

[0080] S112: forming a conductive layer on the upper surface of the oxide layer, wherein the conductive layer may include but is not limited to a doped polysilicon layer or a metal layer; specifically, the conductive layer may be formed by but is not limited to a physical vapor deposition process or a chemical vapor deposition process;

[0081] S113: etching the conductive layer and the oxide layer to form a word line gate 1111;

[0082] S114: forming a sidewall 1112 on the sidewall of the gate structure 111, the sidewall 1112 and the word line gate 1111 together constitute the gate structure 111; specifically, the sidewall 1112 may be formed by, but not limited to, a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process; the sidewall 1112 may include a silicon oxide layer, a silicon nitride layer or an ONO structure (i.e., a stacked structure of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer);

[0083] S115: performing ion implantation on the substrate 10 based on the sidewall spacer 1112 to form a source 112 and a drain 113 on both sides of the gate structure 111 respectively.

[0084] In an example, see Figure 3 , after forming the selection switch transistor 11, the following steps are also included:

[0085] Metal silicide 21 is formed at least on the upper surface of the source 112 and the drain 113. The specific method of forming the metal silicide is known to those skilled in the art and will not be described here. By forming the metal silicide 21 on the upper surface of the source 112 and the drain 113, the contact resistance between the source 112 and the drain 113 and the conductive plug leading out of the source 112 and the drain 113 can be reduced.

[0086] In an example, see Figure 4 After forming the metal silicide 21, the following steps are also included:

[0087] A first dielectric layer 13 is formed on the upper surface of the substrate 10 , and the first dielectric layer 13 covers the selection switch transistor 11 .

[0088] Specifically, the first dielectric layer 13 may include but is not limited to a silicon oxide layer; the first dielectric layer 13 may be formed by but is not limited to a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process.

[0089] Specifically, the thickness of the first dielectric layer 13 can be set according to actual needs. In this embodiment, the thickness of the first dielectric layer 13 can be 3000 angstroms to 6000 angstroms. Specifically, the thickness of the first dielectric layer 13 can be 3000 angstroms, 4000 angstroms, 5000 angstroms or 6000 angstroms, etc.

[0090] In one embodiment, see Figure 1 Step S12 in Figures 4 to 9 , step S12 may include the following steps:

[0091] S121: forming a columnar capacitor 12 on the selected switch transistor 11, the columnar capacitor 12 comprising a columnar inner electrode 121, a capacitor dielectric layer 122 and an outer electrode 123; wherein the columnar inner electrode 121 is located on the source 112 of the selected switch transistor 11; the capacitor dielectric layer 122 is located at the periphery of the columnar inner electrode 121; the outer electrode 123 is located at the periphery of the capacitor dielectric layer 122 and is electrically connected to the source 112 of the selected switch transistor 11;

[0092] S122: forming a plate line 17 on the columnar capacitor 12, wherein the plate line 17 is electrically connected to the columnar inner electrode 121;

[0093] S123 : forming a bit line 20 on the plate line 17 , wherein the bit line 20 is electrically connected to the drain 113 of the selection switch transistor 11 .

[0094] In one example, step S121 may include the following steps:

[0095] S1211: forming a capacitor hole (not shown) in the first dielectric layer 13; specifically, the capacitor hole may be formed by an etching process, and the capacitor hole penetrates the first dielectric layer 13 along the thickness direction to expose the source electrode 112;

[0096] S1212: forming an external electrode 123 on the sidewall and the bottom of the capacitor hole; specifically, the external electrode 123 may be formed by, but not limited to, an electroplating process, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process; the external electrode 123 may include, but not limited to, a titanium nitride layer; the thickness of the external electrode 123 may be 200 angstroms to 1000 angstroms, for example, the thickness of the external electrode 123 may be 200 angstroms, 500 angstroms, or 1000 angstroms, etc.;

[0097] S1213: forming a capacitor dielectric layer 122 on the surface of the external electrode 123; specifically, the capacitor dielectric layer 122 may be formed by, but not limited to, an atomic layer deposition process; the capacitor dielectric layer 122 may include, but not limited to, a doped hafnium oxide thin film layer, specifically, the capacitor dielectric layer 122 includes, but not limited to, a zirconium-doped hafnium oxide thin film layer; wherein the molar ratio of zirconium, hafnium and oxygen in the capacitor dielectric layer 122 is 0.3:0.3:0.5 to 0.7:0.7:2.5, for example, the molar ratio of zirconium, hafnium and oxygen in the capacitor dielectric layer 122 may be 0.3:0.3:0.5, 0.5:0.5:2 or 0.7:0.7:2.5, etc.; the thickness of the capacitor dielectric material layer may be set according to actual needs, in this embodiment, the thickness of the capacitor dielectric layer 122 may be 6nm to 10nm, specifically, the thickness of the capacitor dielectric layer 122 may be 6nm, 7nm, 8nm, 9nm or 10nm, etc.;

[0098] S1214: forming a columnar inner electrode 121 on the inner side of the capacitor dielectric layer 122; specifically, the columnar inner electrode 121 may be formed by, but not limited to, an electroplating process, a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process; the columnar inner electrode 121 may include, but not limited to, a titanium nitride layer.

[0099] In one example, an alloying treatment step is also included between step S1212 and step S1213, and the temperature of the alloying treatment can be 500°C to 850°C; specifically, the temperature of the alloying treatment can be 500°C, 600°C, 700°C, 800°C or 850°C, etc.

[0100] In an example, see Figure 5 After forming the columnar capacitor 12, the following steps are also included (that is, the following steps are also included between step S121 and step S122):

[0101] forming a second dielectric layer 14 on the upper surface of the first dielectric layer 13;

[0102] A first interconnection through hole (not shown) is formed in the second dielectric layer 14, and a second interconnection through hole (not shown) is formed in the second dielectric layer 14 and the first dielectric layer 13;

[0103] A first conductive plug 15 is formed in the first interconnection through hole, and a second conductive plug 16 is formed in the second interconnection through hole. The bottom of the first conductive plug 15 contacts the columnar inner electrode 121, and the top of the first conductive plug 15 contacts the plate line. The bottom of the second conductive plug 16 is electrically connected to the drain 113 of the selection switch transistor 11.

[0104] Specifically, the second dielectric layer 14 may include but is not limited to a silicon oxide layer; the second dielectric layer 14 may be formed by, but is not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. The thickness of the second dielectric layer 14 may be set according to actual needs. Specifically, the thickness of the second dielectric layer 14 may be 1000 angstroms to 5000 angstroms. For example, the thickness of the second dielectric layer 14 may be 1000 angstroms, 2000 angstroms, 3000 angstroms, 4000 angstroms, or 5000 angstroms, etc.

[0105] Specifically, the first interconnection through hole and the second interconnection through hole may be formed by, but not limited to, a dry etching process; the first conductive plug 15 and the second conductive plug 16 may be formed by, but not limited to, an electroplating process. The first conductive plug 15 and the second conductive plug 16 may be tungsten plugs or copper plugs.

[0106] In one example, after forming the second dielectric layer 14, the step of annealing the obtained structure is also included; since the hafnium oxide formed by conventional processes has no ferroelectricity, annealing is required to form a special crystal phase in the capacitor dielectric layer 122 to have ferroelectricity. The zirconium-doped hafnium oxide after annealing has a ferroelectric effect. Under the external electric field of the external electrode 123 of the capacitor dielectric layer 122 and the columnar internal electrode 121, the iron domain of the hafnium oxide material presents different polarization states with the electric field in different directions. At the same time, the capacitance of the capacitor dielectric layer 122 will change with the change of the polarization state, so that the amount and polarity of the capacitor storage charge change with the change of the polarization direction and size of the capacitor. At the same time, since the polarization strength of the material can still be maintained when the external electric field is removed, the capacitor has a non-volatile charge storage capacity to achieve data storage.

[0107] Specifically, the annealing temperature during the annealing process may be 450° C. to 750° C., more specifically, the annealing temperature may be 450° C., 550° C., 650° C. or 750° C., and so on.

[0108] See also Figure 6 , step S122 may include the following steps:

[0109] S1221: forming a first metal layer (not shown) on the upper surface of the second dielectric layer 14, wherein the first metal layer may include but is not limited to a copper layer or an aluminum layer, etc.;

[0110] S1222: Etching the first metal layer to form a plate line 17, the plate line 17 is in contact with the top of the second conductive plug 16; it should be noted that when the plate line 17 is formed, a plate line metal layer 171 in contact with the top of the third conductive plug 17 is also formed. Figure 6 shown.

[0111] In an example, see Figure 7 , the following steps are also included between step S122 and step S123:

[0112] A third dielectric layer 18 is formed on the upper surface of the second dielectric layer 14 , and the third dielectric layer 18 covers the plate line 17 ;

[0113] A third interconnection through hole (not shown) is formed in the third dielectric layer 18 , and a third conductive plug 19 is formed in the third interconnection through hole. The bottom of the third conductive plug 19 is electrically connected to the second conductive plug 16 . Specifically, the bottom of the third conductive plug 19 contacts the upper surface of the plate line metal layer 171 .

[0114] Specifically, the third dielectric layer 18 may include but is not limited to a silicon oxide layer; the third dielectric layer 18 may be formed by but is not limited to a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process.

[0115] Specifically, the third interconnection through hole may be formed by, but not limited to, a dry etching process; the third conductive plug 19 may be formed by, but not limited to, an electroplating process. The third conductive plug 19 may be a tungsten plug or a copper plug.

[0116] In step S123 , specifically, a bit line 20 is formed on the upper surface of the third dielectric layer 18 , and the bit line 20 is electrically connected to the drain 113 of the selection switch transistor 11 via the third conductive plug 19 , the plate line metal layer 171 and the second conductive plug 16 .

[0117] In one example, step S123 may include the following steps:

[0118] S1231: forming a second metal layer (not shown) on the upper surface of the third dielectric layer 18, wherein the second metal layer may include but is not limited to a copper layer or an aluminum layer, etc.;

[0119] S1232: Etch the second metal layer to form a bit line 20, where the bit line 20 contacts the top of the third conductive plug 19.

[0120] It should be noted that Fig. 9 In order to show the main structure, the dielectric layers are not shown.

[0121] It should be noted that the bit line 20 and the plate line 17 can be interchanged. Fig. 9 The bit line 20 in the circuit can be changed to the plate line 17. Fig. 9 The plate line 17 in the figure can be changed to the bit line 20.

[0122] In another embodiment, please combine Figures 2 to 3 See also Figures 11 to 17 , step S12 may include the following steps:

[0123] S121: forming a first metal layer on the selection switch transistor 11, the first metal layer including a bit line 20 and a bit line metal layer 201; the bit line 20 is electrically connected to the drain of the selection switch transistor 11, and the bit line metal layer 201 is electrically connected to the source of the selection switch transistor 11;

[0124] S122: forming a columnar capacitor 12 on the upper surface of the bit line metal layer 201, the columnar capacitor 12 comprising a columnar inner electrode 121, a capacitor dielectric layer 122 and an outer electrode 123; wherein the columnar inner electrode 121 is located on the bit line metal layer 201; the capacitor dielectric layer 122 is located at the periphery of the columnar inner electrode 121; the outer electrode 123 is located at the periphery of the capacitor dielectric layer 122 and is in contact with the bit line metal layer 201;

[0125] S123 : forming a plate line 17 on the columnar capacitor 12 , wherein the plate line 17 is electrically connected to the columnar inner electrode 121 .

[0126] In an example, see Fig.12 After forming the first dielectric layer 13 and before step S12, the step of forming a first conductive plug 15 and a second conductive plug 16 in the first dielectric layer 13 is also included, the first conductive plug 15 is in contact with the source 112 of the selection switch transistor 11, and the second conductive plug 16 is in contact with the drain 113 of the selection switch transistor 11.

[0127] See also Fig.12 , step S121 may include the following steps:

[0128] S1211: forming a first metal layer (not shown) on the upper surface of the first dielectric layer 13, wherein the first metal layer may include but is not limited to a copper layer or an aluminum layer, etc.;

[0129] S1212: Etching the first metal layer to form a bit line 20 and a bit line metal layer 201, wherein the bit line 20 is electrically connected to the drain 113 of the selection switch transistor 11 via the second conductive plug 16, and the bit line metal layer 201 is electrically connected to the source of the selection switch transistor 11 via the first conductive plug 15. Fig.12 shown.

[0130] In one example, the following steps are further included between step S121 and step S122: forming a second dielectric layer 14 on the upper surface of the first dielectric layer 13, such as Fig.13As shown. Specifically, the second dielectric layer 14 may include but is not limited to a silicon oxide layer; the second dielectric layer 14 may be formed by but is not limited to a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process. The thickness of the second dielectric layer 14 may be set according to actual needs. Specifically, the thickness of the second dielectric layer 14 may be 1000 angstroms to 5000 angstroms. For example, the thickness of the second dielectric layer 14 may be 1000 angstroms, 2000 angstroms, 3000 angstroms, 4000 angstroms or 5000 angstroms, etc.

[0131] In one example, if Fig.14 As shown, step S122 may include the following steps:

[0132] S1221: forming a plurality of capacitor holes (not shown) in the second dielectric layer. The number of the capacitor holes can be set according to actual needs. Fig.14 Specifically, the capacitor hole can be formed by etching process, and the capacitor hole penetrates the second dielectric layer 14 along the thickness direction to expose the bit line metal layer 201;

[0133] S1222: forming an external electrode 123 on the sidewall and the bottom of the capacitor hole; specifically, the external electrode 123 may be formed by, but not limited to, an electroplating process, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process; the external electrode 123 may include, but not limited to, a titanium nitride layer; the thickness of the external electrode 123 may be 200 angstroms to 1000 angstroms, for example, the thickness of the external electrode 123 may be 200 angstroms, 500 angstroms, or 1000 angstroms, etc.;

[0134] S1223: forming a capacitor dielectric layer 122 on the surface of the external electrode 123; specifically, the capacitor dielectric layer 122 may be formed by, but not limited to, an atomic layer deposition process; the capacitor dielectric layer 122 may include, but not limited to, a doped hafnium oxide thin film layer, specifically, the capacitor dielectric layer 122 includes, but not limited to, a zirconium doped hafnium oxide thin film layer; wherein the molar ratio of zirconium, hafnium and oxygen in the capacitor dielectric layer 122 is 0.3:0.3:0.5 to 0.7:0.7:2.5, for example, the molar ratio of zirconium, hafnium and oxygen in the capacitor dielectric layer 122 may be 0.3:0.3:0.5, 0.5:0.5:2 or 0.7:0.7:2.5, etc.; the thickness of the capacitor dielectric material layer may be set according to actual needs, in this embodiment, the thickness of the capacitor dielectric layer 122 may be 6nm to 10nm, specifically, the thickness of the capacitor dielectric layer 122 may be 6nm, 7nm, 8nm, 9nm or 10nm, etc.;

[0135] S1224: forming a columnar inner electrode 121 on the inner side of the capacitor dielectric layer 122; specifically, the columnar inner electrode 121 may be formed by, but not limited to, an electroplating process, a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process; the columnar inner electrode 121 may include, but not limited to, a titanium nitride layer.

[0136] In an example, see Fig.15 , the following steps are also included between step S122 and step S123:

[0137] forming a third dielectric layer 18 on the upper surface of the second dielectric layer 14;

[0138] A plurality of third interconnection through holes (not shown) are formed in the third dielectric layer 18. The specific number of the third interconnection through holes can be set according to actual needs. In the present embodiment, the number of the third interconnection through holes is the same as the number of the columnar capacitors 12, and the third interconnection through holes are arranged in a one-to-one correspondence with the columnar capacitors 12; and a third conductive plug 19 is formed in the third interconnection through hole, and the bottom of the third conductive plug 19 is electrically connected to the columnar inner electrode 121 of the columnar capacitor 12.

[0139] Specifically, the third dielectric layer 18 may include but is not limited to a silicon oxide layer; the third dielectric layer 18 may be formed by but is not limited to a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process.

[0140] Specifically, the third interconnection through hole may be formed by, but not limited to, a dry etching process; the third conductive plug 19 may be formed by, but not limited to, an electroplating process. The third conductive plug 19 may be a tungsten plug or a copper plug.

[0141] In one example, step S123 may include the following steps:

[0142] S1231: forming a second metal material layer (not shown) on the upper surface of the third dielectric layer 18, wherein the second metal material layer may include but is not limited to a copper layer or an aluminum layer, etc.;

[0143] S1232: Etching the second metal material layer to form a plurality of plate lines 17, the plate lines 17 being in contact with the top of the third conductive plug 19, such as Fig.16 and Fig.17 As shown; the number of plate lines 17 can be set according to actual needs. In this embodiment, the number of plate lines 17 is the same as the number of columnar capacitors 12, and they are electrically connected to the columnar capacitors 12 in a one-to-one correspondence via the third conductive plugs 19.

[0144] It should be noted that Fig.17 In order to show the main structure, the dielectric layers are not shown.

[0145] It should be noted that the bit line 20 and the plate line 17 can be interchanged. Fig.17 The bit line 20 in the circuit can be changed to the plate line 17. Fig.17 The plate line 17 in the figure can be changed to the bit line 20.

[0146] Please continue reading Figure 8 , Fig. 9 , Fig.16 and Fig.17 The present application also provides a memory cell structure, which includes: a selection switch transistor 11, a first metal layer, a second metal layer and a columnar capacitor 12; wherein the selection switch transistor 11 is located on a substrate 10; the first metal layer is located on the selection switch transistor 11 and has a spacing with the selection switch transistor 11; the second metal layer is located on the first metal layer and has a spacing with the first metal layer; the columnar capacitor 12 includes: a columnar inner electrode 121, a capacitor dielectric layer 122 and an outer electrode 123; the capacitor dielectric layer 122 is located on the columnar inner electrode 121 The outer electrode 123 is located at the outer periphery of the capacitor dielectric layer 122; the first metal layer includes at least the bit line 20, the second metal layer includes at least the plate line 17, and the columnar capacitor 12 is located between the first metal layer and the second metal layer; or the first metal layer includes at least the plate line 17, the second metal layer includes at least the bit line 20, and the columnar capacitor 12 is located between the first metal layer and the source 112 of the selection switch transistor 11; the plate line 17 is electrically connected to the columnar capacitor 12 and has a spacing with the columnar capacitor 12; the bit line 20 is electrically connected to the drain of the selection switch transistor 11.

[0147] In one example, the substrate 10 may include, but is not limited to, a silicon substrate.

[0148] In one example, the selection switch transistor 11 includes a gate structure 111 in addition to the source 112 and the drain 113 . The gate structure 111 includes a word line gate 1111 and spacers 1112 located at two opposite sides of the word line gate 1111 .

[0149] In one example, the capacitor dielectric layer 122 may include but is not limited to a doped hafnium oxide thin film layer.

[0150] Specifically, the capacitor dielectric layer 122 may include a zirconium-doped hafnium oxide thin film layer; the molar ratio of zirconium, hafnium and oxygen in the capacitor dielectric layer 122 is 0.3:0.3:0.5 to 0.7:0.7:2.5, and more specifically, the molar ratio of zirconium, hafnium and oxygen in the capacitor dielectric layer 122 may be 0.3:0.3:0.5, 0.5:0.5:1 or 0.7:0.7:2.5, etc.

[0151] In one example, the thickness of the capacitor dielectric layer 122 is set according to actual needs. In this embodiment, the thickness of the capacitor dielectric layer 122 includes 6nm to 10nm. Specifically, the thickness of the capacitor dielectric layer 122 can be 6nm, 7nm, 8nm, 9nm or 10nm, etc.

[0152] In one example, the columnar inner electrode 121 may include but is not limited to a metal layer, such as a titanium nitride layer; the outer electrode 123 may include but is not limited to a metal layer, such as a titanium nitride layer. The thickness of the outer electrode 123 may be 200 angstroms to 1000 angstroms, for example, the thickness of the outer electrode 123 may be 200 angstroms, 500 angstroms, or 1000 angstroms, etc.

[0153] In yet another embodiment, see Figure 8 and Fig. 9 The first metal layer at least includes a plate line 17, the second metal layer at least includes a bit line 20, and the columnar capacitor 12 is located between the first metal layer and the source 112 of the selection switch transistor 11; the memory cell structure also includes: a first dielectric layer 13, the first dielectric layer 13 is located on the substrate 10, and the first dielectric layer 13 covers the selection switch transistor 11, and the columnar capacitor 12 is located in the first dielectric layer 13; a second dielectric layer 14, the second dielectric layer 14 is located between the first dielectric layer 13 and the plate line 17; a first conductive plug 15, the first conductive plug 15 is located in the second dielectric layer 14, and the bottom of the first conductive plug 15 is connected to the columnar inner portion of the columnar capacitor 12 The first conductive plug 15 is in contact with the electrode 121, and the top of the first conductive plug 15 is in contact with the plate line 17; the second conductive plug 16, the second conductive plug 16 is located in the first dielectric layer 13 and the second dielectric layer 14, and the bottom of the second conductive plug 16 is electrically connected to the drain 113 of the selection switch transistor 11; the third dielectric layer 18, the third dielectric layer 18 is located between the second dielectric layer 14 and the bit line 20, and the third dielectric layer 18 covers the plate line 17; the third conductive plug 19, the third conductive plug 19 is located in the third dielectric layer 18, the bottom of the third conductive plug 19 is electrically connected to the second conductive plug 16, and the top of the third conductive plug 19 is in contact with the bit line 20.

[0154] In another embodiment, please continue to refer to Figure 16 to Figure 17The first metal layer at least includes a bit line 20, the second metal layer at least includes a plate line 17, and the columnar capacitor 12 is located between the first metal layer and the second metal layer; the storage unit structure also includes: a first dielectric layer 13, the first dielectric layer 13 is located on the substrate 10 and covers the selection switch transistor 11; the first metal layer also includes a bit line metal layer 201, the bit line 20 and the bit line metal layer 201 are both located on the upper surface of the first dielectric layer 13; the columnar capacitor is located on the upper surface of the bit line metal layer 201; the second dielectric layer 14, the second dielectric layer 14 is located on the upper surface of the first dielectric layer 13 and covers the first metal layer; the columnar capacitor 12 is located in the second dielectric layer 14; the third dielectric layer 18, the third dielectric layer 18 is located between the second dielectric layer 14 and the plate line 17; a first conductive plug 15, the first conductive plug 15 is located in the first dielectric layer 13, the bottom of the first conductive plug 15 is in contact with the source 112 of the selection switch transistor 11, and the top of the first conductive plug 15 is in contact with the bit line metal layer 201; a second conductive plug 16, the second conductive plug 16 is located in the first dielectric layer 13, the bottom of the second conductive plug 16 is in contact with the drain 113 of the selection switch transistor 11, and the top of the second conductive plug 16 is in contact with the bit line 20; a third conductive plug 19, the third conductive plug 19 is located in the third dielectric layer 18, the bottom of the third conductive plug 19 is in contact with the columnar inner electrode 121 of the columnar capacitor 12, and the top of the third conductive plug 19 is in contact with the plate line 17.

[0155] In one example, there are multiple plate lines 17 and columnar capacitors 12 , the number of plate lines 17 and columnar capacitors 12 are the same, and the plate lines 17 and columnar capacitors 12 are electrically connected in a one-to-one correspondence.

[0156] Specifically, the thickness of the first dielectric layer 13 can be set according to actual needs. In this embodiment, the thickness of the first dielectric layer 13 can be 3000 angstroms to 6000 angstroms. Specifically, the thickness of the first dielectric layer 13 can be 3000 angstroms, 4000 angstroms, 5000 angstroms or 6000 angstroms, etc. The thickness of the second dielectric layer 14 can be set according to actual needs. Specifically, the thickness of the second dielectric layer 14 can be 1000 angstroms to 5000 angstroms. For example, the thickness of the second dielectric layer 14 can be 1000 angstroms, 2000 angstroms, 3000 angstroms, 4000 angstroms or 5000 angstroms, etc.

[0157] In one example, the first dielectric layer 13, the second dielectric layer 14 and the third dielectric layer 18 may include but are not limited to silicon oxide layers; the first conductive plug 15, the second conductive plug 16 and the third conductive plug 19 may be tungsten plugs or copper plugs.

[0158] In one example, a metal silicide 21 is further included, and the metal silicide 21 is located between the first conductive plug 15 and the source 112 of the selection switch transistor 11 and between the second conductive plug 16 and the drain 113 of the selection switch transistor 11. The metal silicide 21 can reduce the contact resistance between the first conductive plug 15 and the source 112 and the contact resistance between the second conductive plug 16 and the drain 113.

[0159] In yet another embodiment, please combine Figures 8 to 9 See also Fig.10 The present application also provides a storage array structure, which includes multiple storage cell structures as described in the above embodiments; multiple selection switch transistors 11 and multiple capacitors 12 are arranged in multiple rows and columns; and the gates of the selection switch transistors 11 located in the same row are electrically connected to the same word line, the capacitors 12 located in the same row are electrically connected to the same plate line 17, and the selection switch transistors 11 located in the same column are electrically connected to the same bit line.

[0160] It should be noted that Fig.10 The capacitor 12 is not shown in the figure.

[0161] It should be further explained that the gate of the selection switch transistor 10 may have the same conductive structure as the word line.

[0162] It should be further explained that the bit line 20 and the plate line 17 can be interchanged. Fig. 9 The bit line 20 in the circuit can be changed to the plate line 17. Fig. 9 The plate line 17 in the figure can be changed to the bit line 20.

[0163] In one example, the size of a minimum unit in the storage array structure of this embodiment can reach 0.48 μm*0.75 μm, and the area of ​​a single minimum unit can be as small as 0.36 μm. 2 .

[0164] In yet another embodiment, the present application further provides a method for preparing a memory array structure, comprising the step of preparing a plurality of the memory cell structures using the method for preparing the memory cell structure as described in the above embodiment.

[0165] In yet another embodiment, please combine Figure 16 to Figure 17 See also Fig.18 The present application also provides a storage array structure, which includes multiple storage cell structures as described in the above embodiments; multiple selection switch transistors 11 and multiple capacitors 12 are arranged in multiple rows and columns; and the gates of the selection switch transistors 11 located in the same row are electrically connected to the same word line, the capacitors 12 located in the same row are electrically connected to the same plate line 17, and the selection switch transistors 11 located in the same column are electrically connected to the same bit line.

[0166] It should be noted that Fig.18 The selection switch transistor 11 is not shown in the figure; the columnar capacitors 12 in the same column between two adjacent bit lines are called a group of columnar capacitors. Fig.18 It can be seen that a group of columnar capacitors can be controlled by selecting the node of the switch transistor 11 through a bit line BL or a word line WL, and at the same time, a corresponding columnar capacitor 12 can be individually controlled through each plate line PL.

[0167] It should be further explained that the gate of the selection switch transistor 10 may have the same conductive structure as the word line.

[0168] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0169] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A storage unit structure, characterized in that: include: Select a switch transistor, a first metal layer, a second metal layer and a columnar capacitor; wherein, The selection switch transistor is located on the substrate; The first metal layer is located on the selection switch transistor and has a distance from the selection switch transistor; The second metal layer is located on the first metal layer and has a distance from the first metal layer; the columnar capacitor comprises: a columnar inner electrode, a capacitor dielectric layer and an outer electrode; the capacitor dielectric layer is located at the periphery of the columnar inner electrode; the outer electrode is located at the periphery of the capacitor dielectric layer; the capacitor dielectric layer comprises a zirconium-doped hafnium oxide thin film layer; the capacitor dielectric layer has ferroelectricity; The storage unit structure also includes: A first dielectric layer, located on the substrate and covering the selection switch transistor; A second dielectric layer, located on an upper surface of the first dielectric layer; The first metal layer at least includes a bit line, the second metal layer at least includes a plate line, and the columnar capacitor is located between the first metal layer and the second metal layer, the bit line is located on the upper surface of the first dielectric layer, and the second dielectric layer covers the first metal layer; the columnar capacitor is located in the second dielectric layer; there are multiple plate lines and columnar capacitors, and the plate lines are electrically connected to the columnar capacitors in a one-to-one correspondence; or The first metal layer includes at least a plate line, the second metal layer includes at least a bit line, the columnar capacitor is located between the first metal layer and the source of the selection switch transistor, the columnar capacitor is located in the first dielectric layer, and the second dielectric layer is located between the first dielectric layer and the plate line; The plate line is electrically connected to the columnar capacitor and has a distance therebetween; The bit line is electrically connected to the drain of the selection switch transistor; The annealing temperature of the columnar capacitor is 450° C. to 750° C.

2. The storage unit structure according to claim 1, characterized in that: The molar ratio of zirconium, hafnium and oxygen in the capacitor dielectric layer is 0.3:0.3:0.5 to 0.7:0.7:2.

5.

3. The storage unit structure according to claim 1, characterized in that: When the first metal layer includes at least a plate line, the second metal layer includes at least a bit line, and the columnar capacitor is located between the first metal layer and the source of the selection switch transistor, the memory cell structure further includes: a first conductive plug, located in the second dielectric layer, wherein the bottom of the first conductive plug contacts the columnar inner electrode, and the top of the first conductive plug contacts the plate line; a second conductive plug, located in the first dielectric layer and the second dielectric layer, and electrically connected to the drain of the selection switch transistor; a third dielectric layer, located between the second dielectric layer and the bit line and covering the plate line; The third conductive plug is located in the third dielectric layer, the bottom of the third conductive plug is electrically connected to the second conductive plug, and the top of the third conductive plug is in contact with the bit line.

4. The storage unit structure according to claim 3, characterized in that: The device also includes a metal silicide located between the columnar capacitor and the source of the selection switch transistor and between the second conductive plug and the drain of the selection switch transistor.

5. The storage unit structure according to claim 1, characterized in that: When the first metal layer includes at least a bit line, the second metal layer includes at least a plate line, and the columnar capacitor is located between the first metal layer and the second metal layer, the memory cell structure further includes: The first metal layer further comprises a bit line metal layer, and the bit line metal layer is located on the upper surface of the first dielectric layer; a second dielectric layer, covering the first metal layer; A third dielectric layer, located between the second dielectric layer and the plate line; a first conductive plug, located in the first dielectric layer, wherein the bottom of the first conductive plug contacts the source of the selection switch transistor, and the top of the first conductive plug contacts the bit line metal layer; a second conductive plug, located in the first dielectric layer, wherein the bottom of the second conductive plug contacts the drain of the selection switch transistor, and the top of the second conductive plug contacts the bit line; The third conductive plug is located in the third dielectric layer, the bottom of the third conductive plug is in contact with the columnar inner electrode, and the top of the third conductive plug is in contact with the plate line.

6. The memory cell structure according to any one of claims 1 to 5, characterized in that: The extension direction of the columnar capacitor is perpendicular to the upper surface of the substrate.

7. A method for preparing a memory cell structure, characterized in that: The steps include: Providing a substrate, and preparing a selection switch transistor on the substrate; A first dielectric layer, a columnar capacitor, a first metal layer, a second dielectric layer and a second metal layer are formed on the selection switch transistor; the columnar capacitor includes a columnar inner electrode, a capacitor dielectric layer and an outer electrode; the capacitor dielectric layer is located at the periphery of the columnar inner electrode; the outer electrode is located at the periphery of the capacitor dielectric layer; the capacitor dielectric layer includes a zirconium-doped hafnium oxide thin film layer; the capacitor dielectric layer has ferroelectricity; wherein the first dielectric layer covers the selection switch transistor; the second dielectric layer is located on the upper surface of the first dielectric layer; the first metal layer is located on the selection switch transistor and has a spacing with the selection switch transistor; the second metal layer is located on the first metal layer and has a spacing with the first metal layer; the first metal layer at least includes a bit line, the second metal layer at least includes a plate line, and the columnar capacitor is located between the first metal layer and the second metal layer, the bit line is located on the upper surface of the first dielectric layer, and the second dielectric layer covers the first metal layer; the columnar capacitor is located in the second dielectric layer; the plate line and the columnar capacitor are both multiple, and the plate line and the columnar capacitor are electrically connected in a one-to-one correspondence; or the first metal layer at least includes a plate line, the second metal layer at least includes a bit line, and the columnar capacitor is located between the first metal layer and the source of the selection switch transistor, the columnar capacitor is located in the first dielectric layer, and the second dielectric layer is located between the first dielectric layer and the plate line; the plate line is electrically connected to the columnar capacitor and has a spacing with the columnar capacitor; the bit line is electrically connected to the drain of the selection switch transistor; After forming the second dielectric layer, the method further includes performing an annealing treatment on the obtained structure, and the annealing temperature is 450° C. to 750° C.

8. The method for preparing a memory cell structure according to claim 7, characterized in that: Forming a columnar capacitor, a first metal layer and a second metal layer on the selection switch transistor includes the following steps: A columnar capacitor is formed on the selection switch transistor; wherein the columnar inner electrode is located on the source of the selection switch transistor; and the outer electrode is electrically connected to the source of the selection switch transistor; forming a plate line on the columnar capacitor, wherein the plate line is electrically connected to the columnar inner electrode; A bit line is formed on the plate line, and the bit line is electrically connected to the drain of the selection switch transistor.

9. The method for preparing a memory cell structure according to claim 8, characterized in that: The first dielectric layer covers the selection switch transistor; Forming the columnar capacitor comprises the following steps: forming a capacitor hole in the first dielectric layer; forming external electrodes on the sidewalls and bottom of the columnar capacitor hole; forming a capacitor dielectric layer on the surface of the outer electrode; forming a columnar inner electrode on the inner side of the capacitor dielectric layer; After forming the columnar capacitor and before forming the plate line, the following steps are also included: forming a first interconnection through hole in the second dielectric layer, and forming a second interconnection through hole in the second dielectric layer and the first dielectric layer; A first conductive plug is formed in the first interconnection through hole, and a second conductive plug is formed in the second interconnection through hole, wherein the bottom of the first conductive plug contacts the columnar inner electrode, and the top of the first conductive plug contacts the plate line; and the bottom of the second conductive plug is electrically connected to the drain of the selection switch transistor; After forming the plate line and before forming the bit line, the method further includes the following steps: forming a third dielectric layer on the upper surface of the second dielectric layer, wherein the third dielectric layer covers the plate line; A third interconnection through hole is formed in the third dielectric layer, and a third conductive plug is formed in the third interconnection through hole, wherein the bottom of the third conductive plug is electrically connected to the second conductive plug, and the top of the third conductive plug is in contact with the bit line.

10. The method for preparing a memory cell structure according to claim 9, characterized in that: Before forming the first dielectric layer, the method further includes forming metal silicide on at least the upper surface of the source and the upper surface of the drain; the bottom of the columnar capacitor and the bottom of the second conductive plug are both in contact with the metal silicide.

11. The method for preparing a memory cell structure according to claim 7, characterized in that: Forming a columnar capacitor, a first metal layer and a second metal layer on the selection switch transistor includes the following steps: forming a first metal layer on the selection switch transistor, wherein the first metal layer includes a bit line and a bit line metal layer; the bit line is electrically connected to the drain of the selection switch transistor, and the bit line metal layer is electrically connected to the source of the selection switch transistor; A columnar capacitor is formed on the upper surface of the bit line metal layer; wherein the columnar inner electrode is located on the bit line metal layer; and the outer electrode is in contact with the bit line metal layer; A plate line is formed on the columnar capacitor, and the plate line is electrically connected to the columnar inner electrode.

12. A storage array structure, characterized in that: include: A plurality of memory cell structures according to any one of claims 1 to 6; The plurality of selection switch transistors and the plurality of columnar capacitors are arranged in multiple rows and columns; the gates of the selection switch transistors in the same row are electrically connected to the same word line, the capacitors in the same row are electrically connected to the same plate line, and the selection switch transistors in the same column are electrically connected to the same bit line.

13. A method for preparing a storage array structure, characterized in that: The method comprises the steps of preparing a plurality of the memory cell structures by using the method for preparing a memory cell structure according to any one of claims 7 to 11.

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