Dynamic Random Access Memory Device and Method of Forming the Same

Abstract

The present invention discloses a dynamic random access memory device and a method for forming the same, including a substrate, a plurality of bit lines, a plurality of contacts, a dielectric layer, a plurality of storage node pads, and a capacitor structure. The bit lines are disposed on the substrate and include a plurality of first bit lines and at least one second bit line. The contacts are disposed on the substrate and are alternately and separably disposed with the bit lines. The dielectric layer covers the contacts and the bit lines. The storage node pads are disposed in the dielectric layer and are respectively in contact with the contacts. The capacitor structure is disposed on the storage node pads and includes a plurality of first capacitors and at least one second capacitor located above at least one second bit line. Thus, the dynamic random access memory device can achieve more optimized component performance.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device and a method for forming the same, and more particularly to a semiconductor memory device including a dynamic random access memory and a method for forming the same. Background Art

[0002] With the trend of miniaturization of various electronic products, the design of semiconductor memory devices must also meet the requirements of high integration and high density. For a dynamic random access memory (DRAM) with a recessed gate structure, since it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitive structure, it has gradually replaced the dynamic random access memory with only a planar gate structure under the current mainstream development trend.

[0003] Generally speaking, a dynamic random access memory with a recessed gate structure is formed by aggregating a large number of memory cells to form an array region for storing information. Each memory cell can be composed of a transistor component and a capacitor component connected in series to receive voltage information from a word line (WL) and a bit line (BL). In response to product requirements, the memory cell density in the array region must be continuously increased, resulting in an increasing difficulty and complexity in related manufacturing processes and designs. Therefore, the prior art needs to be further improved to effectively improve the performance and reliability of related memory devices. Summary of the Invention

[0004] An object of the present invention is to provide a dynamic random access memory device and a method for forming the same, which form a storage node pad on a substrate through a self-aligned double patterning process or a self-aligned reverse patterning process. In this way, the subsequent formed capacitive structure can include at least a part of the capacitor located on a dummy bit line, becoming a dummy capacitor. With this setting, a dynamic random access memory device can be formed on the premise of simplifying the manufacturing process, and the overall device performance can be optimized by isolating the dummy capacitor from the surrounding active components.

[0005] To achieve the above object, an embodiment of the present invention provides a dynamic random access memory device, including a substrate, a plurality of bit lines, a plurality of contacts, a dielectric layer, a plurality of storage node pads, and a capacitor structure. The bit lines are disposed on the substrate, including a plurality of first bit lines and at least one second bit line, and the at least one second bit line is disposed outside all of the first bit lines. The contacts are disposed on the substrate and are alternately and separably disposed with the bit lines. The dielectric layer covers above the contacts and the bit lines. The storage node pads are disposed in the dielectric layer and respectively contact the contacts. The capacitor structure is disposed on the storage node pads, including a plurality of first capacitors respectively opposite to the storage node pads, and at least one second capacitor above the at least one second bit line.

[0006] To achieve the above object, an embodiment of the present invention provides a method for forming a dynamic random access memory device, including the following steps. First, a substrate is provided, and a plurality of bit lines are formed on the substrate. The bit lines include a plurality of first bit lines and at least one second bit line, and the at least one second bit line is formed outside all of the first bit lines. Then, a plurality of contacts are formed on the substrate, the bit lines and the contacts are alternately arranged, and a dielectric layer is formed above the contacts and the bit lines to cover the contacts and the bit lines. Next, a plurality of storage node pads are formed in the dielectric layer, and the storage node pads are respectively opposite to the contacts. After that, a capacitor structure is formed on the storage node pads, and the capacitor structure includes a plurality of first capacitors respectively opposite to the storage node pads, and at least one second capacitor above the at least one second bit line. Description of the Drawings

[0007] Figures 1 to 9 It is a schematic diagram of the steps of a method for forming a semiconductor memory device in the first embodiment of the present invention, where:

[0008] Figure 1 It is a top view schematic diagram of a semiconductor memory device after forming bit lines;

[0009] Figure 2 is Figure 1 a cross-sectional schematic diagram along the tangent line A-A' in

[0010] Figure 3 It is a top view schematic diagram of a semiconductor memory device after performing a self-aligned double patterning process;

[0011] Figure 4 is Figure 3 a cross-sectional schematic diagram along the tangent line A-A' in

[0012] Figure 5Schematic cross-sectional view of a semiconductor memory device after forming a storage node pad;

[0013] Figure 6 Schematic cross-sectional view of a semiconductor memory device after forming a stacked structure;

[0014] Figure 7 Schematic cross-sectional view of a semiconductor memory device after forming a bottom electrode layer;

[0015] Figure 8 Schematic cross-sectional view of a semiconductor memory device after forming a top electrode layer; and

[0016] Figure 9 Another schematic cross-sectional view of a semiconductor memory device after forming a top electrode layer.

[0017] Figure 10 Schematic cross-sectional view of the semiconductor memory device in the second embodiment of the present invention.

[0018] Figure 11 Schematic cross-sectional view of the semiconductor memory device in the third embodiment of the present invention.

[0019] Figure 12 Schematic cross-sectional view of the semiconductor memory device in the fourth embodiment of the present invention.

[0020] Wherein, the reference numerals are explained as follows:

[0021] 300, 400, 500, 600 Semiconductor memory device

[0022] 100 Substrate

[0023] 101 Insulating region

[0024] 103 Active region

[0025] 130 Dielectric layer

[0026] 131 Oxide layer

[0027] 133 Nitride layer

[0028] 135 Oxide layer

[0029] 160 Bit line

[0030] 160a Bit line contact

[0031] 161 Semiconductor layer

[0032] 162 First bit line

[0033] 163 Barrier layer

[0034] 164 Second bit line

[0035] 165 Conductive layer

[0036] 167 Capping layer

[0037] 170 Spacer structure

[0038] 171 First spacer

[0039] 173 Second spacer

[0040] 175 Third spacer

[0041] 180 Contact

[0042] 182 First contact

[0043] 184 Second contact

[0044] 210 Metal layer

[0045] 211 Storage node pad

[0046] 221, 223 Patterned mask

[0047] 230 Dielectric layer

[0048] 240 Support layer structure

[0049] 241 First support layer

[0050] 242 First opening

[0051] 243 Second support layer

[0052] 244 Third opening

[0053] 245 Third support layer

[0054] 246 Second opening

[0055] 247 Fourth support layer

[0056] 250, 450, 550, 650 Capacitor structure

[0057] 250a, 650a First capacitor

[0058] 250b, 450b, 550b, 650b Second capacitor

[0059] 250c, 650c Third capacitor

[0060] 251 Bottom electrode layer

[0061] 253 Capacitor dielectric layer

[0062] 255 Top electrode layer

[0063] D1 First direction

[0064] D2 Second direction

[0065] D3 Third direction

[0066] W1, W2 Line widths Detailed implementation manners

[0067] To enable those of ordinary skill in the art to which the present invention pertains to further understand the present invention, several preferred embodiments of the present invention are specifically listed below, and in conjunction with the accompanying drawings, the composition and the achieved effects of the present invention are described in detail. Those skilled in the art to which the present invention pertains can, without departing from the spirit of the present invention, refer to the following embodiments and replace, recombine, and mix the features in several different embodiments to complete other embodiments.

[0068] Please refer to Figures 1 to 8 , which shows a schematic diagram of the steps of the method for forming the semiconductor memory device 300 in the first embodiment of the present invention. First, as Figure 1 shown, a substrate 100 is provided, such as a silicon substrate, a silicon-containing substrate (such as SiC, SiGe, etc.), or a silicon-on-insulator (SOI) substrate, etc. At least one insulating region 101 is further formed in the substrate 100, such as a shallow trench isolation (STI), and a plurality of active areas (AA) 103 are defined on the substrate 100. Preferably, the active areas 103 extend along the first direction D1 parallel to and spaced from each other, and are alternately arranged, wherein the first direction D1, for example, intersects and is not perpendicular to the y direction or the x direction, as Figure 1 shown. In one embodiment, the insulating region 101 is formed, for example, by first forming a plurality of trenches (not shown) in the substrate 100 by an etching method, and then filling an insulating material (such as silicon oxide or silicon oxynitride, etc.) in the trenches, but it is not limited thereto.

[0069] In addition, a plurality of buried gates (not shown) can be further formed in the substrate 100. The buried gates, for example, extend parallel to each other along a direction (such as the y direction) and span the active areas 103 to serve as the buried word lines (BWL, not shown) of the semiconductor memory device 300. A plurality of bit lines 160 and a plurality of contacts 180 can be formed above the substrate 100 ( Figure 1(not shown in the figure), the bit lines 160 extend, for example, in another direction (such as the x direction) perpendicular to the said direction and are staggered with the active region 103. Although the buried gate is not specifically shown in the drawings of this embodiment, those skilled in the art should easily understand that, viewed from a top view, the bit lines 160 extending in the x direction should be perpendicular to the buried gate extending in the y direction and at the same time be staggered with the active region 103 and the buried gate.

[0070] As Figure 1 shown, the bit lines 160 further include a plurality of first bit lines 162 and at least one second bit line 164. The first bit lines 162 and the second bit line 164 are, for example, respectively disposed in the memory cell region (not shown) and the periphery region (not shown) of the semiconductor memory device 300, and can respectively serve as general bit lines (BLs) and dummy bit lines (dummy BLs). Among them, the second bit line 164 can be located on one side of all the first bit lines 162, but not limited thereto. Those skilled in the art should easily understand that, according to the actual component requirements, the memory cell region and the periphery region can also have other setting modes, so that the first bit lines and the second bit lines have other setting methods, or the second bit line has other setting quantities. For example, in one embodiment, the semiconductor memory device preferably includes two of the second bit lines, which are respectively disposed on two opposite sides (i.e., the upper and lower sides) of all the first bit lines 162 to isolate other external components. In addition, in this embodiment, the line width (for example, the width in the y direction) W2 of each second bit line 164 is preferably greater than the line width W1 of each first bit line 162, but not limited thereto. In another embodiment, it is also possible to selectively make the second bit line and the first bit line have the same line width.

[0071] Specifically, as Figure 2As shown, the bit lines 160 are formed on the substrate 100 separately from each other and include semiconductor layers (such as polysilicon) 161, barrier layers 163 (such as titanium and / or titanium nitride), conductive layers 165 (such as metals with low resistivity like tungsten, aluminum or copper), and capping layers 167 (such as silicon oxide, silicon nitride or silicon oxynitride), etc., but not limited thereto. It should be noted that a part of the first bit lines 162 are formed on the dielectric layer 130 above the substrate 100. Among them, the dielectric layer 130 preferably has a composite layer structure, such as an oxide layer 131 - nitride layer 133 - oxide layer 135 (oxide - nitride - oxide, ONO) structure, but not limited thereto; another part of the first bit lines 162 further form bit line contacts (BLC) 160a below them, extending into the substrate 100 and directly contacting the underlying substrate 100 (active region 103). And, the bit line contacts 160a are, for example, integrally formed with the semiconductor layer 161 of the other part of the first bit lines 162, as Figure 2 shown. On the other hand, the contacts 180 are also formed on the substrate 100 separately from each other and are arranged alternately with the bit lines 160. And, the contacts 180 and the bit lines 160 are insulated from each other through the spacer structure 170. In one embodiment, the spacer structure 170 can selectively have a single - layer structure or a composite layer structure as Figure 2 shown, which, for example, includes a first spacer 171 (such as silicon nitride), a second spacer 173 (such as silicon oxide), and a third spacer 173 (such as silicon nitride) stacked in sequence, but not limited thereto. In addition, the contacts 180 further include a plurality of first contacts 182 and a plurality of second contacts 184 arranged alternately, which are disposed in the storage region of the semiconductor memory device 300 and directly contact the underlying substrate 100 (including the active region 103 and the insulating region 101) to serve as the storage node contacts (SNC) of the semiconductor memory device 300. In one embodiment, the contacts 180 are, for example, made of metal materials with low resistivity such as aluminum (Al), titanium (Ti), copper (Cu) or tungsten (W).

[0072] Next, a plurality of storage node pads (SN pads) 211 are formed on the substrate 100. Among them, the formation of the storage node pads 211 is, for example, through a self-aligned double patterning (SADP) manufacturing process or a self-aligned reverse patterning (SARP) manufacturing process, but is not limited thereto. Please refer to Figure 3 and Figure 4 As shown, a metal layer 210 is first formed above the contact 180 and the bit line 160, which, for example, includes a low-resistance metal material such as aluminum, titanium, copper, or tungsten, preferably includes a metal material different from that of the contact 180, but is not limited thereto; then, at least two self-aligned double patterning manufacturing processes are sequentially performed to form a plurality of patterned masks 221 extending parallel to each other along the second direction D2 and a plurality of patterned masks 223 extending parallel to each other along the second direction D3 on the metal layer 210. Among them, the second direction D2 and the second direction D3 are, for example, intersecting with each other and are respectively not perpendicular to the y direction or the x direction. For example, the angle between the second direction D2 or the second direction D3 and the y direction or the x direction is about 60 to 120 degrees, as Figure 3 shown, but is not limited thereto; then, the relative position of the storage node pad 211 is defined by the overlapping portion of the patterned mask 221 and the patterned mask 223, and a mask is formed as an etching mask to perform an etching manufacturing process to pattern the metal layer 210 below, so that the storage node pad 211 can be formed, as Figure 5 shown. It should be noted that in this embodiment, by controlling the overlapping portion of the patterned mask 221 and the patterned mask 223, the storage node pad 211 is formed above the contact 180 and the bit line 160, and selectively only for each first contact 182. In other words, the storage node pad 211 is not formed above each second contact 184.

[0073] Subsequently, a capacitor structure 250 can be continuously formed above the storage node pad 211 to directly contact and electrically connect to the storage node pad 211 below. In one embodiment, the manufacturing process of the capacitor structure 250 includes but is not limited to the following steps. First, as Figure 6As shown, a dielectric layer 230 and a support layer structure 240 are formed above the substrate 100. The dielectric layer 230 covers the contacts 180 (including the first contact 182 and the second contact 184) and the bit line 160. Preferably, the thickness of the dielectric layer 230 is greater than the thickness of the storage node pad 211, such that the storage node pad 211 can be located within the dielectric layer 230. The support layer structure 240 includes, for example, at least one oxide layer and at least one nitride layer stacked alternately. In this embodiment, the support layer structure 240 includes, for example, a first support layer 241 (such as silicon oxide) stacked in sequence from bottom to top, a second support layer 243 (such as silicon nitride or silicon carbonitride), a third support layer 245 (such as silicon oxide), and a fourth support layer 247 (such as silicon nitride or silicon carbonitride, etc.), but is not limited thereto. Preferably, the first support layer 241 and the third support layer 245 can have relatively large thicknesses, for example, about 5 to 10 times or more of the other support layers (the second support layer 243 or the fourth support layer 247), but is not limited thereto. Thus, the overall thickness of the support layer structure 240 can reach about 1600 angstroms to 2000 angstroms, but is not limited thereto. Those skilled in the art should understand that the specific stacking numbers of the foregoing oxide layers (such as the first support layer 241 or the third support layer 245) and the foregoing nitride layers (such as the second support layer 243 or the fourth support layer 247) are not limited to the foregoing numbers and can be adjusted according to actual needs, such as 3 layers, 4 layers, or other numbers, etc. Then, a plurality of first openings 242, at least one second opening 246, and a plurality of third openings 244 are formed within the support layer structure 240, all of which sequentially penetrate the fourth support layer 247, the third support layer 245, the second support layer 243, the first support layer 241, and a part of the dielectric layer 230. The first openings 242 and the third openings 244 are alternately arranged in the storage area, wherein the first openings 242 are respectively aligned with the underlying storage node pads 211 (and the first contacts 182), such that the top surface of the storage node pads 211 can be exposed from the first openings 242; the third openings 244 are respectively aligned with the underlying second contacts 184. However, although the bottom surface of the third opening 244 is lower than the top surface of the dielectric layer 230 but does not penetrate the dielectric layer 230, only a part of the dielectric layer 230 is exposed from the third openings 244. The second openings 246 are arranged outside all the first openings 242 and all the third openings 244 and are aligned with the second bit line 164 within the peripheral area. The second openings 246 also do not penetrate the dielectric layer 230 and only expose a part of the dielectric layer 230, as Figure 6 shown.

[0074] Next, as Figure 7As shown, a bottom electrode layer 251 is formed to fill the first opening 242, the third opening 244, and the second opening 246 respectively. The bottom electrode layer 251 includes, for example, low-resistance metal materials such as aluminum, titanium, copper, or tungsten, and preferably includes titanium, but is not limited thereto. It should be noted that the bottom electrode layer 251 disposed in the first opening 242 is in direct contact with the underlying storage node pad 211; while the bottom electrode layer 251 disposed in the third opening 244 and the second opening 246 is in direct contact with the dielectric layer 230, directly above the second contact 184 and the second bit line 164 respectively. Again, as Figure 7 shown, after the bottom electrode layer 251 is formed, an etching process is performed through a mask layer (not shown) to completely remove the oxide layer (such as the first support layer 241 or the third support layer 245) in the support layer structure 240 and partially remove the nitride layer (such as the second support layer 243 or the fourth support layer 247) in the support layer structure 240.

[0075] Subsequently, as Figure 8 shown, a capacitor dielectric layer 253 and a top electrode layer 255 are sequentially formed on the bottom electrode layer 251. Part of the capacitor dielectric layer 253 and part of the top electrode layer 255 can further fill the space between the remaining second support layer 243 and the fourth support layer 247, and also fill the space between the remaining second support layer 243 and the dielectric layer 230. In one embodiment, the capacitor dielectric layer 253 includes, for example, a high-k dielectric material selected from the group consisting of hafnium oxide (HfO 2 ), hafnium silicate (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), zirconium oxide (ZrO 2 ), titanium oxide (TiO 2 ), and zirconia-alumina-zirconia (ZAZ), and preferably includes zirconia-alumina-zirconia; the top electrode layer 255 includes, for example, low-resistance metal materials such as aluminum, titanium, copper, or tungsten, and preferably includes titanium, but is not limited thereto.

[0076] Thus, the manufacturing process of the capacitor structure 250 is completed. The capacitor structure 250 includes a bottom electrode layer 251, a capacitor dielectric layer 253, and a top electrode layer 255 stacked in sequence, and can form a plurality of capacitors 250a, 250b, 250c extending vertically. It should be noted that the capacitor structure 250 includes a plurality of first capacitors 250a and a plurality of third capacitors 250c, and the first capacitors 250a and the third capacitors 250c are alternately and separately arranged to respectively face the first contact 182 and the second contact 184. Among them, each first capacitor 250a can be electrically connected to a transistor component (not shown) of the semiconductor memory device 300 through the underlying storage node pad 211 and the storage node plug (i.e., the first contact 182). Thereby, the first capacitor 250a can serve as a storage node (SN) of the semiconductor memory device 300, so that a good contact relationship can be maintained between the capacitor structure 250 and the transistor component. On the other hand, there is no storage node pad 211 provided below each third capacitor 250c, and it cannot be electrically connected to the underlying storage node plug (i.e., the contact 184). The bottom surface of the third capacitor 250c (i.e., the bottom surface of the bottom electrode layer 251 filling the second opening 246) only contacts the dielectric layer 230 to form an open circuit, becoming a dummy storage node (dummy SN), isolating the adjacent storage nodes to maintain the overall device performance. Among them, the bottom surface of the third capacitor 250c is lower than the top surface of the dielectric layer 230, as Figure 8 shown.

[0077] It should also be noted that the capacitor structure 250 further includes at least one second capacitor 250b, and there is also no storage node pad 211 provided below it, and at least one second capacitor 250b is located outside all the first capacitors 250a and all the third capacitors 250c, facing the second bit line 164 in the peripheral region. Thus, the bottom surface of at least one second capacitor 250b (i.e., the bottom surface of the bottom electrode layer 251 filling the third opening 244) also only directly contacts the dielectric layer 230 to form an open circuit, and thus becomes the dummy storage node to isolate the adjacent storage nodes. Although Figure 8 the cross-sectional schematic diagram shown only shows one second capacitor 250b located on the second bit line 164, those skilled in the art should easily understand that multiple second capacitors 250b can be presented on the second bit line 164 in the cross-sectional schematic diagrams along other directions, for example, the cross-sectional schematic diagram along the extending direction of the second bit line 164, as Figure 9As shown. Thus, the semiconductor memory device 300 of this embodiment can form a dynamic random access memory (DRAM) device, which consists of at least one of the transistor components and at least one first capacitor 250a to form the smallest constituent unit (memory cell) in the dynamic random access memory array, so as to receive voltage information from the bit line 160 and the buried word line.

[0078] Thus, the semiconductor memory device 300 in the first embodiment of the present invention is completed. According to the forming method of this embodiment, by controlling the overlapping part of the patterning mask 221 and the patterning mask 223, the storage node pad 211 is formed, so that the storage node pad 211 is only disposed above the first contact 182 and not above the second contact 184. In this way, after the capacitor structure 250 is formed, the first capacitor 250a that can be used as a storage node and the second capacitor 250b and / or the third capacitor 250c that can be used as a dummy storage node can be respectively formed. Among them, the storage node (i.e., the first capacitor 250a) is electrically connected to the transistor component (not shown) of the semiconductor memory device 300 through the storage node pad 211 below and the storage node plug (i.e., the first contact 182), while the storage node pad 211 is not disposed below the dummy storage node (i.e., the second capacitor 250b and / or the third capacitor 250c), and thus it cannot be electrically connected to the storage node plug (i.e., the second contact 184) below. The setting of the dummy storage node can stabilize and improve the performance of the storage node, and can isolate adjacent storage nodes to maintain the overall component performance of the semiconductor memory device 300.

[0079] In addition, those skilled in the art should easily understand that in order to meet the requirements of actual products, there may be other aspects in the formation of the semiconductor memory device and its forming method of the present invention, and are not limited to the foregoing. For example, the dummy storage node can also be selected to have other setting aspects. The following will further describe other embodiments or variations of the method of the semiconductor memory device in the present invention. And for simplicity of description, the following description mainly details the differences of each embodiment, and will not repeat the same parts. In addition, the same components in each embodiment of the present invention are labeled with the same reference numerals for easy comparison between embodiments.

[0080] Please refer to Figure 10As shown, it is a schematic diagram of the steps of the method for forming the semiconductor memory device 400 in the second embodiment of the present invention. In this embodiment, the steps of forming the front end of the semiconductor memory device 400 are substantially the same as those of the front end of the semiconductor memory device 300 in the foregoing first embodiment, and will not be elaborated herein. The main difference between this embodiment and the foregoing first embodiment is that at least one second capacitor 450b penetrates the dielectric layer 230 and can directly contact the capping layer 167 of the second bit line 164.

[0081] Specifically, when forming the opening in the support layer structure 240 in the forming method of this embodiment, the etching process conditions are further controlled to selectively make the second opening (not shown) corresponding to the second bit line 164 penetrate the dielectric layer 230 and stop on the top surface of the capping layer 167 of the second bit line 164. In this way, the capping layer 167 of the second bit line 164 can be exposed from the second opening. Subsequently, continue to sequentially form the bottom electrode layer 251, the capacitor dielectric layer 253, and the top electrode layer 255, and the capacitor structure 450 as shown in Figure 10 can be formed. Among them, at least one second capacitor 450b corresponds to the second bit line 164 in the peripheral region, extends into the dielectric layer 230 and directly contacts the top surface of the capping layer 167 of the second bit line 164 through the bottom electrode layer 251. In this way, the at least one second capacitor 450b only contacts the dielectric layer 230 and the capping layer 167 to form an open circuit, and then becomes the dummy storage node. Under this setting, the semiconductor memory device 400 of this embodiment can also form a dynamic random access memory device, and isolate the adjacent storage nodes through the second capacitor 450b and the third capacitor 250c to maintain its overall component performance.

[0082] Please refer to Figure 11 As shown, it is a schematic diagram of the steps of the method for forming the semiconductor memory device 500 in the third embodiment of the present invention. In this embodiment, the steps of forming the front end of the semiconductor memory device 500 are substantially the same as those of the front end of the semiconductor memory device 300 in the foregoing first embodiment, and will not be elaborated herein. The main difference between this embodiment and the foregoing first embodiment is that at least one second capacitor 550b penetrates the dielectric layer 230 and further extends into a part of the capping layer 167 of the second bit line 164.

[0083] In detail, when forming the opening in the support layer structure 240 in this embodiment, the etching process conditions are further controlled to selectively penetrate a second opening (not shown) corresponding to the second bit line 164 through the dielectric layer 230 and a partial capping layer 167 of the second bit line 164, so that the second opening can extend into a part of the capping layer 167. In other words, the bottom surface of the second opening can be lower than the top surface of the second bit line 164, and the part of the capping layer 167 can be exposed from the second opening. Subsequently, the bottom electrode layer 251, the capacitive dielectric layer 253, and the top electrode layer 255 are sequentially formed, and then the capacitor structure 550 as shown in Figure 11 can be formed. Among them, at least one second capacitor 550b corresponds to the second bit line 164 in the peripheral region, and penetrates into the part of the capping layer 167 through its bottom electrode layer 251 and is in direct contact. In this way, the bottom surface of at least one second capacitor 550b (i.e., the bottom surface of the bottom electrode layer 251 filling the second opening) can be lower than the top surface of the second bit line 164, and at least one second capacitor 550b only contacts the capping layer 167 to form an open circuit, and thus can become the dummy storage node. With this setting, the semiconductor memory device 500 of this embodiment can also form a dynamic random access memory device, and isolate adjacent storage nodes through the second capacitor 550b and the third capacitor 250c to maintain the overall component performance.

[0084] Please refer to Figure 12 shown, which is a schematic diagram of the steps of the formation method of the semiconductor memory device 600 in the fourth embodiment of the present invention. The formation steps of the front end of the semiconductor memory device 600 in this embodiment are generally the same as those of the front end of the semiconductor memory device 300 in the foregoing first embodiment, and will not be described in detail here. The main difference between this embodiment and the foregoing first embodiment is that at least one second capacitor 650b is located above a part of the second bit line 164 and a part of the contact 180 at the same time.

[0085] In detail, as shown in Figure 12 when forming the storage node pad 211 in this embodiment, each storage node pad 211 only partially overlaps the underlying first contact 182 to gain a larger process space. Subsequently, the bottom electrode layer 251, the capacitive dielectric layer 253, and the top electrode layer 255 are sequentially formed, and then the structure as shown in Figure 12The capacitive structure 650 shown. Thus, each storage node pad 211 can be simultaneously located above a part of the first contact 182, the spacer structure 170, and a part of the first bit line 162, and the subsequently formed first capacitor 650a can also be simultaneously located above a part of the first contact 182, the spacer structure 170, and the first bit line 162. The third capacitor 650c can be simultaneously located above a part of the second contact 184, the spacer structure 170, and the first bit line 162. In addition, the second capacitor 650b located in the peripheral region can be simultaneously located above a part of the second contact 184, the spacer structure 170, and the second bit line 164. It should be noted that in this embodiment, the etching process conditions can be further controlled to selectively make the opening (not shown) in the peripheral region penetrate only a part of the dielectric layer 230, so that the bottom surface of the second capacitor 650b (i.e., the bottom surface of the bottom electrode layer 251 filling the opening) only contacts the dielectric layer 230, as Figure 12 shown, but not limited thereto. With this arrangement, the semiconductor memory device 600 of this embodiment can also form a dynamic random access memory device, and isolate adjacent storage nodes through the second capacitor 650b and the third capacitor 650c to maintain the overall component performance.

[0086] Overall, the present invention forms storage node pads on a substrate through a self-aligned double patterning process or a self-aligned reverse patterning process. By controlling the overlapping parts of the patterning masks, storage node pads that are only located opposite a part of the contacts are formed. Thus, after the capacitive structure is formed, a first capacitor that can be used as a storage node and a second capacitor that can be used as a dummy storage node can be respectively formed. Among them, the storage node (i.e., the first capacitor) is electrically connected to the transistor components (not shown) of the semiconductor memory device through the underlying storage node pad and the storage node plug (i.e., the contact), while there is no storage node pad below the dummy storage node (i.e., the second capacitor), but it directly contacts the capping layer of the dummy bit line, so it cannot be electrically connected to the storage node plug (i.e., the contact), thereby isolating adjacent storage nodes to maintain the overall component performance of the semiconductor memory device.

[0087] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A dynamic random access memory device, characterized in that, comprising: a substrate; the substrate includes a storage region and a peripheral region; a plurality of bit lines disposed on the substrate, the bit lines include a plurality of first bit lines in the storage region and at least one second bit line in the peripheral region, the at least one second bit line is disposed outside all of the first bit lines; the at least one second bit line is a dummy bit line; a plurality of contacts disposed on the substrate and alternately and separately disposed with the bit lines; a dielectric layer covering above the contacts and the bit lines; a plurality of storage node pads disposed in the dielectric layer and respectively contacting the contacts; and a capacitor structure disposed on the storage node pads, the capacitor structure includes a plurality of first capacitors respectively corresponding to the storage node pads, and at least one second capacitor located above the at least one second bit line.

2. The dynamic random access memory device according to claim 1, characterized in that, the bottom surface of the at least one second capacitor directly contacts the dielectric layer.

3. The dynamic random access memory device according to claim 1, characterized in that, the at least one second capacitor is simultaneously located above a part of the contacts and a part of the second bit lines.

4. The dynamic random access memory device according to claim 1, characterized in that, the bit lines respectively include a semiconductor layer, a barrier layer, a conductive layer and a capping layer stacked in sequence from bottom to top, and the at least one second capacitor directly contacts the capping layer of the at least one second bit line.

5. The dynamic random access memory device according to claim 4, characterized in that, the at least one second capacitor directly contacts the capping layer of the at least one second bit line.

6. The dynamic random access memory device according to claim 1, characterized in that, the bottom surface of the at least one second capacitor is lower than the top surface of the at least one second bit line.

7. The dynamic random access memory device according to claim 1, characterized in that, the line width of the at least one second bit line is greater than the line width of the first bit line.

8. The dynamic random access memory device according to claim 1, characterized in that, the capacitor structure further includes a plurality of third capacitors respectively corresponding to the contacts, and the third capacitors directly contact the dielectric layer.

9. The dynamic random access memory device according to claim 8, characterized in that, the third capacitors and the first capacitors are alternately and separately disposed.

10. The dynamic random access memory device according to claim 8, characterized in that, the bottom surface of the third capacitor is lower than the top surface of the dielectric layer.

11. A method for forming a dynamic random access memory device, characterized in that, comprising: providing a substrate; forming a plurality of bit lines on the substrate, the bit lines include a plurality of first bit lines and at least one second bit line, the at least one second bit line is formed outside all of the first bit lines; forming a plurality of contacts on the substrate, and the bit lines and the contacts are alternately arranged; A dielectric layer is formed over the contact and the bit line, covering the contact and the bit line; A plurality of storage node pads are formed within the dielectric layer, and the storage node pads are respectively aligned with the contacts; And A capacitor structure is formed over the storage node pads, the capacitor structure including a plurality of first capacitors respectively aligned with the storage node pads, and at least one second capacitor located over the at least one second bit line; wherein the at least one second capacitor is isolated from any of the contacts.

12. The method of forming a dynamic random access memory device according to claim 11, wherein, further comprising: Forming a support layer structure on the substrate, the support layer structure including at least one oxide layer and at least one nitride layer stacked alternately; Forming a plurality of openings within the support layer structure, each of the openings penetrating the support layer structure; Forming a bottom electrode layer within the openings; And Completely removing the oxide layer within the support layer structure.

13. The method of forming a dynamic random access memory device according to claim 12, wherein, further comprising sequentially forming a capacitor dielectric layer and a top electrode layer over the bottom electrode layer.

14. The method of forming a dynamic random access memory device according to claim 12, wherein, the openings include a plurality of first openings and at least one second opening, the first openings respectively exposing the storage node pads, and the at least one second opening exposing the at least one second bit line.

15. The method of forming a dynamic random access memory device according to claim 14, wherein, the bottom surface of the at least one second opening is lower than the top surface of the at least one second bit line.

16. The method of forming a dynamic random access memory device according to claim 14, wherein, the at least one second opening is formed outside all of the first openings.

17. The method of forming a dynamic random access memory device according to claim 14, wherein, the openings further include a plurality of third openings, the third openings respectively exposing the dielectric layer.

18. The method of forming a dynamic random access memory device according to claim 17, wherein, the third openings and the first openings are alternately arranged, and the at least one second opening is formed outside all of the first openings and all of the third openings.

19. The method of forming a dynamic random access memory device according to claim 17, wherein, the bottom surface of the third openings is lower than the top surface of the dielectric layer.

20. The method of forming a dynamic random access memory device according to claim 14, wherein, the bit lines respectively include a semiconductor layer, a barrier layer, a conductive layer, and a capping layer stacked in sequence from bottom to top, and the bottom electrode layer formed in the at least one second opening directly contacts the capping layer of the at least one second bit line.

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