Three-dimensional memory and methods of forming the same

Abstract

The application discloses a three-dimensional memory forming method and three-dimensional memory, and the forming method comprises the following steps: providing a substrate, the substrate comprises a first substrate, a bottom oxide layer, a polysilicon layer, a top oxide layer and a stack structure from bottom to top; forming a common source trench in the substrate, the common source trench extends through the bottom oxide layer, the polysilicon layer, the top oxide layer and the stack structure, and extends downwards to the first substrate; forming a filling layer at the bottom of the common source trench, the upper surface of the filling layer is higher than the upper surface of the polysilicon layer and lower than the upper surface of the top oxide layer; forming a common source structure on the surface of the filling layer in the common source trench; removing the first substrate and part of the filling layer to expose the bottom oxide layer; removing the bottom oxide layer; forming a semiconductor substrate on the surface of the polysilicon layer and the filling layer. According to the forming method of the embodiment of the application, the conductive layer and the common source structure are prevented from being in conduction, so that the performance of the three-dimensional memory is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a three-dimensional memory and a method for forming the same. Background Technology

[0002] In the fabrication of 3D memory using related technologies, during the semiconductor etching process, the bottom oxide layer around the common source structure is easily etched through, leading to the exposure of the gate material layer. As a result, when a polycrystalline silicon material layer is subsequently deposited to form a substrate, the polycrystalline silicon material substrate and the gate material layer make contact and conduction, affecting the performance of the 3D memory.

[0003] The specific reasons are as follows: Figure 1 As shown, after the common-source structure 1' is implanted with ions, during the etching operation, the dielectric layer 2' on the surface of the common-source structure 1' and the oxide layer 3' outside the common-source structure 1' are etched. Due to material properties, the etching rate of the oxide layer 3' outside the common-source structure 1' is faster than that of the dielectric layer 2', resulting in a gap 4' between the dielectric layer 2' and the common-source structure 1'. The etching material continues to etch along the gap 4', further accelerating the etching rate of the oxide layer 3', leading to a partial connection between the oxide layer 3' of the common-source structure and the conductive layer 5' of the gate structure, as shown. Figure 1 The oxide layer 3' of the common source structure shown is hollowed out to the gate conductive layer 5'. This causes the substrate material layer 8' to become conductive with the gate conductive layer 5' when the substrate material is filled in later, thus affecting the performance of the three-dimensional memory.

[0004] like Figure 2 As shown, due to the stress of each material layer at the bottom of the common source structure 1', a gap 6' is formed between the common source structure 1' and the surrounding material layers. When etching is performed, the etching material etches along the gap 6', which not only increases the etching rate, but also easily causes the bottom oxide layer 7' to be etched through, exposing the gate conductive layer 5'. The subsequent deposition of substrate material 8' to fill the etched gap 6' leads to a short circuit with the gate conductive layer 5', affecting the performance of the three-dimensional memory. Summary of the Invention

[0005] The purpose of this invention is to provide a method for forming a three-dimensional memory that can prevent the conductive layer from conducting with the common source structure, thereby improving the performance of the three-dimensional memory.

[0006] To address the aforementioned technical problems, this invention provides a method for forming a three-dimensional memory, comprising: providing a substrate, the substrate comprising, from bottom to top, a first substrate, a bottom oxide layer, a polysilicon layer, a top oxide layer, and a stacked structure; forming a common-source trench within the substrate, the common-source trench penetrating the bottom oxide layer, the polysilicon layer, the top oxide layer, and the stacked structure, and extending downward into the first substrate; forming a filling layer at the bottom of the common-source trench, the upper surface of the filling layer being higher than the upper surface of the polysilicon layer and lower than the upper surface of the top oxide layer; forming a common-source structure located on the surface of the filling layer within the common-source trench; removing the first substrate and a portion of the filling layer to expose the bottom oxide layer; removing the bottom oxide layer; and forming a semiconductor substrate on the surfaces of the polysilicon layer and the filling layer.

[0007] According to some embodiments of the present invention, a back-side process is performed prior to the step of removing the first substrate and a portion of the filler layer to expose the surface of the bottom oxide layer, wherein the first substrate is flipped over to remove the first substrate and the filler layer extending beyond the surface of the bottom oxide layer.

[0008] According to some embodiments of the present invention, the thickness of the filling layer extending beyond the upper surface of the polysilicon layer is half the thickness of the top oxide layer.

[0009] According to some embodiments of the present invention, the stacked structure includes a sacrificial layer and an isolation layer stacked at intervals.

[0010] According to some embodiments of the present invention, before forming a common source structure in the common source trench, the method further includes the following steps: removing the sacrificial layer and forming an opening between the isolation layers; forming a dielectric layer covering the surface of the isolation layers; and forming a conductive layer between the dielectric layers to fill the opening.

[0011] According to some embodiments of the present invention, the common source structure includes a first gate layer and a second gate layer formed within the first gate layer. The step of forming a common source structure located on the surface of the filling layer within the common source trench includes: forming a first gate layer covering the conductive layer, the sidewall of the dielectric layer facing the common source trench, and the surface of the filling layer; and forming a second gate layer within the first gate layer.

[0012] According to some embodiments of the present invention, the step of removing the first substrate and a portion of the filler layer to expose the surface of the bottom oxide layer includes: removing a portion of the first substrate and a portion of the filler layer with a high selectivity and retaining a portion of the first substrate and the filler layer, wherein the thickness removed with the high selectivity is a first thickness; removing the first substrate and a portion of the filler layer with a low selectivity to expose the surface of the bottom oxide layer, wherein the thickness removed with the low selectivity is a second thickness, and the first thickness is greater than the second thickness.

[0013] According to some embodiments of the present invention, the first thickness is 50%-90% of the total thickness of the first substrate.

[0014] According to some embodiments of the present invention, the first thickness is 90% of the total thickness of the first substrate, and the second thickness is 10% of the total thickness of the first substrate.

[0015] The present invention also proposes a three-dimensional memory.

[0016] A three-dimensional memory according to an embodiment of the present invention includes: a semiconductor substrate; a top oxide layer formed on the surface of the semiconductor substrate; a stacked structure in which a common source trench is formed, wherein a portion of the semiconductor substrate is located at the bottom of the common source trench; a common source structure filling the common source trench and located above the semiconductor substrate; and a dielectric layer formed between the isolation layer and the conductive layer, between the isolation layer and the common source structure, between the top oxide layer and the conductive layer, and between the top oxide layer and the common source structure.

[0017] According to some embodiments of the present invention, the upper surface of the semiconductor substrate is higher than the lower surface of the top oxide layer and lower than the upper surface of the top oxide layer, and the thickness of the semiconductor bulk substrate above the lower surface of the top oxide layer is less than or equal to half the total thickness of the top oxide layer.

[0018] According to the method for forming a three-dimensional memory according to an embodiment of the present invention, since gaps are easily formed between the common source structure and different material layers due to stress tension, a filling layer is formed at the bottom of the common source trench. The upper surface of the filling layer extends beyond the lower surface of the top oxide layer and is lower than the upper surface of the top oxide layer. This can prevent the etching solution from etching through the top oxide layer to the conductive layer along the gap during the fabrication of the three-dimensional memory.

[0019] Meanwhile, during the etching process of the first substrate, gaps can be avoided between the dielectric layer and the common source structure. Gaps increase the etching rate, thereby preventing the top oxide layer from being exposed by etching through the polysilicon layer along the gap. Finally, in the step of removing the bottom oxide layer, the top oxide layer is exposed by etching through the gap, which ultimately leads to the conductive layer being connected to the common source structure in subsequent deposition. Attached Figure Description

[0020] Figures 1-2 This is a schematic diagram of the fabrication process of a three-dimensional memory in the prior art;

[0021] Figure 3 This is a flowchart illustrating a method for forming a three-dimensional memory according to an embodiment of the present invention;

[0022] Figures 4-13 This is a schematic diagram of the steps in the method for forming a three-dimensional memory according to an embodiment of the present invention;

[0023] Figure label:

[0024] 1: Substrate, 11: First substrate, 12: Bottom oxide layer, 13: Polysilicon layer, 14: Top oxide layer, 15: Stacked structure, 151: Sacrificial layer, 152: Isolation layer, 153: Opening, 16: Conductive layer;

[0025] 2: Common source trench;

[0026] 3: Fill layer;

[0027] 4: Common source structure; 41: First gate layer; 42: Second gate layer;

[0028] 5: Dielectric layer;

[0029] 6: Gaps;

[0030] 7: Stacked structure, 71: Semiconductor substrate. Detailed Implementation

[0031] The following describes in further detail a method for forming a three-dimensional memory 100 according to the present invention, with reference to the accompanying drawings and specific embodiments.

[0032] The following is a reference appendix. Figures 3-13 A method for forming a three-dimensional memory 100 according to an embodiment of the present invention is described.

[0033] like Figure 3 As shown, the method for forming a three-dimensional memory 100 according to an embodiment of the present invention includes:

[0034] S1: A substrate 1 is provided, which includes, from bottom to top, a first substrate 11, a bottom oxide layer 12, a polysilicon layer 13, a top oxide layer 14, and a stacked structure 15; S2: A common-source trench 2 is formed in the substrate 1, which penetrates the bottom oxide layer 12, the polysilicon layer 13, the top oxide layer 14, and the stacked structure 15, and extends downward into the first substrate 11; S3: Polysilicon material is deposited at the bottom of the common-source trench 2 to form a filler layer 3, the upper surface of the filler layer 3 being higher than the upper surface of the polysilicon layer 13 and lower than the upper surface of the top oxide layer 14; S4: A common-source structure 4 is formed in the common-source trench 2; S5: The first substrate 11 and part of the filler layer 3 are removed to expose the surface of the bottom oxide layer 12; S6: The bottom oxide layer 12 is removed; S7: A semiconductor substrate 71 is formed by deposition on the lower surface of the polysilicon layer 13 and the filler layer 3.

[0035] Specifically, such as Figure 4 As shown, the substrate 1, from bottom to top, includes a first substrate 11, a bottom oxide layer 12, a polysilicon layer 13, a top oxide layer 14, and a stacked structure 15. The first substrate 11 is formed below the bottom oxide layer 12, the bottom oxide layer 12 is formed between the first substrate 11 and the polysilicon layer 13, and the top oxide layer 14 is formed between the polysilicon layer 13 and the stacked structure 15. The first substrate 11 can be formed of polysilicon material, meaning the first substrate 11 and the polysilicon layer 13 are made of the same material. The bottom oxide layer 12 and the top oxide layer 14 can be made of different or the same material; this is not specifically limited in the present invention. Optionally, both the bottom oxide layer 12 and the top oxide layer 14 can be silicon oxide layers.

[0036] The stacked structure 15 includes a sacrificial layer 151 and an isolation layer 152 stacked and spaced apart. Specifically, the surface of the top oxide layer 14 is the sacrificial layer 151, meaning the stacked structure 15 can be formed by stacking the sacrificial layer 151 and the isolation layer 152, with the bottommost layer of the stacked structure 15 being the sacrificial layer 151. The sacrificial layer 151 and the isolation layer 152 are formed of different materials. Optionally, the sacrificial layer 151 can be a nitride layer, and the isolation layer 152 can be an oxide layer. For example, the material of the sacrificial layer 151 can be one or more combinations of silicon nitride and silicon oxynitride, and the material of the isolation layer 152 can be a silicon oxide layer.

[0037] like Figure 5As shown, a common source trench 2 is formed in the substrate 1. The common source trench 2 penetrates the stacked structure 15, the top oxide layer 14, the polysilicon layer 13 and the bottom oxide layer 12, and extends downward into the first substrate 11. Specifically, the method of forming the common source trench 2 may include: forming a mask layer on the surface of the stacked structure 15, the mask layer defining the position and size of the common source trench 2, and etching the stacked structure 15 into the first substrate 11 in sequence using the mask layer as a mask to form the common source trench 2 that penetrates the stacked structure 15, the top oxide layer 14, the polysilicon layer 13 and the bottom oxide layer 12 and extends into the first substrate 11.

[0038] like Figure 6 As shown, a filling layer 3 is formed at the bottom of the common source trench 2. The upper surface of the filling layer 3 is higher than the upper surface of the polysilicon layer 13 and lower than the upper surface of the top oxide layer 14. Specifically, chemical vapor deposition, physical vapor deposition, or atomic layer deposition can be used to deposit materials in the common source trench 2 to form the filling layer 3. The filling layer 3 fills part of the common source trench 2 and is located at the bottom of the common source trench 2. The filling layer 3 is in contact with the first substrate 11 and the polysilicon layer 13 respectively. The height of the filling layer 3 can be controlled within the height of the top oxide layer 14, that is, the filling layer 3 extends beyond the polysilicon layer 13. The upper surface of the filling layer 3 is higher than the lower surface of the top oxide layer 14 and lower than the upper surface of the top oxide layer 14.

[0039] Optionally, the thickness of the filling layer 3 extending beyond the upper surface of the polysilicon layer 13 is less than or equal to half the total thickness of the top oxide layer 14, that is, the upper surface of the filling layer 3 does not extend beyond half the height of the top oxide layer 14; further, the thickness of the filling layer 3 extending beyond the upper surface of the polysilicon layer 13 is half the thickness of the top oxide layer 14, that is, the filling layer 3 can be filled to the middle position of the height of the top oxide layer 14 and then stop.

[0040] like Figure 9 As shown, a common source structure 4 is formed in the common source trench 2 on the surface of the filling layer 3. The common source structure 4 fills the remaining space of the common source trench 2 and is located above the filling layer 3. Thus, the common source structure 4 is located above the first substrate 11 and the bottom oxide layer 12. In the subsequent etching step of the first substrate 11, the common source structure 4 can be avoided from being etched. In particular, when the common source structure 4 is cleaned with hydrofluoric acid (HF) after ion implantation, the common source structure 4 and its external dielectric layer 5 will not be etched. This avoids the formation of a gap between the dielectric layer 5 and the common source structure 4, which would lead to etching to the conductive layer 16 of the gate structure. This prevents the semiconductor substrate 71 from becoming conductive with the conductive layer 16 when the semiconductor substrate 71 is formed by subsequent material deposition.

[0041] Optionally, before forming the common source trench 2, such as Figures 7-8As shown, the method for forming the three-dimensional memory 100 further includes: removing the sacrificial layer 151, forming an opening 153 between the isolation layers 152; forming a dielectric layer 5 covering the surface of the isolation layers 152; and forming a conductive layer 16 between the dielectric layers 5 to fill the opening 153. Figure 7 As shown, specifically, the sacrificial layer 151 between the isolation layers 152 can be etched away using a wet etching process to form an opening 153. Then, a dielectric layer 5 is formed on the surface of the isolation layer 152 within the opening 153 and within the common source trench 2, as shown. Figure 8 As shown, a conductive layer 16 is deposited between the dielectric layers 5 in the opening 153, and the conductive layer 16 is located between adjacent isolation layers 152 and fills the opening 153 formed between the isolation layers 152. Optionally, the dielectric layer 5 can be a high-k dielectric layer, for example, the material of the dielectric layer 5 can be aluminum oxide.

[0042] Optionally, the common-source structure 4 may include a first gate layer 41 and a second gate layer 42, wherein the second gate layer 42 is formed within the first gate layer 41, such as... Figure 9 As shown, the steps of forming the common source structure 4 may include: forming a first gate layer 41 covering the conductive layer 16, the dielectric layer 5 facing the sidewall of the common source trench 2 and the surface of the filling layer 3; and filling the first gate layer 41 to form a second gate layer 42.

[0043] Specifically, after forming the conductive layer 16, a first gate layer 41 is deposited and formed within the common source trench 2. The first gate layer 41 covers the conductive layer 16 and the sidewalls of the dielectric layer 5 facing the common source trench 2, as well as the upper surface of the filling layer 3 forming the bottom wall of the common source trench 2. Then, a second gate layer 42 is formed within the first gate layer 41. The first gate layer 41 encapsulates the second gate layer 42, and the first gate layer 41 and the second gate layer 42 fill the common source trench 2. Optionally, the first gate layer 41 can be a silicon oxide layer, and the second gate layer 42 can be a polysilicon material layer.

[0044] like Figures 10-11 As shown, the first substrate 11 and part of the fill layer 3 are removed to expose the surface of the bottom oxide layer 12. Before performing this step, a back-side process can be performed to flip the first substrate 11 to the top to remove the first substrate 11 and the fill layer 3 that extend beyond the surface of the bottom oxide layer 12. This flips the entire three-dimensional memory 100 so that the first substrate 11 is flipped to the top, which facilitates the subsequent operation of removing the first substrate 11 and part of the fill layer 3 to expose the bottom oxide layer 12.

[0045] Optionally, the step of removing the first substrate 11 and part of the fill layer 3 to expose the bottom oxide layer 12 may include the following steps: removing part of the first substrate 11 and part of the fill layer 3 with a high selectivity while retaining part of the first substrate 11 and the fill layer 3, wherein the thickness removed with the high selectivity is a first thickness h2; removing the first substrate 11 and part of the fill layer 3 with a low selectivity to expose the surface of the bottom oxide layer 12, wherein the thickness removed with the low selectivity is a second thickness h1, and the first thickness h2 is greater than the second thickness h1.

[0046] Specifically, the first substrate 11 and part of the filling layer 3 can be etched in two steps to expose the bottom oxide layer 12. First, as shown in the figure... Figure 10 As shown, a high selectivity gas ratio can be used to remove the first substrate 11 and the filler layer 3 at the first height. Because the high selectivity gas etching rate is fast, the etching rate can be accelerated. Then, as... Figure 11 As shown, a low selectivity gas ratio is used to remove the remaining first substrate 11 and filler layer 3 located on the surface of the bottom oxide layer 12, i.e., to remove the first substrate 11 and filler layer 3 at a second height, which is smaller than the first height. Thus, a high selectivity gas ratio is used at a first etching rate to remove most of the first substrate 11 and filler layer 3. The high selectivity gas etching rate is fast, thus accelerating the etching efficiency of the first substrate 11 and filler layer 3. A low selectivity gas ratio is used at a second etching rate to remove the remaining small portion of the first substrate 11 and filler layer 3. The etching rate is lower than the first etching rate. The gas etching rate with a low selectivity ratio is slow, which can effectively control the etching amount of the first substrate 11 and the filling layer 3, thereby reducing the over-etching of the first substrate 11 and the filling layer 3. This ensures that the first substrate 11 and the filling layer 3 located on the surface of the bottom oxide layer 12 are removed, while preventing the first substrate 11 and the filling layer 3 from being over-etched, or even exceeding the thickness of the top oxide layer 14, which would cause the top oxide layer 14 to be hollowed out to the conductive layer 16. This avoids the subsequent conduction between the semiconductor substrate 71 and the conductive layer 16, resulting in poor performance of the three-dimensional memory 100.

[0047] Optionally, the first thickness can be 50%-90% of the total thickness of the first substrate. In a specific example, the first thickness can be 90% of the total thickness of the first substrate, and the second thickness can be 10% of the total thickness of the first substrate.

[0048] like Figure 12As shown, the bottom oxide layer 12 is removed. In this step, since the dielectric layer 5, the common source structure 4 and the bottom oxide layer 12 are separated from the first substrate 11 by the filling layer 3, the cleaning liquid can be prevented from contacting the area with the dielectric layer 5 during the subsequent acid washing before the semiconductor substrate 71 is deposited. This prevents the first gate layer 41 from being etched through to the conductive layer 16 because the first gate layer 41 is etched faster than the dielectric layer 5.

[0049] like Figure 13 As shown, a semiconductor substrate 71 is formed by deposition on the surface of the polysilicon layer 13 and the surface of the filling layer 3. After the bottom oxide layer 12 is removed, materials can be redeposited on the surface of the polysilicon layer 13 and the surface of the filling layer 3 to form a semiconductor substrate 71 of a certain thickness.

[0050] According to the method for forming a three-dimensional memory 100 according to an embodiment of the present invention, since gaps 6 are easily formed between the common source structure 4 and different material layers due to stress tension, a filling layer 3 is formed at the bottom of the common source trench 2. The upper surface of the filling layer 3 extends beyond the lower surface of the top oxide layer 14 and is lower than the upper surface of the top oxide layer 14. This prevents the etching solution from etching through the top oxide layer 152 to the conductive layer 16 along the gaps 6 during the fabrication of the three-dimensional memory 100.

[0051] Meanwhile, during the etching process of the first substrate 11, gaps can be avoided between the dielectric layer 5 and the common source structure 4. The gaps will increase the etching rate, thereby preventing the top oxide layer 14 from being exposed by etching through the polysilicon layer 13 along the gaps. Finally, in the step of removing the bottom oxide layer 12, the top oxide layer 14 is exposed by etching through the gaps, which ultimately leads to the conductive layer 16 being connected to the common source structure 4 through subsequent deposition.

[0052] The present invention also proposes a three-dimensional memory 100, which can be prepared by the method for forming the three-dimensional memory 100 described in the above embodiments.

[0053] like Figure 13As shown, a three-dimensional memory 100 according to an embodiment of the present invention includes a semiconductor substrate 71, a top oxide layer 14, a stacked structure 7, and a dielectric layer 5. The top oxide layer 14 is formed on the surface of the semiconductor substrate 71. A common source trench 2 is formed in the stacked structure 7 and the top oxide layer 14, and a portion of the semiconductor substrate 71 is located at the bottom of the common source trench 2. The common source structure 4 fills the common source trench 2 and is located above the semiconductor substrate 71. The dielectric layer 5 is formed between the isolation layer 152 and the conductive layer 16, between the isolation layer 152 and the common source structure 4, between the top oxide layer 14 and the conductive layer 16, and between the top oxide layer 14 and the common source structure 4.

[0054] Optionally, the upper surface of the semiconductor substrate 71 is higher than the lower surface of the top oxide layer 14 and lower than the upper surface of the top oxide layer 14, and the thickness of the semiconductor substrate 71 above the lower surface of the top oxide layer 14 is less than or equal to half the total thickness of the top oxide layer 14.

[0055] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for forming a three-dimensional memory, characterized in that, include: A substrate is provided, which, from bottom to top, comprises a first substrate, a bottom oxide layer, a polysilicon layer, a top oxide layer, and a stacked structure; A common source trench is formed within the substrate, the common source trench penetrating the bottom oxide layer, the polysilicon layer, the top oxide layer and the stacked structure, and extending downward into the first substrate; A filling layer is formed at the bottom of the common source trench, and the upper surface of the filling layer is higher than the upper surface of the polysilicon layer and lower than the upper surface of the top oxide layer; A common source structure is formed within the common source trench, located on the surface of the filling layer; Remove the first substrate and a portion of the filler layer to expose the bottom oxide layer; Remove the bottom oxide layer; A semiconductor substrate is formed on the surface of the polycrystalline silicon layer and the filling layer.

2. The method for forming a three-dimensional memory according to claim 1, characterized in that, Before the step of removing the first substrate and a portion of the filler layer to expose the surface of the bottom oxide layer, a back-side process is performed by flipping the first substrate up to remove the first substrate and the filler layer that extend beyond the surface of the bottom oxide layer.

3. The method for forming a three-dimensional memory according to claim 1, characterized in that, The thickness of the filling layer extending beyond the upper surface of the polycrystalline silicon layer is half the thickness of the top oxide layer.

4. The method for forming a three-dimensional memory according to claim 1, characterized in that, The stacked structure includes sacrificial layers and isolation layers stacked at intervals.

5. The method for forming a three-dimensional memory according to claim 4, characterized in that, Before forming the common source structure within the common source trench, the following steps are also included: Remove the sacrificial layer to form an opening between the isolation layers; A dielectric layer is formed covering the surface of the isolation layer; A conductive layer is formed between the dielectric layers to fill the opening.

6. The method for forming a three-dimensional memory according to claim 5, characterized in that, The common source structure includes a first gate layer and a second gate layer formed within the first gate layer. The step of forming the common source structure located on the surface of the filling layer within the common source trench includes: A first gate layer is formed covering the conductive layer, the sidewalls of the dielectric layer facing the common source trench, and the surface of the filling layer; A second gate layer is formed within the first gate layer.

7. The method for forming a three-dimensional memory according to claim 1, characterized in that, The step of removing the first substrate and a portion of the filler layer to expose the surface of the bottom oxide layer includes: A portion of the first substrate and a portion of the filler layer are removed using a high selectivity ratio, while retaining a portion of the first substrate and the filler layer. The thickness removed using the high selectivity ratio is a first thickness. The first substrate and a portion of the filler layer are removed using a low selectivity ratio to expose the surface of the bottom oxide layer. The thickness removed using the low selectivity ratio is a second thickness, and the first thickness is greater than the second thickness.

8. The method for forming a three-dimensional memory according to claim 7, characterized in that, The first thickness is 50%-90% of the total thickness of the first substrate.

9. The method for forming a three-dimensional memory according to claim 8, characterized in that, The first thickness is 90% of the total thickness of the first substrate, and the second thickness is 10% of the total thickness of the first substrate.

10. A three-dimensional memory, characterized in that, include: Semiconductor substrate; A top oxide layer is formed on the surface of the semiconductor substrate; A stacked structure, wherein a common source trench is formed within the stacked structure and the oxide layer, and a portion of the semiconductor substrate is located at the bottom of the common source trench; the stacked structure includes a conductive layer and an isolation layer disposed at intervals in layers. A common source structure, wherein the common source structure fills the common source trench and is located above the semiconductor substrate, and in the corresponding region of the common source structure, the upper surface of the semiconductor substrate is higher than the lower surface of the top oxide layer and lower than the upper surface of the top oxide layer; A dielectric layer is formed between the isolation layer and the conductive layer, between the isolation layer and the common source structure, between the top oxide layer and the conductive layer, and between the top oxide layer and the common source structure.

11. The three-dimensional memory according to claim 10, characterized in that, The thickness of the semiconductor substrate above the lower surface of the top oxide layer is less than or equal to half the total thickness of the top oxide layer.

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