Flash memory device and preparation method thereof

Abstract

The present invention provides a flash memory device and a preparation method thereof, comprising: a substrate having a groove; a control gate layer located in the groove and extending upward; two floating gate layers located in the groove and respectively located on both sides of the control gate layer; a connecting oxide layer located between the drain region and the control gate layer; and a word line layer located outside one of the floating gate layers and used to connect the floating gate layer in the other groove. The coupling between the control gate layer and the floating gate layer is changed from a planar structure to a three-dimensional structure, and the overlapping area between the control gate layer and the floating gate layer in the vertical direction in the groove is not limited by the planar area of ​​the floating gate layer. While ensuring the coupling coefficient between the control gate layer and the floating gate layer, the length of the floating gate layer on the plane is reduced; at the same time, the floating gate layers in the two storage bits of the present invention share the same word line layer, further reducing the area of ​​the flash memory device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a flash memory device and a preparation method thereof. Background Art

[0002] Flash memory has become a hot topic in non-volatile memory research due to its convenience, high storage density, and good reliability. Since the first flash memory product came out in the 1980s, with the development of technology and the demand for storage in various electronic products, flash memory has been widely used in mobile communication devices such as mobile phones, notebooks, and USB flash drives.

[0003] As a non-volatile memory, flash memory works by changing the critical voltage of transistors or storage cells to control the switching of the gate channel in order to store data. Generally speaking, flash memory is divided into split-gate structure, stacked structure and a hybrid structure of the two structures. Split-gate flash memory has more unique performance advantages in programming and erasing compared to stacked flash memory due to its special structure. Split-gate flash memory has also been widely used due to its high programming efficiency and word line structure to avoid over-erasure. However, split-gate flash memory uses coupling between the storage gate or source line structure and the floating gate to provide high voltage, thereby realizing thermal electron programming of the floating gate. Therefore, the floating gate must have a certain length to ensure the coupling coefficient with the control gate or source line structure. Figure 1 This is a scanning electron microscope morphology image of a flash memory device. Figure 1 As shown, the length of the overlapping portion of the control gate layer 20 and the floating gate 10 accounts for half of the length of the floating gate 10. During programming, the control gate layer 20 couples with the floating gate 10 to generate high voltage, attracting electrons to tunnel to the floating gate 10. However, the longer coupling area limits the reduction of the planar space of the floating gate 10, thereby affecting the reduction of the size of the flash memory device. Summary of the invention

[0004] The object of the present invention is to provide a flash memory device and a method for preparing the same, which can reduce the size of the flash memory device while ensuring the coupling coefficient between the floating gate and the source line structure.

[0005] In order to achieve the above object, the present invention provides a flash memory device, including a substrate and two storage bits located on the substrate, wherein the storage bits include:

[0006] a groove located in the substrate;

[0007] A drain region, located at the bottom of the trench;

[0008] A connecting oxide layer is located on the drain region;

[0009] A control gate layer, located in the trench and extending upward;

[0010] Two floating gate layers, located in the trench and extending to cover a portion of the substrate, and the two floating gate layers are respectively located on both sides of the control gate layer;

[0011] The word line layer is located between the two storage bits, and the two storage bits share the word line layer.

[0012] Optionally, a portion of the floating gate layer located on the substrate has a floating gate tip, and the floating gate tip is aligned with the word line layer.

[0013] Optionally, the flash memory device utilizes hot electron injection to perform programming operations, utilizes FN tunneling effect to perform erasing operations, and utilizes electrons flowing from the drain region in one storage bit to the drain region in another storage bit to perform reading operations.

[0014] Optionally, the depth of the groove is

[0015] Based on the same inventive concept, the present invention also provides a method for preparing a flash memory device, characterized in that it comprises:

[0016] Providing a substrate, wherein two trenches and two drain regions are formed in the substrate, and the drain regions are located at the bottoms of the corresponding trenches;

[0017] forming a connection oxide layer on each of the drain regions;

[0018] A control gate layer and two floating gate layers are formed in each of the trenches, the control gate layer is located in the corresponding trench and extends upward, the two floating gate layers are located in the corresponding trench and extend to cover a portion of the substrate, and the two floating gate layers are respectively located on both sides of the corresponding control gate layer, and the corresponding trenches, drain regions, control gate layers and two floating gate layers constitute a storage bit;

[0019] A word line layer is formed on the substrate between the two storage bits, and the two storage bits share the word line layer.

[0020] Optionally, before forming the two drain regions in the trench, the method further comprises:

[0021] forming a mask layer on the substrate;

[0022] Etching the mask layer to form two first openings penetrating therethrough;

[0023] Continue etching a portion of the thickness of the substrate along each of the first openings to form the trench;

[0024] The mask layer is laterally etched to widen the first opening to form a second opening, wherein the lateral width of the second opening is greater than the lateral width of the trench.

[0025] Optionally, the step of forming the control gate layer and the two floating gate layers in each of the trenches includes:

[0026] forming a floating gate polysilicon layer in each of the trenches, wherein the floating gate polysilicon layer fills the corresponding trench and the second opening;

[0027] Etching a portion of the floating gate polysilicon layer in the second opening by an isotropic process so that a surface of the floating gate polysilicon is arc-shaped;

[0028] forming a first sidewall on a sidewall of each of the second openings, wherein a lateral width between the first sidewalls is smaller than a lateral width of the groove;

[0029] The floating gate polysilicon layer is etched using the first sidewall as a mask until the substrate is exposed, the floating gate polysilicon layer remaining in each of the first opening and the second opening constitutes two floating gate layers, and the portion of the floating gate layer located on the substrate has a floating gate tip;

[0030] Ions are implanted into the substrate at the bottom of the trench to form the drain region.

[0031] Optionally, the step of forming the control gate layer includes:

[0032] forming a second sidewall spacer in each of the second openings, wherein the second sidewall spacer covers the corresponding floating gate layer;

[0033] forming the connection oxide layer on the drain region;

[0034] The control gate layer is filled in a partial depth of the second opening.

[0035] Optionally, after forming the floating gate polysilicon layer, the method further includes:

[0036] The mask layer, the floating gate polysilicon layer and the substrate are etched to form a plurality of shallow trench isolation structures perpendicular to the floating gate layer.

[0037] Optionally, the step of forming the word line layer includes:

[0038] removing the mask layer;

[0039] The word line layer is formed between two of the storage bits.

[0040] The present invention provides a flash memory device and a preparation method thereof, wherein the flash memory device comprises: a substrate having a groove and a drain region at the bottom of the groove; a control gate layer located in the groove and extending upward; two floating gate layers located in the groove and extending to cover part of the substrate and respectively located on both sides of the control gate layer; a connecting oxide layer located between the drain region and the control gate layer; and a word line layer located outside one of the floating gate layers and used to connect the floating gate layer in the other groove. The plane coupling between the control gate layer and the floating gate layer is changed into a three-dimensional coupling, the overlapping area between the control gate layer and the floating gate layer in the vertical direction is not limited by the plane area of ​​the floating gate layer, and the overlapping area between the floating gate layer and the control gate layer can be adjusted by adjusting the depth of the groove, while ensuring the coupling coefficient between the control gate layer and the floating gate layer, the length of the floating gate layer on the plane is reduced, thereby reducing the area of ​​the flash memory device; at the same time, the floating gate layers in the two storage bits of the present invention share the same word line layer, further reducing the area of ​​the flash memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 The figure is a scanning electron microscope morphology image of a flash memory device;

[0042] Figure 2 A flow chart of a method for preparing a flash memory device provided by the present invention;

[0043] Figures 3 to 13 A schematic structural diagram corresponding to corresponding steps of a method for preparing a flash memory device provided by the present invention;

[0044] The accompanying drawings are as follows:

[0045] 100-substrate; 102-tunneling oxide layer; 104-mask layer; 105-first opening; 106-groove; 107-second opening; 108-dielectric layer; 110-floating gate polysilicon layer; 111-deep trench; 112-oxide layer; 114-first sidewall; 110a-floating gate layer; 116-second sidewall; 118-drain region; 119-connecting oxide layer; 120-control gate layer; 122-word line layer; 124-word line sidewall;

[0046] y - first direction; x - second direction. DETAILED DESCRIPTION

[0047] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0048] Hereinafter, the terms "first", "second", etc. are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms used in this manner are interchangeable where appropriate. Similarly, if the method described herein includes a series of steps, the steps presented herein are not necessarily the only order in which the steps can be performed, and some of the steps described may be omitted and / or other steps not described in the text may be added to the method.

[0049] Figure 2 A flowchart of a method for preparing a flash memory device provided in this embodiment is shown in FIG. Figure 2 As shown, the present invention provides a method for preparing a flash memory device, comprising:

[0050] Step S1: providing a substrate, wherein two trenches and two drain regions are formed in the substrate, and the drain regions are located at the bottoms of the corresponding trenches;

[0051] Step S2: forming a connection oxide layer on each of the drain regions;

[0052] Step S3: forming a control gate layer and two floating gate layers in each of the trenches, wherein the control gate layer is located in the corresponding trench and extends upward, the two floating gate layers are located in the corresponding trench and extend to cover a portion of the substrate, and the two floating gate layers are respectively located on both sides of the corresponding control gate layer, and the corresponding trenches, drain regions, control gate layers and two floating gate layers constitute a storage bit;

[0053] Step S4: forming a word line layer on the substrate between the two storage bits, wherein the two storage bits share the word line layer.

[0054] Figure 3 to Figure 13 The structural schematic diagram corresponding to the corresponding steps of the method for preparing a flash memory device provided by the present invention is shown below in conjunction with the attached Figure 3 to Figure 13 A method for preparing a flash memory device provided in this embodiment is described in more detail, wherein a preferred embodiment of the present invention is illustrated. Since the two storage bits in this embodiment are formed synchronously, only Figure 3 to Figure 13 The steps involved in forming two storage bits only schematically show one storage bit.

[0055] like Figure 3 and Figure 4As shown, a substrate 100 is provided, and a tunneling oxide layer 102 and a mask layer 104 are sequentially formed on the substrate 100, wherein the tunneling oxide layer 102 is silicon oxide, which can be formed by thermal oxidation, physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc. The mask layer 104 can be made of various suitable mask materials, such as oxide, nitride, oxynitride, etc. In this embodiment, the mask layer 104 is made of silicon nitride.

[0056] The mask layer 104 is etched to form two first openings 105 penetrating along the first direction y, and the tunneling oxide layer 102 and a portion of the substrate 100 are continuously etched along each of the first openings 105 to form two trenches 106 in the substrate 100. The bottom of the trench 106 has rounded corners to reduce stress between subsequent film layers and the substrate 100.

[0057] According to the actual situation and process requirements, the depth of the groove 106 is

[0058] See also Figure 4 and Figure 5 , the mask layer 104 is etched back to expand each of the first openings 105 to form a second opening 107, wherein the lateral width of the second opening 107 is greater than the lateral width of the corresponding groove 106. In this embodiment, the mask layer 104 is etched by a wet etching process, and the wet etching process includes a wet etching process such as hydrofluoric acid and phosphoric acid.

[0059] like Figure 6 and Figure 7 As shown, a dielectric layer 108 and a floating gate polysilicon layer 110 are formed in each of the second openings 107, the dielectric layer 108 covers the inner wall of the groove 106 and extends to cover the substrate 100 and the mask layer 104 and the side wall of the tunneling oxide layer 102 in the corresponding second opening 107, and the floating gate polysilicon layer 110 covers the dielectric layer 108 and at least fills the corresponding groove 106 and the second opening 107.

[0060] The mask layer 104 , the tunneling oxide layer 102 , the floating gate polysilicon layer 110 , the dielectric layer 108 and a portion of the substrate 100 are etched along the second direction x to form a plurality of deep trenches 111 along the second direction x. The deep trenches 111 penetrate the floating gate polysilicon layer 110 and the dielectric layer 108 and extend into the substrate 100 .

[0061] The bottom of the deep trench 111 has rounded corners to reduce stress between subsequent film layers and the deep trench 111 .

[0062] Furthermore, an oxide layer 112 is formed in the deep trench 111 , and the oxide layer 112 fills the deep trench 111 . The deep trench 111 and the filled oxide layer 112 form a trench isolation structure.

[0063] like Figure 8 As shown, the floating gate polysilicon layer 110 and the dielectric layer 108 in each of the second openings 107 are etched. Since isotropic etching is adopted, the upper surface of the floating gate polysilicon layer 110 has a certain curvature, and the size of the curvature depends on the isotropic etching time. The longer the isotropic etching time is, the greater the curvature of the upper surface of the floating gate polysilicon is. The portion of the floating gate polysilicon close to the mask layer 104 forms a slope, and the slope forms a floating gate tip structure in the subsequent process. The floating gate tip structure affects the coupling voltage of the floating gate during programming and erasing, thereby affecting the performance of the flash memory device during programming and erasing.

[0064] like Fig. 9 As shown, a first sidewall spacer 114 is formed in each second opening 107 , the first sidewall spacer 114 covers the inner wall of the mask layer 104 , and the lateral width between two first sidewall spacers 114 is smaller than the lateral width of the corresponding trench 106 .

[0065] like Fig.10 As shown, the remaining floating gate polysilicon layer and the dielectric layer 108 are etched along each of the first sidewalls 114 until the substrate 100 is exposed, so as to form two floating gate layers 110a in each of the grooves 106, wherein the floating gate layers 110a are located in the corresponding grooves 106 and extend upward to cover a portion of the substrate 100, and the portion of the floating gate layer 110a located on the surface of the substrate 100 has a floating gate tip structure.

[0066] Furthermore, a second spacer 116 is formed on the sidewall of each of the floating gate layers 110 a ; and a first ion implantation process is performed on the substrate 100 at the bottom of the trench 106 to form a drain region 118 .

[0067] like Fig.11 As shown, a source line polysilicon layer is formed in each of the grooves 106, the source line polysilicon layer fills the corresponding groove 106 and the second opening 107, and a portion of the source line polysilicon layer is etched back to form a control gate layer 120, and the height of the control gate layer 120 is greater than or equal to the height of the floating gate layer 110a.

[0068] The depth of the groove 106 and the height of the portion of the floating gate layer 110a located on the substrate 100 can be adjusted according to actual needs to adjust the coupling area between the control gate layer 120 and the floating gate layer 110a, and the coupling between the control gate layer and the floating gate layer is changed from planar coupling to three-dimensional coupling. While ensuring the coupling coefficient between the control gate layer 120 and the floating gate layer 110a, the length of the floating gate layer 110a on the plane is reduced, so that the area of ​​the flash memory device is further reduced; at the same time, adjusting the height of the floating gate layer 110a can achieve a higher coupling coefficient without affecting the planar area.

[0069] like Fig.12 and Fig.13 As shown, the remaining mask layer 104 on both sides of the floating gate layer 110a is removed by wet etching, and a word line layer 122 is formed between the floating gate layers 110a on two adjacent grooves. The floating gate layers 110a in two adjacent grooves 106 share one word line layer 122, further reducing the size of the flash memory device.

[0070] The present embodiment also provides a flash memory device, comprising: a substrate 100, wherein the substrate 100 has a groove 106 and a drain region 118 located at the bottom of the groove 106; a control gate layer 120, located in the groove 106 and extending upward; two floating gate layers 110a, located in the groove 106 and extending to cover a portion of the substrate 100, and respectively located on both sides of the control gate layer 120; a connecting oxide layer 119, located between the drain region 118 and the control gate layer 120; and a word line layer 122, located on the outside of one floating gate layer 110a, and used to connect the floating gate layer 110a in another groove.

[0071] The portion of the floating gate layer 110 a located on the substrate 100 has a floating gate tip, and the floating gate tip is aligned with the corresponding word line layer 124 .

[0072] In this embodiment, the depth of the groove 100 is The coupling area between the control gate layer 120 and the floating gate layer 110 a may be adjusted by adjusting the depth of the trench 100 .

[0073] The flash memory device provided in this embodiment utilizes hot electron injection to perform programming operations, utilizes FN tunneling effect to perform erasing operations, and utilizes electrons flowing from the drain region in one storage bit to the drain region in another storage bit to perform reading operations.

[0074] In summary, the present invention provides a flash memory device and a preparation method thereof, wherein the flash memory device comprises: a substrate 100 and two storage bits located on the substrate 100, wherein the storage bits comprise: a groove 106 located in the substrate 100; a drain region 118 located at the bottom of the groove 100; a connecting oxide layer 119 located on the drain region 118; a control gate layer 120 located in the groove 106 and extending upward; two floating gate layers 110a located in the groove 106 and extending to cover a portion of the substrate 100, and respectively located on both sides of the control gate layer 120; and a word line layer 122 located between the two storage bits, wherein the two storage bits share the word line layer 122. The present invention changes the planar coupling between the control gate layer 120 and the floating gate layer 110a into three-dimensional coupling. The overlapping area between the control gate layer 120 and the floating gate layer 110a in the vertical direction is not limited by the planar area of ​​the floating gate layer 110a, and the overlapping area between the floating gate layer 110a and the control gate layer 120 can be adjusted by adjusting the depth of the groove 106. While ensuring the coupling coefficient between the control gate layer 120 and the floating gate layer 110a, the length of the floating gate layer 110a on the plane is reduced, thereby reducing the area of ​​the flash memory device. At the same time, the floating gate layers 110a in the two storage bits of the present invention share the same word line layer 122, further reducing the area of ​​the flash memory device.

[0075] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A flash memory device, It is characterized in that The invention comprises a substrate and two storage bits located on the substrate, wherein the storage bits comprise: a groove located in the substrate; A drain region, located at the bottom of the trench; A connecting oxide layer is located on the drain region; A control gate layer, located in the trench and extending upward; Two floating gate layers, located in the trench and extending to cover a portion of the substrate, and the two floating gate layers are respectively located on both sides of the control gate layer, and a portion of the floating gate layer located on the substrate has a floating gate tip; A word line layer is located between the two storage bits, and the two storage bits share the word line layer, wherein the floating gate layers in two adjacent trenches share one word line layer.

2. A flash memory device as claimed in claim 1, It is characterized in that The floating gate tip is aligned with the word line layer.

3. A flash memory device as claimed in claim 1, It is characterized in that The flash memory device performs programming operation by hot electron injection, performs erasing operation by FN tunneling effect, and performs reading operation by electrons flowing from the drain region in one storage bit to the drain region in another storage bit.

4. A flash memory device as claimed in claim 1, It is characterized in that The depth of the groove is 5. A method for preparing a flash memory device, It is characterized in that include: Providing a substrate, wherein two trenches and two drain regions are formed in the substrate, and the drain regions are located at the bottoms of the corresponding trenches; forming a connection oxide layer on each of the drain regions; A control gate layer and two floating gate layers are formed in each of the trenches, the control gate layer is located in the corresponding trench and extends upward, the two floating gate layers are located in the corresponding trench and extend to cover a portion of the substrate, and the two floating gate layers are respectively located on both sides of the corresponding control gate layer, the corresponding trenches, drain regions, control gate layers and two floating gate layers constitute a storage bit, and a portion of the floating gate layer located on the substrate has a floating gate tip; A word line layer is formed on the substrate between the two storage bits, and the two storage bits share the word line layer, wherein the floating gate layers in two adjacent trenches share one word line layer.

6. A method for preparing a flash memory device as claimed in claim 5, It is characterized in that Before forming the two drain regions in the trench, the method comprises: forming a mask layer on the substrate; Etching the mask layer to form two first openings penetrating therethrough; Continue etching a portion of the thickness of the substrate along each of the first openings to form the trench; The mask layer is laterally etched to widen the first opening to form a second opening, wherein the lateral width of the second opening is greater than the lateral width of the trench.

7. A method for preparing a flash memory device according to claim 6, It is characterized in that The step of forming the control gate layer and the two floating gate layers in each of the trenches comprises: forming a floating gate polysilicon layer in each of the trenches, wherein the floating gate polysilicon layer fills the corresponding trench and the second opening; Etching a portion of the floating gate polysilicon layer in the second opening by an isotropic process so that a surface of the floating gate polysilicon is arc-shaped; forming a first sidewall on a sidewall of each of the second openings, wherein a lateral width between the first sidewalls is smaller than a lateral width of the groove; Using the first sidewall as a mask, etching the floating gate polysilicon layer until the substrate is exposed, and the remaining floating gate polysilicon layer in each of the first opening and the second opening constitutes two floating gate layers; Ions are implanted into the substrate at the bottom of the trench to form the drain region.

8. A method for preparing a flash memory device as claimed in claim 7, It is characterized in that The step of forming the control gate layer comprises: forming a second sidewall spacer in each of the second openings, wherein the second sidewall spacer covers the corresponding floating gate layer; forming the connection oxide layer on the drain region; The control gate layer is filled in a partial depth of the second opening.

9. A method for preparing a flash memory device according to claim 7, It is characterized in that After forming the floating gate polysilicon layer, the method further includes: The mask layer, the floating gate polysilicon layer and the substrate are etched to form a plurality of shallow trench isolation structures perpendicular to the floating gate layer.

10. A method for preparing a flash memory device according to claim 7, It is characterized in that The step of forming the word line layer comprises: removing the mask layer; The word line layer is formed between two of the storage bits.

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