Semiconductor memory device and method for manufacturing semiconductor memory device

Abstract

Embodiments provide a semiconductor storage device that can improve electrical characteristics, and a manufacturing method of a semiconductor storage device. A semiconductor storage device of an embodiment has a substrate, a charge holding portion, and a channel layer. The charge holding portion is curved at least in part in a cross section along a surface of the substrate. The channel layer is located inside the charge holding portion in the cross section, and is curved at least in part. The curvature of the charge holding portion differs depending on the position in the cross section. The film thickness of the channel layer differs depending on the curvature of the charge holding portion in the cross section.

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2020-144747 (filed on August 28, 2020). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing a semiconductor memory device. Background Technology

[0004] A known semiconductor memory device comprises: a stack of alternating insulating layers and word lines; and a plurality of memory pillars penetrating the stack in the thickness direction. Further improvements in the electrical properties of this semiconductor memory device are anticipated. Summary of the Invention

[0005] The present invention provides a semiconductor memory device with improved electrical characteristics and a method for manufacturing the semiconductor memory device.

[0006] The semiconductor memory device of this embodiment includes a substrate, a charge holding portion, and a channel layer. The charge holding portion is at least partially curved in a cross-section along the surface of the substrate. The channel layer is located inside the charge holding portion in the cross-section and is also at least partially curved. The curvature of the charge holding portion varies depending on its location in the cross-section. The thickness of the channel layer varies depending on the curvature of the charge holding portion in the cross-section. Attached Figure Description

[0007] Figure 1 This is a cross-sectional view showing an embodiment of a semiconductor memory device.

[0008] Figure 2 yes Figure 1 The cross-sectional view of the semiconductor memory device shown is along line F2-F2.

[0009] Figure 3 yes Figure 1 The diagram shows a cross-sectional view of the semiconductor memory device along line F3-F3.

[0010] Figure 4 This is a cross-sectional view showing an example of a memory cell in an implementation method.

[0011] Figure 5 yes Figure 1 The diagram shows a cross-sectional view of the semiconductor memory device along line F5-F5.

[0012] Figure 6(a) to (d) are cross-sectional views showing the manufacturing method of the semiconductor memory device according to the embodiments.

[0013] Figure 7 (a) to (c) are cross-sectional views showing the manufacturing method of the semiconductor memory device according to the embodiments.

[0014] Figure 8 (a) and (b) are cross-sectional views used to illustrate the function of the semiconductor memory device in the implementation method.

[0015] Figure 9 This is a cross-sectional view of a semiconductor memory device illustrating a variation of the implementation method. Detailed Implementation

[0016] Hereinafter, a semiconductor memory device according to an embodiment and a method for manufacturing a semiconductor memory device will be described with reference to the accompanying drawings. In the following description, components having the same or similar functions are referred to by the same reference numerals. Furthermore, repeated descriptions of these components are sometimes omitted. In this specification, "parallel" includes the case of "generally parallel". In this specification, "orthogonal" includes the case of "generally orthogonal". In this specification, "connected" includes not only the case where two components are adjacent without any object being placed between them, but also the case where other components are placed between the two components. In this specification, "ring-shaped" is not limited to a circular ring shape, but also includes a rectangular or triangular ring shape. In this specification, "XX is disposed on YY" is not limited to the case where XX and YY are connected, but also includes the case where other components are placed between XX and YY.

[0017] First, the X, Y, and Z directions are defined. The X and Y directions are along the surface 10a of the silicon substrate 10 described below (refer to...). Figure 1 The X direction is the direction of the following letter line WL (refer to...). Figure 1 The Y direction extends in the direction that intersects (e.g., is orthogonal) the X direction. The Y direction is the bit line BL described below (refer to...). Figure 1 The Z-direction extends in the direction of the X and Y directions. The Z-direction is the direction that intersects (e.g., is orthogonal) the X and Y directions. The Z-direction is the direction of extension of the silicon substrate 10 (refer to...). Figure 1 The thickness direction of the layer. In this specification, the direction in the Z direction from the silicon substrate 10 toward the laminate 20 described below is sometimes referred to as "upper" and its opposite direction as "lower". However, these expressions are used for convenience and do not specify the direction of gravity.

[0018] A semiconductor memory device includes: a stack of layers, consisting of alternating layers of insulating layers and word lines; and a plurality of memory pillars extending through the stack in the thickness direction of the stack. In this semiconductor memory device, the intersections of word lines and memory pillars function as memory cells. In this semiconductor memory device, when the number of layers increases, due to manufacturing reasons, the cross-sectional shape of the memory cells may become non-circular. In this case, the electrical characteristics (e.g., write characteristics) of the semiconductor memory device may sometimes degrade.

[0019] Therefore, in the semiconductor memory device of this embodiment, a specific portion of the channel layer contained in the memory column is formed to be thicker. This improves the electrical characteristics of the semiconductor memory device. The semiconductor memory device will now be described. However, the present invention is not limited to the embodiments described below.

[0020] (Implementation Method)

[0021] <1. Composition of Semiconductor Memory Devices>

[0022] First, the configuration of the semiconductor memory device 1 in the embodiment will be described. The semiconductor memory device 1 is a non-volatile semiconductor memory device, such as a NAND flash memory.

[0023] <1.1 Overall Structure of Semiconductor Memory Devices>

[0024] Figure 1 This is a cross-sectional view showing a semiconductor memory device 1. The semiconductor memory device 1, for example, includes a silicon substrate 10, a stack 20, a plurality of memory pillars 30, a plurality of contacts 40, a plurality of contacts 50, a plurality of bit lines BL, and a plurality of support pillars 60. Figure 1 (Only one is shown in the figure). From another perspective, the semiconductor memory device 1 has: a memory region 1a, on which the memory cell MC is disposed; and a contact region 1b, on which a plurality of conductive layers 21 are arranged in a stepped manner.

[0025] The silicon substrate 10 is a substrate serving as the base of the semiconductor memory device 1. At least a portion of the silicon substrate 10 is formed as a plate along the X and Y directions. The silicon substrate 10 has a surface 10a facing the laminate 20. The silicon substrate 10 is formed of a semiconductor material containing silicon (Si). The silicon substrate 10, for example, has a source region 10b that functions as part of a source line SL, in which impurities are diffused. However, the source line SL may also be disposed on an insulating layer laminated to the silicon substrate 10 instead of being disposed on the silicon substrate 10. The silicon substrate 10 is an example of a "substrate".

[0026] The stack 20 is disposed on the silicon substrate 10. The stack 20 includes, for example, a plurality of conductive layers 21 and a plurality of insulating layers 22. The plurality of conductive layers 21 and the plurality of insulating layers 22 are stacked alternately in the Z direction. Figure 1 The example only shows 10 conductive layers 21, but in reality there are more conductive layers 21 and insulating layers 22 stacked together.

[0027] The conductive layer 21 is formed as a plate along the X and Y directions. The conductive layer 21 extends in the X direction. The conductive layer 21 is formed of a conductive material such as tungsten (W). One (or two) of the conductive layers 21 closest to the silicon substrate 10 functions as a first selected gate line SGL1. The intersection of the first selected gate line SGL1 and the memory pillar 30 functions as a first selected transistor ST1. A specific voltage is applied to the first selected gate line SGL1 when the first selected transistor ST1 is turned on, electrically connecting the memory pillar 30 to the source line SL. The first selected gate line SGL1 is provided in a common manner relative to the multiple memory pillars 30.

[0028] On the other hand, one (or two) of the multiple conductive layers 21 furthest from the silicon substrate 10 functions as the second selection gate line SGL2. The intersection of the second selection gate line SGL2 and the memory pillar 30 functions as the second selection transistor ST2. When the second selection transistor ST2 is turned on and electrically connects the memory pillar 30 to the bit line BL, a specific voltage is applied to the second selection gate line SGL2. The second selection gate line SGL2 is provided in a common manner for the multiple memory pillars 30.

[0029] The remaining conductive layers 21, spaced between the conductive layers 21 that function as either the first select gate line SGL1 or the second select gate line SGL2, function as word lines WL. The intersections of the word lines WL with the memory pillars 30 function as memory cells (memory cell transistors) MC. Thus, the multiple memory cells MC are arranged in a matrix, spaced apart in the X, Y, and Z directions. The memory cells MC will be described in detail below. A voltage is applied to the word lines WL when writing data to, reading data from, or erasing data from the memory cells MC. Each word line WL is provided in a common manner relative to the multiple memory cells MC located at the same height in the Z direction.

[0030] The conductive layer 21 spans the memory region 1a and the contact region 1b. Regarding the length of the conductive layer 21 located in the contact region 1b, its length decreases the further away from the silicon substrate 10. Thus, the multiple conductive layers 21 are arranged in a stepped configuration. In the contact region 1b, contacts 50 are respectively connected to the multiple conductive layers 21. Therefore, voltage can be applied to the multiple conductive layers 21 independently.

[0031] The insulating layer 22 is formed in a plate shape along the X and Y directions. The insulating layer 22 is formed of an insulating material such as silicon oxide (SiO2).

[0032] Multiple memory pillars 30 are disposed in memory region 1a. The multiple memory pillars 30 extend along the Z direction and penetrate the stack 20 in the Z direction. The multiple memory pillars 30 are arranged in a matrix in the X and Y directions. Each memory pillar 30 has a multilayer film MF, a channel layer 34, and a core insulating portion 35. In this embodiment, the lower end of each memory pillar 30 is connected to the source region 10b of the silicon substrate 10 via a connection portion 10c disposed on the silicon substrate 10. The connection portion 10c is formed, for example, from a single crystal of amorphous silicon (a-Si). The configuration of the memory pillars 30 will be described in detail in the description related to the configuration of the memory cell MC.

[0033] Multiple contacts 40 are disposed on multiple memory pillars 30. The multiple contacts 40 are connected to the multiple memory pillars 30 in a one-to-one relationship.

[0034] Multiple bit lines BL are disposed on multiple contacts 40. Each bit line BL is connected to the corresponding memory cylinder 30 via the contact 40. Thus, by combining word lines WL and bit lines BL, any memory cell MC can be selected from multiple memory cells MC arranged in a three-dimensional manner.

[0035] Multiple support pillars 60 are disposed in the contact region 1b. Each support pillar 60 extends along the Z direction and penetrates one or more conductive layers 21 in the Z direction and is connected to the silicon substrate 10 via a connection portion 10c. The multiple support pillars 60 are a structure that supports multiple conductive layers 21 in the contact region 1b in a replacement process (hereinafter) as a manufacturing process of the semiconductor memory device 1. In this embodiment, the support pillars 60 are formed using the same process as the memory pillars 30 and have the same structure as the memory pillars 30. That is, the thickness of the channel layer 34 is locally increased as described below.

[0036] <1.2 Composition of Memory Units>

[0037] Next, the structure of the memory cell MC will be explained.

[0038] Figure 2 yes Figure 1The diagram shows a cross-sectional view of the semiconductor memory device 1 along line F2-F2. The memory pillar 30 is formed by depositing multiple functional layers inside a memory hole MH penetrating the laminate 20 in the Z direction. In this embodiment, the memory pillar 30 includes, for example, a multilayer film MF, a channel layer 34, and a core insulating portion 35. The multilayer film MF includes a barrier insulating film 31, a memory film 32, and a tunnel insulating film 33.

[0039] A barrier insulating film 31 is disposed on the inner peripheral surface of the memory hole MH. For example, the barrier insulating film 31 is annular along the inner peripheral surface of the memory hole MH. The barrier insulating film 31 is surrounded by and connected to the word line WL. The barrier insulating film 31 is disposed between the word line WL and the memory film 32. The barrier insulating film 31 is an insulating film that suppresses reverse tunneling. Reverse tunneling is the phenomenon of charge returning from the word line WL to the memory film 32. The barrier insulating film 31 extends in the Z direction, spanning most of the Z direction of the memory pillar 30. The barrier insulating film 31 is, for example, a stacked structure of multiple insulating films such as silicon oxide film or metal oxide film. An example of metal oxide is aluminum oxide (Al2O3). The barrier insulating film 31 may also contain a high-k material such as silicon nitride (SiN) or hafnium oxide (HfO).

[0040] The memory film 32 is disposed inside the barrier insulating film 31. In this embodiment, "disposed inside" means that in a cross-section along the X and Y directions, it is disposed on the inner circumference of a certain bend, for example, it is disposed on the center side of the memory pillar 30. This definition also applies to other components (such as the tunnel insulating film 33 and the core insulating portion 35).

[0041] In this embodiment, the memory film 32 is disposed on the inner peripheral surface of the barrier insulating film 31. For example, the memory film 32 is annular along the inner peripheral surface of the barrier insulating film 31. The memory film 32 is disposed between the barrier insulating film 31 and the tunnel insulating film 33. In this embodiment, the memory film 32 extends in the Z direction across most of the memory pillar 30. The memory film 32 is a charge trapping film capable of storing charge in crystal defects. The charge trapping film is, for example, formed of silicon nitride (Si3N4). The memory film 32 may also be referred to as a "charge retention film".

[0042] In this embodiment, a region in the memory film 32 located at the same height as the word line WL in the Z direction functions as a charge holding section 70. The charge holding section 70 stores data based on the amount of charge it holds. The charge holding section 70 is bent in at least a portion of its cross-section along both the X and Y directions. In this embodiment, the charge holding section 70 is formed in a ring shape and is bent entirely in the cross-section. However, the charge holding section 70 may be formed in an arc shape, or it may have a straight portion.

[0043] A tunnel insulating film 33 is disposed inside the memory film 32. In this embodiment, the tunnel insulating film 33 is disposed on the inner peripheral surface of the memory film 32. The tunnel insulating film 33 is annular along the inner peripheral surface of the memory film 32. The tunnel insulating film 33 is disposed between the memory film 32 and the channel layer 34. In this embodiment, the tunnel insulating film 33 extends in the Z direction across most of the memory pillar 30. The tunnel insulating film 33 acts as a potential barrier between the memory film 32 and the channel layer 34. The tunnel insulating film 33 comprises silicon oxide (SiO2), or silicon oxide (SiO2) and silicon nitride (SiN).

[0044] A channel layer 34 is disposed inside the tunnel insulating film 33. In this embodiment, the channel layer 34 is disposed on the inner peripheral surface of the tunnel insulating film 33. For example, the channel layer 34 is formed in a ring shape along the inner peripheral surface of the tunnel insulating film 33. The channel layer 34 is disposed between the tunnel insulating film 33 and the core insulating portion 35. The channel layer 34 extends in the Z direction across the entire length (full height) of the memory pillar 30. The lower end of the channel layer 34 is connected to the source region 10b of the silicon substrate 10 via the aforementioned connection portion 10c. The upper end of the channel layer 34 is connected to the bit line BL via a contact 40. The channel layer 34 is formed of a semiconductor material such as polysilicon (Poly-Si). The channel layer 34 may also be doped with impurities. The impurities contained in the channel layer 34 may be, for example, any one selected from the group consisting of carbon, phosphorus, boron, and germanium. When a voltage is applied to the word line WL, the channel layer 34 forms a channel and electrically connects the bit line BL to the silicon substrate 10.

[0045] The channel layer 34 is at least partially bent in cross-sections along the X and Y directions. In this embodiment, the channel layer 34 is formed in a ring shape and is bent throughout the cross-section. However, depending on the shape of the charge holding portion 70, the channel layer 34 may be formed in an arc shape, or may have a portion with a straight section.

[0046] A core insulating portion 35 is disposed inside the channel layer 34. In this embodiment, the core insulating portion 35 is formed as a cylinder (or an inverted frustum-shaped cone) along the inner circumferential surface of the channel layer 34, embedded in the inner circumferential side of the channel layer 34. The core insulating portion 35 extends in the Z direction, spanning most of the memory pillar 30. The core insulating portion 35 is formed of an insulating material such as silicon oxide (SiO2). The core insulating portion 35 is an example of an "insulating portion".

[0047] In this embodiment, a MANOS (Metal-Al-Nitride-Oxide-Silicon) type memory cell MC is formed by the end of the word line WL adjacent to the memory column 30, the blocking insulating film 31, the charge holding part 70, the tunnel insulating film 33, and the channel layer 34.

[0048] Here, the data writing and reading operations performed on the memory cell MC are explained. During the data writing operation, a programming pulse is applied to the word line WL adjacent to the memory cell MC to which the data is being written. The programming pulse is a pulse in which the voltage gradually increases periodically. As a result, electrons are drawn from the channel layer 34 into the charge holding section 70, where charge is stored. The sense amplifier circuit (not shown) included in the semiconductor memory device 1 determines, in each cycle of the programming pulse, whether the threshold voltage of the memory cell MC to be written has reached a voltage preset according to the data to be written (hereinafter referred to as "written data"). Furthermore, the programming pulse continues to be applied until the sense amplifier circuit determines that the threshold voltage of the memory cell MC has reached the voltage corresponding to the written data.

[0049] On the other hand, during the data readout operation, the bit line BL corresponding to the memory cell MC to be read out is pre-charged. Then, various determination potentials (threshold determination voltages) are sequentially applied to determine the threshold voltage of the memory cell MC to be read out. The sense amplifier circuit determines the data stored in the memory cell MC to be read out by detecting what determination voltage the charge stored in the bit line BL due to the pre-charge will flow out through the channel layer 34 to the source line SL. Hereinafter, the current flowing from the bit line BL to the source line SL through the channel layer 34 during the readout operation will sometimes be referred to as the "readout current".

[0050] <1.3 Cross-sectional shape of memory cell>

[0051] like Figure 2 As shown, at a certain cross section (e.g., along) Figure 1 When viewed from the cross-section of line F2-F2 (hereinafter referred to as "section A"), the cross-sectional shape of the memory cell MC is perfectly circular. That is, the barrier insulating film 31, the memory film 32, the tunnel insulating film 33, and the channel layer 34 are each perfectly circular or nearly circular annular in section A. The core insulating portion 35 is perfectly circular in section A. However, the memory pillar 30 is not limited to including a portion formed as perfectly circular. The cross-sectional shape of the memory pillar 30 may also be elliptical spanning the entire length of the memory pillar 30 in the Z direction.

[0052] On the other hand, when viewed from a cross-section closer to the silicon substrate 10 than cross-section A, the cross-sectional shape of the memory cell MC is deformed into an elliptical shape due to manufacturing reasons, etc. This will be explained below.

[0053] Figure 3 yes Figure 1 The diagram shows a cross-sectional view of the semiconductor memory device 1 along line F3-F3. Hereinafter, it will be described along... Figure 1The cross section of line F3-F3 is called "section B". Section B is a cross section along surface 10a of silicon substrate 10. Section B is an example of "section 1".

[0054] The barrier insulating film 31, the memory film 32, and the tunnel insulating film 33 are each elliptical annular in section B and include curved portions. The barrier insulating film 31, the memory film 32, and the tunnel insulating film 33 each have portions with smaller curvature and portions with larger curvature.

[0055] Here, refer to Figure 4 The term "curvature" as used in this embodiment will be explained.

[0056] Figure 4 This is a cross-sectional view representing an example of a memory cell MC. For example... Figure 4 As shown, in the actual product, the various layers contained in the memory cell MC are not completely annular, but rather contain deformations and undulations. Therefore, in this embodiment, the memory cell MC is divided into several regions, and the "curvature" of each region under macroscopic observation is defined as the curvature of each part.

[0057] Specifically, a major axis A1 and a minor axis A2 are defined for the elliptical memory cell MC. The major axis A1 is defined as a straight line passing through the two furthest points P1 and P2 on the outer periphery of the memory film 32. The minor axis A2 is defined as a straight line passing through the midpoint P3 of the two points P1 and P2 on the major axis A1 in a direction orthogonal to the major axis A1. Furthermore, the memory cell MC is divided into four regions R1, R2, R3, and R4 by setting two dividing lines B1 and B2 inclined at 45 degrees relative to the major axis A1.

[0058] Regions R1 and R3 are the regions traversed by the minor axis A2. Specifically, region R1 includes one end of the memory cell MC located on the minor axis A2. Region R3 includes the other end of the memory cell MC located on the minor axis A2. Region R3 is located on the opposite side of region R1 relative to the center of the memory cell MC (e.g., the intersection of the major axis A1 and the minor axis A2 (midpoint P3)).

[0059] On the other hand, regions R2 and R4 are areas traversed by the major axis A1. Specifically, region R2 includes one end of the memory cell MC located on the major axis A1. Region R4 includes the other end of the memory cell MC located on the major axis A1. Region R4 is located on the opposite side of region R2 relative to the center of the memory cell MC (e.g., the intersection of the major axis A1 and the minor axis A2 (midpoint P3)). From another viewpoint, the four regions R1, R2, R3, and R4 are arranged sequentially along the circumference of the memory cell MC relative to its center.

[0060] In the following description, the "curvature" related to the barrier insulating film 31, memory film 32, tunnel insulating film 33, channel layer 34, and core insulating portion 35 refers to the average curvature of the four regions R1, R2, R3, and R4. "Curvature" can refer to the curvature of the outer periphery or the inner periphery of each layer. Unless otherwise specified, "curvature" refers to the curvature of the outer periphery of each layer.

[0061] Furthermore, in the following description, unless otherwise specified, the "film thickness" related to the barrier insulating film 31, memory film 32, tunnel insulating film 33, and channel layer 34 refers to the average film thickness in the four regions R1, R2, R3, and R4. However, if specifically stated, it may also refer to the "maximum film thickness" or the "minimum film thickness".

[0062] Here, the major axis A1 and the minor axis A2 are as follows: Figure 4 The direction shown may be different from the X and Y directions. However, for ease of explanation, the following explanation will refer to the diagram with the major axis A1 along the X direction and the minor axis A2 along the Y direction.

[0063] return Figure 3 Continuing with the explanation, the memory film 32 has a charge holding portion 70 (hereinafter referred to as "charge holding portion 70_B") as shown in section B. The curvature of the charge holding portion 70_B in section B varies depending on its position. For example, the charge holding portion 70_B has a first portion 70a, a second portion 70b, a third portion 70c, and a fourth portion 70d. The first portion 70a, the second portion 70b, the third portion 70c, and the fourth portion 70d are respectively contained in regions R1, R2, R3, and R4. In this embodiment, the curvature of the second portion 70b is greater than the curvature of the first portion 70a and the curvature of the third portion 70c, respectively. The curvature of the fourth portion 70d is greater than the curvature of the first portion 70a and the curvature of the third portion 70c, respectively.

[0064] In this embodiment, the curvature of the charge holding portion 70_B (e.g., the curvature of the outer periphery and the curvature of the inner periphery) gradually increases (continuously increases) as it moves from the first portion 70a toward the second portion 70b, gradually decreases (continuously decreases) as it moves from the second portion 70b toward the third portion 70c, gradually increases (continuously increases) as it moves from the third portion 70c toward the fourth portion 70d, and gradually decreases (continuously decreases) as it moves from the fourth portion 70d toward the first portion 70a. The charge holding portion 70_B is an example of a "first charge holding portion".

[0065] The film thickness of the charge holding portion 70_B is fixed in the circumferential direction of the charge holding portion 70_B. That is, the film thicknesses of the first portion 70a, the second portion 70b, the third portion 70c, and the fourth portion 70d are the same. In this embodiment, "fixed film thickness" or "same film thickness" means that the difference between the maximum film thickness and the minimum film thickness is less than 1 nm.

[0066] The thickness of the channel layer 34 in section B varies depending on the curvature of the charge holding portion 70_B. For example, the channel layer 34 has a first portion 34a, a second portion 34b, a third portion 34c, and a fourth portion 34d. The first portion 34a, the second portion 34b, the third portion 34c, and the fourth portion 34d are respectively the portions contained in regions R1, R2, R3, and R4 (see reference). Figure 4 Part 1, 34a, is adjacent to Part 1, 70a of Charge Holding Part 70-B, separated by Tunnel Insulating Film 33. Part 2, 34b, is adjacent to Part 2, 70b of Charge Holding Part 70-B, separated by Tunnel Insulating Film 33. Part 3, 34c, is adjacent to Part 3, 70c of Charge Holding Part 70-B, separated by Tunnel Insulating Film 33. Part 4, 34d, is adjacent to Part 4, 70d of Charge Holding Part 70-B, separated by Tunnel Insulating Film 33.

[0067] From another perspective, part 34a is located at one end of the channel layer 34 on the short axis A2. Part 34a is an example of a "first thin film portion". Part 34c is located at the other end of the channel layer 34 on the short axis A2. Part 34c is an example of a "second thin film portion". Part 2 34b is located at one end of the channel layer 34 on the long axis A1. Part 2 34b is an example of a "first thick film portion". Part 4 34d is located at the other end of the channel layer 34 on the long axis A1. Part 4 34d is an example of a "second thick film portion".

[0068] In this embodiment, the film thickness (e.g., average film thickness) of the second part 34b is thicker than the film thickness (e.g., average film thickness) of the first part 34a and thicker than the film thickness (e.g., average film thickness) of the third part 34c. From another perspective, the maximum film thickness of the second part 34b is thicker than the maximum film thickness of the first part 34a and thicker than the maximum film thickness of the third part 34c. Furthermore, from another perspective, the minimum film thickness of the second part 34b is thicker than the minimum film thickness of the first part 34a and thicker than the minimum film thickness of the third part 34c. For example, the maximum film thickness of the second part 34b is at least 1 nm thicker (more specifically, at least 2 nm thicker) than the minimum film thicknesses of both the first part 34a and the third part 34c.

[0069] Similarly, the film thickness (e.g., average film thickness) of part 4 34d is thicker than the film thickness (e.g., average film thickness) of part 1 34a and thicker than the film thickness (e.g., average film thickness) of part 34c. From another perspective, the maximum film thickness of part 4 34d is thicker than the maximum film thickness of part 1 34a and thicker than the maximum film thickness of part 34c. Furthermore, from another perspective, the minimum film thickness of part 4 34d is thicker than the minimum film thickness of part 1 34a and thicker than the minimum film thickness of part 34c. For example, the maximum film thickness of part 4 34d is at least 1 nm thicker (more specifically, at least 2 nm thicker) than the minimum film thicknesses of both part 1 34a and part 34c.

[0070] In this embodiment, the thickness of the channel layer 34 gradually increases (continuously increases) as it moves from the first portion 34a toward the second portion 34b, gradually decreases (continuously decreases) as it moves from the second portion 34b toward the third portion 34c, gradually increases (continuously increases) as it moves from the third portion 34c toward the fourth portion 34d, and gradually decreases (continuously decreases) as it moves from the fourth portion 34d toward the first portion 34a.

[0071] In one example, in section B, the maximum film thickness of the first portion 34a and the maximum film thickness of the third portion 34c of the channel layer 34 are each less than the sum of the maximum film thickness of the barrier insulating film 31 and the maximum film thickness of the memory film 32. On the other hand, in section B, the maximum film thickness of the second portion 34b and the maximum film thickness of the fourth portion 34d of the channel layer 34 are each greater than the sum of the maximum film thickness of the barrier insulating film 31 and the maximum film thickness of the memory film 32.

[0072] In one example, in section B, the maximum film thickness of the first portion 34a and the maximum film thickness of the third portion 34c of the channel layer 34 are each less than the sum of the maximum film thickness of the memory film 32 and the maximum film thickness of the tunnel insulating film 33. On the other hand, in section B, the maximum film thickness of the second portion 34b and the maximum film thickness of the fourth portion 34d of the channel layer 34 are each greater than the sum of the maximum film thickness of the memory film 32 and the maximum film thickness of the tunnel insulating film 33.

[0073] From another perspective, the film thickness of the charge holding portion 70_B is fixed in the circumferential direction. On the other hand, the film thickness of the channel layer 34 varies in the circumferential direction at a rate greater than the rate of change of the film thickness of the charge holding portion 70_B.

[0074] Furthermore, from another perspective, the channel layer 34 has an inner perimeter e1 and an outer perimeter e2 as shown in section B. The inner perimeter e1 is the perimeter adjacent to the core insulation portion 35. The outer perimeter e2 is the perimeter located on the opposite side of the inner perimeter e1 and adjacent to the tunnel insulation film 33. Moreover, the sphericity of the inner perimeter e1 is higher than that of the outer perimeter e2.

[0075] The core insulating portion 35 has a first portion 35a, a second portion 35b, a third portion 35c, and a fourth portion 35d in section B. The first portion 35a, the second portion 35b, the third portion 35c, and the fourth portion 35d are respectively contained within regions R1, R2, R3, and R4 (see reference). Figure 4 Part 1, 35a, is parallel to Part 1, 70a of Charge Holding Part 70-B, separated by Channel Layer 34 and Tunnel Insulating Film 33. Part 2, 35b, is parallel to Part 2, 70b of Charge Holding Part 70-B, separated by Channel Layer 34 and Tunnel Insulating Film 33. Part 3, 35c, is parallel to Part 3, 70c of Charge Holding Part 70-B, separated by Channel Layer 34 and Tunnel Insulating Film 33. Part 4, 35d, is parallel to Part 4, 70d of Charge Holding Part 70-B, separated by Channel Layer 34 and Tunnel Insulating Film 33. The curvature difference between Part 1, 35a and Part 2, 35b of Core Insulating Part 35 is smaller than the curvature difference between Part 1, 70a and Part 2, 70b of Charge Holding Part 70-B.

[0076] Figure 5 yes Figure 1 The diagram shows a cross-sectional view of the semiconductor memory device 1 along line F5-F5. Hereinafter, it will be described along... Figure 1 The cross section along line F5-F5 is called "section C". Section C is a cross section along surface 10a of silicon substrate 10, and is a cross section further away from silicon substrate 10 than section B. Section C is an example of "second section".

[0077] The barrier insulating film 31, the memory film 32, and the tunnel insulating film 33 are each elliptical rings in section C, which are gentler than those in section B, and include curved portions. The barrier insulating film 31, the memory film 32, and the tunnel insulating film 33 each have portions with smaller curvature and portions with larger curvature.

[0078] The memory film 32 has a charge holding portion 70 (hereinafter referred to as "charge holding portion 70_C") manifested in cross section C. The curvature of the charge holding portion 70_C in cross section C varies depending on its position. For example, the charge holding portion 70_C has a first portion 70a, a second portion 70b, a third portion 70c, and a fourth portion 70d. Even within the charge holding portion 70_C, the curvature of the second portion 70b is greater than that of the first portion 70a and the third portion 70c, respectively. The curvature of the fourth portion 70d is greater than that of the first portion 70a and the third portion 70c, respectively. The charge holding portion 70_C is an example of a "second charge holding portion".

[0079] On the other hand, the channel layer 34 has a first portion 34a, a second portion 34b, a third portion 34c, and a fourth portion 34d in section C. The first portion 34a is adjacent to the first portion 70a of the charge holding portion 70_C, separated by the tunnel insulating film 33. The second portion 34b is adjacent to the second portion 70b of the charge holding portion 70_C, separated by the tunnel insulating film 33. The third portion 70c is adjacent to the third portion 70c of the charge holding portion 70_C, separated by the tunnel insulating film 33. The fourth portion 70d is adjacent to the fourth portion 70d of the charge holding portion 70_C, separated by the tunnel insulating film 33. From a certain point of view, the first portion 70a of the charge holding portion 70_C is an example of "the third portion", and the second portion 70b of the charge holding portion 70_C is an example of "the fourth portion".

[0080] In this embodiment, the thickness difference between the first portion 34a and the second portion 34b of the channel layer 34 in section B (e.g., the difference between the minimum thickness of the first portion 34a and the maximum thickness of the second portion 34b) is greater than the thickness difference between the first portion 34a and the second portion 34b of the channel layer 34 in section C (e.g., the difference between the minimum thickness of the first portion 34a and the maximum thickness of the second portion 34b). In this embodiment, the closer to the silicon substrate 10, the greater the thickness difference between the first portion 34a and the second portion 34b of the channel layer 34.

[0081] <2. Manufacturing method of semiconductor memory device>

[0082] Figure 6 This is a cross-sectional view showing the manufacturing method of semiconductor memory device 1, and it is also a diagram showing the overall process. First, as... Figure 6 As shown in (a), an insulating layer 22 formed of silicon oxide (SiO2) and an insulating layer 81 formed of silicon nitride (SiN) are alternately stacked on a silicon substrate 10. This forms an intermediate stack 20A. The insulating layer 81 formed of silicon nitride (SiN) is a sacrificial layer that is replaced by a conductive layer 21 in a later process.

[0083] Next, as Figure 6 As shown in (b), a memory hole MH is provided in the intermediate laminate 20A. The memory hole MH is a hole extending in the Z direction. Next, a single crystal of amorphous silicon (a-Si) is grown at the bottom of the memory hole MH to form a connection portion 10c.

[0084] Next, as Figure 6 As shown in (c), the materials of the barrier insulating film 31, the memory film 32, the tunnel insulating film 33, and the channel layer 34 are sequentially supplied to the inner peripheral surface of the memory hole MH to form the barrier insulating film 31, the memory film 32, the tunnel insulating film 33, and the channel layer 34. Next, silicon oxide (SiO2) is supplied to the inside of the channel layer 34 to form the core insulating portion 35.

[0085] Next, as Figure 6 As shown in (d), a replacement process is performed where the insulating layer 81 in the intermediate laminate 20A is replaced by the conductive layer 21. Specifically, the silicon nitride (SiN) forming the insulating layer 81 is removed through holes (not shown) provided in the intermediate laminate 20A. Next, tungsten (W) conductive material is supplied to the space where the insulating layer 81 has been removed, thereby forming the word line WL, the first select gate line SGL1, and the second select gate line SGL2. Thus, the laminate 20 is formed. Subsequently, contacts 40 and bit lines BL are formed, completing the semiconductor memory device 1.

[0086] Figure 7 This is a cross-sectional view showing a method for manufacturing semiconductor memory device 1, and it also shows a reference. Figure 6 Details of the process described in (c) (i.e., the process of forming the memory column 30). Figure 7 This is a cross-sectional view showing section B, omitting the diagram of the structure surrounding the memory cell MC.

[0087] like Figure 7 As shown in (a), amorphous silicon (a-Si), a semiconductor material, is supplied to the inner peripheral surface of the tunnel insulating film 33 as the material for the channel layer 34, and a heat treatment is performed to crystallize the amorphous silicon, thereby forming a channel layer intermediate 91 that becomes the source of the channel layer 34. In this stage, the thickness of the channel layer intermediate 91 is formed to be thicker than that of the channel layer 34. On the inner peripheral side of the channel layer intermediate 91, a thermal oxide film 92, such as silicon oxide (SiO2), is formed.

[0088] Next, as Figure 7As shown in (b), the thermal oxide film 92 is removed by wet etching using a first solution (first chemical solution) in a manner that retains a portion of the thermal oxide film 92. The first solution dissolves the thermal oxide film 92 more readily than the second solution described below, and the etching rate of the thermal oxide film 92 is above a certain rate. The first solution is, for example, dilute hydrofluoric acid (DHF). In this embodiment, the wet etching time of the first solution, the concentration of the first solution, etc., are adjusted so that a portion of the thermal oxide film 92 remains inside the channel layer intermediate 91 after the wet etching process using the first solution.

[0089] Here, when removing the elliptical annular thermal oxide film 92 by wet etching, the two ends 92b and 92d along the long axis of the thermal oxide film 92 are more difficult to etch than the two ends 92a and 92c along the short axis due to stress or other reasons. Therefore, when removing the thermal oxide film 92 while retaining a portion of it, the thermal oxide film 92 is retained inside the channel layer intermediate 91 with a thicker film thickness at ends 92b and 92d and a thinner film thickness at ends 92a and 92c. Alternatively, in this process, the ends 92a and 92c of the thermal oxide film 92 can also be removed, as long as the ends 92b and 92d of the thermal oxide film 92 are retained inside the channel layer intermediate 91.

[0090] Next, as Figure 7 As shown in (c), with a portion of the thermal oxide film 92 remaining inside the channel layer intermediate 91, the channel layer 34 is formed by wet etching using a second solution (second reagent) different from the first solution to refine the channel layer intermediate 91. The second solution dissolves the channel layer intermediate 91 more readily than the first solution. That is, the second solution has a higher etching rate on the channel layer intermediate 91 than the first solution. On the other hand, the second solution dissolves the thermal oxide film 92 less readily than the first solution. That is, the second solution has a lower etching rate on the thermal oxide film 92 than the first solution. The second solution is, for example, a mixture of hydrogen peroxide, water, choline, and water.

[0091] When performing wet etching using the second solution, firstly, the ends 92a and 92c of the thermal oxide film 92 are removed, and the portion located on the short axis in the intermediate body 91 of the channel layer is refined. Then, after removing the ends 92b and 92d of the thermal oxide film 92 with a time difference, the portion located on the long axis in the intermediate body 91 of the channel layer is refined. This yields a channel layer 34 with a film thickness varying according to its circumferential position. Finally, a core insulating portion 35 is formed on the inner side of the channel layer 34, completing the process. Figure 6 (c) process.

[0092] <3. Advantages>

[0093] In semiconductor memory devices, it is difficult to fabricate all memory pillars into perfect circles from top to bottom. Therefore, for example, the cross-sectional shape of the memory cell in the lower layer becomes elliptical. In this case, electrical characteristics (e.g., write performance) may sometimes degrade.

[0094] Figure 8 This is a cross-sectional view used to illustrate the function of semiconductor memory device 1. Figure 8 In the diagram, (a) represents a memory cell MCX as a comparative example. In this memory cell MCX, the barrier insulating film 31, the memory film 32, the tunnel insulating film 33, and the channel layer 34 are all elliptical rings, and the thickness of the channel layer 34 is fixed. In the memory cell MCX, when a voltage is applied to the word line WL during a data write operation, an electric field is easily generated in the regions J2 and J4 with greater curvature, and the charge e in the memory cell MC is easily concentrated and stored in the regions J2 and J4 with greater curvature.

[0095] On the other hand, when the read current flows through the channel layer 34 during a data read operation, the read current will flow through regions J1 and J3 in the channel layer 34 where the charge e is less. That is, the regions J2 and J4 that function during the write operation in the memory cell MC are different from the regions J1 and J3 that function during the read operation. In this case, even if sufficient charge e is stored in regions J2 and J4 of the memory cell MC, it will still be judged as insufficient charge e. As a result, there may be a situation where more charge e needs to be stored in the memory cell MC during the write operation, which slows down the write speed. Therefore, the difference in write speed between memory cells MC with good roundness and memory cells MC with poor roundness becomes larger, thus reducing the write characteristics.

[0096] Therefore, the semiconductor memory device 1 of this embodiment has a channel layer 34 with a film thickness that varies depending on the curvature of the charge holding portion 70. Based on this configuration, as... Figure 8 As shown in (b), the read current tends to flow more easily through the thicker portion of the channel layer 34 (i.e., near the region where more charge e is stored) due to current density. In other words, in the memory cell MC, regions J1 and J3 that function during read operations can be made closer to regions J2 and J4 that function during write operations. As a result, compared to the configuration of the comparative example, the necessity of storing more charge e in the memory cell MC is reduced, and the write speed can be improved. Consequently, the difference in write speed between the memory cell MC with good sphericity and the memory cell MC with poor sphericity is reduced, resulting in good write characteristics.

[0097] (Example of variation)

[0098] Figure 9 This is a cross-sectional view of a semiconductor memory device 1A showing a variation of the implementation. Figure 9 The diagram shows a cross-section B of the semiconductor memory device 1A. In this variation, the memory cell MC is triangular in shape. The barrier insulating film 31, the memory film 32, and the tunnel insulating film 33 are each formed into a triangular ring along the inner peripheral surface of the triangular memory hole MH. The charge holding portion 70 includes a first portion 100a and a second portion 100b with a curvature greater than that of the first portion 100a. The first portion 100a corresponds to the center of the side of the triangle. On the other hand, the second portion 100b corresponds to the corner of the triangle.

[0099] In this variation, the channel layer 34 has a thin film portion 110a and a thick film portion 110b, which is thicker than the thin film portion 110a. The thin film portion 110a is disposed in the region corresponding to the center of the sides of the triangle, and is placed side by side with the first portion 100a of the charge holding portion 70, separated by the tunnel insulating film 33. On the other hand, the thick film portion 110b is disposed in the region corresponding to the corners of the triangle, and is placed side by side with the second portion 100b of the charge holding portion 70, separated by the tunnel insulating film 33. Even with this configuration, the electrical characteristics can be improved in the same way as in the previous embodiment.

[0100] The semiconductor memory device and its manufacturing method according to the embodiments have been described above. However, the embodiments are not limited to the examples described above. In the above embodiments, an example was described in which the charge holding portion 70 is formed by a memory film 32 that serves as a charge trapping film. However, the charge holding portion 70 of the memory cell MC may also be a floating gate capable of storing data by the amount of charge stored, or a strong dielectric film (FeFET (ferroelectric field-effect transistor)) capable of storing data by the polarization orientation. The charge holding portion 70 may also be disposed between two adjacent insulating layers 22 in the Z direction in the laminate 20, rather than being part of the memory pillar 30.

[0101] According to at least one embodiment described above, the semiconductor memory device has a channel layer with a film thickness varying according to the curvature of the charge-holding portion. Based on this configuration, a semiconductor memory device with improved electrical characteristics and a method for manufacturing the semiconductor memory device can be provided.

[0102] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, as well as in the invention as described in the claims and its equivalents.

[0103] [Explanation of Symbols]

[0104] 1: Semiconductor memory devices

[0105] 31: Barrier insulating film

[0106] 32: Memory membrane

[0107] 33: Tunnel insulation film

[0108] 34: Channel Layer

[0109] 34a: Part 1

[0110] 34b: Part 2

[0111] 34c: Part 3

[0112] 34d: Part 4

[0113] 35: Core Insulation Section

[0114] 70, 70_B, 70_C: Charge holding section

[0115] 70a: Part 1

[0116] 70b: Part 2

[0117] 70c: Part 3

[0118] 70d: Part 4.

Claims

1. A semiconductor memory device comprising: Substrate; The first charge-holding portion is at least partially bent in a first cross-section along the surface of the substrate; and The channel layer, located inside the first charge-holding portion in the first cross-section, is at least partially curved; and The curvature of the first charge-holding portion in the first cross-section varies depending on its position. The thickness of the channel layer in the first cross section varies depending on the curvature of the first charge-holding portion; The semiconductor memory device further includes a second charge holding portion, which is disposed further away from the substrate than the first charge holding portion, and at least a portion of it is bent. The first charge-holding portion in the first cross-section includes a first part and a second part with a curvature greater than that of the first part. The second charge-retaining portion, in a second cross-section that is farther from the substrate than the first cross-section and along the surface of the substrate, includes a first portion and a second portion with a curvature greater than that of the first portion. The channel layer, in the first cross-section, includes a first portion parallel to the first portion of the first charge holding portion and a second portion parallel to the second portion of the first charge holding portion; and in the second cross-section, it includes a third portion parallel to the first portion of the second charge holding portion and a fourth portion parallel to the second portion of the second charge holding portion. The thickness difference between the first and second portions of the channel layer is greater than the thickness difference between the third and fourth portions.

2. The semiconductor memory device according to claim 1, wherein The second portion of the channel layer is thicker than the first portion of the channel layer.

3. The semiconductor memory device according to claim 2, wherein... The maximum film thickness of the second portion of the channel layer is more than 1 nm thicker than the minimum film thickness of the first portion of the channel layer.

4. The semiconductor memory device according to any one of claims 1 to 3, wherein The thickness of the channel layer in the first cross section varies at a rate greater than the rate of change of the thickness of the first charge-holding portion.

5. The semiconductor memory device according to any one of claims 1 to 3, comprising an insulating portion disposed inside the channel layer. The insulating portion in the first cross-section includes a first portion that is parallel to the first portion of the first charge holding portion, separated by the channel layer, and a second portion that is parallel to the second portion of the first charge holding portion, separated by the channel layer. The curvature difference between the first portion and the second portion of the insulating part is smaller than the curvature difference between the first portion and the second portion of the first charge holding part.

6. The semiconductor memory device according to any one of claims 1 to 3, wherein The channel layer is annular in the first cross-section and has an outer periphery and an inner periphery. The inner periphery has a higher degree of roundness than the outer periphery.

7. The semiconductor memory device according to any one of claims 1 to 3, wherein The channel layer is elliptical in the first cross-section and has: a first thick film portion located at one end of the channel layer on the major axis of the ellipse; a second thick film portion located at the other end of the channel layer on the major axis; a first thin film portion located at one end of the channel layer on the minor axis of the ellipse orthogonal to the major axis; and a second thin film portion located at the other end of the channel layer on the minor axis. The thickness of the first thick film portion is greater than that of the first thin film portion and the second thin film portion, respectively. The thickness of the second thick film portion is greater than that of the first thin film portion and the second thin film portion.

8. The semiconductor memory device according to any one of claims 1 to 3, further comprising: The first conductor is disposed on the outer side of the first cross section, covering the entire circumference of the first charge holding portion.

9. The semiconductor memory device according to any one of claims 1 to 3, wherein The thickness difference between the first portion and the second portion of the channel layer is greater than the thickness difference between the first portion and the second portion of the first charge holding portion.

10. A method for manufacturing a semiconductor memory device, By supplying semiconductor material into the memory holes disposed in the laminate and performing heat treatment, a channel layer intermediate and an oxide film disposed inside the channel layer intermediate are formed. The oxide film is removed using the first solution in a manner that retains a portion of the oxide film. A channel layer is formed by refining the intermediate of the channel layer using a second solution different from the first solution while retaining a portion of the oxide film.

11. The method of manufacturing a semiconductor memory device according to claim 10, wherein... The second solution is more difficult to dissolve the oxide film than the first solution.

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