Microelectronic devices including stepped structures, and related electronic systems and methods

Abstract

This application relates to microelectronic devices including a staircase structure and related electronic systems and methods. A microelectronic device includes a first tier structure including alternating conductive structures and insulative structures arranged in levels, each of the levels individually including one of the conductive structures and one of the insulative structures; a second tier structure vertically overlying the first tier structure and including additional levels of the conductive structures and the insulative structures; a staircase structure within the first tier structure and having steps including edges of the levels; a dielectric material covering the steps of the staircase structure and extending through the first tier structure; and a liner material interposed between the steps of the staircase structure and terminating at a tier-to-tier region between the first tier structure and the second tier structure. Related microelectronic devices, electronic systems, and methods are also described.

Description

[0001] Priority Claim

[0002] This application claims the benefit of U.S. Patent Application No. 17 / 006,600, filed August 28, 2020, entitled “Microelectronic Devices Including STAIR STEP STRUCTURES, AND RELATED ELECTRONIC SYSTEMS AND METHODS”. Technical Field

[0003] In various embodiments, this disclosure generally relates to the field of microelectronic device design and fabrication. More specifically, this disclosure relates to microelectronic devices and related electronic systems, and methods of forming microelectronic devices. Background Technology

[0004] A continuous goal of the microelectronics industry is to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (e.g., NAND flash memory devices). One way to increase the memory density of non-volatile memory devices is to utilize vertical memory array (also known as "three-dimensional (3D) memory array") architectures. A conventional vertical memory array comprises vertical memory strings extending through openings in a hierarchy of conductive structures (e.g., word lines) and dielectric material at each junction of the vertical memory strings with the conductive structures. Compared to structures with conventional planar (e.g., two-dimensional) transistor arrangements, this configuration allows a larger number of switching devices (e.g., transistors) to be positioned within a unit die area (i.e., the length and width of the effective surface consumed) by building the array upwards (e.g., vertically, on the die).

[0005] Conventional vertical memory arrays include electrical connections between conductive structures and access lines (e.g., word lines) that allow memory cells in the vertical memory array to be uniquely selected for write, read, or erase operations. One method of forming this electrical connection involves forming at least one so-called "staircase" (or "stair step") structure at the edge (e.g., horizontal end) of the conductive structure hierarchy. The staircase structure includes individual "steps" providing contact areas for the conductive structures, on which conductive contact structures can be positioned to provide electrical access to the conductive structures.

[0006] With advancements in vertical memory array technology, vertical memory arrays offer increased memory density by forming additional layers containing conductive structures and thus including associated additional staircase structures and / or additional steps within individual staircase structures. However, increasing the number of layers of conductive structures in the stacked structure (and thus the number of staircase structures and / or the number of steps within individual staircase structures) without undesirably increasing the overall width of the stacked structure (e.g., lateral footprint) can lead to undesirably complex and congested wiring paths for additional components (e.g., string drivers) that electrically connect the conductive structures to the memory devices. In some cases, as the height of the staircase structure increases, the risk of improperly forming conductive contacts with individual steps increases, potentially causing the vertical memory array to fail. Summary of the Invention

[0007] In some embodiments, a microelectronic device includes: a first layer structure including alternating conductive and insulating structures arranged in a hierarchy, each of the layers individually including one of the conductive structures and one of the insulating structures; a second layer structure vertically covering the first layer structure and including additional layers of the conductive and insulating structures; a stepped structure within the first layer structure and having steps including the edges of the layers; a dielectric material covering the steps of the stepped structure and extending through the first layer structure; and a liner material inserted between the steps of the stepped structure and the dielectric material and terminating in an interlayer region between the first and second layer structures.

[0008] In an additional embodiment, a microelectronic device includes a conductive stack structure vertically overlying a source structure and comprising alternating conductive and insulating structures arranged in a hierarchical manner. The conductive stack structure includes a first layer structure and a second layer structure vertically overlying the first layer structure. The microelectronic device further includes: a memory cell string extending vertically through the conductive stack structure; a stepped structure within the first layer structure and having steps including lateral ends of the layers; and a liner material on the steps of the stepped structure, the thickness of which decreases with increasing distance from the source structure.

[0009] In another additional embodiment, a method of forming a microelectronic device includes: forming a stepped structure in a first layer structure; forming a liner material on the steps of the stepped structure; forming a second layer structure vertically covering an interlayer region of the first layer structure and vertically covering the interlayer region; forming an additional stepped structure and an opening in the second layer structure vertically above and within the horizontal boundary of the stepped structure of the first layer structure; forming an additional liner material on the additional steps of the additional stepped structure and within the opening in the second layer structure; removing a portion of the additional liner material at the lower vertical boundary of the opening; and forming a conductive contact structure contacting the steps of the stepped structure of the first layer structure and the additional steps of the additional stepped structure.

[0010] In another embodiment, a method of forming a microelectronic device includes: forming a first oxide liner material over a step of a stepped structure in a first layer structure; forming a first nitride liner material over the first oxide liner material; forming a second layer structure over the first layer structure; forming a second oxide liner material over a step of an additional stepped structure in the second layer structure and over an opening surface in the second layer structure that vertically covers the stepped structure of the first layer structure; forming a second nitride liner material over the second oxide liner material; and removing a laterally extended portion of the second nitride liner material within the opening of the second layer structure.

[0011] In yet another embodiment, an electronic system includes: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device. The at least one electronic device includes: a first step structure within a first layer structure comprising alternating conductive and insulating layers; a second step structure within a second layer structure vertically overlying the first layer structure; and a nitride liner material adjacent to the steps of the first step structure, wherein the region between the first layer structure and the second layer structure is free of the nitride liner material. Attached Figure Description

[0012] Figures 1A to 1G This is a simplified cross-sectional view illustrating a method for forming a microelectronic device structure according to embodiments of the present disclosure;

[0013] Figures 2A to 2D This is a simplified cross-sectional view illustrating a method for forming a microelectronic device structure according to other embodiments of the present disclosure;

[0014] Figure 3This is a simplified cross-sectional perspective view of a microelectronic device according to an embodiment of the present disclosure;

[0015] Figure 4 This is a block diagram of an electronic system according to embodiments of the present disclosure; and

[0016] Figure 5 This is a block diagram of a processor-based system according to embodiments of the present disclosure. Detailed Implementation

[0017] The illustrations contained herein are not intended to be actual diagrams of any particular system, microelectronic structure, microelectronic device, or its integrated circuit, but are merely idealized representations used to describe the embodiments described herein. Common elements and features between the illustrations may retain the same numerical designation, except that, for ease of following the description, reference numbers begin with the number of the illustration in which the element is introduced or most fully described.

[0018] The following description provides specific details, such as material type, material thickness, and processing conditions, to provide a detailed description of the embodiments described herein. However, those skilled in the art will understand that these specific details can be used to practice the embodiments disclosed herein. In fact, the embodiments can be practiced in conjunction with conventional manufacturing techniques used in the semiconductor industry. Furthermore, the description provided herein does not form a complete process flow for manufacturing microelectronic device structures or microelectronic devices (e.g., memory devices, such as 3D NAND flash memory devices) or complete microelectronic devices. The structures described below do not form complete microelectronic devices. Only those process actions and structures necessary for understanding the embodiments described herein are described in detail below. Additional actions for forming complete microelectronic devices from the structures can be performed using conventional techniques.

[0019] The materials described herein can be formed using conventional techniques, including (but not limited to) spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD). Alternatively, the materials can be grown in situ. Depending on the specific material to be formed, the technique used for depositing or growing the material can be selected by one of ordinary skill in the art. Unless the context otherwise indicates, the removal of the material can be achieved by any suitable technique, including (but not limited to) etching, abrasive planarization (e.g., chemical mechanical planarization), or other known methods.

[0020] As used herein, the term “configured” refers to the size, shape, material composition, orientation, and arrangement of one or more of the structures and devices that facilitate the operation of one or more of the structures and devices in a predetermined manner.

[0021] As used herein, the terms “longitudinal,” “vertical,” “lateral,” and “horizontal” refer to the principal plane of a substrate (e.g., substrate material, substrate structure, substrate configuration, etc.) in which one or more structures and / or features are formed, and are not necessarily defined by the Earth’s gravitational field. A “lateral” or “horizontal” direction is a direction substantially parallel to the principal plane of the substrate, while a “longitudinal” or “vertical” direction is a direction substantially perpendicular to the principal plane of the substrate. The principal plane of the substrate is defined by a surface of the substrate having a relatively larger area than the other surfaces of the substrate.

[0022] As used herein, the term "substantially" with respect to a given parameter, property, or condition means, and includes, as understood by one of ordinary skill in the art, the degree to which a given parameter, property, or condition is satisfied within a certain range of variation (e.g., within acceptable tolerances). By way of example, depending on the specific parameter, property, or condition that is substantially satisfied, it may be satisfied at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100%.

[0023] As used herein, “about” or “approximately” with respect to a particular parameter includes the degree of variation of the value within acceptable tolerances for that particular parameter, as understood by one of ordinary skill in the art. For example, “about” or “approximately” with respect to a value may include additional values ​​within the range of 90.0% to 110.0% of the value, such as within the range of 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0024] As used herein, for ease of description, spatially relative terms (e.g., “below,” “under,” “down,” “bottom,” “above,” “top,” “front,” “back,” “left,” “right,” and the like) may be used to describe the relationship of one element or feature to another(s) illustrated in the figures. Unless otherwise specified, spatially relative terms are intended to cover not only the orientation depicted in the figures but also different orientations of the material. For example, if the material in the figures were reversed, an element described as being “below,” “under,” “below,” or “on the bottom” of other elements or features would be oriented “above” or “on the top” of other elements or features. Thus, those skilled in the art will understand that the term “below” can encompass both above and below orientations, depending on the context in which the term is used. Material may be oriented in other ways (e.g., rotated 90 degrees, reversed, flipped, etc.) and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0025] As used herein, features described as “adjacent” to each other (e.g., regions, materials, structures, devices) represent and include features of one (or more) disclosed individuals positioned closest to each other (e.g., closest to each other). Additional features (e.g., additional regions, additional materials, additional structures, additional devices) of one (or more) disclosed individuals that do not match “adjacent” features may be positioned between “adjacent” features. In other words, “adjacent” features may be positioned directly adjacent to each other such that no other features intervene between “adjacent” features; or “adjacent” features may be positioned indirectly adjacent to each other such that at least one feature of an individual having a different feature from that of an individual associated with at least one “adjacent” feature is positioned between “adjacent” features. Thus, features described as “vertically adjacent” to each other represent and include features of one (or more) disclosed individuals positioned vertically closest to each other (e.g., vertically closest to each other). Furthermore, features described as “horizontally adjacent” to each other represent and include features of one (or more) disclosed individuals positioned horizontally closest to each other (e.g., horizontally closest to each other).

[0026] As used herein, the term "memory device" means and includes, but is not limited to, microelectronic devices that exhibit memory functionality. In other words, by way of example only, the term "memory device" means and includes not only conventional memory (e.g., conventional volatile memory, such as conventional dynamic random access memory (DRAM); conventional non-volatile memory, such as conventional NAND memory), but also application-specific integrated circuits (ASICs) (e.g., system-on-a-chip (SoC)), microelectronic devices combining logic and memory, and graphics processing units (GPUs) incorporating memory.

[0027] As used herein, “conductive material” means and includes conductive materials, such as one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), alloys (e.g., Co) The term "conductive structure" refers to and includes structures formed from conductive materials and containing conductive materials. These include: basic alloys, Fe-based alloys, Ni-based alloys, Fe and Ni-based alloys, Co and Ni-based alloys, Fe and Co-based alloys, Co and Ni and Fe-based alloys, Al-based alloys, Cu-based alloys, magnesium (Mg)-based alloys, Ti-based alloys, steel, low-carbon steel, and stainless steel; conductive metallic materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, and conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polycrystalline silicon, conductive doped germanium (Ge), and conductive doped silicon-germanium (SiGe)). Furthermore, "conductive structure" indicates and includes structures formed from conductive materials and containing conductive materials.

[0028] As used herein, “insulating material” means and includes electrically insulating materials, such as one or more of the following: at least one dielectric oxide material (such as one or more of the following: silicon oxide (SiO2)). x Phosphorus silicate glass, borosilicate glass, borosilicate-phosphorus silicate glass, fluorosilicate glass, alumina (AlO) x ), hafnium oxide (HfO) x ), niobium oxide (NbO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x ()), at least one dielectric nitride material (e.g., silicon nitride (SiN) y ()), at least one dielectric oxide material (e.g., silicon oxynitride (SiO) x N y and at least one dielectric carbon nitride material (e.g., silicon carbon nitride (SiO2)). x C z N y This article contains the chemical formula of one or more of "x", "y" and "z" (e.g., SiO2). x AlO x HfO x NbO x TiO x SiN y SiO x Ny SiO x C z N y The chemical formula represents a material containing "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if present) for each atom of the other element (e.g., Si, Al, Hf, Nb, Ti). Since a chemical formula represents a relative atomic ratio and does not limit the chemical structure, an insulating material may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", and "z" (if present) may be integers or non-integers. As used herein, the term "non-stoichiometric compound" means and includes a chemical compound composed of elements that cannot be expressed by a ratio of well-defined natural numbers and violates the law of definite proportions. Additionally, "insulating structure" means and includes a structure formed of and containing insulating material.

[0029] According to embodiments described herein, a method for forming a microelectronic device comprising a stepped region including vertically alternating layers of conductive and insulating structures is described. The stepped structure is formed within a first layer structure comprising vertically alternating insulating structures and other insulating structures, and a liner material is formed on the steps of the stepped structure of the first layer structure. In some embodiments, the liner material comprises a nitride material, such as silicon nitride. A dielectric material may be formed on the liner material and within the stepped structure of the first layer structure. A second layer structure may be formed on the first layer structure, and additional stepped structures may be formed within the second layer structure. An opening may be formed within the second layer structure above the stepped structure of the first layer structure. A second liner material may be formed on the stepped structure of the second layer structure and within the opening of the second layer structure. Lateral extensions of the second liner material may be removed from the opening. After removing the lateral extensions of the second liner material, dielectric material may be formed within the opening and on the stepped structure of the first layer structure. Other insulating structures of the first and second layer structures may be replaced with conductive materials to form conductive structures. A conductive contact structure that penetrates the dielectric material and forms a conductive structure that contacts the stepped structure in the first layer structure and the second layer structure.

[0030] Removing the lateral extensions of the second liner material before forming the dielectric material within the opening improves the placement accuracy of the conductive contact structure on the conductive structure of the first layer structure. In contrast, a conventional microelectronic device that does not remove the second liner material may include lateral extensions of the first liner material within the stepped structure of the lower layer structure and lateral extensions of the second liner material within the opening above the stepped structure of the lower layer structure. During the formation of the conductive contact structure with the conductive structure of the stepped structure of the first layer structure, the second liner material can cause the conductive contact structure of the first layer structure to separate from the conductive structure of the first layer structure due to the different etch rate of the second liner material relative to the dielectric material. In other words, the second liner material can lead to insufficient etching of the dielectric material and improper placement of the conductive contact structure within the first layer structure (e.g., vertical placement).

[0031] In some embodiments, the microelectronic device may include a liner material on the steps of the stepped structure of the first layer structure and may not include a liner material on the sides of the insulating and conductive structures of the second layer structure that vertically overlies the stepped structure of the first layer structure. In other embodiments, the liner material on the sides of the insulating and conductive structures of the second layer structure that vertically overlies the stepped structure of the first layer structure may have a thickness less than the thickness of the liner material on the steps of the stepped structure of the first layer structure.

[0032] Figures 1A to 1G A method for forming a microelectronic device structure 100 according to an embodiment of the present disclosure is described. Figure 1A It is a simplified cross-sectional view of a microelectronic device structure 100 including a first layer structure 101 comprising an insulating structure 104 arranged in layers 108 and other insulating materials 106, in a vertical alternating (e.g., in the Z direction) sequence.

[0033] The insulating structure 104 may each individually consist of and contain an insulating material, such as one or more of the following: oxide materials (e.g., silicon dioxide (SiO2), phosphosilicate glass, borosilicate glass, borosilicate phosphosilicate glass, fluorosilicone glass, titanium dioxide (TiO2), hafnium oxide (HfO2), zirconium dioxide (ZrO2), hafnium oxide (HfO2), tantalum oxide (TaO2), magnesium oxide (MgO), aluminum oxide (Al2O3) or combinations thereof) and amorphous carbon. In some embodiments, the insulating structure 104 comprises silicon dioxide.

[0034] Other insulating structures 106 may be formed of and comprise an insulating material exhibiting etch selectivity relative to insulating structure 104. Other insulating structures 106 may comprise, for example, nitride materials (e.g., silicon nitride (Si3N4), oxide nitride materials (e.g., silicon oxynitride)). In some embodiments, other insulating structures 106 comprise nitride materials, such as silicon nitride.

[0035] although Figure 1A A specific number of layers 108 are described for insulating structure 104 and other insulating structures 106, but this disclosure is not limited thereto. In some embodiments, the first layer structure 101 includes a desired number of layers 108, such as sixty-four (64) layers 108. In other embodiments, the first layer structure 101 includes a different number of layers 108, such as fewer than sixty-four (64) layers 108 (e.g., fewer than or equal to sixty (60) layers 108, fewer than or equal to fifty (50) layers 108, fewer than or equal to forty (40) layers 108, fewer than or equal to thirty (30) layers 108, fewer than or equal to twenty (20) layers 108, fewer than or equal to ten (10) layers 108); or more than sixty-four (64) layers 108 of the insulating structure 104 and other insulating structures 106 (e.g., more than or equal to seventy (70) layers 108, more than or equal to one hundred (100) layers 108, more than or equal to one hundred and twenty-eight (128) layers 108).

[0036] The first layer structure 101 can be patterned to form a stair step structure 112 (also referred to herein as a "staircase structure") comprising a first stair step structure 112a and a second stair step structure 112b. Although Figure 1A The first-level structure 101 is described as containing only two step structures 112, but this disclosure is not limited thereto, and the microelectronic device structure 100 may contain fewer (e.g., one) or more (e.g., three, four, five, six, seven, or eight) step structures 112. Each of the step structures 112 may be referred to herein as a so-called “step” because the step structure 112 contains steps 111 that face each other (e.g., opposite). In some embodiments, the first step structure 112a may be positioned closer to the source structure 110 (e.g., common source plate (CSP)) than the second step structure 112b. In other words, the steps 111 of the first step structure 112a may be positioned closer to the source structure 110 than the steps 111 of the second step structure 112b.

[0037] The formation of the stepped structure 112 may include, for example, forming a first mask (e.g., a chamfered mask) on the microelectronic device structure 100 and forming an opening in the first mask at a position corresponding to the second stepped structure 112b, and removing portions of the layers 108 of the insulating structure 104 and other insulating structures 106 through the opening in the first mask. After removing portions of the layers 108 of the insulating structure 104 and other insulating structures 106 through the opening in the first mask, the first mask can be removed.

[0038] A second mask (e.g., a photoresist material) may be formed on the microelectronic device structure 100, and openings may be formed in the second mask at positions corresponding to the first step structure 112a and the second step structure 112b to expose the underlying layers 108 of the insulating structure 104 and other insulating structures 106. A portion of the uppermost layer 108 of the insulating structure 104 and other insulating structures 106 exposed through the openings in the second mask may be removed. After the removal of the portion of the uppermost layer 108, the second mask may be exposed to trimming chemicals to trim the second mask and increase the lateral dimension of the openings (e.g., in the X direction) and expose a portion of the uppermost layer 108 corresponding to the width (in the X direction) of the step 111. After trimming the second mask, the exposed underlying layers 108 of the insulating structure 104 and other insulating structures 106 may be removed. The process of trimming the second mask and removing the exposed portion of the underlying layer 108 can be repeated a desired number of times (e.g., up to a desired number of steps 111) to form the first step structure 112a and the second step structure 112b.

[0039] Each level 108 may contain steps 111 defined by an edge (e.g., a horizontal end) of the level 108. For example... Figure 1A As shown, in some embodiments, the steps 111 of the stepped structure 112 are arranged in sequence such that steps 111 that are directly horizontally adjacent to each other (e.g., in the x-direction) correspond to levels 108 of the first layer structure 101 that are directly vertically adjacent to each other. In an additional embodiment, the steps 111 of the stepped structure 112 are arranged in random order such that at least some steps 111 of the stepped structure 112 that are directly horizontally adjacent to each other in the horizontal direction correspond to levels 108 of the first layer structure 101 that are not directly vertically adjacent to each other.

[0040] The height H of the first layer structure 101 (e.g., in the Z direction) may be in the range of about 4.0 micrometers (μm) to about 8.0 μm, for example, from about 4.0 μm to about 5.0 μm, from about 5.0 μm to about 6.0 μm, from about 6.0 μm to about 7.0 μm, or from about 7.0 μm to about 8.0 μm. In some embodiments, the height H is in the range of about 6.0 μm to about 7.0 μm, for example, about 6.5 μm. However, this disclosure is not limited thereto, and the height H may differ from the height described.

[0041] refer to Figure 1B A first liner material 114 may be formed on the surfaces of the first stepped structure 112a and the second stepped structure 112b. A second liner material 116 may be formed on the first liner material 114 within the horizontal boundaries (e.g., in the X direction) of the first stepped structure 112a and the second stepped structure 112b. A dielectric material 118 may be formed on the second liner material 116 and may fill the remaining portion of the opening in the first layer structure 101 defined by the first stepped structure 112a and the second stepped structure 112b. In some embodiments, portions of the first liner material 114, the second liner material 116, and the dielectric material 118 formed outside the boundaries (e.g., horizontal boundaries, vertical boundaries) of the opening defined by the first stepped structure 112a and the second stepped structure 112b may be removed. For example, the microelectronic device structure 100 may be exposed to a chemical mechanical planarization (CMP) process to remove portions of the first liner material 114, the second liner material 116, and the dielectric material 118 outside the opening defined by the first step structure 112a and the second step structure 112b.

[0042] The first lining material 114 and the second lining material 116 may be formed conformally within the opening defined by the stepped structure 112 (e.g., within the opening defined by the step) and on the step 111. In some embodiments, the first lining material 114 and the second lining material 116 may extend substantially vertically along the sidewall of the opening defining the upper portion of the second stepped structure 112b and the first layer structure 101.

[0043] The first liner material 114 may be formed of and comprise one or more of the materials described above with reference to the insulating structure 104. In some embodiments, the first liner material 114 comprises silicon dioxide. In some embodiments, the first liner material 114 comprises the same material composition as the insulating structure 104.

[0044] The second substrate material 116 may be formed of and comprise a material exhibiting etch selectivity relative to the first substrate material 114. By way of non-limiting example, the second substrate material 116 may be formed of and comprise a dielectric material, such as one or more of the following: silicon nitride (e.g., stoichiometric silicon nitride, non-stoichiometric silicon nitride), oxynitride (e.g., silicon oxynitride), carbon-doped silicon nitride, silicon carbonitride (e.g., SiCN), carbon-doped silicon oxynitride, polycrystalline silicon, alumina, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, cerium oxide, titanium nitride, tantalum nitride, tungsten nitride, or another material. In some embodiments, the second substrate material 116 comprises silicon nitride.

[0045] The dielectric material 118 may be formed of and comprise one or more insulating materials, such as those described above with reference to insulating structure 104. In some embodiments, the dielectric material 118 comprises the same material composition as insulating structure 104. In some embodiments, the dielectric material 118 comprises silicon dioxide.

[0046] The thickness T1 of the first lining material 114 can be from approximately To about 100 to about Within a certain range, for example from approximately To date From the agreement To date From the agreement To date From the agreement To date Or from the agreement To date In some embodiments, the thickness T1 of the first liner material 114 is approximately... To date Within the range. However, this disclosure is not limited thereto, and the thickness T1 of the first liner material 114 may be different from the thickness described.

[0047] The thickness T2 of the second lining material 116 can be from approximately To about 100 to about Within a certain range, for example from approximately To date From the agreement To date From the agreement To date From the agreement To date Or from the agreement To date In some embodiments, the thickness T2 of the second liner material 116 is approximately... To date Within the range. However, this disclosure is not limited thereto, and the thickness T2 of the second liner material 116 may differ from the thickness described.

[0048] After forming the first liner material 114, the second liner material 116, and the dielectric material 118 within the opening defined by the stepped structure 112, different portions of the microelectronic device structure 100 can be patterned to form pillars of semiconductive material extending through the first layer structure 101. These pillars can be formed as memory cells (e.g., memory cell 303). Figure 3 )) string (e.g., vertical string 307) Figure 3As will be described herein. In other embodiments, the struts of the semiconducting material may be formed prior to the formation of the stepped structure 112.

[0049] refer to Figure 1C After each of the first liner material 114, the second liner material 116, and the dielectric material 118 is formed, the interlayer region 120 may be formed on the first layer structure 101, and the second layer structure 121 may be formed on the interlayer region 120 to form a stacked structure 125 including the first layer structure 101, the interlayer region 120, and the second layer structure 121.

[0050] In some embodiments, the interlayer region 120 comprises substantially the same material composition as the layers 108 of the insulating structure 104 and other insulating structures 106. In some embodiments, the interlayer region 120 comprises one (1) layer 108 of the insulating structure 104 and another insulating structure 106.

[0051] The second layer structure 121 may be substantially the same as the first layer structure 101. For example, the second layer structure 121 may include a vertically alternating (e.g., in the Z direction) sequence of insulating structures 104 and other insulating structures 106 arranged in a layer 108.

[0052] In some embodiments, the number of levels 108 in the second layer structure 121 may be the same as the number of levels 108 in the first layer structure 101. In some embodiments, the height of the second layer structure 121 (e.g., in the Z direction) may be the same as the height H of the first layer structure 101. Figure 1A They are basically the same.

[0053] Continue to refer to Figure 1C After the second layer structure 121 is formed, additional stepped structures 112 (e.g., third stepped structures 112c and fourth stepped structures 112d) may be formed within the second layer structure 121. Additionally, an opening 122 may be formed above the stepped structures 112 (e.g., first stepped structures 112a and second stepped structures 112b) of the first layer structure 101 to expose (e.g., reveal) the interlayer region 120. The opening 122 may be positioned directly vertically above the stepped structures 112 (e.g., first stepped structures 112a and second stepped structures 112b) of the first layer structure 101 and within the horizontal boundaries of the stepped structures 112 of the first layer structure 101. In some embodiments, the opening 122 may be at least partially defined by a vertically extending sidewall 123.

[0054] In some embodiments, the fourth step structure 112d may be positioned further away from the source structure 110 than the third step structure 112c. In other words, the step 111 of the fourth step structure 112d may be positioned vertically higher than (e.g., in the Z direction) the step 111 of the third step structure 112c.

[0055] In some embodiments, since the third step structure 112c and the fourth step structure 112d are formed within the second layer structure 121 which is positioned vertically above the first layer structure 101 (e.g., in the Z direction), the third step structure 112c and the fourth step structure 112d may be referred to as "upper step structure" or "upper step structure", and the first step structure 112a and the second step structure 112b may be referred to as "lower step structure" or "lower step structure".

[0056] refer to Figure 1D After the stepped structure 112 is formed, a third liner material 124 may be formed on the surface defining the opening 122, the surface of the third stepped structure 112c, and the surface of the fourth stepped structure 112d, and a fourth liner material 126 may be formed on the third liner material 124, the third stepped structure 112c, and the fourth stepped structure 112d. In some embodiments, the third liner material 124 and the fourth liner material 126 formed outside the boundary of the stepped structure 112 may be removed, for example, by exposing the microelectronic device structure 100 to a CMP process to remove the portions of the third liner material 124 and the fourth liner material 126 outside the boundary of the stepped structure 112.

[0057] The third lining material 124 and the fourth lining material 126 may be formed conformally within an additional opening defined by the stepped structure 112 (e.g., within an additional opening defined by an additional upper step) and above its steps 111. In some embodiments, the third lining material 124 and the fourth lining material 126 may extend substantially vertically along the sidewall of the additional opening defining the upper portion of the third stepped structure 112c and the second layer structure 121. Additionally, the third lining material 124 and the fourth lining material 126 may extend conformally along the sidewall of the second layer structure 121 defining the opening 122.

[0058] The third liner material 124 may be formed of and comprise one or more of the materials described above with reference to the first liner material 114. In some embodiments, the third liner material 124 comprises silicon dioxide. In some embodiments, the third liner material 124 comprises the same material composition as the first liner material 114.

[0059] The fourth liner material 126 may be formed of and comprise one or more of the materials described above with reference to the second liner material 116. In some embodiments, the fourth liner material 126 comprises silicon nitride. In some embodiments, the fourth liner material 126 comprises the same material composition as the second liner material 116.

[0060] The thickness T3 of the third lining material 124 can be from approximately To about 100 to about Within a certain range, for example from approximately To date From the agreement To date From the agreement To date From the agreement To date Or from the agreement To date In some embodiments, the thickness T3 of the third liner material 124 is approximately... To date Within the range. However, this disclosure is not limited thereto, and the thickness T3 of the third liner material 124 may differ from the described thickness. In some embodiments, the thickness T3 of the third liner material 124 may be substantially the same as the thickness T1 of the first liner material 114.

[0061] The thickness T4 of the fourth liner material 126 can be from approximately To about 100 to about Within a certain range, for example from approximately To date From the agreement To date From the agreement To date From the agreement To date Or from the agreement To date In some embodiments, the thickness T4 of the fourth liner material 126 is approximately... To date Within the range. However, this disclosure is not limited thereto, and the thickness T4 of the fourth liner material 126 may differ from the described thickness. In some embodiments, the thickness T4 of the fourth liner material 126 may be substantially the same as the thickness T2 of the second liner material 116.

[0062] For reference Figure 1EAfter the third liner material 124 and the fourth liner material 126 are formed, a mask material 128 (e.g., a photoresist material) may be formed on the microelectronic device structure 100 and patterned. The mask material 128 may be formed on some stepped structures 112 (e.g., all stepped structures 112).

[0063] After the mask material 128 is formed, it can be removed from the surfaces of some of the stepped structures 112. In some embodiments, a portion of the mask material 128 that is directly vertically overly (e.g., in the Z direction) and within the horizontal boundaries of the stepped structures 112 of the first layer structure 101 (e.g., first stepped structures 112a and second stepped structures 112b) can be removed to form an opening 130 in the mask material 128, at least partially defined by the second layer structure 121. The surface of the fourth liner material 126 (e.g., the laterally extending surface of the fourth liner material 126) can be exposed through the opening 130. The mask material 128 can be vertically overly over and fill the additional opening defined by the stepped structures 112 of the second layer structure 121 (e.g., third stepped structures 112c and fourth stepped structures 112d).

[0064] In some embodiments, the lateral extensions of the fourth liner material 126 and the third liner material 124 (e.g., in the X direction, in the Y direction (in and out) Figure 1E The page in the view can be removed through opening 130 while the mask material 128 remains on at least the stepped structures 112 (e.g., the third stepped structure 112c and the fourth stepped structure 112d) of the second layer structure 121. In some embodiments, the vertical extension of the fourth liner material 126 (e.g., in the Z direction) can be removed simultaneously with the removal of the lateral extensions of the fourth liner material 126 and the third liner material 124. In other words, the portion of the fourth liner material 126 on the vertically extending sidewall 123 can be removed simultaneously with the removal of the lateral extension of the fourth liner material 126. In other embodiments, at least one portion of the fourth liner material 126 can remain on the vertically extending sidewall 123 of the second layer structure 121 that partially defines the opening 130. In some embodiments, the vertical extension of the third liner material 124 on the sidewall 123 is substantially not removed during the removal of the fourth liner material 126.

[0065] A portion of the fourth liner material 126 can be removed by exposing the fourth liner material 126 to one or more dry etchants, such as oxygen (O2), nitrogen (N2), nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), difluoromethane (CH2F2), fluoroform (CHF3), a mixture of hexafluoroethane and hexafluoropropylene (C2F6 / C3F6), a mixture of hexafluoropropylene and hydrogen (C3F6 / H2), and sulfur hexafluoride (SF6). In other embodiments, a portion of the fourth liner material 126 is removed by exposing the fourth liner material 126 to one or more wet etchants, such as phosphoric acid (H3PO4). Although Figure 1E This indicates that the vertical extension of the fourth liner material 126 is removed, but is not limited to this. For example, and as discussed above, at least a portion of the vertical extension of the fourth liner material 126 may be retained (e.g., the thickness of the vertical extension of the fourth liner material 126). Figure 4 ( Figure 1D The thickness T4 can be reduced, but it can remain on the sidewall 123 that partially defines the opening 130. In some such embodiments, the thickness T4 of the fourth liner material 126 can decrease as the distance from the source structure 110 increases. Therefore, in some embodiments, the thickness T4 of the fourth liner material 126 can be variable (e.g., with the distance from the source structure 110).

[0066] A portion of the third liner material 124 can be removed by exposing the third liner material 124 to one or more dry etchants, such as O2, N2, NF3, CF4, and ammonia (NH3) (e.g., one of NH3, NF3, and CH4). In some embodiments, removing the third liner material 124 with a dry etchant can facilitate the removal of the lateral extensions of the third liner material 124 while substantially not removing the vertical extensions of the third liner material 124.

[0067] Removing the lateral extensions of the fourth liner material 126 and the third liner material 124 exposes a portion of the interlayer region 120 vertically overlying (e.g., in the Z direction) the stepped structures 112 (e.g., the first stepped structure 112a and the second stepped structure 112b) of the first layer structure 101. Continuing to refer to... Figure 1E The exposed portion of the interlayer region 120 can be removed to expose the upper portion of the dielectric material 118 and the second liner material 116 covering the stepped structure 112 (e.g., the first stepped structure 112a and the second stepped structure 112b) of the first layer structure 101.

[0068] In some embodiments, other insulating structures 106 of the layer 108 of the interlayer region 120 can be removed in substantially the same manner as the removal of the fourth liner material 126, and insulating structures 104 of the layer 108 of the interlayer region 120 can be removed in substantially the same manner as the removal of the third liner material 124. By way of non-limiting example, other insulating structures 106 can be removed by exposing other insulating structures 106 to one or more of O2, N2, NF3, CF4, CH2F2, CHF3, C2F6, C3F6, H2, and SF6, and insulating structures 104 can be removed by exposing insulating structures 104 to one or more of O2, N2, NF3, CF4, and NH3. However, this disclosure is not limited thereto, and other insulating materials 106 and insulating structures 104 can be removed by methods different from those described.

[0069] Now for reference Figure 1F After the dielectric material 118 is exposed, it can be removed from the surface of the stepped structure 112 (e.g., the third stepped structure 112c and the fourth stepped structure 112d) of the second layer structure 121 and from the surface of the second layer structure 121 horizontally between the stepped structures 112 of the first layer structure 101 (e.g., from the opening 130 between the first stepped structure 112a and the second stepped structure). Figure 1E Mask material 128 (between) Figure 1E Removal of mask material 128 may expose (e.g., reveal) a portion of fourth liner material 126 within an additional opening defined by the stepped structure 112 of the second layer structure 121.

[0070] After the mask material 128 is removed, the dielectric material 132 may be formed on the microelectronic device structure 100, for example, on each of the stepped structures 112. In some embodiments, the dielectric material 132 is formed on the fourth substrate material 126 of the stepped structures 112 of the second layer structure 121 (e.g., the third stepped structure 112c and the fourth stepped structure 112d) and the dielectric material 118 of the stepped structures 112 of the first layer structure 101 (e.g., the first stepped structure 112a and the second stepped structure 112b). Figure 1E Above. In some embodiments, the dielectric material 132 directly contacts the opening 130 above the stepped structure 112 of the first layer structure 101. Figure 1E The third lining material 124 on the side wall 123 of the )

[0071] Dielectric material 132 can be derived from dielectric material 118 mentioned above. Figure 1BThe dielectric material 132 is formed from and comprises one or more of the materials described in the description. In some embodiments, the dielectric material 132 comprises silicon dioxide. In some embodiments, the dielectric material 132 comprises the same material composition as the dielectric material 118. Since the dielectric material 132 may comprise the same material composition as the dielectric material 118 (…), Figure 1E Since they have the same material composition, dielectric material 132 and dielectric material 118 can be collectively referred to as dielectric material 132 herein. In other words, and referring to... Figure 1F The dielectric material 132 may include a dielectric material 118 positioned within an opening defined by the stepped structure 112 of the first layer structure 101. Figure 1E ).

[0072] After the dielectric material 132 is formed, the dielectric material 132 may be exposed to a CMP process to planarize the dielectric material 132 and remove the portion of the dielectric material 132 located outside the boundaries (e.g., horizontal boundaries, vertical boundaries) of the stepped structure 112.

[0073] In some embodiments, after the step structure 112 of the second layer structure 121 is formed, pillars (e.g., cell pillars) formed of and containing a semiconductive material may be formed to extend vertically through the second layer structure 121, as described above with reference to the first layer structure 101. The pillars may be vertically positioned (e.g., directly vertically positioned) on the pillars formed to extend vertically through the first layer structure 101. The pillars may be formed as memory cells (e.g., memory cell 303). Figure 3 )) string (e.g., vertical string 307) Figure 3 As will be described herein. In other embodiments, the struts may be formed prior to the formation of the stepped structures 112 (e.g., the third stepped structure 112c and the fourth stepped structure 112d) of the second layer structure 121.

[0074] refer to Figure 1G Other insulation structures 106 ( Figure 1F The gate can be removed and replaced with a conductive structure 134 in a so-called "replacement gate" process to form a layer 136 (corresponding to layer 108). Figure 1FA vertically alternating conductive stack structure 135 of conductive structure 134 and insulating structure 104. For example, a slot may be formed to extend vertically (e.g., in the Z direction) through the second layer structure 121, the interlayer region 120, and the first layer structure 101, and at least some other insulating structures 104 of the subsequent layer 108 can be selectively removed through the slot. By a non-limiting example, the second layer structure 121, the interlayer region 120, and the first layer structure 101 can be selectively removed through the slot by exposure to one or more wet etchants comprising one or more of phosphoric acid, sulfuric acid, ammonium fluoride, or ammonium bifluoride. Figure 1F Subsequently, conductive material can be deposited within the open volume formed by the extraction of other insulating structures 106 to form conductive structure 134 in a so-called "replacement gate" process. The lowest conductive structure 134 (e.g., the conductive structure 134 closest to the source structure 110) can form a select gate structure that may include a select gate source (SGS) structure. The uppermost conductive structure 134 can form a select gate structure that may include a select gate drain (SGD) structure.

[0075] The conductive structure 134 may include local access lines, which may also be referred to as local word lines. The conductive structure 134 may include conductive materials, such as (for example) tungsten, titanium, nickel, platinum, rhodium, ruthenium, iridium, aluminum, copper, molybdenum, silver, gold, metal alloys, and metal-containing materials (e.g., metal nitrides, metal silicides, metal carbides, metal oxides), including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), and iridium oxide (IrO). x ), Ruthenium oxide (RuO) x The conductive structure 134 may be a material of at least one of the following: an alloy thereof, a conductive doped semiconductor material (e.g., conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.), polycrystalline silicon, other materials exhibiting conductivity, or combinations thereof. In some embodiments, the conductive structure 134 includes tungsten.

[0076] In some embodiments, the conductive structure 134 may include one or more liner materials (e.g., conductive liner materials) surrounding the conductive structure 134, such as between the conductive structure 134 and the insulating structure 104. The liner material may include, for example, a seed material from which the conductive structure 134 may be formed. The liner material may be formed from and include, for example, a metal (e.g., titanium, tantalum), a metal nitride (e.g., tungsten nitride, titanium nitride, tantalum nitride), aluminum oxide, or another material. In some embodiments, the liner material includes titanium nitride. In some embodiments, the liner material further includes aluminum oxide. In some embodiments, the conductive structure 134 includes aluminum oxide directly adjacent to the insulating structure 104, titanium nitride directly adjacent to the aluminum oxide, and tungsten directly adjacent to the titanium nitride. For clarity and ease of understanding, one or more liner materials are not mentioned in the text. Figure 1G As explained herein, it should be understood that the liner material may be placed around the conductive structure 134.

[0077] Continue to refer to Figure 1G After the conductive structure 134 is formed, the conductive contact structure 138 (for clarity and to facilitate understanding of the embodiments of this disclosure, in) Figure 1G The conductive contact structures 138 (only some of which are described herein) may be formed through the dielectric material 132 to individually contact the conductive stack structure 135 at the steps 111 of the stepped structure 112. The conductive contact structures 138 may include conductive materials, such as one or more of the conductive materials described above with reference to the conductive structure 134. In some embodiments, the conductive contact structure 138 includes substantially the same material composition as the conductive structure 134. In some embodiments, the conductive contact structure 138 includes tungsten.

[0078] In some embodiments, the second liner material 116 includes a so-called etch-stop material for the stepped structure 112 of the first layer structure 101, which is substantially not removed during the removal of portions of the dielectric material 132 when an opening is formed in the dielectric material 132 prior to the formation of the conductive contact structure 138. Similarly, in some embodiments, the fourth liner material 126 includes an etch-stop material for the stepped structure 112 of the second layer structure 121, which is substantially not removed during the removal of portions of the dielectric material when an opening is formed in the dielectric material 132 prior to the formation of the conductive contact structure 138 in the second layer structure 121. After an opening is formed in the dielectric material 132, a so-called through-etch is performed to remove portions of the first liner material 116 and the fourth liner material 126 and expose the underlying conductive structure 134 prior to the formation of the conductive contact structure 138.

[0079] Therefore, removing the lateral extension of the fourth liner material 126 facilitates the formation of a conductive contact structure 138 on the steps 111 of the stepped structure 112 of the first layer structure 101. In contrast, during conventional fabrication of a microelectronic device structure, the lateral extension of the liner material may not be removed, and the microelectronic device structure may include two lateral extensions of the liner material between the upper surface of the second layer structure 121 and the steps of the lower stepped structure (e.g., the stepped structure of the first layer structure). The presence of the lateral extension of the second liner material can serve as an etch stop material during the formation of the opening in the dielectric material (e.g., dielectric material 132) and prevent the conductive contact structure (e.g., conductive contact structure 138) from being directly formed on and electrically connected to the conductive structure (e.g., conductive structure 134) of the stepped structure of the first layer structure.

[0080] Although it has been Figures 1A to 1G Explain and describe the process using mask material 128 ( Figure 1E Opening 130 in ) Figure 1E The portion of the interlayer region 120 may be removed, but this disclosure is not limited thereto. Figures 2A to 2D This is a simplified cross-sectional view illustrating a method for forming a microelectronic device structure according to an additional embodiment of the present disclosure.

[0081] Figure 2A Is with Figure 1C The simplified cross-sectional view of the microelectronic device structure 200 is substantially the same as that of the microelectronic device structure 100, except that a portion of the layer 108 of the interlayer region 120 directly above the stepped structure 112 (e.g., the first stepped structure 112a and the second stepped structure 112b) of the first layer structure 101 has been removed to expose the underlying dielectric material 118.

[0082] refer to Figure 2B After removing a portion of the layer 108 of the interlayer region 120, a third liner material 224 may be formed on the surface of the microelectronic device structure 200, and a fourth liner material 226 may be formed on the third liner material 224. In some embodiments, the third liner material 224 may be formed on the steps 111 of the stepped structures 112 (e.g., the third stepped structure 112c and the fourth stepped structure 112d) of the second layer structure 121 and on the dielectric material 118 of the stepped structures 112 (e.g., the first stepped structure 112a and the second stepped structure 112b) of the first layer structure 101.

[0083] The third lining material 224 can be obtained from the third lining material 124 mentioned above. Figure 1D The fourth liner material 226 may be formed and comprised of one or more of the materials described above, with reference to the fourth liner material 126 ( Figure 1DThe material described herein is formed by and contains one or more of the material.

[0084] For reference Figure 2C After the third liner material 224 and the fourth liner material 226 are formed, a mask material 228 (e.g., a photoresist material) may be formed on and patterned on the surface of the microelectronic device structure 200. Openings may be formed in the mask material 228 on the stepped structure 112 of the first layer structure 101. In some embodiments, the lateral extensions (e.g., in the X direction) of the fourth liner material 226 and the third liner material 224 may be removed from the stepped structure 112 of the first layer structure 101, as referenced above. Figure 1E describe.

[0085] For reference Figure 2D Mask material 228 ( Figure 2C The dielectric material 232 can be removed from the surface of the microelectronic device structure 200, and the dielectric material 232 can be formed on the microelectronic device structure 200. The dielectric material 232 can be made from the dielectric material 132 mentioned above. Figure 1F The material described herein is formed by and contains one or more of the material.

[0086] refer to Figure 2D Other insulation structures 106 ( Figure 2C The gate can be removed and replaced with a conductive structure 234 in a so-called "replacement gate" process to form a layer 236 (corresponding to layer 108). Figure 2C The conductive structure 234 and the insulating structure 104 are vertically alternating conductive stacked structures 235, as described above with reference to conductive structure 134. Figure 1G ) and conductive stacked structure 135 ( Figure 1G The formation description is as follows. For example, a slot may be formed to extend vertically (e.g., in the Z direction) through the second layer structure 121, the interlayer region 120, and the first layer structure 101, and then at least some other insulating structures 104 of layer 108 may be selectively removed through the slot. The conductive structure 234 may be formed and comprise one or more of the materials described above with reference to conductive structure 134.

[0087] After the dielectric material 232 is formed, the conductive contact structure 238 (for clarity and to facilitate understanding of the embodiments of this disclosure, in) Figure 2D Only some of the conductive contact structures 238 are described above. These structures can be formed by dielectric material 232 to individually contact the conductive stack structure 235 at the steps 111 of the stepped structure 112, as described above with reference to conductive contact structure 138. Figure 1GThe conductive contact structure 238 may be formed from and include one or more of the materials described above with reference to the conductive contact structure 138.

[0088] Figure 3 This illustration shows a partial cross-sectional perspective view of a portion of a microelectronic device 300 (e.g., a memory device, such as a dual-layer 3D NAND flash memory device) including a microelectronic device structure 301. The microelectronic device structure 301 may be substantially similar to the previously referenced... Figures 1A to 1G and Figures 2A to 2D The microelectronic device structures described are 100 and 200. For example... Figure 3 As shown, the microelectronic device structure 301 may include a stacked structure 325 (e.g., a conductive stacked structure 135). Figure 1G ), conductive stacked structure 235 ( Figure 2D The definition defines the connection of access line 306 to conductive layer 305 (e.g., conductive layer, conductive plate, conductive structure 134). Figure 1G The stepped structure 320 (e.g., stepped structure 112) of the contact area of ​​the conductive structure 234 (e.g., 2D) and the conductive structure 234 (e.g., 2D) Figure 1G , Figure 2D The microelectronic device structure 301 may include a vertical string 307 of memory cells 303 coupled in series with each other. The vertical string 307 may extend vertically (e.g., in the Z direction) and orthogonally to conductive lines and conductive layers 305, such as data lines 302 and source layers 304 (e.g., source structure 110). Figure 1G , Figure 2D ), conductive layer 305, access line 306, first select gate 308 (e.g., upper select gate, drain select gate (SGD), e.g., conductive structure 134 ( Figure 1G ) and conductive structure 234 ( Figure 2D The selection line 309 and the second selection gate 310 (e.g., lower selection gate, source selection gate (SGS)). The selection gate 308 may be horizontally divided (e.g., in the Y direction) into a plurality of blocks 332 that are horizontally separated from each other (e.g., in the Y direction) by slots 330.

[0089] Vertical conductive contact 311 (e.g., conductive contact structure 138) Figure 1G ) and conductive contact structure 238 ( Figure 2DComponents can be electrically coupled to each other, as shown. For example, select line 309 can be electrically coupled to a first select gate 308, and access line 306 can be electrically coupled to conductive layer 305. The microelectronic device 300 may also include a control unit 312 positioned below the memory array. The control unit 312 may include at least one of a string driver circuitry, a pass gate, a circuitry for selecting a gate, a circuitry for selecting conductive lines (e.g., data line 302, access line 306), a circuitry for amplifying signals, and a circuitry for sensing signals. For example, the control unit 312 may be electrically coupled to data line 302, source layer 304, access line 306, first select gate 308, and second select gate 310. In some embodiments, the control unit 312 includes a CMOS (Complementary Metal-Oxide-Semiconductor) circuitry. In such embodiments, the control unit 312 may be characterized to have an "under-array CMOS" ("CuA") configuration.

[0090] The first selection gate 308 may extend horizontally in a first direction (e.g., the X direction) and may be coupled at a first end (e.g., the upper end) of the vertical string 307 to a corresponding first group of vertical strings 307 of the memory cell 303. The second selection gate 310 may be coupled at a second opposite end (e.g., the lower end) of the vertical string 307 of the memory cell 303, which is formed in a substantially planar configuration.

[0091] Data lines 302 (e.g., bit lines) may extend horizontally in a second direction (e.g., in the Y direction) at an angle (e.g., perpendicular) to a first direction in which the first select gate 308 extends. Data lines 302 may be coupled at a first end (e.g., the upper end) of a vertical string 307 to a corresponding second group of vertical strings 307. Vertical strings 307 coupled to the first group of corresponding first select gates 308 may share a specific vertical string 307 with vertical strings 307 coupled to the second group of corresponding data lines 302. Therefore, a specific vertical string 307 at the intersection of a specific first select gate 308 and a specific data line 302 can be selected. Thus, the first select gate 308 can be used to select a memory cell 303 of a vertical string 307 of memory cell 303.

[0092] Conductive layers 305 (e.g., word lines) may extend in a corresponding horizontal plane. The conductive layers 305 may be vertically stacked such that each conductive layer 305 is coupled to all vertical strings 307 of memory cells 303, and the vertical strings 307 of memory cells 303 extend vertically through the stack of conductive layers 305. The conductive layers 305 may be coupled to or may form the control gate of the memory cell 303 coupled to the conductive layer 305. Each conductive layer 305 may be coupled to one memory cell 303 of a particular vertical string 307 of memory cells 303.

[0093] The first select gate 308 and the second select gate 310 are operable to select a specific vertical string 307 of memory cells 303 between a specific data line 302 and the source layer 304. Therefore, a specific memory cell 303 can be selected and electrically coupled to the data line 302 by operation of appropriate first select gate 308, second select gate 310, and conductive layer 305 coupled to the specific memory cell 303 (e.g., by selecting appropriate first select gate 308, second select gate 310, and conductive layer 305).

[0094] The stepped structure 320 can be configured to provide an electrical connection between the access line 306 and the conductive level 305 via a vertical conductive contact 311. In other words, a particular level of the conductive level 305 can be selected via an access line 306 electrically connected to a corresponding vertical conductive contact 311 electrically connected to the particular conductive level 305.

[0095] Therefore, a microelectronic device according to an embodiment of the present disclosure includes: a first layer structure including alternating conductive and insulating structures arranged in a hierarchy, each of the layers individually including one of the conductive structures and one of the insulating structures; a second layer structure vertically covering the first layer structure and including additional layers of the conductive and insulating structures; a stepped structure within the first layer structure and having steps including the edges of the layers; a dielectric material covering the steps of the stepped structure and extending through the first layer structure; and a liner material inserted between the steps of the stepped structure and terminating in an interlayer region between the first and second layer structures.

[0096] Therefore, according to an additional embodiment of this disclosure, a microelectronic device includes a conductive stack structure vertically overlying a source structure and comprising alternating conductive and insulating structures arranged in a hierarchical manner. The conductive stack structure includes a first layer structure and a second layer structure vertically overlying the first layer structure. The microelectronic device further includes: a memory cell string extending vertically through the conductive stack structure; a stepped structure within the first layer structure and having steps including lateral ends of the layers; and a liner material on the steps of the stepped structure, the thickness of which decreases with increasing distance from the source structure.

[0097] Therefore, according to another embodiment of the present disclosure, a method of forming a microelectronic device includes: forming a stepped structure in a first layer structure; forming a liner material on the steps of the stepped structure; forming a second layer structure vertically covering an interlayer region of the first layer structure and vertically covering the interlayer region; forming an additional stepped structure and an opening in the second layer structure vertically above and within the horizontal boundary of the stepped structure of the first layer structure; forming an additional liner material on the additional steps of the additional stepped structure and within the opening in the second layer structure; removing a portion of the additional liner material at the lower vertical boundary of the opening; and forming a conductive contact structure contacting the steps of the stepped structure of the first layer structure and the additional steps of the additional stepped structure.

[0098] Therefore, according to yet another embodiment of this disclosure, a method of forming a microelectronic device includes: forming a first oxide liner material on the steps of a stepped structure in a first layer structure; forming a second layer structure on the first layer structure; forming a second oxide liner material on the steps of an additional stepped structure in the second layer structure and on an opening surface in the second layer structure that vertically covers the stepped structure of the first layer structure; forming a second nitride liner material on the second oxide liner material; and removing a laterally extended portion of the second nitride liner material within the opening of the second layer structure.

[0099] The microelectronic device includes a microelectronic device (e.g., microelectronic device 300) and a microelectronic device structure (e.g., microelectronic device structure 100, 200, 301) formed according to embodiments of the present disclosure. For example, Figure 4 This is a block diagram of an electronic system 403 according to an embodiment of the present disclosure. The electronic system 403 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet computer, such as (for example) or Tablet computers, e-books, navigation devices, etc. Electronic system 403 includes at least one memory device 405. Memory device 405 may include, for example, microelectronic device structures previously described herein (e.g., microelectronic device structures 100, 200, 300) or previously referenced... Figures 1A to 1G , Figures 2A to 2D and Figure 3 Embodiments of the described microelectronic device (e.g., microelectronic device 300).

[0100] Electronic system 403 may further include at least one electronic signal processor device 407 (generally referred to as a “microprocessor”). Electronic signal processor device 407 may optionally include embodiments of the microelectronic devices or microelectronic device structures previously described herein (e.g., previously referenced...). Figures 1A to 1G , Figures 2A to 2D and Figure 3 The described microelectronic device 300 or one or more of the microelectronic device structures 100, 200, 301. The electronic system 403 may further include one or more input devices 409 for a user to input information into the electronic system 403, such as (for example) a mouse or other pointing device, keyboard, touchpad, button, or control panel. The electronic system 403 may further include one or more output devices 411 for outputting information (e.g., visual or audio output) to the user, such as (for example) a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, the input device 409 and output device 411 may include a single touchscreen device for inputting information into the electronic system 403 while simultaneously outputting visual information to the user. The input device 409 and output device 411 may be in electrical communication with one or more of the memory device 405 and the electronic signal processor device 407.

[0101] refer to Figure 5 The present invention describes a processor-based system 500. The processor-based system 500 may include various microelectronic devices and microelectronic device structures manufactured according to embodiments of the present disclosure (e.g., microelectronic devices and microelectronic device structures including one or more of microelectronic device 300 or microelectronic device structures 100, 200, 301). The processor-based system 500 may be any of various types, such as a computer, pager, cellular phone, personal memo pad, control circuitry, or other electronic device. The processor-based system 500 may include one or more processors 502, such as microprocessors, for processing system functions and requests in the processor-based system 500. The processor 502 and other sub-components of the processor-based system 500 may include microelectronic devices and microelectronic device structures manufactured according to embodiments of the present disclosure (e.g., microelectronic devices and microelectronic device structures including one or more of microelectronic device 300 or microelectronic device structures 100, 200, 301).

[0102] The processor-based system 500 may include a power supply 504 operatively communicating with the processor 502. For example, if the processor-based system 500 is a portable system, the power supply 504 may include one or more of a fuel cell, a power harvesting device, a permanent battery, a replaceable battery, and a rechargeable battery. The power supply 504 may also include an AC adapter; thus, for example, the processor-based system 500 can be plugged into a wall outlet. The power supply 504 may also include a DC adapter, allowing the processor-based system 500 to be plugged into, for example, a vehicle cigarette lighter or a vehicle power port.

[0103] Various other devices may be coupled to processor 502 depending on the functions performed by processor-based system 500. For example, user interface 506 may be coupled to processor 502. User interface 506 may include input devices such as buttons, switches, keyboards, light pens, mice, digitizers and light pens, touch screens, voice recognition systems, microphones, or combinations thereof. Display 508 may also be coupled to processor 502. Display 508 may include LCD displays, SED displays, CRT displays, DLP displays, plasma displays, OLED displays, LED displays, 3D projections, audio displays, or combinations thereof. In addition, RF subsystem / baseband processor 510 may also be coupled to processor 502. RF subsystem / baseband processor 510 may include antennas coupled to RF receivers and RF transmitters (not shown). Communication port 512 or more may also be coupled to processor 502. The communication port 512 can be adapted to couple to one or more peripheral devices 514, such as a modem, printer, computer, scanner or camera, or to a network, such as (for example) a local area network, a remote local area network, an intranet or the Internet.

[0104] Processor 502 can control processor-based system 500 by implementing software programs stored in memory. The software programs may include, for example, operating systems, database software, graphics software, word processing software, media editing software, or media playback software. Memory is operatively coupled to processor 502 to store various programs and facilitate their execution. For example, processor 502 may be coupled to system memory 516, which may include one or more of spin torque-converting magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), race memory, and other known memory types. System memory 516 may include volatile memory, non-volatile memory, or combinations thereof. System memory 516 is typically large enough to dynamically store loaded applications and data. In some embodiments, system memory 516 may include semiconductor devices, such as the microelectronic devices and microelectronic device structures described above (e.g., microelectronic device 300 and microelectronic device structures 100, 200, 301), or combinations thereof.

[0105] Processor 502 may also be coupled to non-volatile memory 518, which does not imply that system memory 516 must be volatile. Non-volatile memory 518 may include one or more of STT-MRAM, MRAM, read-only memory (ROM) (e.g., EPROM, resistive read-only memory (RROM)), and flash memory used in conjunction with system memory 516. The size of non-volatile memory 518 is typically selected to be large enough to store any necessary operating system, applications, and fixed data. Additionally, non-volatile memory 518 may include high-capacity memory, such as disk drive memory, or, for example, a hybrid drive containing resistive memory or other types of non-volatile solid-state memory. Non-volatile memory 518 may include microelectronic devices, such as the microelectronic devices and microelectronic device architectures described above (e.g., microelectronic device 300 and microelectronic device architectures 100, 200, 301), or combinations thereof.

[0106] Therefore, according to embodiments of this disclosure, an electronic system includes: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device. The at least one electronic device includes: a first step structure within a first layer structure comprising alternating conductive and insulating structures; a second step structure within a second layer structure vertically covering the first layer structure; and a nitride liner material adjacent to the steps of the first step structure, wherein the region between the first layer structure and the second layer structure is free of the nitride liner material.

[0107] Additional non-limiting example embodiments of this disclosure include:

[0108] Example 1: A microelectronic device includes: a first layer structure comprising alternating conductive and insulating structures arranged in a hierarchy, each of the layers individually including one of the conductive structures and one of the insulating structures; a second layer structure vertically covering the first layer structure and including additional layers of the conductive and insulating structures; a stepped structure within the first layer structure and having steps including the edges of the layers; a dielectric material covering the steps of the stepped structure and extending through the first layer structure; and a liner material inserted between the steps of the stepped structure and the dielectric material and terminating in an interlayer region between the first and second layer structures.

[0109] Example 2: The microelectronic device according to Example 1, wherein the substrate material includes one or more of silicon nitride, oxynitride, carbon-doped silicon nitride, silicon carbonitride, carbon-doped silicon oxynitride, polycrystalline silicon, aluminum oxide, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, cerium oxide, titanium nitride, tantalum nitride, and tungsten nitride.

[0110] Example 3: The microelectronic device according to Example 1, wherein the substrate material comprises silicon nitride.

[0111] Example 4: A microelectronic device according to any one of Examples 1 to 3, further comprising an additional liner material between the liner material and the steps of the stepped structure.

[0112] Example 5: The microelectronic device according to Example 4, wherein the additional substrate material comprises silicon dioxide.

[0113] Example 6: A microelectronic device according to Example 4 or Example 5, wherein the additional liner material extends from the step of the stepped structure to the upper part of the second layer structure.

[0114] Example 7: A microelectronic device according to any one of Examples 4 to 6, wherein the additional liner material terminates at the interlayer region.

[0115] Example 8: A microelectronic device according to any one of Examples 1 to 7, further comprising a conductive contact structure extending through the dielectric material and contacting the steps of the stepped structure.

[0116] Example 9: The microelectronic device according to any one of Examples 1 to 8 further includes an additional stepped structure within the second layer structure.

[0117] Example 10: The microelectronic device according to Example 9 further includes an additional liner material, the additional liner material comprising a nitride material covering additional steps of the additional stepped structure.

[0118] Example 11: A microelectronic device according to any one of Examples 1 to 10, wherein the liner material extends substantially vertically from one of the steps of the stepped structure to the interlayer region.

[0119] Example 12: A microelectronic device comprising: a conductive stack structure vertically overlying a source structure and including alternating conductive and insulating structures arranged in a hierarchy, the conductive stack structure comprising: a first layer structure; and a second layer structure vertically overlying the first layer structure; a stepped structure within the first layer structure and having steps including lateral ends of the steps; and a liner material on the steps of the stepped structure, the thickness of the liner material decreasing with increasing distance from the source structure.

[0120] Example 13: The microelectronic device according to Example 12, wherein the substrate material comprises silicon nitride.

[0121] Example 14: The microelectronic device according to Example 12 or Example 13, wherein the liner material terminates in the interlayer region between the first layer structure and the second layer structure.

[0122] Example 15: A microelectronic device according to any one of Examples 12 to 14, wherein the liner material extends over the steps of the stepped structure and the vertically extending sidewalls of the second layer structure defining the openings in the second layer structure.

[0123] Example 16: A microelectronic device according to any one of Examples 12 to 15, further comprising an additional stepped structure within the second layer structure.

[0124] Example 17: A method of forming a microelectronic device, the method comprising: forming a stepped structure in a first layer structure; forming a liner material on the steps of the stepped structure; forming a second layer structure vertically covering an interlayer region of the first layer structure and vertically covering the interlayer region; forming an additional stepped structure and an opening in the second layer structure vertically above and within the horizontal boundary of the stepped structure of the first layer structure; forming an additional liner material on the additional steps of the additional stepped structure and within the opening in the second layer structure; removing a portion of the additional liner material at the lower vertical boundary of the opening; and forming a conductive contact structure contacting the steps of the stepped structure of the first layer structure and the additional steps of the additional stepped structure.

[0125] Example 18: The method according to Example 17, wherein forming the additional liner material includes forming the additional liner material comprising substantially the same material composition as the liner material.

[0126] Example 19: The method according to Example 17 or Example 18 further includes removing at least a portion of the vertically extending portion of the additional lining material extending through the opening.

[0127] Example 20: The method according to any of Examples 17 to 19 further includes removing a portion of the interlayer region within the horizontal boundary of the opening after removing the lateral extension of the additional liner material.

[0128] Example 21: The method according to any of Examples 17 to 20, wherein forming the additional liner material includes forming the additional liner material comprising silicon nitride.

[0129] Example 22: The method according to any of Examples 17 to 21 further includes forming a mask material on the additional stepped structure before removing the lateral extension of the additional liner material from the opening.

[0130] Example 23: The method according to any of Examples 17 to 22, wherein forming the additional liner material includes forming the additional liner material that is vertically offset from the liner material.

[0131] Example 24: The method according to any of Examples 17 to 23 further includes removing the portion of the interlayer region above the stepped structure of the first layer structure and within its horizontal boundary before forming the additional liner material.

[0132] Example 25: A method of forming a microelectronic device, the method comprising: forming a first oxide liner material on a step of a stepped structure in a first layer structure; forming a second layer structure on the first layer structure; forming a second oxide liner material on a step of an additional stepped structure in the second layer structure and on an opening surface within the second layer structure that vertically overlies the stepped structure of the first layer structure; forming a second nitride liner material on the second oxide liner material; and removing a laterally extended portion of the second nitride liner material within the opening of the second layer structure.

[0133] Example 26: According to the method of Example 25, removing the lateral extension of the second nitride liner material within the opening of the second layer structure includes a region that exposes the interlayer region between the first layer structure and the second layer structure.

[0134] Example 27: The method according to Example 25 or Example 26, wherein removing the lateral extension of the second nitride liner material within the opening of the second layer structure includes exposing the portion of the dielectric material within the stepped structure of the first layer structure.

[0135] Example 28: The method according to any of Examples 25 to 27 further includes forming a dielectric material on a portion of the first nitride liner material within an additional opening defined by the stepped structure of the first layer structure prior to forming the second layer structure.

[0136] Example 29: The method according to any of Examples 25 to 28, wherein forming the second nitride liner material includes forming a second nitride liner material comprising one or more of the following: silicon nitride, oxynitride, carbon-doped silicon nitride, silicon carbonitride, carbon-doped silicon oxynitride, polycrystalline silicon, aluminum oxide, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, cerium oxide, titanium nitride, tantalum nitride, and tungsten nitride.

[0137] Example 30: The method according to any one of Examples 25 to 29 further includes forming a dielectric material within the opening after removing the laterally extended portion of the second nitride liner material.

[0138] Example 31: An electronic system comprising: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device, the at least one electronic device comprising: a first step structure within a first layer structure comprising alternating conductive and insulating structures; a second step structure within a second layer structure vertically overlying the first layer structure; and a nitride liner material adjacent to the step of the first step structure, wherein the region between the first layer structure and the second layer structure is free of the nitride liner material.

[0139] Example 32: The electronic system according to Example 31 further includes a dielectric material extending through the second layer structure and overlying the nitride liner material.

[0140] Example 33: The electronic system according to Example 32, wherein the nitride liner material is between the level of the second layer structure and the dielectric material, and the thickness of the nitride liner adjacent to the level of the second layer structure is greater than the thickness of the vertically extending sidewall along the opening in the second layer structure.

[0141] Example 34: An electronic system according to any one of Examples 31 to 33, wherein the nitride liner material has a range from approximately To date The thickness inside.

[0142] While certain illustrative embodiments have been described with reference to the drawings, those skilled in the art will recognize that the embodiments covered by this disclosure are not limited to those explicitly shown and described herein. Indeed, many additions, deletions, and modifications can be made to the embodiments described herein without departing from the scope of the embodiments covered by this disclosure, such as those additions, deletions, and modifications claimed below, including legal equivalents. Furthermore, features from one embodiment of the disclosure may be combined with features from another embodiment of the disclosure while still being covered within the scope of this disclosure.

Claims

1. A microelectronic device comprising: The first layer structure includes alternating conductive and insulating structures arranged in a hierarchy, each of the hierarchy individually including one of the conductive structures and one of the insulating structures. The second layer structure is vertically overlaid on the first layer structure and includes an additional layer of the conductive structure and the insulating structure. A stepped structure, which is within the first layer structure and has steps including the edges of the layer; A dielectric material that covers the steps of the stepped structure and extends through the first layer structure; A liner material, inserted between the steps of the stepped structure and the dielectric material, and terminating in the interlayer region between the first and second layer structures; and Additional lining material between the lining material and the steps of the stepped structure.

2. The microelectronic device according to claim 1, wherein the substrate material comprises one or more of silicon nitride, oxynitride, carbon-doped silicon nitride, silicon carbonitride, carbon-doped silicon oxynitride, polycrystalline silicon, aluminum oxide, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, cerium oxide, titanium nitride, tantalum nitride, and tungsten nitride.

3. The microelectronic device of claim 1, wherein the substrate material comprises silicon nitride.

4. The microelectronic device of claim 1, wherein the additional substrate material comprises silicon dioxide.

5. The microelectronic device of claim 1, wherein the additional liner material extends from the step of the stepped structure to the upper part of the second layer structure.

6. The microelectronic device of claim 1, wherein the additional liner material terminates at the interlayer region.

7. The microelectronic device of claim 1, further comprising a conductive contact structure extending through the dielectric material and contacting the steps of the stepped structure.

8. The microelectronic device according to any one of claims 1 to 7, further comprising an additional stepped structure within the second layer structure.

9. The microelectronic device of claim 8, further comprising an additional liner material, said additional liner material comprising a nitride material covering additional steps of said additional stepped structure.

10. The microelectronic device according to any one of claims 1 to 7, wherein the liner material extends substantially vertically from one of the steps of the stepped structure to the interlayer region.

11. A microelectronic device comprising: A conductive stacked structure, vertically superimposed on a source structure, includes alternating conductive and insulating structures arranged in layers, the conductive stacked structure comprising: First-level structure; and The second layer structure is vertically overlaid on the first layer structure; A string of memory cells extends vertically through the conductive stacked structure; A stepped structure, which is within the first layer structure and has steps including the lateral ends of the layers; The thickness of the liner material on the steps of the stepped structure decreases as the distance from the source structure increases; and Additional lining material between the lining material and the steps of the stepped structure.

12. The microelectronic device of claim 11, wherein the substrate material comprises silicon nitride.

13. The microelectronic device of claim 11, wherein the liner material terminates in the interlayer region between the first layer structure and the second layer structure.

14. The microelectronic device of claim 11, wherein the liner material extends over the steps of the stepped structure and the vertically extending sidewalls of the second layer structure defining the openings in the second layer structure.

15. The microelectronic device according to any one of claims 11 to 14, further comprising an additional stepped structure within the second layer structure.

16. A method of forming a microelectronic device, the method comprising: A stepped structure is formed in the first-level structure; A lining material is formed on the steps of the stepped structure; A second layer structure is formed that vertically covers the interlayer region of the first layer structure and vertically covers the interlayer region; An additional stepped structure and opening are formed in the second layer structure above the vertically above the stepped structure of the first layer structure and within its horizontal boundary; Remove the portion of the interlayer region above the stepped structure of the first layer structure and within its horizontal boundary; After removing the portion of the interlayer region, additional lining material is formed on the additional steps of the additional stepped structure and within the openings in the second layer structure. Remove a portion of the additional lining material at the lower vertical boundary of the opening; and A conductive contact structure is formed for the steps of the stepped structure that contact the first layer structure and the additional steps of the additional stepped structure.

17. The method of claim 16, wherein forming the additional liner material comprises forming the additional liner material comprising substantially the same material composition as the liner material.

18. The method of claim 16, further comprising removing at least a portion of a vertically extending portion of the additional lining material extending through the opening.

19. The method of claim 16, further comprising removing a portion of the interlayer region within the horizontal boundary of the opening after removing the lateral extension of the additional liner material.

20. The method of claim 16, wherein forming the additional liner material comprises forming the additional liner material comprising silicon nitride.

21. The method of claim 16, further comprising forming a mask material on the additional stepped structure before removing the lateral extension of the additional liner material from the opening.

22. The method according to any one of claims 16 to 21, wherein forming the additional liner material comprises forming the additional liner material that is vertically offset from the liner material.

23. A method of forming a microelectronic device, the method comprising: A first oxide liner material is formed on the steps of the stepped structure in the first layer structure; A first nitride liner material is formed on top of the first oxide liner material; A second-level structure is formed on top of the first-level structure; A second oxide liner material is formed on the steps of the additional step structure in the second layer structure and on the opening surface of the second layer structure that is vertically overlaid on the step structure of the first layer structure. A second nitride liner material is formed on top of the second oxide liner material; and Remove the lateral extension of the second nitride liner material within the opening of the second layer structure.

24. The method of claim 23, wherein removing the lateral extension of the second nitride liner material within the opening of the second layer structure includes a region that exposes the interlayer region between the first layer structure and the second layer structure.

25. The method of claim 23, wherein removing the lateral extension of the second nitride liner material within the opening of the second layer structure includes exposing a portion of the dielectric material within the stepped structure of the first layer structure.

26. The method of claim 23, further comprising forming a dielectric material on a portion of the first nitride liner material within an additional opening defined by the stepped structure of the first layered structure prior to forming the second layered structure.

27. The method according to any one of claims 23 to 26, wherein forming the second nitride liner material comprises forming a second nitride liner material comprising one or more of the following: silicon nitride, oxynitride, carbon-doped silicon nitride, silicon carbonitride, carbon-doped silicon oxynitride, polycrystalline silicon, aluminum oxide, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, cerium oxide, titanium nitride, tantalum nitride, and tungsten nitride.

28. The method according to any one of claims 23 to 26, further comprising forming a dielectric material within the opening after removing the laterally extended portion of the second nitride liner material.

29. An electronic system comprising: Input device; Output device; A processor device operatively coupled to the input device and the output device; and A memory device operatively coupled to the processor device and including at least one microelectronic device, the at least one microelectronic device comprising: The first step structure is within a first layer structure comprising alternating conductive and insulating structures. A second-layer structure, which vertically overlies the first-layer structure; and A nitride liner material is provided adjacent to the steps of the first stepped structure, and the region between the first layer structure and the second layer structure does not contain the nitride liner material.

30. The electronic system of claim 29, further comprising a dielectric material extending through the second layer structure and overlying the nitride liner material.

31. The electronic system of claim 30, wherein the nitride liner material is located between the level of the second layer structure and the dielectric material, and the thickness of the nitride liner adjacent to the level of the second layer structure is greater than the thickness of the vertically extending sidewall along the opening within the second layer structure.

32. The electronic system according to any one of claims 29 to 31, wherein the nitride liner material has a thickness ranging from 200 Å to 1,000 Å.

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