Three-dimensional memory and methods of making the same, electronic devices

Abstract

The three-dimensional memory provided in the application is provided with an electric connection layer on one side of a substrate, a first sub-step structure and a second sub-step structure are respectively arranged on two sides of the electric connection layer, and the size of the first sub-step structure and the second sub-step structure on the side close to the electric connection layer is greater than the size on the side away from the electric connection layer, which greatly reduces the size of the three-dimensional memory; since the first channel structure and the second channel structure are conducted through the electric connection layer, the second channel structure and the first channel structure do not need to be aligned, the problems such as circuit short circuit, quality hidden danger and yield loss caused by alignment and coverage are avoided, meanwhile, the preparation step of alignment is reduced, the preparation difficulty of the three-dimensional memory is reduced, the quality and yield of the three-dimensional memory are improved, and a preparation method of the three-dimensional memory and an electronic equipment are provided.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, specifically relating to three-dimensional memory and its fabrication method, and electronic devices. Background Technology

[0002] Due to their low power consumption, light weight, and high-performance non-volatile memory, 3D memory is increasingly widely used in electronic products. However, users' expectations and requirements for 3D memory are also rising. As the number of memory structure layers, storage density, and interconnect density continue to increase, precise alignment and overlay control between the various structures in the fabricated memory structure become increasingly difficult. The resulting short circuits, quality issues, and yield losses caused by these alignment and overlay problems remain unresolved. Summary of the Invention

[0003] In view of this, the first aspect of this application provides a three-dimensional memory, comprising:

[0004] Substrate;

[0005] An electrical connection layer is disposed on one side of the substrate;

[0006] The stepped structure includes a first sub-step structure and a second sub-step structure, the first sub-step structure and the second sub-step structure are respectively disposed on both sides of the electrical connection layer, and the first sub-step structure is connected to the substrate. The size of the first sub-step structure and the second sub-step structure on the side closer to the electrical connection layer is larger than the size on the side away from the electrical connection layer.

[0007] A first channel structure extends through the first sub-step structure, with one end of the first channel structure connected to the electrical connection layer and the other end connected to the substrate.

[0008] The second channel structure extends through the second sub-step structure and connects to the electrical connection layer.

[0009] The first aspect of this application provides a three-dimensional memory, in which an electrical connection layer is disposed on one side of a substrate, a first sub-step structure is connected to the substrate, and a first sub-step structure and a second sub-step structure are respectively disposed on both sides of the electrical connection layer. The dimensions of the first and second sub-step structures on the side closer to the electrical connection layer are larger than the dimensions on the side away from the electrical connection layer, significantly reducing the size of the three-dimensional memory. Since a first channel structure penetrates the first sub-step structure and connects to the electrical connection layer and the substrate at both ends, and a second channel structure penetrates the second sub-step structure and connects to the electrical connection layer, the first and second channel structures are electrically connected through the electrical connection layer. This eliminates the need for alignment between the second and first channel structures, avoiding problems such as short circuits, quality issues, and yield losses caused by alignment and overlay. It also reduces the alignment preparation steps, greatly reducing the fabrication difficulty of the three-dimensional memory and improving its quality and yield.

[0010] A second aspect of this application provides an electronic device including a processor and the three-dimensional memory as provided in the first aspect of this application, the processor being configured to write data to and read data from the three-dimensional memory.

[0011] The electronic device provided in the second aspect of this application, by employing a processor and a three-dimensional memory as provided in the first aspect of this application, greatly reduces the size of the three-dimensional memory, avoids problems such as short circuits, quality risks and yield losses caused by alignment and overlay, and also reduces the alignment preparation steps, greatly reducing the difficulty of three-dimensional memory preparation and improving the quality and yield of three-dimensional memory.

[0012] A third aspect of this application provides a method for fabricating a three-dimensional memory, comprising:

[0013] Provide a base;

[0014] A laminated structure is formed on the substrate, and a first channel structure is formed through the laminated structure;

[0015] An electrical connection layer is formed on the stacked structure; wherein the extension direction of the electrical connection layer is the same as the extension direction of the substrate, one end of the first channel structure is connected to the electrical connection layer, and the other end is connected to the substrate;

[0016] A second sub-step structure is formed on the side of the electrical connection layer opposite to the stacked structure;

[0017] A second channel structure is formed that penetrates the second sub-step structure, and the second channel structure is connected to the electrical connection layer;

[0018] Remove the substrate;

[0019] The edges of the stacked structure are etched to form a first sub-step structure; wherein the dimensions of the first sub-step structure and the second sub-step structure on the side closer to the electrical connection layer are larger than the dimensions on the side away from the electrical connection layer.

[0020] The method for fabricating a three-dimensional memory provided in the third aspect of this application greatly reduces the size of the three-dimensional memory by forming a first sub-step structure and a second sub-step structure on both sides of the electrical connection layer. The first channel structure penetrates the first sub-step structure and connects the electrical connection layer and the substrate at both ends. The second channel structure penetrates the second sub-step structure and connects the electrical connection layer, so that the first channel structure and the second channel structure are connected through the electrical connection layer. During the fabrication of the second channel structure and the first channel structure, there is no need to consider the alignment problem between the two, avoiding problems such as short circuits, quality risks and yield losses caused by alignment and coverage. At the same time, it also reduces the alignment fabrication steps, greatly reduces the fabrication difficulty of the three-dimensional memory, and improves the quality and yield of the three-dimensional memory. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the embodiments of this application will be described below.

[0022] Figure 1 This is a schematic diagram of the structure of a three-dimensional memory in one embodiment of this application.

[0023] Figure 2 This is a schematic diagram of the structure of a three-dimensional memory in another embodiment of this application.

[0024] Figure 3 This is a schematic diagram of the structure of a three-dimensional memory in another embodiment of this application.

[0025] Figure 4 This is a schematic diagram of the structure of a three-dimensional memory in another embodiment of this application.

[0026] Figure 5 This is a schematic diagram of the structure of a three-dimensional memory in another embodiment of this application.

[0027] Figure 6 This is a partial structural diagram of a three-dimensional memory according to one embodiment of this application.

[0028] Figure 7 This is a process flow diagram of the fabrication method of a three-dimensional memory according to one embodiment of this application.

[0029] Figure 8 This is a process flow diagram of a method for fabricating a three-dimensional memory in another embodiment of this application.

[0030] Figure 9This is a process flow diagram of a method for fabricating a three-dimensional memory in another embodiment of this application.

[0031] Figure 10 This is a process flow diagram of a method for fabricating a three-dimensional memory in another embodiment of this application.

[0032] Label Explanation:

[0033] Three-dimensional memory-1, substrate-10, stepped structure-20, first sub-stepped structure-21, first stepped region-A, first memory region-B, second sub-stepped structure-22, second stepped region-C, second memory region-D, stacked pair-23, insulating layer-231, gate layer-232, electrical connection layer-30, first channel structure-40, first sub-channel structure-41, channel layer-411, memory layer-412, second sub-channel structure-42, second channel structure-50, first gate gap structure-60, second gate gap structure-70, first planarization layer-80, first capping layer-81, first interlayer dielectric layer-82, first contact-83, first connector-84, first plug-85, second planarization layer-90, second capping layer-91, second interlayer dielectric layer-92, second contact-93, second connector-94, second plug-95. Detailed Implementation

[0034] The following are preferred embodiments of this application. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principles of this application, and these improvements and modifications are also considered to be within the scope of protection of this application.

[0035] Before introducing the technical solution of this application, let's go over the background issues in the relevant technologies in detail.

[0036] Due to their low power consumption, light weight, and high-performance non-volatile memory, 3D memory is being used more and more widely in electronic products. However, users' expectations and requirements for 3D memory are also increasing.

[0037] Specifically, to improve the storage and interconnect density of 3D NAND flash memory, the number of stacked layers is increasing (e.g., dual decks), and the film thickness is correspondingly multiplying. Simultaneously, channel holes are being etched twice instead of once. Current memory structure fabrication processes mainly include: Lower Layer Step (LSS) - Lower Layer Channel (LCH) - Upper Layer Step (USS) - Upper Layer Channel (UCH) - Gate Structure (GL) - Lower Layer Step Contact (LCT) - Upper Layer Step Contact (UCT). However, during the fabrication of the upper layer channel, the alignment difficulty between the two channels increases with the continuous increase in the number of layers in the 3D NAND flash memory structure. This increasing alignment difficulty leads to a series of problems such as short circuits, quality issues, and yield losses. Furthermore, the continuous increase in the number of layers in the 3D NAND flash memory structure also results in a continuous increase in its size.

[0038] Therefore, it is necessary to provide a three-dimensional memory 1 that solves this problem, as well as its fabrication method and electronic device. Please refer to the following: Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the structure of a three-dimensional memory according to one embodiment of this application. Figure 2 This is a schematic diagram of the structure of a three-dimensional memory according to another embodiment of this application. The three-dimensional memory 1 provided in this embodiment includes a substrate 10. An electrical connection layer 30 is disposed on one side of the substrate 10. A step structure 20 includes a first sub-step structure 21 and a second sub-step structure 22, which are respectively disposed on both sides of the electrical connection layer 30. The first sub-step structure 21 is connected to the substrate 10, and the dimensions of the first sub-step structure 21 and the second sub-step structure 22 on the side closer to the electrical connection layer 30 are larger than the dimensions on the side away from the electrical connection layer 30. A first channel structure 40 penetrates the first sub-step structure 21, with one end of the first channel structure 40 connected to the electrical connection layer 30 and the other end connected to the substrate 10. A second channel structure 50 penetrates the second sub-step structure 22 and is connected to the electrical connection layer 30.

[0039] The substrate 10 provided in this embodiment may include a silicon oxide substrate 10, a silicon substrate 10, a germanium substrate 10, a silicon-germanium substrate 10, a silicon-on-insulator (SOI) substrate 10, or a germanium-on-insulator (GOI) substrate 10, etc. Optionally, the substrate 10 may also be a p-type doped substrate 10 or an n-type doped substrate 10. Suitable materials can be selected as the substrate 10 according to actual needs, and this application does not impose specific limitations in this regard. Of course, in other embodiments, the material of the substrate 10 may also be a semiconductor or compound including other elements. For example, the substrate 10 may be a gallium arsenide (GaAs) substrate 10, an indium phosphide (InP) substrate 10, or a silicon carbide (SiC) substrate 10, etc. Further optionally, the substrate 10 may be a single-layer structure, or the substrate 10 may be a layer structure formed by stacking or connecting multiple layers; this is not strictly limited here.

[0040] Optionally, defining the substrate 10 here does not necessarily mean that the substrate 10 is the original substrate during the fabrication process. Preferably, the substrate 10 is a substrate formed after processing the original substrate.

[0041] The electrical connection layer 30 provided in this embodiment can play the role of electrical connection and interconnection. When the first channel structure 40 and the second channel structure 50 are simultaneously electrically connected to the electrical connection layer 30, the first channel structure 40 and the second channel structure 50 can be connected.

[0042] Optionally, the material of the electrical connection layer 30 may include, but is not limited to, polycrystalline silicon, monocrystalline silicon, etc.

[0043] The stepped structure 20 provided in this embodiment includes a first sub-step structure 21 and a second sub-step structure 22. Specifically, the fact that the dimensions of the first sub-step structure 21 and the second sub-step structure 22 on the side closer to the electrical connection layer 30 are greater than the dimensions on the side away from the electrical connection layer 30 can be understood as the first sub-step structure 21 on the side closer to the electrical connection layer 30 being greater than the dimension on the side away from the electrical connection layer 30, and the second sub-step structure 22 on the side closer to the electrical connection layer 30 also being greater than the dimension on the side away from the electrical connection layer 30.

[0044] Optionally, both the first sub-step structure 21 and the second sub-step structure 22 include one or more stacked pairs 23. The stacked pair 23 can be understood as the step included in the first sub-step structure 21 and the second sub-step structure 22. The above-mentioned dimensions refer to the dimensions of the step or stacked pair 23 included in the first sub-step structure 21 and the second sub-step structure 22, or the length of the step or stacked pair 23 along the extension direction of the electrical connection layer 30.

[0045] The first channel structure 40 and the second channel structure 50 provided in this embodiment have the same structure, but are positioned differently. The first channel structure 40 penetrates the first sub-step structure 21 and connects the electrical connection layer 30 and the substrate 10 at both ends. The second channel structure 50 penetrates the second sub-step structure 22, meaning that the first channel structure 40 is closer to the substrate 10 than the second channel structure 50. Additionally, in some embodiments, the end of the second channel structure 50 facing away from the electrical connection layer 30 is exposed from the side of the step structure 20 away from the substrate 10 to facilitate connection with subsequent connectors.

[0046] Optionally, since the first channel structure 40 and the second channel structure 50 only need to be electrically connected to the electrical connection layer 30 to achieve conduction between them, it is not necessary to prepare the first channel structure 40 and the second channel structure 50. This reduces the preparation steps for alignment while ensuring a stable electrical connection between them, avoiding problems such as short circuits, quality risks, and yield losses caused by alignment difficulties.

[0047] Based on this, since the first channel structure 40 and the second channel structure 50 are respectively located on both sides of the electrical connection layer 30, the lengths of the first channel structure 40 and the second channel structure 50 are significantly shortened compared to the integrated channel structure. The lengths of the internal layers are also correspondingly shortened, which is beneficial to improving the electrical performance of the three-dimensional memory. Furthermore, the shortened lengths of the first channel structure 40 and the second channel structure 50 also reduce the difficulty of etching the channel holes of the first sub-step structure 21 and the second sub-step structure 22, which is beneficial to improving the fabrication efficiency of the three-dimensional memory 1.

[0048] Optionally, the structures of the first channel structure 40 and the second channel structure 50 may also be different, as long as the electrical connection between the two and the electrical connection layer 30 is ensured, and no strict limitation is imposed here.

[0049] Optionally, the electrical connection between the first channel structure 40 and the second channel structure 50 and the electrical connection layer 30 can be a direct structural connection or an indirect connection through other structural connections. The above connection method requires that the three are electrically connected, but the structure is not strictly limited.

[0050] Therefore, the three-dimensional memory 1 provided in this application has an electrical connection layer 30 disposed on one side of a substrate 10, a first sub-step structure 21 connected to the substrate 10, and a first sub-step structure 21 and a second sub-step structure 22 respectively disposed on both sides of the electrical connection layer 30. The dimensions of the first sub-step structure 21 and the second sub-step structure 22 on the side closer to the electrical connection layer 30 are larger than the dimensions on the side away from the electrical connection layer 30, greatly reducing the size of the three-dimensional memory 1. Since the first channel structure 40 penetrates the first sub-step structure 21 and its two ends are connected to the electrical connection layer 30 and the substrate 10, and the second channel structure 50 penetrates the second sub-step structure 22 and is also connected to the electrical connection layer 30, the first channel structure 40 and the second channel structure 50 are connected through the electrical connection layer 30, eliminating the need to align the second channel structure 50 and the first channel structure 40. This avoids problems such as short circuits, quality risks, and yield losses caused by alignment and coverage, while also reducing the alignment preparation steps, greatly reducing the fabrication difficulty of the three-dimensional memory 1, and improving the quality and yield of the three-dimensional memory 1.

[0051] Based on this, since the first channel structure 40 in the first sub-step structure 21 and the second channel structure 50 in the second sub-step structure 22 are connected by the electrical connection layer 30, when forming the second sub-step structure 22, it is not strictly required that the second sub-step structure 22 precisely cover the first sub-step structure 21, which greatly reduces the difficulty of fabricating the step structure 22.

[0052] In one embodiment, both the first sub-step structure 21 and the second sub-step structure 22 include a plurality of stacked pairs 23, the length of which decreases sequentially from near the electrical connection layer 30 to away from the electrical connection layer 30. Optionally, each stacked pair 23 may include an insulating layer 231 and a gate layer 232, with the insulating layer 231 on the side closest to the substrate 10, and the gate layer 232 closest to the substrate 10 serving as a bottom selection gate to control the three-dimensional memory 1. Of course, in other embodiments, the layer closest to the substrate 10 may also be the gate layer 232, with the substrate 10 acting as the insulating layer 231.

[0053] Optionally, each stack pair 23 may also include an insulating layer 231 and a replacement layer. The insulating layer 231 may be made of an oxide, such as silicon oxide. The replacement layer may be made of a nitride, such as silicon nitride. Optionally, the replacement layer may be made of another material with a high selectivity to the insulating layer 231. The replacement layer may then be replaced with a metal (such as tungsten) to form a gate layer 232, ultimately transforming the intermediate stepped structure 20 into the final stacked structure.

[0054] Therefore, it is understandable that when the length of the stacked pair 23 along the extension direction of the electrical connection layer 30 decreases sequentially from the direction close to the electrical connection layer 30 to the direction far away from the electrical connection layer 30, the dimensions of the first sub-step structure 21 and the second sub-step structure 22 on the side close to the electrical connection layer 30 will be larger than the dimensions on the side away from the electrical connection layer 30.

[0055] Preferably, from the direction closest to the electrical connection layer 30 to the direction furthest from the electrical connection layer 30, the dimensions of the stacked pairs 23 of the first sub-step structure 21 and the second sub-step structure 22 decrease sequentially on only one side. More preferably, the dimensions of the stacked pairs 23 of the first step structure 20 and the second step structure 20 decrease sequentially on the same side.

[0056] In one embodiment, the first sub-step structure 21 and the second sub-step structure 22 have the same number of steps. It is understood that since the step structure 20 includes the first sub-step structure 21 and the second sub-step structure 22, and the electrical connection layer 30 is disposed between the first sub-step structure 21 and the second sub-step structure 22, when the first sub-step structure 21 and the second sub-step structure 22 have the same number of steps (i.e., the number of stacked pairs 23 is the same), the number of layers in the first sub-step structure 21 and the second sub-step structure 22 is also approximately the same. Therefore, the electrical properties of the upper and lower parts of the step structure 20 can be balanced. Furthermore, since both have the same number of steps, the etching lengths of the first channel structure 40 and the second channel structure 50 are also approximately equal, further ensuring the electrical performance of the three-dimensional memory 1 and reducing process errors caused by excessive etching lengths in the first channel structure 40 and the second channel structure 50, thereby improving the yield of the three-dimensional memory 1.

[0057] Please continue reading. Figure 2 In one embodiment, the orthographic projection of the first channel structure 40 on the electrical connection layer 30 and the orthographic projection of the second channel structure 50 on the electrical connection layer 30 are at least partially overlapped or spaced apart. Optionally, this embodiment can be understood as the connection positions of the first channel structure 40 and the second channel structure 50 on both sides of the electrical connection layer 30 may or may not overlap. In other words, due to the presence of the electrical connection layer 30, the orthographic projections of the first channel structure 40 and the second channel structure 50 on the electrical connection layer 30 can at least partially overlap or spaced apart, eliminating the need to align the second channel structure 50 and the first channel structure 40. This avoids problems such as short circuits, quality risks, and yield losses caused by alignment and overlap, while also reducing the alignment preparation steps, greatly reducing the fabrication difficulty of the three-dimensional memory 1, and improving the quality and yield of the three-dimensional memory 1.

[0058] Of course, in other embodiments, the orthographic projection of the first channel structure 40 on the substrate 10 and the orthographic projection of the second channel structure 50 on the substrate 10 may completely overlap, and this is not strictly limited.

[0059] In one embodiment, the opening size of the first channel structure 40 gradually increases from the direction away from the electrical connection layer 30 to the direction closer to the electrical connection layer 30, and the opening size of the second channel structure 50 gradually decreases from the direction away from the electrical connection layer 30 to the direction closer to the electrical connection layer 30. It is understood that since the channel holes containing the first channel structure 40 and the second channel structure 50 are formed by etching, to prevent excessive etching of the first channel structure 40 from damaging the substrate 10, or to prevent excessive etching of the second channel structure 50 from damaging the electrical connection layer 30, the amount of etching solvent can be controlled during the etching of the channel holes. This allows the opening size of the first channel structure 40 to gradually increase from the direction away from the electrical connection layer 30 to the direction closer to the electrical connection layer 30, and the opening size of the second channel structure 50 to gradually decrease from the direction away from the electrical connection layer 30 to the direction closer to the electrical connection layer 30, thereby ensuring the integrity of the electrical connection layer 30 and the substrate 10, and thus improving the electrical performance and electrical stability of the three-dimensional memory 1.

[0060] Optionally, the extension directions of the first channel structure 40 and the second channel structure 50 are perpendicular to the extension direction of the electrical connection layer 30. It is understood that when the extension directions of the first channel structure 40 and the second channel structure 50 are perpendicular to the extension direction of the electrical connection layer 30, the first channel structure 40 and the second channel structure 50 are in a straight shape, and this straight shape is beneficial to improving the electrical performance and electrical performance stability of the first channel structure 40 and the second channel structure 50.

[0061] Please continue reading. Figure 1 and Figure 2 In one embodiment, the electrical connection layer 30 protrudes from the step structure 20 in the horizontal direction. It can be understood that this embodiment can also be understood as the electrical connection layer 30 having a length in its extending direction greater than the length of the stacked pair 23 (step) of the first sub-step structure 21 and the second sub-step structure 22 closest to the electrical connection layer 30. Optionally, when the electrical connection layer 30 protrudes from the step structure 20 in the horizontal direction, in subsequent fabrication processes, contacts or connectors can be used to connect the protruding portion of the electrical connection layer 30 to bring the electrical connection layer 30 out.

[0062] Please refer to the following: Figure 2 and Figure 3 , Figure 3 This is a schematic diagram of the structure of a three-dimensional memory in another embodiment of this application. In one embodiment, the three-dimensional memory 1 further includes a first gate slit structure 60 and a second gate slit structure 70. The first gate slit structure 60 penetrates the first sub-step structure 21 and is connected to the electrical connection layer 30. The second gate slit structure 70 penetrates the second sub-step structure 22 and is connected to the electrical connection layer 30.

[0063] Specifically, in the fabrication process of the three-dimensional memory 1, the replacement layer needs to be replaced with the gate layer 232. Since the step structure 20 includes a first sub-step structure 21 and a second sub-step structure 22, and the first sub-step structure 21 and the second sub-step structure 22 are located on both sides of the electrical connection layer 30, a first gate gap structure 60 and a second gate gap structure 70 need to be respectively provided on both sides of the electrical connection layer 30. However, if the first gate gap structure 60 and the second gate gap structure 70 are etched on the same side, it is necessary to consider whether the electrical connection layer 30 will block the etching of the gate gap structure. Therefore, in this embodiment, by providing the first gate gap structure 60 and the second gate gap structure 70 on both sides of the electrical connection layer 30, and the electrical connection layer 30 in the middle can also act as a barrier layer during the etching of the first gate gap structure 60 and the second gate gap structure 70, it is beneficial for the subsequent replacement of the replacement layer of the three-dimensional memory 1, making full use of the step structure 20 unique to the three-dimensional memory 1 of this application, and reducing the fabrication difficulty of the three-dimensional memory 1.

[0064] Please refer to the following: Figure 4 , Figure 4 This is a schematic diagram of the structure of a three-dimensional memory according to another embodiment of the present application. In one embodiment, the three-dimensional memory 1 further includes a first planarization layer 80, a second planarization layer 90, a plurality of first contacts 83, a plurality of second contacts 93, a plurality of first connectors 84, and a plurality of second connectors 94; the first sub-step structure 21 includes a first step area A and a first storage area B, the second sub-step structure 22 includes a second step area C and a second storage area D, the first planarization layer 80 covers the first sub-step structure 21, the second planarization layer 90 covers the second sub-step structure 22, the plurality of first contacts 83 penetrate the first planarization layer 80 and connect to the first step area A, the plurality of second contacts 93 penetrate the second planarization layer 90 and connect to the second step area C, the first connectors 84 penetrate the first planarization layer 80 and connect to the first channel structure 40, and the second connectors 94 penetrate the second planarization layer 90 and connect to the second channel structure 50.

[0065] Optionally, since the first sub-step structure 21 and the second sub-step structure 22 in this embodiment are located on opposite sides of the electrical connection layer 30, it is impossible to use the conventional outgoing method to outgoing the first sub-step structure 21 and the second sub-step structure 22 on the same side. Therefore, this embodiment provides a first flattening layer 80 and a second flattening layer 90, respectively, and uses a first contact member 83 and a second contact member 93 to lead out the first sub-step structure 21 and the second sub-step structure 22, respectively, and uses a first connector 84 and a second connector 94 to lead out the first channel structure 40 and the second channel structure 50, respectively, so that the internal structure of the three-dimensional memory 1 is led out from both sides of the electrical connection layer 30 without interfering with each other. Furthermore, since the electrical connection layer 30 connects the first channel structure 40 and the second channel structure 50, the outgoing method from both sides also makes full use of the space of the three-dimensional memory 1, so that the size of the three-dimensional memory 1 can be further reduced.

[0066] Optionally, the materials of the first contact 83 and the second contact 93 include, but are not limited to, tungsten and tungsten compounds.

[0067] Optionally, the materials of the first connector 84 and the second connector 94 include, but are not limited to, tungsten and tungsten compounds.

[0068] Please refer to the following: Figure 5 , Figure 5 This is a schematic diagram of the structure of a three-dimensional memory according to another embodiment of this application. Optionally, the first planarization layer 80 includes a first cover layer 81 and a first interlayer dielectric layer 82, and the second planarization layer 90 includes a second cover layer 91 and a second interlayer dielectric layer 92. The materials of the first interlayer dielectric layer 82 and the second interlayer dielectric layer 92 include, but are not limited to, insulating materials, etc., to prevent short circuits between active or passive devices and the interconnections constituting the wiring structure.

[0069] In one embodiment, the first channel structure 40 and the first grid slot structure 60 are located in the first storage area B, the second channel structure 50 and the second grid slot structure 70 are located in the second storage area D, and one of the first connectors 84 is also connected to the first grid slot structure 60, and one of the second connectors 94 is also connected to the second grid slot structure 70.

[0070] In one embodiment, the three-dimensional memory 1 further includes a first plug 85 and a second plug 95. The first plug 85 is disposed on the side of the first channel structure 40 away from the electrical connection layer 30 and connected to the first connector 84. The second plug 95 is disposed on the side of the second channel structure 50 away from the electrical connection layer 30 and connected to the second connector 94. It is understood that the first plug 85 provided in this embodiment can provide the electrical performance and electrical performance stability of the first channel structure 40 and the first connector 84, and the second plug 95 can improve the electrical performance and electrical performance stability between the second channel structure 50 and the second connector 94.

[0071] Optionally, the first plug 85 and the second plug 95 are plugs made of conductive material; preferably, the first plug 85 and the second plug 95 are polycrystalline silicon plugs.

[0072] Please refer to the following: Figure 6 , Figure 6 This is a partial structural diagram of a three-dimensional memory according to one embodiment of this application. In one embodiment, the first channel structure 40 includes a first sub-channel structure 41 and a second sub-channel structure 42. The first sub-channel structure 41 is closer to the electrical connection layer 30 than the second sub-channel structure 42. The first sub-channel structure 41 is connected to the electrical connection layer 30, and the second sub-channel structure 42 protrudes from the substrate 10. The first sub-channel structure 41 includes a channel layer 411 and a memory layer 412 disposed around the periphery of the channel layer 411. The second sub-channel structure 42 includes the channel layer 411. It is understood that in this embodiment, the channel layer 411 of the first channel structure 40 protrudes from the side of the substrate 10 away from the step structure 20, and the channel layer 411 can serve as a back-side lead-out.

[0073] Optionally, the channel layer 411 may be made of materials including, but not limited to, amorphous, polycrystalline, or monocrystalline silicon, while the memory layer 412 may include a tunneling layer, a memory layer, and a barrier layer stacked sequentially along a direction away from the channel layer 411. Optionally, the tunneling layer and the barrier layer may be made of silicon oxide, while the memory layer may be made of silicon nitride.

[0074] Optionally, the three-dimensional memory 1 may also include a third plug connected to the channel layer 411 to improve the electrical performance and electrical performance stability of the channel layer 411.

[0075] This application also provides an electronic device, which includes a processor and a three-dimensional memory 1 as described in the above embodiments, wherein the processor is used to write data to and read data from the three-dimensional memory 1.

[0076] Specifically, the electronic device can be a computer, smartphone, smart TV, smart set-top box, smart router, digital camera, or other device with a storage device. The electronic device of this application typically also includes a processor, input / output devices, and a display device. The three-dimensional memory 11 provided in this application is fabricated into a flash memory or other storage device through processes such as packaging. The storage device is used to store files or data and is accessible to the processor. Specifically, the processor can write data to the storage device, i.e., the three-dimensional memory 11 provided in this application, and can also read data from the storage device, i.e., the three-dimensional memory 11 provided in this application. The input / output device is used to input instructions or output signals, and the display device visualizes the signals, realizing various functions of the electronic device. The electronic device provided in this application, by adopting the three-dimensional memory 1 provided in the above-described embodiments, greatly reduces the size of the three-dimensional memory 1, avoids problems such as short circuits, quality risks, and yield losses caused by alignment and overlay, and also reduces the alignment preparation steps, greatly reducing the fabrication difficulty of the three-dimensional memory 1 and improving the quality and yield of the three-dimensional memory 1.

[0077] Please refer to the following: Figure 7 , Figure 7 This is a process flow diagram of the fabrication method of a three-dimensional memory according to one embodiment of this application. This application also provides a method for fabricating a three-dimensional memory 1, which can be implemented based on the three-dimensional memory 1 and an electronic device as described in this embodiment, or it can be used independently. The method is as follows:

[0078] S100 provides the substrate;

[0079] The substrate provided in this embodiment is not the same structure as the substrate 10 described above. Specifically, the substrate serves to support other structures subsequently fabricated. The substrate may include, but is not limited to, silicon oxide substrates, silicon substrates, germanium substrates, silicon-germanium substrates, silicon-on-insulator (SOI) substrates, or germanium-on-insulator (GOI) substrates. Optionally, the substrate may also be a P-type doped substrate or an N-type doped substrate. Suitable materials can be selected as the substrate according to actual needs, and this application does not impose specific limitations on this. Of course, in other embodiments, the substrate material may also be a semiconductor or compound including other elements. For example, the substrate may be a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, or a silicon carbide (SiC) substrate. Further optionally, the substrate may be a single-layer structure, or it may be a layered structure formed by stacking or connecting multiple layers; this is not strictly limited.

[0080] S200, a laminated structure is formed on the substrate, and a first channel structure 40 is formed through the laminated structure;

[0081] The stacked structure provided in this embodiment includes one or more stacked pairs 23 for preparing the subsequently formed first sub-step structure 21. However, since the stacked structure is located on the substrate in this step, it cannot be directly etched. Therefore, the substrate needs to be removed before forming the first sub-step structure 21. Specifically, the formation steps of the first sub-step structure 21 will be described in detail later.

[0082] S300, an electrical connection layer 30 is formed on the stacked structure; wherein the extension direction of the electrical connection layer 30 is the same as the extension direction of the substrate, one end of the first channel structure 40 is connected to the electrical connection layer 30, and the other end is connected to the substrate;

[0083] In this embodiment, forming the electrical connection layer 30 on the laminated structure means forming the electrical connection layer 30 over the entire laminated structure, i.e., the electrical connection layer 30 covers the entire laminated structure. Of course, in other embodiments, the electrical connection layer 30 may only cover a portion of the laminated structure, and this is not strictly limited here.

[0084] S400, a second sub-step structure 22 is formed on the side of the electrical connection layer 30 away from the stacked structure;

[0085] In this embodiment, the second sub-step structure 22 is formed by forming a second stacked structure on the electrical connection layer 30, and etching the edges of the second stacked structure to form the second sub-step structure 22. In this case, the dimension of the second sub-step structure 22 near the electrical connection layer 30 is larger than the dimension away from the electrical connection layer 30.

[0086] S500, forming a second channel structure 50 that penetrates the second sub-step structure 22, the second channel structure 50 being connected to the electrical connection layer 30;

[0087] In this embodiment, the first channel structure 40 penetrates the stacked structure, and the second channel structure 50 penetrates the second sub-step structure 22, and both are connected to both sides of the electrical connection layer 30. Since the first channel structure 40 and the second channel structure 50 are already connected through the electrical connection layer 30, it is not necessary to deliberately align the second channel structure 50 with the first channel structure 40 when fabricating it. This avoids problems such as short circuits, quality risks, and yield losses caused by alignment and overlay. At the same time, it also reduces the alignment preparation steps, greatly reduces the fabrication difficulty of the three-dimensional memory 1, and improves the quality and yield of the three-dimensional memory 11.

[0088] Optionally, the opening size of the second channel structure 50 gradually decreases from the direction away from the electrical connection layer 30 to the direction closer to the electrical connection layer 30.

[0089] Alternatively, the electrical connection layer 30 can serve as an etch barrier layer for the second channel structure 50.

[0090] S600, Remove the substrate;

[0091] As described above, since the stacked structure is located on the substrate in this step, it cannot be directly etched. Therefore, the substrate needs to be removed before forming the first sub-step structure 21. During the fabrication of the three-dimensional memory 1, the three-dimensional memory 1 needs to be flipped over first, and the substrate at the bottom of the three-dimensional memory 1 needs to be removed by means of etching or thinning.

[0092] S700, the edges of the stacked structure are etched to form a first sub-step structure 21; wherein the dimensions of the first sub-step structure 21 and the second sub-step structure 22 on the side closer to the electrical connection layer 30 are greater than the dimensions on the side away from the electrical connection layer 30.

[0093] In this embodiment, since the second sub-step structure 22 and the first sub-step structure 21 are located on both sides of the electrical connection layer 30, the size of the three-dimensional memory 1 is greatly reduced compared with the traditional three-dimensional memory 1 structure.

[0094] Furthermore, in the fabrication method of the three-dimensional memory 1 provided in this embodiment, the first channel structure 40 penetrates the first sub-step structure 21 while its two ends are connected to the electrical connection layer 30 and the substrate 10, and the second channel structure 50 penetrates the second sub-step structure 22 while also being connected to the electrical connection layer 30, so that the first channel structure 40 and the second channel structure 50 are connected through the electrical connection layer 30. During the fabrication of the second channel structure 50 and the first channel structure 40, there is no need to consider the alignment problem between the two, avoiding problems such as short circuits, quality risks and yield losses caused by alignment and coverage. At the same time, it also reduces the alignment fabrication steps, greatly reducing the fabrication difficulty of the three-dimensional memory 1 and improving the quality and yield of the three-dimensional memory 1.

[0095] Please refer to the following: Figure 8 , Figure 8 This is a process flow diagram of a method for fabricating a three-dimensional memory according to another embodiment of this application. In one embodiment, after S500 "forming a second channel structure 50 penetrating the second sub-step structure 22, the second channel structure 50 connecting the electrical connection layer 30", S510 is further included. After S700 "etching the edge of the stacked structure to form a first sub-step structure 21; wherein the dimensions of the first sub-step structure 21 and the second sub-step structure 22 on the side closer to the electrical connection layer 30 are larger than the dimensions on the side away from the electrical connection layer 30", S710 is further included. The descriptions of S510 and S710 are as follows:

[0096] S510, forming a second grid structure 70 that penetrates the second sub-step structure 22;

[0097] S710, forming a first slit structure 60 that penetrates the first sub-step structure 21.

[0098] As described above, specifically, in the fabrication process of the three-dimensional memory 1, the replacement layer needs to be replaced with the gate layer 232. Since the first sub-step structure 21 and the second sub-step structure 22 are located on both sides of the electrical connection layer 30, the first gate gap structure 60 and the second gate gap structure 70 need to be respectively provided on both sides of the electrical connection layer 30. However, if the first gate gap structure 60 and the second gate gap structure 70 are etched on the same side, it is necessary to consider whether the electrical connection layer 30 will block the etching of the gate gap structure. Therefore, in this embodiment, by providing the first gate gap structure 60 and the second gate gap structure 70 on both sides of the electrical connection layer 30, and the electrical connection layer 30 in the middle can also act as a barrier layer during the etching of the first gate gap structure 60 and the second gate gap structure 70, it is beneficial for the subsequent replacement of the replacement layer of the three-dimensional memory 1, making full use of the step structure 20 unique to the three-dimensional memory 1 of this application, and reducing the fabrication difficulty of the three-dimensional memory 1.

[0099] Optionally, the opening size of the first slit structure 60 and the second slit structure 70 gradually increases from the direction away from the electrical connection layer 30 to the direction closer to the electrical connection layer 30.

[0100] Please refer to the following: Figure 9 , Figure 9 This is a process flow diagram of a method for fabricating a three-dimensional memory according to another embodiment of this application. In one embodiment, after S600 "removing the substrate", steps S610, S620, and S630 are further included.

[0101] S610, deposit substrate 10 on the first sub-step structure 21;

[0102] S620, at least a portion of the substrate 10 is removed to expose the first channel structure 40; wherein the first channel structure 40 includes a channel layer 411 and a memory layer 412 disposed around the channel layer 411.

[0103] S630, remove the exposed portion of the memory layer 412 to expose the channel layer 411.

[0104] In this embodiment, exposing the channel layer 411 is to bring out the first channel structure 40 and the second channel structure 50 from the back. Since the first channel structure 40 is connected to the substrate 10, at least a portion of the substrate 10 needs to be removed. First, a portion of the first channel structure 40 is exposed, and then the memory layer 412 of the first channel structure 40 is removed to expose the channel layer 411, thus achieving back-side exposure. Since the substrate 10 is made of silicon oxide, the structure on the substrate 10 can be protected to prevent damage during the removal of the memory layer 412 of the first channel structure 40, which could cause short circuits, leakage, or other problems.

[0105] Please refer to the following: Figure 10 , Figure 10 This is a process flow diagram of a method for fabricating a three-dimensional memory according to another embodiment of this application. In one embodiment, after S500 "forming a second channel structure 50 penetrating the second sub-step structure 22, the second channel structure 50 connecting the electrical connection layer 30", S520, S530, and S540 are further included. After S700 "etching the edge of the stacked structure to form a first sub-step structure 21; wherein the dimensions of the first sub-step structure 21 and the second sub-step structure 22 on the side closer to the electrical connection layer 30 are larger than the dimensions on the side away from the electrical connection layer 30", S720, S730, and S740 are further included. The descriptions of S520, S530, S540, S720, S730, and S740 are as follows:

[0106] S520, a second flat layer 90 is formed covering the second sub-step structure 22; wherein the second sub-step structure 22 has a second step area C and a second storage area D;

[0107] S530, forming a plurality of second contact holes and a plurality of second through holes penetrating the second planarization layer 90, wherein the second contact holes correspond to the second step region C and the second through holes correspond to the second channel structure 50;

[0108] S540, a conductive material is provided to form a second contact 93 in the second contact hole and a second connector 94 in the second through hole.

[0109] S720, a first flat layer 80 is formed covering the first sub-step structure 21; wherein the first sub-step structure 21 has a first step area A and a first storage area B;

[0110] S730, forming a plurality of first contact holes and a plurality of first through holes penetrating the first planarization layer 80, wherein the first contact holes correspond to the first step region A and the first through holes correspond to the first channel structure 40;

[0111] S740 provides a conductive material to form a first contact 83 in the first contact hole and a first connector 84 in the first through hole.

[0112] It is worth noting that, in one embodiment, steps S100, S200, etc., do not represent a fixed order of the fabrication method of the three-dimensional memory 11 provided in this application; S100, S200, etc., are merely labels representing the steps. S100 and S200 can be performed simultaneously or in separate steps, and are not strictly limited here.

[0113] It is understood that the features mentioned above in the specification, claims, and drawings can be arbitrarily combined with each other, as long as they are meaningful within the scope of this application. The advantages and features described for the three-dimensional memory 1 and the electronic device are applied in a corresponding manner to the method for preparing the three-dimensional memory 1, and vice versa, and will not be repeated here.

[0114] A complete implementation process of this application is as follows: providing a substrate; forming a laminated structure on the substrate, and forming a first channel structure 40 penetrating the laminated structure; forming an electrical connection layer 30 on the laminated structure; forming a second sub-step structure 22 on the side of the electrical connection layer 30 opposite to the laminated structure; forming a second channel structure 50 penetrating the second sub-step structure 22; forming a second grid structure 70 penetrating the second sub-step structure 22; forming a second planarization layer 90 covering the second sub-step structure 22; forming a plurality of second contact holes and a plurality of second through holes penetrating the second planarization layer 90; forming a second contact element 93 in the second contact holes; and so on. A second connector 94 is formed in the second through-hole; the three-dimensional memory 1 is flipped over and the substrate is removed; a substrate 10 is deposited on the first sub-step structure 21; at least part of the substrate 10 is removed to expose the channel layer 411 of the first channel structure 40; the edges of the stacked structure are etched to form the first sub-step structure 21; a first gate structure 60 is formed through the first sub-step structure 21; a first planarization layer 80 is formed covering the first sub-step structure 21; a plurality of first contact holes and a plurality of first through holes are formed through the first planarization layer 80; a first contact 83 is formed in the first contact hole and a first connector 84 is formed in the first through hole.

[0115] The above provides a detailed description of the embodiments provided in this application. This document elucidates and explains the principles and implementation methods of this application. The above description is only intended to help understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A three-dimensional memory, characterized in that, include: Substrate; An electrical connection layer is disposed on one side of the substrate; The stepped structure includes a first sub-step structure and a second sub-step structure, the first sub-step structure and the second sub-step structure are respectively disposed on both sides of the electrical connection layer, and the first sub-step structure is connected to the substrate. The size of the first sub-step structure and the second sub-step structure on the side closer to the electrical connection layer is larger than the size on the side away from the electrical connection layer. A first channel structure extends through the first sub-step structure, with one end of the first channel structure connected to the electrical connection layer and the other end connected to the substrate. The second channel structure penetrates the second sub-step structure and is connected to the electrical connection layer; The electrical connection layer protrudes from the stepped structure in the horizontal direction, such that the length of the electrical connection layer in its extension direction is greater than the lengths of the first sub-step structure and the second sub-step structure on the side closest to the electrical connection layer.

2. The three-dimensional memory as described in claim 1, characterized in that, Both the first sub-step structure and the second sub-step structure include multiple stacked pairs, the length of which decreases sequentially from the direction closest to the electrical connection layer to the direction furthest from the electrical connection layer.

3. The three-dimensional memory as described in claim 1, characterized in that, The orthographic projection of the first channel structure on the electrical connection layer and the orthographic projection of the second channel structure on the electrical connection layer at least partially overlap or are spaced apart.

4. The three-dimensional memory as described in claim 1, characterized in that, The opening size of the first channel structure gradually increases from the direction away from the electrical connection layer to the direction closer to the electrical connection layer, and the opening size of the second channel structure gradually decreases from the direction away from the electrical connection layer to the direction closer to the electrical connection layer.

5. The three-dimensional memory as described in claim 1, characterized in that, The three-dimensional memory further includes a first gate structure and a second gate structure. The first gate structure penetrates the first sub-step structure and is connected to the electrical connection layer. The second gate structure penetrates the second sub-step structure and is connected to the electrical connection layer.

6. The three-dimensional memory as described in claim 1, characterized in that, The three-dimensional memory further includes a first planarization layer, a second planarization layer, a plurality of first contacts, a plurality of second contacts, a plurality of first connectors, and a plurality of second connectors; the first sub-step structure includes a first step area and a first storage area, the second sub-step structure includes a second step area and a second storage area, the first planarization layer covers the first sub-step structure, the second planarization layer covers the second sub-step structure, the plurality of first contacts penetrate the first planarization layer and connect to the first step area, the plurality of second contacts penetrate the second planarization layer and connect to the second step area, the first connectors penetrate the first planarization layer and connect to the first channel structure, and the second connectors penetrate the second planarization layer and connect to the second channel structure.

7. The three-dimensional memory as described in claim 6, characterized in that, The three-dimensional memory further includes a first plug and a second plug. The first plug is disposed on the side of the first channel structure away from the electrical connection layer and is connected to the first connector. The second plug is disposed on the side of the second channel structure away from the electrical connection layer and is connected to the second connector.

8. The three-dimensional memory as described in claim 1, characterized in that, The first channel structure includes a first sub-channel structure and a second sub-channel structure. The first sub-channel structure is closer to the electrical connection layer than the second sub-channel structure. The first sub-channel structure is connected to the electrical connection layer, and the second sub-channel structure protrudes from the substrate. The first sub-channel structure includes a channel layer and a memory layer disposed around the periphery of the channel layer, and the second sub-channel structure includes the channel layer.

9. An electronic device, characterized in that, The electronic device includes a processor and a three-dimensional memory as described in any one of claims 1-8, the processor being configured to write data to and read data from the three-dimensional memory.

10. A method for fabricating a three-dimensional memory, characterized in that, include: Provide a base; A laminated structure is formed on the substrate, and a first channel structure is formed through the laminated structure; An electrical connection layer is formed on the stacked structure; wherein the extension direction of the electrical connection layer is the same as the extension direction of the substrate, one end of the first channel structure is connected to the electrical connection layer, and the other end is connected to the substrate; A second sub-step structure is formed on the side of the electrical connection layer opposite to the stacked structure; A second channel structure is formed that penetrates the second sub-step structure, and the second channel structure is connected to the electrical connection layer; Remove the substrate; The edges of the stacked structure are etched to form a first sub-step structure; wherein the dimensions of the first sub-step structure and the second sub-step structure on the side closer to the electrical connection layer are greater than the dimensions on the side away from the electrical connection layer, the step structure includes the first sub-step structure and the second sub-step structure, and the electrical connection layer protrudes from the step structure in the horizontal direction, such that the length of the electrical connection layer in its extension direction is greater than the length of the first sub-step structure and the second sub-step structure on the side closer to the electrical connection layer.

11. The method for fabricating a three-dimensional memory as described in claim 10, characterized in that, After "forming a second channel structure that penetrates the second sub-step structure, the second channel structure connecting the electrical connection layer", the method further includes: A second grid seam structure is formed that penetrates the second sub-step structure; Following "etching the edges of the stacked structure to form a first sub-step structure", the method further includes: A first grid structure is formed that runs through the first sub-step structure.

12. The method for fabricating a three-dimensional memory as described in claim 10, characterized in that, Following "etching the edges of the stacked structure to form a first sub-step structure", the method further includes: A substrate is deposited on the first sub-step structure; At least a portion of the substrate is removed to expose the first channel structure; wherein the first channel structure includes a channel layer and a memory layer disposed around the periphery of the channel layer; Remove the exposed portion of the memory layer to expose the channel layer.

13. The method for fabricating a three-dimensional memory as described in claim 10, characterized in that, After "forming a second channel structure that penetrates the second sub-step structure, the second channel structure connecting the electrical connection layer", the method further includes: A second flat layer is formed covering the second sub-step structure; wherein the second sub-step structure has a second step area and a second storage area; A plurality of second contact holes and a plurality of second through holes are formed penetrating the second planarization layer, wherein the second contact holes correspond to the second step area and the second through holes correspond to the second channel structure; A conductive material is provided to form a second contact in the second contact hole and a second connector in the second through hole; Following "etching the edges of the stacked structure to form a first sub-step structure", the process includes: A first flat layer is formed covering the first sub-step structure; wherein the first sub-step structure has a first step area and a first storage area; A plurality of first contact holes and a plurality of first through holes are formed through the first planarization layer, wherein the first contact holes correspond to the first step area and the first through holes correspond to the first channel structure; A conductive material is provided to form a first contact in the first contact hole and a first connector in the first through hole.

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