storage device

Abstract

The storage device of one embodiment includes: a first storage cell array; a second storage cell array disposed relative to the first storage cell array in a first direction; a first contact plug extending in the first storage cell array along the first direction; and a second contact plug extending in the second storage cell array along the first direction and electrically connected to the first contact plug. The first storage cell array includes a plurality of first electrode layers stacked in the first direction and a first semiconductor pillar penetrating the plurality of first electrode layers. The second storage cell array includes a plurality of second electrode layers stacked in the first direction and a second semiconductor pillar penetrating the plurality of second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar.

Description

[0001] Information related to divisional application

[0002] This case is a divisional application. The parent application of this divisional application is the invention patent application filed on September 6, 2017, with application number 201710796424.7 and title "Storage Device".

[0003] [Related Applications]

[0004] This application claims priority to Japanese Patent Application No. 2017-42675 (filed on March 7, 2017). This application incorporates the entire contents of that basic application by reference. Technical Field

[0005] The implementation relates to a storage device. Background Technology

[0006] The industry is advancing the development of memory devices that incorporate memory cells with a three-dimensional configuration. For example, NAND (Not AND) type memory devices have multiple stacked electrode layers and semiconductor pillars disposed within memory holes that extend through the stacked electrode layers. Memory cells are disposed at the intersection of the semiconductor pillars and electrode layers, arranged along the semiconductor pillars. Such memory devices can increase storage capacity by increasing the number of stacked electrode layers and by miniaturizing the memory holes to increase their number. However, given the limited chip size of memory devices, there are limits to increasing the number of memory holes and the number of stacked electrode layers. Summary of the Invention

[0007] The implementation provides a storage device capable of increasing storage capacity.

[0008] The storage device of one embodiment includes: a first storage cell array; a second storage cell array disposed relative to the first storage cell array in a first direction; a first contact plug extending in the first storage cell array along the first direction; and a second contact plug extending in the second storage cell array along the first direction and electrically connected to the first contact plug. The first storage cell array includes: a plurality of first electrode layers stacked in the first direction; and a first semiconductor pillar penetrating the plurality of first electrode layers in the first direction. The second storage cell array includes: a plurality of second electrode layers stacked in the first direction; and a second semiconductor pillar penetrating the plurality of second electrode layers in the first direction. The first contact plug is electrically connected to the first semiconductor pillar. The second contact plug is electrically connected to the second semiconductor pillar. Attached Figure Description

[0009] Figure 1 This is a schematic cross-sectional view showing the storage device of the first embodiment.

[0010] Figure 2A and Figure 2B This is a schematic top view showing the configuration of the storage cell array of the storage device according to the first embodiment.

[0011] Figure 3 This is a schematic top view showing the upper surface of the storage cell array of the storage device according to the first embodiment.

[0012] Figure 4 This is a schematic cross-sectional view showing the storage cell array of the storage device according to the first embodiment.

[0013] Figure 5A , Figure 5B , Figure 5C and Figure 5D , Figure 6A , Figure 6B and Figure 6C , Figure 7A and Figure 7B , Figure 8A and Figure 8B , Figure 9 and Figure 10 This is a schematic cross-sectional view showing the manufacturing process of the storage cell array of the storage device according to the first embodiment.

[0014] Figure 11 This is a schematic top view showing the configuration of the storage cell array of the storage device according to the second embodiment.

[0015] Figure 12A and Figure 12B This is a schematic diagram showing the storage cell array of the storage device according to the second embodiment.

[0016] Figures 13A-13C This is a schematic diagram illustrating the manufacturing process of the storage cell array of the storage device according to the second embodiment.

[0017] Figures 14A-14C This is a schematic diagram illustrating the manufacturing process of the storage cell array of a storage device according to a variation of the second embodiment.

[0018] Figures 15A-15C This is a schematic diagram illustrating the manufacturing process of a storage cell array of a storage device according to another variation of the second embodiment.

[0019] Figure 16A and Figure 16B This is a schematic cross-sectional view showing the manufacturing process of the storage device according to the third embodiment.

[0020] Figures 17A-17CThis is a schematic cross-sectional view illustrating the manufacturing process of a storage device according to a variation of the third embodiment.

[0021] Figure 18A and Figure 18B This is a schematic cross-sectional view illustrating the manufacturing process of a storage device according to another variation of the third embodiment.

[0022] Figure 19A and Figure 19B This is a schematic top view showing the storage device according to the fourth embodiment.

[0023] Figure 20 This is another schematic top view showing the storage device of the fourth embodiment.

[0024] Figure 21 This is a schematic cross-sectional view showing the storage device according to the fourth embodiment.

[0025] Figure 22 This is another schematic cross-sectional view showing the storage device of the fourth embodiment.

[0026] Figure 23A and Figure 23B This is a schematic cross-sectional view of a storage device showing a variation of the fourth embodiment. Detailed Implementation

[0027] The following is a reference to the appendix. Figure 1 The implementation methods will be described below. Identical parts in the accompanying drawings will be labeled with the same numbers, and detailed descriptions will be omitted where appropriate. Different parts will be described. Furthermore, the accompanying drawings are schematic diagrams or conceptual diagrams, and the relationships between the thickness and width of each part, the ratios between the sizes of the parts, etc., may not be the same as in reality. Additionally, even when representing the same parts, there may be instances where the dimensions or ratios of the parts are represented differently in the accompanying drawings.

[0028] Furthermore, the configuration and structure of each part are explained using the X, Y, and Z axes shown in each figure. The X, Y, and Z axes are orthogonal to each other, representing the X, Y, and Z directions, respectively. In addition, for convenience, there are instances where the description is based on the top and bottom of the figure, but this is not intended to represent all common top-bottom relationships.

[0029] [First Implementation]

[0030] Figure 1 This is a schematic cross-sectional view showing the storage device 1 according to the first embodiment. The storage device 1 is, for example, a NAND flash memory device, having a structure in which memory cell arrays 20, 30, and 40 are stacked on top of the drive circuit 10. Furthermore, Figure 1 In order to illustrate the structure of storage device 1, the insulating film disposed between the various components is omitted.

[0031] The driving circuit 10, for example, includes a substrate 11 on which electronic devices such as CMOS (Complementary Metal Oxide Semiconductor) transistors are disposed, and a wiring layer 13 disposed on the substrate 11. The substrate 11 is, for example, a silicon substrate. A CMOS integrated circuit, for example, is disposed on the upper surface of the substrate 11.

[0032] The memory cell array 20 has multiple electrode layers 21 stacked in the Z direction, multiple semiconductor pillars 23, and source lines 25. The semiconductor pillars 23 extend along the Z direction, penetrating the electrode layers 21. One end of each semiconductor pillar 23 is electrically connected to the source line 25. Multiple semiconductor pillars 23 share a single source line 25. Additionally, the other end of each semiconductor pillar 23 is electrically connected to a wiring 27.

[0033] The memory cell array 30 has multiple electrode layers 31 stacked in the Z direction, multiple semiconductor pillars 33, and source lines 35. The semiconductor pillars 33 extend along the Z direction, penetrating the electrode layers 31. One end of each semiconductor pillar 33 is electrically connected to a source line 35. Multiple semiconductor pillars 33 share a single source line 35. Additionally, the other end of each semiconductor pillar 33 is electrically connected to a wiring 37.

[0034] The memory cell array 40 has multiple electrode layers 41 stacked in the Z direction, multiple semiconductor pillars 43, and source lines 45. The semiconductor pillars 43 extend along the Z direction, penetrating the electrode layers 41. One end of each semiconductor pillar 43 is electrically connected to a source line 45. Multiple semiconductor pillars 43 share a single source line 45. Additionally, the other end of each semiconductor pillar 43 is electrically connected to a wiring 47.

[0035] Electrode layers 21, 31, and 41 are electrically connected to contact plugs 51 at their stepped ends. Furthermore, electrode layers 21, 31, and 41 are electrically connected to the drive circuit 10 via contact plugs 51 and 53. Contact plugs 53 are arranged to pass through each memory cell array 20, 30, and 40. Contact plugs 53 electrically connect the electrode layers 21, 31, and 41 in each memory cell array stacked on the drive circuit 10 to wiring 15 in wiring layer 13.

[0036] Additionally, other contact plugs 55 are provided in each memory cell array, extending through each memory cell array. These contact plugs 55, for example, electrically connect the drive circuit 10 and an interface circuit (not shown).

[0037] The storage device 1 also includes contact plugs 60 extending along the Z-direction in each storage cell array. The contact plugs 60 are provided in each storage cell array, for example, in a manner that penetrates multiple electrode layers 21. The contact plugs 60 extend, for example, longer than the full width Ws of the multiple electrode layers 21, 31, and 41 stacked in the Z-direction. The contact plugs 60 may contain, for example, a metal such as tungsten.

[0038] like Figure 1 As shown, contact plug 60a is provided in memory cell array 20, and contact plugs 60b and 60c are provided in memory cell arrays 30 and 40, respectively. In this specification, contact plugs 60a, 60b, and 60c are sometimes referred to as contact plug 60. Other components are also referred to in the same way.

[0039] Furthermore, connection pads 61 and 63 are respectively provided on each memory cell array. Connection pad 61 is provided on the lower surface of each memory cell array, and connection pad 63 is provided on the upper surface of each memory cell array.

[0040] like Figure 1 As shown, at the boundary between memory cell array 20 and memory cell array 30, connection pads 63a and 61b are interconnected. Contact plug 60a is electrically connected to connection pad 63a. On the other hand, contact plug 60b is electrically connected to connection pad 61b via wiring 65b. That is, contact plug 60a and contact plug 60b are electrically connected via connection pads 63a and 61b.

[0041] Similarly, at the boundary between memory cell array 20 and memory cell array 30, connection pads 63b and 61c are configured to be interconnected. Furthermore, contact plugs 60b and 60c are electrically connected via connection pads 63b and 61c.

[0042] Furthermore, in the memory cell array 20, the wiring 27 connected to the semiconductor pillar 23 is connected to wiring 65a, and wiring 65a is electrically connected to contact plug 60a. Similarly, in the memory cell array 30, the wiring 37 connected to the semiconductor pillar 33 is electrically connected to contact plug 60b and connection pad 61b via wiring 65b. Additionally, in the memory cell array 40, the wiring 47 connected to the semiconductor pillar 43 is electrically connected to contact plug 60c and connection pad 61c via wiring 65c.

[0043] In this way, the semiconductor pillars contained in each memory cell array stacked on the drive circuit 10 can be interconnected via contact plugs 60. Furthermore, the semiconductor pillars interconnected via contact plugs 60 are connected to, for example, a readout amplifier (not shown) of the drive circuit 10 via connection pads 61a located between the drive circuit 10 and the memory cell array 20, or connection pads 63c provided on the upper surface of the memory cell array 40, upper wiring (not shown), and contact plugs 53.

[0044] In this embodiment, the semiconductor pillars 23, 33, and 43 included in the memory cell arrays 20, 30, and 40 can be interconnected to form memory cells MC (refer to) that include, for example, memory cells arranged along each semiconductor pillar. Figure 4 One memory string action.

[0045] For example, if memory cell arrays 20, 30, and 40 each contain 64 electrode layers, then memory device 1 can achieve the same storage capacity as a memory cell array with 192 electrode layers. For instance, forming memory vias in a continuously stacked matrix of 192 electrode layers and forming semiconductor pillars inside those vias requires extremely advanced wafer fabrication technology. In contrast, in memory device 1, memory cell arrays 20, 30, and 40, formed individually by stacking, and electrically connected to each other using contact plugs 60 and connecting pads 61 and 63, can easily achieve the same storage capacity as in the case of continuously stacked matrix of 192 electrode layers.

[0046] Furthermore, in the case of semiconductor pillars extending through 192 electrode layers, there is a concern that the resistance of these semiconductor pillars may reduce the cell current, making it difficult to read data from the memory cell MC. In this embodiment, for example, semiconductor pillars 23, 33, and 43 extending through 64 electrode layers are connected in parallel, so the resistance of each semiconductor pillar is lower than that of the semiconductor pillar extending through 192 electrode layers. Therefore, the memory device 1 can suppress the decrease in cell current.

[0047] Furthermore, this embodiment is not limited to the example described above. For example, the memory cell array stacked on the driving circuit 10 can be two, or four or more memory cell arrays can be stacked. Next, refer to... Figures 2A to 4 The composition of each storage cell array is described in detail.

[0048] Figure 2A and Figure 2B This is a schematic top view showing the configuration of the storage cell array 20 of the storage device 1 in the first embodiment. Figure 2B It means Figure 2A The diagram shows a top view of region MP. Storage cell arrays 30 and 40 have the same construction as storage cell array 20.

[0049] like Figure 2A As shown, electrode layers 21 extend in the X direction, are stacked in the Z direction, and are arranged along the Y direction. A slit ST is provided between adjacent electrode layers 21 in the Y direction to electrically separate them. Furthermore, a stepped lead-out portion HUP is provided at the end of the electrode layer 21 in the X direction. Also, a contact region CA is provided in a portion of the electrode layer 21.

[0050] like Figure 2B As shown, a plurality of memory holes MH are provided in the electrode layer 21. The memory holes MH extend along the Z direction through the plurality of electrode layers 21, and semiconductor pillars 23 are respectively disposed inside the memory holes MH (see reference). Figure 1 Furthermore, multiple wirings 27 extending along the Y direction are provided. One of the multiple semiconductor pillars 23 through which two adjacent electrode layers 21 in the Y direction are respectively connected to one of the multiple wirings 27. That is, one wiring 27 is shared by one semiconductor pillar 23 through which multiple electrode layers 21 arranged along the Y direction are respectively connected.

[0051] Additionally, a contact hole PH is provided in the contact area CA. The contact hole PH extends along the Z direction, penetrating multiple electrode layers 21. For example... Figure 2B As shown, a contact plug 60a is disposed inside the contact hole PH. The contact plug 60a contains a metal such as tungsten and is electrically insulated from the electrode layer 21 by an insulating film 67 disposed inside the contact hole PH. The insulating film 67 is, for example, a silicon oxide film.

[0052] Figure 3 This is a schematic top view showing the lower surface of the memory cell array 20. (Example) Figure 3 As shown, multiple wirings 27 are arranged along the X direction between contact areas CA. The wirings 27 extend along the Y direction. Multiple contact plugs 60a are arranged along the Y direction in contact areas CA. Furthermore, multiple connecting pads 61a are arranged between contact areas CA.

[0053] Connecting pads 61a are disposed on wiring 27 and connected to each contact plug 60a via wiring 65a. For example, the number of connecting pads 61a disposed between contact areas CA is the same as the number of wiring 27 disposed therebetween. Wiring 65a is connected to contact plug 60a via contact plug 71. In addition, wiring 65a is connected to one wiring 27 via contact plug 73.

[0054] Figure 4 This is a schematic cross-sectional view showing the memory cell array 20. Furthermore, Figure 4 It is Figure 1 A cross-sectional view that is upside down. Additionally, Figure 4In order to clearly show the structure of the storage cell array 20, the insulating film that provides electrical insulation between the constituent elements is appropriately omitted.

[0055] like Figure 4 As shown, multiple electrode layers 21 are stacked on the source line 25. The source line 25 is, for example, a plate-shaped conductive layer extending along the X and Y directions. The source line 25 has, for example, a structure in which a metal layer 25a and a semiconductor layer 25b are stacked. The metal layer 25a is, for example, a tungsten layer, and the semiconductor layer 25b is, for example, polysilicon. The electrode layers 21 are, for example, metal layers containing tungsten or the like.

[0056] Semiconductor pillar 23 extends through electrode layer 21 in the stacking direction (Z direction), and its lower end is connected to source line 25. Additionally, the upper end of semiconductor pillar 23 is electrically connected to wiring 27 via contact plug 26.

[0057] A memory film 29 is disposed between the electrode layer 21 and the semiconductor pillar 23. The memory film 29 has a structure in which, for example, a first silicon oxide film, a silicon nitride film, and a second silicon oxide film are sequentially deposited in the direction from the electrode layer 21 toward the semiconductor pillar 23, enabling it to retain and release charge within and from the memory film 29. Memory cells MC are disposed in the portion of the semiconductor pillar 23 that penetrates the electrode layer 21, and each includes a portion of the memory film 29 as a charge holding portion.

[0058] like Figure 4 As shown, the contact plug 60a extends along the Z direction, penetrating multiple electrode layers 21 and source lines 25. The contact plug 60a is electrically insulated from the electrode layers 21 and source lines 25 by an insulating film 67.

[0059] The lower end of contact plug 60a is electrically connected to connection pad 63a. Additionally, the upper end of contact plug 60a is electrically connected to wiring 65a via intermediate wiring 69 and contact plugs 71 and 77. Intermediate wiring 69 is configured to, for example, be at the same height as wiring 27. Contact plug 77 connects contact plug 60a and intermediate wiring 69. Contact plug 71 connects wiring 65a and intermediate wiring 69. Furthermore, wiring 65a is connected to wiring 27 via contact plug 73 and electrically connected to connection pad 61a via contact plug 75.

[0060] Additionally, the memory cell array 20 includes contact plugs 80 electrically connected to the source line 25. The contact plugs 80 extend along the Z direction, penetrating multiple electrode layers 21. The contact plugs 80 are disposed, for example, together with contact plugs 60a, in the contact region CA.

[0061] The lower end of contact plug 80 is electrically connected to source line 25. The upper end of contact plug 80 is electrically connected to connection pad 81 via intermediate wirings 85 and 87, and contact plugs 91, 93, and 95. Intermediate wirings 85 and 87 are set to the same height as wirings 65a and 27, respectively. Contact plug 91 connects contact plug 80 and intermediate wiring 87. Contact plug 93 connects intermediate wirings 85 and 87. Furthermore, intermediate wiring 85 is electrically connected to connection pad 81 via contact plug 91. Additionally, source line 25 is electrically connected to connection pad 83, for example, via contact plug 97.

[0062] Storage cell arrays 30 and 40 also similarly include contact plugs 80, connection pads 81 and 83. For example... Figure 1 As shown, in the stacked memory cell arrays 20, 30, and 40, the source lines 25, 35, and 45 are electrically connected via contact plugs 80, connection pads 81, and 83. Specifically, at the boundary between memory cell arrays 20 and 30, connection pad 83 of memory cell array 20 and connection pad 81 of memory cell array 30 are connected. Furthermore, at the boundary between memory cell arrays 30 and 40, connection pad 83 of memory cell array 30 and connection pad 81 of memory cell array 40 are connected.

[0063] Next, refer to Figures 5A to 10 The manufacturing method of the storage device 1 according to the first embodiment will be described. Figures 5A to 10 This is a schematic cross-sectional view showing the manufacturing process of the memory cell arrays 20, 30 and 40 stacked on the driving circuit 10.

[0064] like Figure 5A As shown, a substrate 110 is formed with a protrusion 101 on its upper surface. The protrusion 101 is formed, for example, by selectively etching the substrate 110. The substrate 110 is, for example, a silicon substrate.

[0065] like Figure 5B As shown, an insulating film 103 is formed covering the upper surface of the substrate 110. The insulating film 103 is, for example, a silicon nitride film formed using LPCVD (Low Pressure Chemical Vapor Deposition).

[0066] like Figure 5C As shown, an insulating film 105 is formed on the insulating film 103. The insulating film 105 is, for example, a silicon oxide film formed by CVD (Chemical Vapor Deposition) using TEOS (Tetraethyl orthosilicate) as a raw material.

[0067] like Figure 5DAs shown, the insulating film 105 is planarized, exposing a portion of the insulating film 103 formed on the protrusion 101. The insulating film 105 is planarized, for example, using CMP (Chemical Mechanical Polishing).

[0068] like Figure 6A As shown, an insulating film 107 is formed on the insulating film 105 and on the protrusion 101. The insulating film 107 is, for example, a silicon oxide film formed using TEOS-CVD. Next, a contact plug 111 is formed from the upper surface of the insulating film 107 to the protrusion 101.

[0069] like Figure 6B As shown, an insulating film 109 is formed on the insulating film 107. The insulating film 109 is, for example, a silicon oxide film formed using TEOS-CVD. Next, the insulating film 109 is selectively removed to form wiring 115. The wiring 115 is electrically connected to the substrate 110, for example, via contact plugs 111.

[0070] like Figure 6C As shown, a memory cell array 20 is formed on an insulating film 109. The memory cell array 20 includes a plurality of electrode layers 21 stacked in the Z direction, a plurality of semiconductor pillars 23 penetrating the electrode layers 21 in the Z direction, and a source line 25. Furthermore, the memory cell array 20 includes contact plugs 51 connected to the electrode layers 21 and contact plugs 53 connected to the wiring 115. Moreover, contact plugs 60a and 80 are formed in portions not shown.

[0071] like Figure 7A As shown, an insulating film 121 is formed on the memory cell array 20. The insulating film 121 is, for example, a silicon oxide film formed using TEOS-CVD. Next, connection pads 123 are formed in the insulating film 121. The connection pads 123 are electrically connected to the contact plug 53, for example, via contact plugs 125. Additionally, connection pads 61a and 81 are also formed in portions not shown (see reference). Figure 4 Connecting pads 61a, 81, and 123 may contain copper or copper alloys, for example.

[0072] like Figure 7B As shown, the drive circuit 10 and the memory cell array 20 are bonded together. For example, the upper surface of the insulating film 121 is brought into contact with the upper surface of the drive circuit 10, and the bonding is performed at a temperature of 300–400°C and a specified pressure. At this time, the connecting pad 123 is connected to the connecting pad 127 on the drive circuit 10 side. The connecting pad 127 may also contain copper or a copper alloy, for example.

[0073] like Figure 8AAs shown, substrate 110 is removed. For example, after grinding or lapping the back side of substrate 110 to form a thin film, it is selectively removed by wet etching. As a result, insulating film 103 is exposed, and after removing protrusion 101, recess 131 is formed. On the bottom surface of recess 131, the upper surface of contact plug 111 is exposed.

[0074] like Figure 8B As shown, a connecting pad 133 is formed by embedding a metal such as copper or a copper alloy inside the recess 131. At this time, connecting pads 63a and 83 are also formed in the portion not shown.

[0075] Connecting pad 133 is connected, for example, to contact plug 111. Connecting pad 133 has, for example, a width W on its upper surface. T1 Width W of the lower surface B1 The shape of the contact plug 111. In contrast, the contact plug 111 has a width W on its upper surface. T2 smaller than the width W of the lower surface B2 The shape.

[0076] like Figure 9 As shown, a memory cell array 30 is bonded onto the memory cell array 20. The memory cell array 30 is formed using the same method as the memory cell array 20. Figure 9 A connection pad 133 is formed on the upper surface of the memory cell array 30. A connection pad 123 is connected to the connection pad 133 at the boundary between the memory cell array 20 and the memory cell array 30. Additionally, in a portion not shown, the connection pad 63a of the memory cell array 20 and the connection pad 61b of the memory cell array 30 are connected (see reference). Figure 1 Furthermore, the connection pads 83 of the memory cell array 20 and 81 of the memory cell array 30 are connected (see reference). Figure 4 Source line 25 and source line 35 are electrically connected.

[0077] like Figure 10 As shown, a memory cell array 40 is bonded onto the memory cell array 30. The memory cell array 40 is formed using the same method as memory cell arrays 20 and 30. Figure 10 A connection pad 135 is formed on the upper surface of the memory cell array 40. The connection pad 135 may contain aluminum, for example. That is, the connection pad 135 is the uppermost layer of wiring, and is formed in a manner that allows it to be connected to an external circuit via wires.

[0078] like Figure 10 As shown, at the boundary between memory cell array 30 and memory cell array 40, connection pad 123 is also connected to connection pad 133. Additionally, in a portion not shown, connection pad 63b of memory cell array 30 and connection pad 61c of memory cell array 40 are connected (see reference). Figure 1Furthermore, the connection pads 83 of the memory cell array 30 and 81 of the memory cell array 40 are connected (see reference). Figure 4 Source line 35 and source line 45 are electrically connected.

[0079] During the manufacturing process, by providing protrusions 101 on the upper surface of the substrate 110, connection pads can be formed on the upper surface of each memory cell array after bonding. Furthermore, as long as the protrusions 101 are formed in a manner with a wiring pattern, connection pads and wiring connected to these connection pads can be formed. Therefore, photolithography and etching of the insulating film after bonding can be omitted, simplifying the manufacturing process of the memory device 1.

[0080] [Second Implementation]

[0081] Figure 11 This is a schematic top view showing the configuration of the memory cell array 50 of the memory device according to the second embodiment. The memory cell array 50 includes electrode layers 21a, 21b, and 21c arranged along the Y direction. The electrode layers 21a, 21b, and 21c extend along the X direction, and the electrode layers 21a and 21b, and 21b and 21c are separated by a slit ST. In addition, the electrode layers 21a, 21b, and 21c are stacked in the Z direction and are penetrated by a plurality of memory holes MH extending along the Z direction. Semiconductor pillars 23 (not shown) are disposed inside each memory hole MH.

[0082] The memory cell array 50 includes a plurality of wirings 27 extending along the Y direction on electrode layers 21a, 21b, and 21c. The wirings 27 are arranged, for example, along the X direction. The wirings 27 are electrically connected to a semiconductor pillar extending through electrode layer 21a, a semiconductor pillar extending through electrode layer 21b, and a semiconductor pillar extending through electrode layer 21c, respectively.

[0083] In this example, contact plugs 160 are disposed inside the slit ST. The contact plugs 160 extend along the Z-direction, and their length is longer than the total height of the electrode layers 21a, 21b, and 21c stacked in the Z-direction. Furthermore, each contact plug 160 is electrically connected to a wiring 27 via a contact plug 141. That is, the same number of contact plugs 160 as wiring 27 are disposed inside the slit ST.

[0084] Figure 12A and Figure 12B This is a schematic diagram showing the storage cell array 50 of the storage device according to the second embodiment. Figure 12A This is a schematic top view showing the upper surface of the storage cell array 50. Figure 12B It means along Figure 12A A schematic diagram of the cross-section of line 12B-12B shown.

[0085] like Figure 12A As shown, a plurality of connecting pads 140 are provided on the wiring 27. Each connecting pad 140 is electrically connected to one wiring 27. That is, the same number of connecting pads 140 as the wiring 27 are arranged on top of a plurality of wirings 27 arranged along the X direction.

[0086] like Figure 12B As shown, the contact plug 160 extends along the Z-direction inside the slit ST. The contact plug 160 is relative to the stacking width W of the electrode layer 21. S It extends further. In addition, the contact plug 160 is electrically insulated from the electrode layer 21 and the source line 120 by an insulating film 167.

[0087] Contact plug 160 is connected to connection pad 150 at its lower end. Additionally, contact plug 160 is electrically connected to a wire 27 at its upper end via contact plug 141. Furthermore, wire 27 is electrically connected to connection pad 140 via contact plug 143. Thus, contact plug 160 is electrically connected to both wire 27 and connection pad 140.

[0088] In this embodiment, multiple memory cell arrays 50 are stacked on top of the driving circuit 10 (see reference). Figure 1 ). The storage cell array 50 is a... Figure 12B The stacking is performed with the top and bottom of the structure shown reversed. At this time, the connection pad 150 of one memory cell array 50 is connected to the connection pad 140 of the other memory cell array 50 stacked thereon. Thus, the semiconductor pillars 23 of the stacked memory cell arrays 50 are electrically connected.

[0089] Additionally, in this embodiment, a contact plug (e.g., not shown) is also used. Figure 4 The contact plug 80 in the middle is electrically connected to the source line 120 of the upper and lower stacked memory cell array 50.

[0090] Figures 13A-13C This is a schematic diagram illustrating the manufacturing process of the memory cell array 50 according to the second embodiment. Figures 13A-13C This is a schematic top view showing the formation process of the contact plug 160.

[0091] like Figure 13A As shown, an insulating film 167 is embedded in the slit ST between the electrode layers 21. The insulating film 167 is, for example, a silicon oxide film formed using CVD. At this time, semiconductor pillars 23 (not shown) and a memory film 29 are formed inside the memory hole MH, respectively.

[0092] like Figure 13BAs shown, an etching mask 181, such as a resist film, is formed to cover the memory hole MH and the insulating film 167. The etching mask 181 has an opening 181a located on the slit ST. Then, the insulating film 167 is selectively removed using the etching mask 181, forming a portion extending in the Z direction within the slit ST and communicating with the portion that becomes the connection pad 150 (see reference). Figure 6A and Figure 12B Contact hole 185.

[0093] like Figure 13C As shown, a contact plug 160 is formed inside the contact hole 185. The contact plug 160 is a metal layer, such as tungsten, embedded inside the contact hole 185.

[0094] Figures 14A-14C This is a schematic diagram illustrating the manufacturing process of the memory cell array 50, a variation of the second embodiment. Figures 14A to 14C This is a schematic top view illustrating the formation process of the contact plug 170. The contact plug 170 is located within the slit ST relative to the lamination width W of the electrode layer 21. S Extend further.

[0095] like Figure 14A As shown, the slit ST formed between the electrode layers 21 includes a first part WP and a second part NP. The width W1 of the first part WP in the Y direction is greater than the width W2 of the second part NP in the Y direction.

[0096] like Figure 14B As shown, an insulating film 167 is formed inside the slit ST. The insulating film 167 is, for example, a silicon oxide film formed using CVD. The insulating film 167 is formed, for example, with a thickness that closes the second portion NP and leaves a residual contact hole 187 in the first portion WP. In other words, it is formed such that the difference between the width W1 of the first portion WP and the width W2 of the second portion NP is greater than the width of the contact plug 170 in the Y direction.

[0097] like Figure 14C As shown, a contact plug 170 is formed inside the contact hole 187. The contact plug 170 is a metal layer, such as tungsten, embedded inside the contact hole 187.

[0098] Figures 15A-15C This is a schematic cross-sectional view illustrating the manufacturing process of a storage cell array 50, which is a variation of the second embodiment. Figures 15A-15C This is a schematic top view illustrating the formation process of the contact plug 180. The contact plug 180 is located within the slit ST relative to the lamination width W of the electrode layer 21. S Extend further.

[0099] like Figure 15AAs shown, the slits ST formed between the electrode layers 21 have, for example, circular openings and are shaped as a plurality of contact holes CH connected in the X direction. The contact holes CH extend, for example, along the Z direction and communicate with the portion that forms the connecting pad 150 (see reference). Figure 6A and Figure 12B The contact hole CH is formed in a manner such as its diameter R. S It is formed in a manner that is 180mm larger than the diameter of the contact plug.

[0100] like Figure 15B As shown, an insulating film 167 is formed inside the slit ST. The insulating film 167 is, for example, a silicon oxide film formed using CVD. The insulating film 167 is formed, for example, with a thickness that leaves a residual contact space 189 within the contact hole CH.

[0101] like Figure 15C As shown, a contact plug 180 is formed inside the contact space 189. The contact plug 180 is a metal layer, such as tungsten, embedded inside the contact space 189.

[0102] [Third Implementation]

[0103] Figure 16A and Figure 16B This is a schematic cross-sectional view showing the manufacturing process of the storage device 1 according to the third embodiment. Figure 16A This is a schematic top view showing, for example, a chip 5 formed by bonding memory cell array 20 and memory cell array 30 together (see reference). Figure 1 ). Figure 16B It is along Figure 16A A schematic cross-sectional view of line 16B-16B shown.

[0104] like Figure 16A As shown, wafer 5 includes, for example, an air gap AG extending along the X direction. The air gap AG extends to the outer edge of wafer 5 and is configured to communicate with the outside at both ends.

[0105] like Figure 16B As shown, an air gap AG is provided at the boundary between the memory cell array 20 and the memory cell array 30. That is, the air gap AG is formed at the boundary between the adjacent memory cell array 20 and the memory cell array 30, becoming a path for the exhaust of air remaining between them. Thus, a so-called gap is formed at the boundary between the memory cell array 20 and the memory cell array 30, which can prevent poor bonding.

[0106] The air gap AG is formed by forming a slot EG in one or both of the memory cell arrays 20 and 30 and then bonding them together.

[0107] An air gap AG is provided, for example, in a so-called dicing region KR between chips cut from wafer 5. The dicing region KR is configured to surround the device region DR containing the memory cells MC and each wiring. This improves the tightness of the bonding surfaces between the memory cell arrays in the device region DR.

[0108] Figures 17A-17C This is a schematic cross-sectional view showing the manufacturing process of storage device 1, a variation of the third embodiment. Figures 17A-17C It means equivalent to along Figure 16A A schematic diagram of a portion of the cross-section of line 16B-16B shown.

[0109] like Figure 17A As shown, after the memory cell array 20 and the driving circuit 10 are bonded together, recesses 131 and 201 are formed on the upper surface of the memory cell array 20. Recesses 131 and 201 are formed, for example, by removing the substrate 110 from the memory cell array 20 (see Figure 1). Figure 8A ).

[0110] like Figure 17B As shown, metal is embedded in the recesses 131 and 201 to form a connecting pad 133 and a metal pattern 205. The connecting pad 133 and the metal pattern 205 are formed, for example, using copper or a copper alloy.

[0111] In this process, for example, a metal layer thicker than the depth of the recesses 131 and 201 is formed on the upper surface of the memory cell array 20. Then, for example, CMP is used to remove the metal layer in such a way that only a portion of the recesses 131 and 201 remains.

[0112] At this time, if the ratio of the area of ​​the metal pattern 205 to the surface area of ​​the cut region KR is large, a groove EG is formed in the cut region KR by so-called dishing. That is, by forming a groove EG in the cut region KR, the ratio of the area of ​​the metal pattern 205 to the surface area of ​​the cut region KR becomes greater than, for example, the ratio of the area of ​​the connection pad 133 to the area of ​​the device region DR of the memory cell array 20.

[0113] like Figure 17C As shown, memory cell array 20 and memory cell array 30 are bonded together. In the device region DR, for example, the connection pad 133 of memory cell array 20 and the connection pad 123 of memory cell array 30 are connected. On the other hand, in the cut region KR, an air gap AG is formed at the location of the slot EG. As a result, gaps can be avoided between the memory cell arrays, and the tightness of the connection between them can be improved.

[0114] Furthermore, by arranging multiple grooves EG in a straight line on the wafer and extending them unidirectionally, wafer warpage can be reduced. Additionally, as described above, by utilizing the concave deformation during CMP, the grooves EG can be formed without the use of techniques such as photolithography and selective etching. This simplifies the manufacturing process of each memory cell array.

[0115] Figure 18A and Figure 18B This is a schematic cross-sectional view showing the manufacturing process of storage device 1, which is a variation of the third embodiment. Figure 18A and Figure 18B It means equivalent to along Figure 16A A schematic diagram of a portion of the cross-section of line 16B-16B shown.

[0116] like Figure 18A As shown, in the air gap AG, the metal pattern 215 can also be formed by exposing the entire inner surface of the groove EG. That is, the metal pattern 215 can also be formed in such a way that its width in the X direction is approximately the same as the width of the groove EG in the X direction. As a result, the concave deformation during CMP becomes larger, and the groove EG can be formed more deeply. Consequently, the width of the air gap AG in the Z direction can be increased. The metal pattern 215 is formed, for example, using copper or a copper alloy.

[0117] exist Figure 18B In the example shown, memory cell array 220 and memory cell array 230 are mated together. Memory cell arrays 220 and 230 include contact plugs 223 and 233, the end faces of which function as connection pads. That is, as... Figure 18B As shown, when the memory cell array 220 and the memory cell array 230 are bonded together, the contact plugs 233 and 223 of the memory cell array 220 can also be directly connected. In addition, a metal pattern 215 is exposed on the inner surface of the air gap AG formed at the boundary between the two.

[0118] In the embodiment described above, when the storage device 1 is cut from the wafer 5 and chipped, a portion of the air gap AG remains at the outer edge of the chip. That is, in the storage device 1 of the third embodiment, the area ratio of the metal pattern 205 exposed in the portion of the air gap AG to the insulating film 105 is greater than the area ratio of the connecting pad 133 at the boundary between the storage cell arrays to the insulating film 105.

[0119] [Fourth Implementation]

[0120] Figure 19A and Figure 19B This is a schematic top view showing the storage device 2 of the fourth embodiment. Figure 19A This is a top view showing the configuration of the storage unit MC of storage device 2. Figure 19BThis is a top view of the storage unit MC of storage device 2.

[0121] like Figure 19A As shown, the storage device 2 includes a plurality of electrode layers 321 extending along the X direction. The electrode layers 321 are arranged along the Y direction. In addition, the electrode layers 321 are deposited in the Z direction with an interlayer insulating film (not shown) in between. An insulator 311 is embedded in the space MT between adjacent electrode layers 321 in the Y direction. The insulator 311 is, for example, silicon oxide.

[0122] The memory hole MH of the storage device 2 is provided so that it penetrates the insulator 311 in the Z direction. Furthermore, the memory hole MH is formed in such a way that the insulator 311 is divided into multiple parts. The storage device 2 also includes a contact hole STH that penetrates the insulator 311 in the Z direction. Contact plugs 330 and 340 are disposed inside the contact hole STH. Additionally, an insulating film 331 is provided inside the contact hole STH to electrically insulate the contact plugs 330 and 340 from the electrode layer 321.

[0123] like Figure 19B As shown, a semiconductor pillar 310 extending along the Z-direction is disposed inside the memory hole MH. The semiconductor pillar 310 includes an insulating core 313 and a semiconductor layer 315. The insulating core 313 is, for example, silicon oxide extending along the Z-direction. The semiconductor layer 315 covers the sides of the insulating core 313 and extends along the Z-direction. The semiconductor layer 315 is, for example, polysilicon.

[0124] An insulating film 317 is also disposed inside the memory hole MH. The insulating film 317 is disposed between the inner wall of the memory hole MH and the semiconductor pillar 310. The insulating film 317 is, for example, a silicon oxide film.

[0125] like Figure 19B As shown, the memory cell of the memory device 2 includes, for example, a floating gate FG. The floating gate FG is arranged such that an insulating film 317 extending from the inner wall of the memory hole MH to the interior of the electrode layer 321. An insulating film 323 is provided between the floating gate FG and the electrode layer 321.

[0126] The floating gates (FGs) are arranged to extend into the interior of each of the electrode layers 321 stacked in the Z direction, and are spaced apart from each other along the memory holes extending in the Z direction. One memory hole (MH) is disposed between two adjacent electrode layers 321 in the Y direction, and a floating gate (FG) is disposed on each of the two electrode layers 321. The two floating gates (FGs) function independently of each other. That is, in the storage device 2, two memory cells (MCs) can be configured for each memory hole (MH) located between electrode layers 321 at the same height in the Z direction.

[0127] In each memory cell (MC), a portion of the insulating film 317 located between the semiconductor pillar 310 and the floating gate FG functions as a tunnel insulating film. Furthermore, a portion of the insulating film 323 located between the electrode layer 321 and the floating gate FG functions as a barrier insulating film.

[0128] Figure 20 These are other schematic top views representing storage device 2. For example... Figure 20 As shown, a plurality of bit lines 350 are provided in the Y direction intersecting with the electrode layer 321. The bit lines 350 are disposed above the memory hole MH and electrically connected to the semiconductor pillar 310 via contact plugs 351.

[0129] like Figure 20 As shown, the contact holes STH are arranged along the Y direction. The bit line 530 is not positioned above the contact holes STH. Each bit line 350 is electrically connected via wiring 333 to a contact plug 330 disposed inside the contact hole STH. The bit line 350 is electrically connected to any one of the plurality of contact plugs 330.

[0130] Figure 21 This is a schematic cross-sectional view showing storage device 2. Figure 21 It is along Figure 20 The sectional view of line 20A-20A shown includes contact plug 330. Furthermore, for convenience, Figure 21 The diagrams of the insulating film and insulator that provide electrical insulation between the various elements are omitted.

[0131] like Figure 21 As shown, the storage device 2 includes multiple memory cell arrays 20, such as memory cell arrays 20A, 20B, 20C, and 20D, stacked on the drive circuit 10. The number of stacked memory cell arrays 20 is arbitrary and not limited to this example.

[0132] Each memory cell array 20 includes multiple semiconductor pillars 310, contact plugs 330, bit lines 350, and source lines 370. One end of each semiconductor pillar 310 is electrically connected to the bit line 350, and the other end is electrically connected to the source line 370. For convenience, Figure 21 The diagram of contact plug 351 is omitted.

[0133] The source line 370 is, for example, a plate-shaped conductor extending along the X and Y directions. An electrode layer 321 is deposited on the source line 370 (see 19A). Furthermore, a contact plug 330 is provided extending along the Z direction through a through-hole SH provided in the source line 370. The contact plug 330 is electrically insulated from the source line 370 by an insulating film 331.

[0134] In each memory cell array 20, contact plugs 330 are electrically connected to a bit line 350 via wiring 333. For example... Figure 21As shown, wiring 333 is connected to the positioning line 350 via contact plug 339 and to contact plug 330 via contact plug 337.

[0135] Furthermore, the contact plugs 330 of each memory cell array 20 are connected in series in the Z direction. The contact plugs 330 of memory cell arrays 20B and 20C are respectively connected to the upper and lower contact plugs 330 via pads 343 and 345. For example... Figure 21 As shown, pad 343 is electrically connected to wiring 333 via contact plug 335. Pad 345 is connected to one end of contact plug 330.

[0136] The configuration of pads 343 and 345 is not limited to this example; for example, it can also be configured as follows: Figure 1 and Figure 3 It is typically positioned between bit line 350 and source line 370.

[0137] The contact plugs 330 of the memory cell array 20D are electrically connected to the wiring 410 via pads 345 and contact plugs 347. The wiring 410 is, for example, connected via contact plugs 53 located around the periphery of the memory cell array 20 (see reference). Figure 1 The readout amplifier SA is electrically connected to the drive circuit 10. As a result, the bit lines 350 of each memory cell array 20 are connected in parallel to the readout amplifier SA via contact plugs 330. Thus, the memory cell array 20 can be stacked in multiple segments without reducing the cell current flowing through each semiconductor pillar 310, thereby increasing the storage capacity of the storage device 2.

[0138] Figure 22 This is another schematic cross-sectional view representing storage device 2. Figure 21 It is along Figure 20 The sectional view shown for line 20B-20B includes contact plug 340. For convenience, Figure 21 The diagrams of the insulating film and insulator that provide electrical insulation between the various elements are also omitted.

[0139] like Figure 22 As shown, in each memory cell array 20, a contact plug 340 is connected to the source line 370. Additionally, the contact plug 340 is electrically connected to the pad 343 via wiring 333, contact plugs 335 and 337. On the other hand, the source line 370 is electrically connected to the pad 345 via contact plug 349.

[0140] For example, the source lines 370 of memory cell arrays 20B and 20C are electrically connected to the source lines 370 of the memory cell arrays 20 located above and below each other via pads 343 and 345.

[0141] The contact plugs 340 of the memory cell array 20D are electrically connected to the wiring 420 via pads 345 and contact plugs 349. The wiring 420 is, for example, connected via contact plugs 53 disposed around the periphery of the memory cell array 20 (see reference). Figure 1 The driving transistors are electrically connected to the driving circuit 10. As a result, the source lines 370 of each memory cell array 20 are connected in series via contact plugs 340 and electrically connected to the driving circuit 10.

[0142] Figure 23A and Figure 23B This is a schematic cross-sectional view of the storage device 3, which represents a variation of the fourth embodiment. Figure 23A and Figure 23B These are schematic diagrams showing cross-sections including the contact plug 330. Figure 23B It means and Figure 23A Schematic diagrams of different cross-sections.

[0143] exist Figure 23A In the example shown, the contact plugs 330 of the memory cell array 20B are electrically connected to the bit line 350 via wiring 333. On the other hand, the contact plugs 330 of memory cell arrays 20A, 20C, and 20D are not electrically connected to the bit line 350. That is, one bit line 350 is electrically connected to wiring 410B via a series-connected contact plug 330, and then connected to the sense amplifier SA.

[0144] exist Figure 23B In the example shown, the contact plugs 330 of the memory cell array 20C are electrically connected to the bit line 350 via wiring 333. On the other hand, the contact plugs 330 of memory cell arrays 20A, 20B, and 20D are not electrically connected to the bit line 350. Therefore, one bit line 350 is electrically connected to wiring 410C via contact plugs 330 connected in series.

[0145] Thus, in the storage device 3, one bit line 350 of the multi-segment stacked memory cell array 20 is connected to a sense amplifier SA via a series-connected contact plug 330. As a result, the multi-segment stacked memory cell array 20 can be improved without reducing the cell current flowing through each semiconductor pillar 310, and the data readout speed from each memory cell MC can be increased.

[0146] As described, this embodiment illustrates an example of connecting all bit lines 350 of a multi-layered memory cell array 20 in parallel to a sense amplifier SA via series-connected contact plugs 330, and an example of connecting one bit line 350 from the multi-layered memory cell array 20 to one sense amplifier SA, but the embodiment is not limited to these. For example, depending on the number of bit lines in each memory cell array 20 and the number of contact holes STH, any number of bit lines 350 from the multi-layered memory cell array 20 can be connected in parallel to a sense amplifier SA via series-connected contact plugs 330.

[0147] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention as set forth in the claims and its equivalents.

Claims

1. A storage device, characterized in that... include: The first memory cell array includes a plurality of first electrode layers stacked in a first direction and a first semiconductor pillar extending in the first direction and penetrating the plurality of first electrode layers, wherein the plurality of first electrode layers include a first end disposed in a stepped manner; A first contact plug extends in the first direction and contacts one of the plurality of first electrode layers at the first end; The second contact plug penetrates the first memory cell array and extends along the first direction; The second memory cell array is disposed relative to the first memory cell array in the first direction, and includes a plurality of second electrode layers stacked in the first direction and a second semiconductor pillar extending in the first direction and penetrating the plurality of second electrode layers, wherein the plurality of second electrode layers include a second end portion arranged in a stepped manner. The third contact plug extends in the first direction and contacts one of the plurality of second electrode layers at the second end; The fourth contact plug penetrates the second memory cell array, extends along the first direction, and is electrically connected to the second contact plug; A first connecting pad is disposed between the first storage cell array and the second storage cell array, and the second contact plug is connected to the first connecting pad; as well as The second connection pad is abutted against the first connection pad between the first memory cell array and the second memory cell array, and the fourth contact plug is connected to the second connection pad; and The third contact plug is electrically connected to the fourth contact plug, thereby being electrically connected to the second contact plug.

2. The storage device according to claim 1, characterized in that... Also includes: The first wiring connects the third and fourth contact plugs electrically.

3. The storage device according to claim 1, characterized in that... Also includes: The driving circuit is electrically connected to one of the plurality of second electrode layers via the second to fourth contact plugs, and the first memory cell array is located between the driving circuit and the second memory cell array.

4. The storage device according to claim 3, characterized in that... Also includes: The fifth contact plug extends through the first memory cell array; as well as The second wiring connects the first contact plug to the fifth contact plug electrically; and The drive circuit is electrically connected to one of the plurality of first electrode layers via the first contact plug and the fifth contact plug.

5. The storage device according to claim 1, characterized in that: The first and second memory cell arrays further include first and second source lines, respectively. The plurality of first electrode layers are stacked on the first source line, the plurality of second electrode layers are stacked on the second source line, the first semiconductor pillar is electrically connected to the first source line, and the second semiconductor pillar is electrically connected to the second source line.

6. The storage device according to claim 5, characterized in that... Also includes: The first connecting conductor electrically connects the first and second source lines; as well as The second connecting conductor electrically connects the first and second semiconductor pillars; in The first connecting conductor includes a first and a second connecting portion. The first connecting portion extends through the first memory cell array, and the second connecting portion extends through the second memory cell array. The first connecting portion is electrically connected to the first source line, and the second connecting portion is electrically connected to the second source line. The second connecting conductor includes a third and a fourth connecting portion, the third connecting portion extending through the first memory cell array, the fourth connecting portion extending through the second memory cell array, the third connecting portion being electrically connected to the first semiconductor pillar, and the fourth connecting portion being electrically connected to the second semiconductor pillar.

7. The storage device according to claim 6, characterized in that: The first semiconductor pillar has a first end and a second end opposite to the first end. The first end of the first semiconductor pillar is electrically connected to the first source line, and the second end of the first semiconductor pillar is electrically connected to the third connection portion. The second semiconductor pillar has a first end and a second end opposite to the first end. The first end of the second semiconductor pillar is electrically connected to the second source line, and the second end of the second semiconductor pillar is electrically connected to the fourth connection portion.

8. The storage device according to claim 6, characterized in that: The second connecting conductor further includes a third connecting pad and a fourth connecting pad, the third connecting pad being attached to the fourth connecting pad between the first and second memory cell arrays, the third connecting portion being electrically connected to the third connecting pad, and the fourth connecting portion being electrically connected to the fourth connecting pad.

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