Display device

Abstract

This invention relates to a display device. According to one embodiment, the display device includes: a planarization layer disposed on a substrate; a plurality of inner sidewalls and a plurality of outer sidewalls disposed on the planarization layer and extending in one direction; a first alignment electrode and a second alignment electrode disposed on the plurality of inner sidewalls and spaced apart from each other; a light-emitting element disposed on the first alignment electrode and the second alignment electrode, and disposed between the first alignment electrode and the second alignment electrode; and a first contact electrode and a second contact electrode, the first contact electrode being disposed on the first alignment electrode and contacting one end of the light-emitting element, and the second contact electrode being disposed on the second alignment electrode and contacting the other end of the light-emitting element, wherein the plurality of outer sidewalls and the plurality of inner sidewalls are disposed on the same layer, and the plurality of outer sidewalls space the plurality of inner sidewalls between them.

Description

Technical Field

[0001] This invention relates to a display device. Background Technology

[0002] With the development of multimedia, the importance of display devices is increasing. As a result, various types of display devices, such as organic light-emitting displays (OLEDs) and liquid crystal displays (LCDs), are being put into use.

[0003] As a device for displaying images of a display device, it includes display panels such as organic light-emitting display panels or liquid crystal display panels. Among them, as a light-emitting display panel, it can include light-emitting elements, such as organic light-emitting diodes (OLEDs) that use organic materials as fluorescent materials and inorganic light-emitting diodes that use inorganic materials as fluorescent materials. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a display device that can prevent ink from overflowing into adjacent sub-pixels and reduce masking processes.

[0005] The technical problems of this invention are not limited to those mentioned above. Other technical problems not mentioned can be clearly understood by those skilled in the art through the following content.

[0006] A display device according to an embodiment for solving the above-mentioned technical problems may include: a planarization layer disposed on a substrate; a plurality of inner sidewalls and a plurality of outer sidewalls disposed on the planarization layer and extending in one direction; a first alignment electrode and a second alignment electrode disposed on the plurality of inner sidewalls and spaced apart from each other; a light-emitting element disposed on the first alignment electrode and the second alignment electrode and disposed between the first alignment electrode and the second alignment electrode; and a first contact electrode and a second contact electrode, the first contact electrode being disposed on the first alignment electrode and contacting one end of the light-emitting element, the second contact electrode being disposed on the second alignment electrode and contacting the other end of the light-emitting element, wherein the plurality of outer sidewalls and the plurality of inner sidewalls are disposed on the same layer, and the plurality of outer sidewalls place the plurality of inner sidewalls between them and space them apart from each other.

[0007] The plurality of inner dikes and the plurality of outer dikes can be connected to the planarization layer, and the plurality of inner dikes and the plurality of outer dikes are configured to have the same height.

[0008] The plurality of inner dikes can be configured as islands, and the plurality of outer dikes can be configured as lines extending continuously along the direction.

[0009] The plurality of outer dikes may each include a linear portion parallel to the plurality of inner dikes and a plurality of protruding portions that protrude from the linear portion toward the plurality of inner dikes and are spaced apart from each other.

[0010] The plurality of outer dikes may include a first outer dike and a second outer dike that are adjacent to each other, wherein the plurality of protrusions of the second outer dike are respectively arranged on a horizontal line passing through each of the plurality of protrusions of the first outer dike.

[0011] The first alignment electrode and the second alignment electrode may be arranged between the plurality of protrusions of the first outer embankment and the plurality of protrusions of the second outer embankment.

[0012] The spacing between each of the plurality of protrusions of the first outer embankment and each of the plurality of protrusions of the opposing second outer embankment may be the same or different from each other.

[0013] The plurality of inner dikes may include a first inner dike and a second inner dike that are adjacent to each other, wherein the interval between each of the plurality of protrusions of the first outer dike and each of the plurality of protrusions of the opposing second outer dike is greater than the distance from one side of the first inner dike to the other side of the second inner dike.

[0014] The spacing between opposing linear sections of the plurality of outer embankments can be the same.

[0015] The first alignment electrode and the second alignment electrode may overlap with the plurality of inner dikes, but not with the plurality of outer dikes.

[0016] Specific details of other embodiments are included in the detailed description and accompanying drawings.

[0017] Based on the display device according to the embodiment, by including outer dikes spaced apart from each other, when ink including light-emitting elements is sprayed, the ink can be guided to diffuse along the outer dikes, thereby preventing ink from overflowing into adjacent sub-pixels.

[0018] Furthermore, the outer and inner dikes are formed through a masking process, which reduces the need for masking processes.

[0019] The effects of the embodiments are not limited to those illustrated above, and more diverse effects are included in this specification. Attached Figure Description

[0020] Figure 1 This is a schematic plan view of a display device according to one embodiment.

[0021] Figure 2 This is a plan view showing a pixel of a display device according to an embodiment.

[0022] Figure 3 It is shown Figure 2 A planar image of a subpixel.

[0023] Figure 4 It is along Figure 3 A cross-sectional view taken from the Q1-Q1' line.

[0024] Figure 5 It is along Figure 3 A cross-sectional view taken from the Q2-Q2' line.

[0025] Figure 6 It is along Figure 3 A cross-sectional view taken from the Q3-Q3' line.

[0026] Figure 7 It is shown Figure 2 A plan view of an example of the inner and outer dikes.

[0027] Figure 8 It is shown Figure 2 Plan view of another example of the inner and outer dikes.

[0028] Figure 9 This is a schematic perspective view of a light-emitting element according to one embodiment.

[0029] Figures 10 to 15 This is a cross-sectional view showing a manufacturing method of a display device according to an embodiment, arranged by process.

[0030] Figure 16 This is a plan view showing a display device according to another embodiment.

[0031] Figure 17 This is a plan view showing the outer and inner embankments of a display device according to another embodiment.

[0032] Figure 18 This is a plan view showing a display device according to yet another embodiment.

[0033] Figure 19 It is along Figure 18 A cross-sectional view taken from the Q4-Q4' line.

[0034] Explanation of reference numerals in the attached figures

[0035] 10: Display device; 21: First alignment electrode

[0036] 22: Second alignment electrode; 30: Light-emitting element

[0037] IBNL1: Inner breakwater; EBNL: Outer breakwater

[0038] PAS1: First insulating layer; PAS2: Second insulating layer

[0039] CNE1: First contact electrode; CNE2: Second contact electrode Detailed Implementation

[0040] References and Appendix Figure 1 The advantages and features of the invention, as well as the methods for achieving them, will become clear from the detailed embodiments described below. However, the invention can take many different forms and is not limited to the embodiments disclosed below. These embodiments are provided only to make the disclosure of the invention complete and to fully inform those skilled in the art of the invention of its scope. The invention is defined only by the scope of the claims.

[0041] The reference to elements or layers being "on" other elements or layers includes situations where they are immediately above or adjacent to other elements, or where other layers or elements are sandwiched in between. Throughout this specification, the same reference numerals refer to the same constituent elements. The shapes, sizes, proportions, angles, quantities, etc., disclosed in the drawings used to illustrate embodiments are exemplary, and therefore the invention is not limited to the matters illustrated.

[0042] Although terms such as "first" and "second" are used to describe multiple constituent elements, these constituent elements are clearly not limited to these terms. These terms are only used to distinguish one constituent element from another. Therefore, the "first constituent element" mentioned below can obviously also be a "second constituent element" within the technical concept of this invention.

[0043] The various features of the multiple embodiments of the present invention can be partially or completely combined or integrated with each other, and can be linked and driven in various ways in terms of technology. Each embodiment can be implemented independently or together in a related relationship.

[0044] The specific embodiments will now be described with reference to the accompanying drawings.

[0045] Figure 1 This is a schematic plan view of a display device according to one embodiment.

[0046] Reference Figure 1The display device 10 displays video or still images. The display device 10 can refer to any electronic device that provides a display screen. For example, the display device 10 may include televisions, laptops, monitors, billboards, Internet of Things devices, mobile phones, smartphones, tablet PCs (PCs), electronic watches, smartwatches, watch phones, head-mounted displays, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigators, game consoles, digital cameras, camcorders, etc.

[0047] The display device 10 includes a display panel that provides a displayed image. Examples of display panels may include inorganic light-emitting diode (LED) display panels, organic light-emitting diode (OLED) display panels, quantum dot (QD) light-emitting diode (OLED) display panels, plasma display panels, field emission display panels, etc. Hereinafter, as an example of a display panel, the application of an inorganic LED display panel is illustrated, but it is not limited thereto; other display panels may be applied as long as the same technical concept can be applied.

[0048] The shape of the display device 10 can vary considerably. For example, the display device 10 can be a rectangle with a long horizontal length, a rectangle with a long vertical length, a square, a quadrilateral with rounded corners (vertices), other polygons, a circle, etc. The shape of the display area DPA of the display device 10 can also be similar to the overall shape of the display device 10. Figure 1 The image illustrates, by way of example, a rectangular display device 10 with a long horizontal length and a display area DPA.

[0049] The display device 10 may include a display area DPA and a non-display area NDA. The display area DPA is the area where the image can be displayed, and the non-display area NDA is the area where the image is not displayed. The display area DPA may also be referred to as the effective area, and the non-display area NDA may also be referred to as the ineffective area. The display area DPA may occupy approximately the center of the display device 10.

[0050] The display area DPA may include multiple pixels PX. The multiple pixels PX may be arranged along a row and column direction. The shape of each pixel PX in a plane may be rectangular or square, but is not limited to these; it may also be a rhombus shape with each side tilted relative to one direction. The individual pixels PX may be arranged alternately in a striped pattern or a pen-tile pattern. Furthermore, each of the pixels PX may include one or more light-emitting elements 30 that emit light of a specific wavelength (see reference). Figure 2 It displays a specific color.

[0051] Non-display areas NDA can be arranged around the display area DPA. The non-display areas NDA can completely or partially surround the display area DPA. The display area DPA can be rectangular, and the non-display areas NDA are arranged adjacent to the four sides of the display area DPA. The non-display areas NDA can form the frame of the display device 10. Wiring or circuit driving parts included in the display device 10 can be arranged in each non-display area NDA, or external devices can be mounted thereon.

[0052] Figure 2 This is a plan view showing a pixel of a display device according to an embodiment.

[0053] Reference Figure 2 Each of a plurality of pixels PX can include a plurality of sub-pixels PXn (n being an integer from 1 to 3). For example, a pixel PX can include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3. The first sub-pixel PX1 can emit light of a first color, the second sub-pixel PX2 can emit light of a second color, and the third sub-pixel PX3 can emit light of a third color. As an example, the first color could be blue, the second color could be green, and the third color could be red. However, this is not a limitation; each sub-pixel PXn can also emit light of the same color. Furthermore, in Figure 2 Although the example illustration shows a pixel PX consisting of three sub-pixels PXn, it is not limited to this; a pixel PX may include a greater number of sub-pixels PXn.

[0054] Each sub-pixel PXn of the display device 10 may include a light-emitting region EMA and a non-light-emitting region (not shown). The light-emitting region EMA may be an area where a light-emitting element 30 is arranged and emits light of a specific wavelength, while the non-light-emitting region may be an area where no light-emitting element 30 is arranged and where light emitted from the light-emitting element 30 cannot reach and therefore does not emit light. The light-emitting region EMA may include an area where a light-emitting element 30 is arranged, and may also include an area adjacent to the light-emitting element 30 where light emitted from the light-emitting element 30 is emitted.

[0055] Not limited to this, the light-emitting area EMA may also include the area where light emitted from the light-emitting element 30 is reflected or refracted by another component. Multiple light-emitting elements 30 may be arranged in each sub-pixel PXn, and may include the area where they are arranged and the area adjacent to them to form the light-emitting area EMA.

[0056] Furthermore, each sub-pixel PXn may include a cut-out region CBA disposed in a non-light-emitting area. The cut-out region CBA may be disposed on one side of the light-emitting region EMA in the second direction DR2. The cut-out region CBA may be disposed between the light-emitting regions EMA of adjacent sub-pixels PXn along the second direction DR2. A plurality of light-emitting regions EMA and cut-out regions CBA may be arranged in the display area DPA of the display device 10. For example, the plurality of light-emitting regions EMA and cut-out regions CBA may be repeatedly arranged in the first direction DR1, and the light-emitting regions EMA and cut-out regions CBA may be alternately arranged in the second direction DR2. Furthermore, the spacing between the cut-out regions CBA in the first direction DR1 may be smaller than the spacing between the light-emitting regions EMA in the first direction DR1. A protrusion of the outer embankment EBNL, described later, may be disposed between the cut-out region CBA and the light-emitting region EMA. The cut-out region CBA does not have a light-emitting element 30 disposed therein and does not emit light, but a portion of the alignment electrodes 21, 22 disposed in each sub-pixel PXn may be disposed therein. The alignment electrodes 21 and 22 arranged in each sub-pixel PXn can be arranged separately from each other in the cut region CBA. However, this is not a limitation; the alignment electrodes 21 and 22 can also be arranged in the cut region CBA without being separated.

[0057] Figure 3 It is shown Figure 2 A planar image of a subpixel. Figure 4 It is along Figure 3 A cross-sectional view taken from the Q1-Q1' line. Figure 5 It is along Figure 3 A cross-sectional view taken from the Q2-Q2' line. Figure 6 It is along Figure 3 A cross-sectional view taken from the Q3-Q3' line. Figure 7 It is shown Figure 2 A plan view of an example of the inner and outer dikes. Figure 8 It is shown Figure 2 Plan view of another example of the inner and outer dikes.

[0058] Although Figures 4 to 6 Only the illustration is shown. Figure 2 The cross-section of the first sub-pixel PX1 can be used, but the same applies to other pixels PX or sub-pixels PXn. Figure 4 and Figure 5 The illustration shows a cross-section spanning one end and the other end of the light-emitting element 30 arranged transversely in the first sub-pixel PX1. Furthermore, in Figure 4 and Figure 5 The diagram only shows one first transistor T1, but it is not limited to this. As mentioned above, each sub-pixel PXn can have three transistors and a storage capacitor.

[0059] Combination Figure 2 Reference Figures 3 to 6 The display device 10 may include a substrate 11 and a semiconductor layer, a plurality of conductive layers, and a plurality of insulating layers disposed on the substrate 11. The semiconductor layer, conductive layers, and insulating layers may respectively constitute the circuit layer and the light-emitting element layer of the display device 10.

[0060] Specifically, the substrate 11 can be an insulating substrate. The substrate 11 can be made of insulating materials such as glass, quartz, or polymer resin. Furthermore, the substrate 11 can be a rigid substrate, but it can also be a flexible substrate capable of bending, folding, rolling, etc.

[0061] A light-blocking layer BML can be disposed on the substrate 11. The light-blocking layer BML is disposed to overlap with the active layer ACT1 of the first transistor T1. The light-blocking layer BML may include a light-blocking material, thereby preventing light from incident on the active layer ACT1 of the first transistor T1. Furthermore, the light-blocking layer BML can be electrically connected to the source electrode S1 of the first transistor T1 through a contact hole to suppress voltage changes of the first transistor T1. For example, the light-blocking layer BML is an opaque metallic material that blocks light transmission, and can be configured as a Ti / Cu bilayer film of titanium and copper layers stacked together. However, it is not limited to this, and the light-blocking layer BML can be omitted.

[0062] The buffer layer 12 may include a light-blocking layer BML disposed on the entire substrate 11. The buffer layer 12 is formed on the substrate 11 to protect the first transistor T1 of the pixel PX from moisture that may penetrate through the moisture-permeable substrate 11, and also performs a surface planarization function. The buffer layer 12 may be configured as a plurality of alternating inorganic layers. For example, the buffer layer 12 may be formed as a silicon oxide (SiO2) layer. x ), silicon nitride (SiN) x ), silicon nitride oxide (SiO) x N y A multilayer consisting of at least one of the inorganic layers alternately stacked.

[0063] Semiconductor layers are disposed on buffer layer 12. These semiconductor layers may include the active layer ACT1 of the first transistor T1. They may be arranged to partially overlap with the gate electrode G1 of the first gate conductive layer, as described later.

[0064] The semiconductor layer may include polycrystalline silicon, monocrystalline silicon, oxide semiconductors, etc. When the semiconductor layer includes an oxide semiconductor, each active layer ACT1 may include multiple conductive regions and channel regions between them. The oxide semiconductor may be an indium (In)-containing oxide semiconductor. For example, the oxide semiconductor may be indium-tin oxide (ITO), indium-zinc oxide (IZO), indium-gallium oxide (IGO), indium-zinc-tin oxide (IZTO), indium-gallium-tin oxide (IGTO), indium-gallium-zinc-tin oxide (IGZTO), etc.

[0065] In another embodiment, the semiconductor layer may also comprise polycrystalline silicon. Polycrystalline silicon can be formed by crystallizing amorphous silicon, in which case the conductive region of the active layer ACT1 can be a doped region doped with various impurities.

[0066] A first gate insulating layer 13 is disposed on the semiconductor layer and the buffer layer 12. The first gate insulating layer 13 can function as the gate insulating film of each transistor. The first gate insulating layer 13 can be configured to include inorganic materials (e.g., silicon oxide (SiO2)). x ), silicon nitride (SiN) x ), silicon nitride oxide (SiO) x N y Inorganic layers, or structures formed by stacking them.

[0067] A first gate conductive layer is disposed on a first gate insulating layer 13. The first gate conductive layer may include a gate electrode G1 of a first transistor T1. The gate electrode G1 may be arranged to overlap with the channel region of the active layer ACT1 in the thickness direction. In addition, although not shown, the first gate conductive layer may also include a first capacitor electrode of a storage capacitor, scan lines, and sensing lines, etc.

[0068] The first gate conductive layer can be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof. However, it is not limited to this.

[0069] A first interlayer insulating layer 15 is disposed on the first gate conductive layer. The first interlayer insulating layer 15 functions as an insulating film between the first gate conductive layer and other layers disposed thereon. Furthermore, the first interlayer insulating layer 15 can be arranged to cover the first gate conductive layer to protect it. The first interlayer insulating layer 15 can be configured to include inorganic materials (e.g., silicon oxide (SiO2)). x ), silicon nitride (SiN) x ), silicon nitride oxide (SiO) x N y Inorganic layers, or structures formed by stacking them.

[0070] A first data conductive layer is disposed on a first interlayer insulating layer 15. The first data conductive layer may include a source electrode S1 and a drain electrode D1 of a first transistor T1 disposed in the display area DPA.

[0071] The source electrode S1 and drain electrode D1 of the first transistor T1 can be contacted with the doped region of the active layer ACT1 through contact holes penetrating the first interlayer insulating layer 15 and the first gate insulating layer 13, respectively. Furthermore, the source electrode S1 of the first transistor T1 can be electrically connected to the light-blocking layer BML through another contact hole.

[0072] The first data conductive layer can be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof. However, it is not limited to this.

[0073] A second interlayer insulating layer 17 is disposed on the first data conductive layer. The second interlayer insulating layer 17 functions as an insulating film between the first data conductive layer and other layers disposed on the first data conductive layer. Furthermore, the second interlayer insulating layer 17 can cover the first data conductive layer and function as a protective layer. The second interlayer insulating layer 17 can be configured to include inorganic materials (e.g., silicon oxide (SiO2)). x ), silicon nitride (SiN) x ), silicon nitride oxide (SiO) x N y Inorganic layers, or structures formed by stacking them.

[0074] The second data conductive layer is disposed on the second interlayer insulating layer 17. The second data conductive layer may include a first voltage wiring VL1, a second voltage wiring VL2, and a first conductive pattern CDP. The first voltage wiring VL1 may be applied with a high potential voltage (or a first power supply voltage) supplied to the first transistor T1, and the second voltage wiring VL2 may be applied with a low potential voltage (or a second power supply voltage) supplied to the second alignment electrode 22. Furthermore, the second voltage wiring VL2 may also be applied with alignment signals required for aligning the light-emitting element 30 during the manufacturing process of the display device 10.

[0075] The first conductive pattern CDP can be connected to the source electrode S1 of the first transistor T1 through a contact hole formed in the second interlayer insulating layer 17. The first conductive pattern CDP can be electrically connected to the first drain electrode D1 and can also contact the first alignment electrode 21 described later. The first transistor T1 can transfer the first power supply voltage applied from the first voltage wiring VL1 to the first alignment electrode 21 through the first conductive pattern CDP. Furthermore, although the figures illustrate a second data conductive layer comprising one second voltage wiring VL2 and one first voltage wiring VL1, it is not limited thereto. The second data conductive layer may include a greater number of first voltage wirings VL1 and second voltage wirings VL2.

[0076] The second conductive layer can be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or their alloys. However, it is not limited to this.

[0077] A first planarization layer 19 is disposed on the second data conductive layer. The first planarization layer 19 can perform a surface planarization function. The first planarization layer 19 may include an organic insulating material (e.g., an organic material such as polyimide). However, in some embodiments, the first planarization layer 19 may be omitted.

[0078] Multiple inner sidewalls IBNL, multiple outer sidewalls EBNL, multiple alignment electrodes 21, 22, light-emitting elements 30, and multiple contact electrodes CNE1, CNE2 can be arranged on the first planarization layer 19. Furthermore, multiple insulating layers PAS1, PAS2, and PAS3 can be arranged on the first planarization layer 19.

[0079] Specifically, a plurality of inner sidewalls IBNL and a plurality of outer sidewalls EBNL can be arranged on the substrate 11. For example, the plurality of inner sidewalls IBNL and the plurality of outer sidewalls EBNL can be arranged on the first planarization layer 19. The plurality of inner sidewalls IBNL and the plurality of outer sidewalls EBNL can be arranged within each sub-pixel PXn in a shape that extends along the second direction DR2, and does not extend to another sub-pixel PXn adjacent along the second direction DR2. For example, the plurality of inner sidewalls IBNL can be arranged within the light-emitting region EMA of each sub-pixel PXn in such a way that the length of their extension along the second direction DR2 does not cross the cut-out region CBA and another sub-pixel PXn, and can be formed to be shorter than the length of the light-emitting region EMA.

[0080] Furthermore, multiple inner dams IBNL can be arranged spaced apart from each other in the first direction DR1 and have a predetermined width in the first direction DR1. The multiple inner dams IBNL can be arranged in an island shape. Two inner dams IBNL can be arranged in a sub-pixel PXn, and the two inner dams IBNL can be arranged spaced apart from each other, so that a light-emitting element 30 is arranged between them.

[0081] While the accompanying drawings illustrate an example of two inner dams (IBNLs) arranged in a single sub-pixel PXn, the arrangement is not limited to this. Depending on the number of alignment electrodes 21 and 22 described later, a greater number of inner dams (IBNLs) can be arranged. Furthermore, the shape of the inner dams (IBNLs) is not limited to this arrangement; they can also be arranged to occupy a smaller or larger area within each sub-pixel PXn.

[0082] The plurality of inner sidewalls IBNLs may have a structure in which at least a portion protrudes relative to the upper surface of the first planarization layer 19. The protruding portions of the plurality of inner sidewalls IBNLs may have inclined sides, and light emitted from the light-emitting element 30 may be reflected by alignment electrodes 21, 22 disposed on the plurality of inner sidewalls IBNLs and emitted toward the upper direction of the first planarization layer 19. While providing an area for arranging the light-emitting element 30, the plurality of inner sidewalls IBNLs may also function as reflective partitions that reflect light emitted from the light-emitting element 30 toward the upper direction. The sides of the plurality of inner sidewalls IBNLs may be inclined in a linear shape, but are not limited thereto; the plurality of inner sidewalls IBNLs may also have a semi-circular or semi-elliptical shape with a curved outer surface. The plurality of inner sidewalls IBNLs may include, but are not limited to, an organic insulating material such as polyimide (PI).

[0083] Multiple outer sidewalls EBNL can be arranged on the first planarization layer 19. For example, multiple outer sidewalls EBNL can be arranged on the first planarization layer 19 in contact with it, thus being arranged on the same layer as multiple inner sidewalls IBNL. The multiple outer sidewalls EBNL can be arranged to surround and divide the light-emitting area EMA and the cut-out area CBA on which the light-emitting element 30 is arranged. The multiple outer sidewalls EBNL can be arranged to extend along the second direction DR2, thus forming a line shape that extends continuously across the entire surface of the display area DPA of the substrate 11. For example, the multiple outer sidewalls EBNL can be formed as a stripe pattern extending in the second direction.

[0084] Multiple outer embankments (EBNLs) can separate inks containing different light-emitting elements 30 distributed according to different sub-pixels (PXn) without mixing with each other. The sides of the multiple outer embankments (EBNLs) can be inclined in a linear shape, but are not limited to this; the multiple outer embankments (EBNLs) can also have a semi-circular or semi-elliptical shape with a curved outer surface. In an exemplary embodiment, the multiple outer embankments (EBNLs) can include an organic insulating material such as polyimide (PI), similar to the multiple inner embankments (IBNLs) described above, but are not limited to this.

[0085] Reference Figure 7 In an exemplary embodiment, the plurality of outer embankments EBNL may include a first outer embankment EBNL1 and a second outer embankment EBNL2. The first outer embankment EBNL1 and the second outer embankment EBNL2 can divide a plurality of pixels PXn arranged along the second direction DR2, and can divide the cut-out region CBA and the light-emitting region EMA of each pixel PX1.

[0086] The first outer dike EBNL1 and the second outer dike EBNL2 can be arranged facing each other and adjacent to each other. The first outer dike EBNL1 and the second outer dike EBNL2 can be arranged with multiple inner dikes IBNL between them and spaced apart from each other. The first outer dike EBNL1 may include a first linear portion LA1 parallel to the inner dikes IBNL and multiple protrusions PR1, PR2, PR3 protruding from the first linear portion LA1 along a first direction DR1. The multiple protrusions PR1, PR2, PR3 may protrude toward the inner dikes IBNL. Similarly, the second outer dike EBNL2 may include a second linear portion LA2 parallel to the inner dikes IBNL and multiple protrusions PR4, PR5, PR6 protruding from the second linear portion LA2 toward the first outer dike EBNL1. The multiple protrusions PR4, PR5, PR6 may protrude toward the inner dikes IBNL.

[0087] The protrusions PR1, PR2, and PR3 of the first outer embankment EBNL1 can be arranged facing each other with the protrusions PR4, PR5, and PR6 of the second outer embankment EBNL2. The protrusions PR1, PR2, and PR3 of the first outer embankment EBNL1 can include a first protrusion PR1, a second protrusion PR2, and a third protrusion PR3 spaced apart from each other. The protrusions PR4, PR5, and PR6 of the second outer embankment EBNL2 can include a fourth protrusion PR4, a fifth protrusion PR5, and a sixth protrusion PR6 spaced apart from each other. The first protrusion PR1 can be arranged facing the fourth protrusion PR4 and on the same horizontal line. The second protrusion PR2 can be arranged facing the fifth protrusion PR5 and on the same horizontal line. The third protrusion PR3 can be arranged facing the sixth protrusion PR6 and on the same horizontal line.

[0088] Each of the plurality of protrusions PR1, PR2, PR3 of the first outer embankment EBNL1 can be arranged at a predetermined interval from each of the plurality of protrusions PR4, PR5, PR6 of the opposing second outer embankment EBNL2. The first interval W1 separating the first protrusion PR1 from the fourth protrusion PR4 can be equal to the second interval W2 separating the second protrusion PR2 from the fifth protrusion PR5 and the third interval W3 separating the third protrusion PR3 from the sixth protrusion PR6.

[0089] In one embodiment, a plurality of outer dams EBNL1, EBNL2 may be arranged extending along and spaced apart from each other in the second direction DR2, thereby guiding the ink to diffuse along the outer dams EBNL1, EBNL2 when ink including the light-emitting element 30 is sprayed, thus preventing ink from overflowing into adjacent sub-pixels PXn. In other words, ink can be diffused along the second direction DR2 between a plurality of protrusions PR1, PR2, PR3 of the first outer dam EBNL1 and a plurality of protrusions PR4, PR5, PR6 of the second outer dam EBNL2, thereby preventing overflow into adjacent sub-pixels PXn in the first direction DR1.

[0090] Furthermore, the intervals W1, W2, and W3 separating the plurality of protrusions PR1, PR2, and PR3 of the first outer dike EBNL1 from the plurality of protrusions PR4, PR5, and PR6 of the second outer dike EBNL2 can be greater than the distance between the plurality of inner dikes IBNL. For example, the plurality of inner dikes IBNL may include the first inner dike IBNL1 and the second inner dike IBNL2. Here, the intervals W1, W2, and W3 separating the plurality of protrusions PR1, PR2, and PR3 of the first outer dike EBNL1 from the plurality of protrusions PR4, PR5, and PR6 of the second outer dike EBNL2 can be configured to be greater than the distance W4 from one side of the first inner dike IBNL1 to the other side of the second inner dike IBNL2. Accordingly, ink including the light-emitting element 30 can easily diffuse along the second direction DR2 in the intervals between the protrusions. That is, ink can easily diffuse in the second interval W2 between the second protrusion PR2 and the fifth protrusion PR5 and the third interval W3 between the third protrusion PR3 and the sixth protrusion PR6.

[0091] The interval W5 between the first linear portion LA1 of the first outer embankment EBNL1 and the second linear portion LA2 of the second outer embankment EBNL2 can be formed identically at any location, so that the light-emitting areas EMA of each pixel PXn are formed with the same area. However, it is not limited to this; in the cutting region CBA, the interval W5 between the first linear portion LA1 of the first outer embankment EBNL1 and the second linear portion LA2 of the second outer embankment EBNL2 can also be configured to be narrower than the interval of the light-emitting areas EMA.

[0092] like Figure 8 As shown, in another exemplary embodiment, the intervals separating the plurality of protrusions PR1, PR2, PR3 of the first outer embankment EBNL1 from the plurality of protrusions PR4, PR5, PR6 of the second outer embankment EBNL2 can be different from each other. For example, the intervals separating the plurality of protrusions PR1, PR2, PR3 of the first outer embankment EBNL1 from the plurality of protrusions PR4, PR5, PR6 of the second outer embankment EBNL2 can gradually increase. That is, the first interval W1 separating the first protrusion PR1 from the fourth protrusion PR4 can be smaller than the second interval W2 separating the second protrusion PR2 from the fifth protrusion PR5, and the second interval W2 separating the second protrusion PR2 from the fifth protrusion PR5 can be smaller than the third interval W3 separating the third protrusion PR3 from the sixth protrusion PR6. However, this is not a limitation; the intervals separating the plurality of protrusions PR1, PR2, PR3 of the first outer embankment EBNL1 from the plurality of protrusions PR4, PR5, PR6 of the second outer embankment EBNL2 can also gradually decrease.

[0093] In one embodiment, as the spacing between the plurality of protrusions PR1, PR2, PR3 of the first outer bank EBNL1 and the plurality of protrusions PR4, PR5, PR6 of the second outer bank EBNL2 gradually decreases, when ink including the light-emitting element 30 is ejected, the reduced spacing between the protrusions causes a capillary effect, allowing for faster diffusion. Accordingly, the ink can be guided to diffuse more quickly in the second direction DR2, thereby preventing spillage onto adjacent pixels in the first direction DR1.

[0094] Furthermore, the height of the multiple outer embankments EBNL can be the same as the height of the multiple inner embankments IBNL. For each of the multiple outer embankments EBNL, the height of the linear portions LA1 and LA2 can be the same as the height of the protrusions PR1, PR2, PR3, PR4, PR5, and PR6. For example, the height of the first linear portion LA1 of the first outer embankment EBNL1 can be the same as the height of the first protrusion PR1, the second protrusion PR2, and the third protrusion PR3. Similarly, the height of the second linear portion LA2 of the second outer embankment EBNL2 can also be the same as the height of the first linear portion LA1, and can be the same as the height of the fourth protrusion PR4, the fifth protrusion PR5, and the sixth protrusion PR6.

[0095] In another exemplary embodiment, for each of the plurality of outer embankments EBNL, the height of the linear portions LA1, LA2 may differ from the height of the protrusions PR1, PR2, PR3, PR4, PR5, PR6. For example, the height of the linear portions LA1, LA2 may be greater than the height of the protrusions PR1, PR2, PR3, PR4, PR5, PR6. The linear portions LA1, LA2 serve to prevent ink, including the light-emitting element 30, from overflowing into adjacent pixels, and therefore preferably have a higher height. Conversely, the protrusions PR1, PR2, PR3, PR4, PR5, PR6 serve to divide the light-emitting area EMA and the cut-out area CBA, and therefore do not need to have a higher height, and can be formed at a lower height, thereby allowing ink to diffuse easily.

[0096] Additionally, refer to Figure 4 and Figure 5 Multiple alignment electrodes 21 and 22 are disposed on multiple inner sidewalls IBNL and the first planarization layer 19. The multiple alignment electrodes 21 and 22 may include a first alignment electrode 21 and a second alignment electrode 22. The first alignment electrode 21 and the second alignment electrode 22 may extend in the second direction DR2 and be disposed spaced apart from each other in the first direction DR1.

[0097] The first alignment electrode 21 and the second alignment electrode 22 may extend along the second direction DR2 within each sub-pixel PXn and be separated from other alignment electrodes 21 and 22 in the cut-out region CBA. For example, a cut-out region CBA may be arranged between the light-emitting regions EMA of adjacent sub-pixels PXn along the second direction DR2, and the first alignment electrode 21 and the second alignment electrode 22 may be separated from other first alignment electrodes 21 and second alignment electrodes 22 arranged in the cut-out region CBA of adjacent sub-pixels PXn along the second direction DR2. However, this is not a limitation; the alignment electrodes 21 and 22 may not be separated for each sub-pixel PXn, but may extend across adjacent sub-pixels PXn along the second direction DR2, or only one of the first alignment electrodes 21 and the second alignment electrode 22 may be separated.

[0098] The first alignment electrode 21 can be electrically connected to the first transistor T1 through the first contact hole CT1, and the second alignment electrode 22 can be electrically connected to the second voltage wiring VL2 through the second contact hole CT2. For example, the first alignment electrode 21 can contact the first conductive pattern CDP through the first contact hole CT1 penetrating the first planarization layer 19 at a predetermined distance from the inner bank IBNL along the second direction DR2. The second alignment electrode 22 can also contact the second voltage wiring VL2 through the second contact hole CT2 penetrating the first planarization layer 19 at a predetermined distance from the inner bank IBNL along the second direction DR2. However, it is not limited to this. In another embodiment, the first contact hole CT1 and the second contact hole CT2 can overlap with the inner bank IBNL.

[0099] Reference Figure 2 and Figure 7 The first contact hole CT1 of the first alignment electrode 21 and the second contact hole CT2 of the second alignment electrode 22 can be arranged between the outer embankments EBNL. Specifically, the first contact hole CT1 of the first alignment electrode 21 and the second contact hole CT2 of the second alignment electrode 22 can be arranged between the second protrusion PR2 of the first outer embankment EBNL1 and the fifth protrusion PR5 of the second outer embankment EBNL2. However, it is not limited to this; the first contact hole CT1 of the first alignment electrode 21 and the second contact hole CT2 of the second alignment electrode 22 can also be arranged in the light-emitting area EMA or the cutting area CBA between the outer embankments EBNL.

[0100] The first alignment electrode 21 and the second alignment electrode 22 may extend along a second direction DR2 between the outer embankments EBNL. The first alignment electrode 21 and the second alignment electrode 22 may be arranged between the protrusions PR1, PR2, PR3 of the first outer embankment EBNL1 and the protrusions PR4, PR5, PR6 of the second outer embankment EBNL2. The first alignment electrode 21 and the second alignment electrode 22 may be arranged without overlapping the outer embankments EBNL, and may be arranged at a predetermined interval from the protrusions PR1, PR2, PR3 of the first outer embankment EBNL1 and the protrusions PR4, PR5, PR6 of the second outer embankment EBNL2.

[0101] Although the accompanying drawings illustrate an example of a configuration where one first alignment electrode 21 and one second alignment electrode 22 are arranged for each sub-pixel PXn, the illustration is not limited to this, and the number of first alignment electrodes 21 and two alignment electrodes 22 arranged for each sub-pixel PXn can be greater. Furthermore, the first alignment electrodes 21 and two alignment electrodes 22 arranged for each sub-pixel PXn do not necessarily have a shape extending in one direction; they can be arranged in various structures. For example, the first alignment electrodes 21 and two alignment electrodes 22 can have a partially curved or tortuous shape, and either electrode can be arranged to surround the other electrode.

[0102] The first alignment electrode 21 and the second alignment electrode 22 can be respectively arranged on the inner embankment IBNL. The first alignment electrode 21 and the second alignment electrode 22 can each be formed to have a width greater than the width of the inner embankment IBNL. For example, the first alignment electrode 21 and the second alignment electrode 22 can each be arranged to completely cover the inner embankment IBNL. The spacing between the first alignment electrode 21 and the second alignment electrode 22 can be narrower than the spacing between the inner embankments IBNL. Furthermore, at least a portion of the first alignment electrode 21 and the second alignment electrode 22 can be directly arranged on the first planarization layer 19, thereby being arranged on the same plane. However, this is not a limitation. Depending on the situation, the width of each alignment electrode 21, 22 can be smaller than the width of the inner embankment IBNL.

[0103] Each alignment electrode 21, 22 may include a conductive material with high reflectivity. For example, each alignment electrode 21, 22 may include metals such as silver (Ag), copper (Cu), aluminum (Al), etc., as materials with high reflectivity, or alloys including aluminum (Al), nickel (Ni), lanthanum (La), etc. Each alignment electrode 21, 22 may cause light emitted from the light-emitting element 30 and traveling towards the side of the inner embankment IBNL to be reflected towards the upper part of each sub-pixel PXn.

[0104] However, this is not the only possibility; each alignment electrode 21, 22 may also include a transparent conductive material. For example, each alignment electrode 21, 22 may include materials such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium zinc tin oxide (IZTO). In several embodiments, each alignment electrode 21, 22 may be constructed by stacking one or more layers of a transparent conductive material and a highly reflective metal layer, or may include the aforementioned materials to form a single layer. For example, each alignment electrode 21, 22 may have a stacked structure of ITO / silver (Ag) / ITO, ITO / Ag / IZO, or ITO / Ag / ITZO / IZO, etc.

[0105] Multiple alignment electrodes 21 and 22 can be electrically connected to the light-emitting element 30 and are subject to a predetermined voltage to make the light-emitting element 30 emit light. The multiple alignment electrodes 21 and 22 can be electrically connected to the light-emitting element 30 through contact electrodes CNE1 and CNE2, and the electrical signals applied to the alignment electrodes 21 and 22 can be transmitted to the light-emitting element 30 through the contact electrodes CNE1 and CNE2.

[0106] Either the first alignment electrode 21 or the second alignment electrode 22 can be electrically connected to the anode electrode of the light-emitting element 30, and the other can be electrically connected to the cathode electrode of the light-emitting element 30. However, this is not a limitation, and the opposite situation may also be possible.

[0107] Furthermore, each alignment electrode 21, 22 can also be used to form an electric field within the sub-pixel PXn for aligning the light-emitting element 30. The light-emitting element 30 can be arranged between the first alignment electrode 21 and the second alignment electrode 22 by means of the electric field formed on the first alignment electrode 21 and the second alignment electrode 22. The light-emitting element 30 of the display device 10 can be sprayed onto the alignment electrodes 21, 22 by an inkjet printing process. If ink including the light-emitting element 30 is sprayed onto the alignment electrodes 21, 22, an alignment signal is applied to the alignment electrodes 21, 22 to generate an electric field. The light-emitting element 30 dispersed in the ink can be aligned on the alignment electrodes 21, 22 by receiving dielectric electrophoretic force through the electric field generated on the alignment electrodes 21, 22.

[0108] The first insulating layer PAS1 is disposed on the first planarization layer 19. The first insulating layer PAS1 can be arranged to cover the inner dam IBNL, the outer dam EBNL, and the first alignment electrode 21 and the second alignment electrode 22. The first insulating layer PAS1 can protect the first alignment electrode 21 and the second alignment electrode 22 while insulating them from each other. Furthermore, it can also prevent the light-emitting element 30 disposed on the first insulating layer PAS1 from being damaged by direct contact with other components.

[0109] The first insulating layer PAS1 can expose at least a portion of each of the first alignment electrode 21 and the second alignment electrode 22. The first insulating layer PAS1 can cover one end of the first alignment electrode 21 and one end of the second alignment electrode 22. The first insulating layer PAS1 can expose the other ends of the first alignment electrode 21 and the other ends of the second alignment electrode 22. The exposed other ends of the first alignment electrode 21 and the second alignment electrode 22 can contact the first contact electrode CNE1 and the second contact electrode CNE2 described later.

[0110] The first insulating layer PAS1 can expose at least a portion of the first planarization layer 19 without overlapping it. The first planarization layer 19 exposed through the first insulating layer PAS1 can be hydrophobically treated to prevent ink, including the light-emitting element 30, from spilling into adjacent pixels.

[0111] The first insulating layer PAS1 can be arranged within the light-emitting region EMA, overlapping the inner embankment IBNL and the light-emitting element 30, and extending along the second direction DR2. At least a portion of the first insulating layer PAS1 is arranged not to cover the cut-out region CBA adjacent to the light-emitting region EMA, such that the first alignment electrode 21 and the second alignment electrode 22 can be short-circuited in the cut-out region CBA. Furthermore, another portion of the first insulating layer PAS1 can respectively cover the outer embankment EBNL and extend along the second direction DR2. The first insulating layer PAS1 can be arranged in an island-shaped pattern.

[0112] The light-emitting element 30 can be disposed on the first insulating layer PAS1 between the first alignment electrode 21 and the second alignment electrode 22. In an exemplary embodiment, the light-emitting element 30 may have a shape extending in one direction, and multiple light-emitting elements 30 may be arranged spaced apart from each other and substantially aligned parallel to each other. The spacing between the light-emitting elements 30 is not particularly limited. Depending on the situation, multiple light-emitting elements 30 may also be arranged adjacent to each other to form a group, and other multiple light-emitting elements 30 may form a group with a predetermined interval, or they may be arranged with a non-uniform density. Furthermore, the direction in which each alignment electrode 21, 22 extends may be substantially perpendicular to the direction in which the light-emitting element 30 extends. However, this is not a limitation; the light-emitting element 30 may also be arranged at an angle rather than perpendicular to the direction in which each alignment electrode 21, 22 extends.

[0113] The light-emitting elements 30 arranged in each sub-pixel PXn may include light-emitting layers containing different materials from each other. Figure 9 The first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 can emit light of a first color, a second color, and a third color, respectively, by including the same type of light-emitting element 30 ("36"). However, this is not a limitation; each sub-pixel PXn can also include the same type of light-emitting element 30 to emit light of substantially the same color.

[0114] The light-emitting element 30 can be arranged on the first insulating layer PAS1 between the respective alignment electrodes 21 and 22. For example, at least one end of the light-emitting element 30 can be arranged on the first alignment electrode 21 or the second alignment electrode 22. As shown, the extension length of the light-emitting element 30 can be longer than the interval between the first alignment electrode 21 and the second alignment electrode 22, and both ends of the light-emitting element 30 are respectively arranged on the first alignment electrode 21 and the second alignment electrode 22. However, it is not limited to this; only one end of the light-emitting element 30 can be arranged on the respective alignment electrodes 21 and 22, or the two ends can not be arranged on the respective alignment electrodes 21 and 22 respectively. Even if the light-emitting element 30 is not arranged on the alignment electrodes 21 and 22, the two ends can still be electrically connected to the respective alignment electrodes 21 and 22 through the contact electrodes CNE1 and CNE2 described later.

[0115] In the light-emitting element 30, multiple layers may be arranged in a direction perpendicular to the upper surface of the substrate 11 or the first planarization layer 19. According to one embodiment, the light-emitting element 30 may have a shape extending in one direction and a structure in which multiple semiconductor layers are arranged sequentially in that direction. The light-emitting element 30 of the display device 10 may be arranged parallel to the first planarization layer 19 in an extending direction, and the multiple semiconductor layers included in the light-emitting element 30 may be arranged sequentially in a direction parallel to the upper surface of the first planarization layer 19. However, this is not a limitation. Depending on the situation, if the light-emitting element 30 has other structures, the multiple layers may also be arranged in a direction perpendicular to the first planarization layer 19.

[0116] Furthermore, the two ends of the light-emitting element 30 can respectively contact the contact electrodes CNE1 and CNE2. According to one embodiment, since an insulating film is not formed on the extended side end surface of the light-emitting element 30... Figure 9 The insulating film 38 (as described in section 38) is partially exposed, allowing the exposed semiconductor and electrode layers to contact the contact electrodes CNE1 and CNE2 as described later. However, this is not a limitation. Depending on the circumstances, for the light-emitting element 30, at least a portion of the insulating film 38 may be removed, and the insulating film 38 may be removed, thereby partially exposing the two end sides of the semiconductor and electrode layers. The exposed sides of the semiconductor and electrode layers may also directly contact the contact electrodes CNE1 and CNE2.

[0117] The second insulating layer PAS2 can be partially disposed on the light-emitting element 30 disposed between the first alignment electrode 21 and the second alignment electrode 22. The second insulating layer PAS2 can be disposed to partially surround the outer surface of the light-emitting element 30. The portion of the second insulating layer PAS2 disposed on the light-emitting element 30 can have a shape extending along the second direction DR2 between the first alignment electrode 21 and the second alignment electrode 22 in a plane. As an example, the second insulating layer PAS2 can be formed into a linear or island pattern within each sub-pixel PXn.

[0118] The second insulating layer PAS2 can be disposed on the light-emitting element 30, exposing one end and the other end of the light-emitting element 30. The exposed end of the light-emitting element 30 can contact the contact electrodes CNE1 and CNE2 described later. The shape of such a second insulating layer PAS2 can be formed using a conventional masking process by patterning the material constituting the second insulating layer PAS2. The mask used to form the second insulating layer PAS2 can have a width narrower than the length of the light-emitting element 30, and the material constituting the second insulating layer PAS2 can be patterned to expose both ends of the light-emitting element 30. However, this is not a limitation.

[0119] The second insulating layer PAS2 can also perform the function of fixing the light-emitting element 30 during the manufacturing process of the display device 10 while protecting the light-emitting element 30. Furthermore, in an exemplary embodiment, a portion of the material of the second insulating layer PAS2 can be disposed between the lower surface of the light-emitting element 30 and the first insulating layer PAS1. As described above, the second insulating layer PAS2 can also be formed to fill the space between the first insulating layer PAS1 formed during the manufacturing process of the display device 10 and the light-emitting element 30. Accordingly, the second insulating layer PAS2 can be arranged to surround the outer surface of the light-emitting element 30, thereby fixing the light-emitting element 30 during the manufacturing process of the display device 10 while protecting it.

[0120] Multiple contact electrodes CNE1, CNE2 and a third insulating layer PAS3 can be arranged on the second insulating layer PAS2.

[0121] Multiple contact electrodes CNE1 and CNE2 may have a shape extending along a unidirectional direction and be arranged on respective alignment electrodes 21 and 22. Contact electrodes CNE1 and CNE2 may include a first contact electrode CNE1 arranged on the first alignment electrode 21 and a second contact electrode CNE2 arranged on the second alignment electrode 22. The contact electrodes CNE1 and CNE2 may be spaced apart from each other and arranged facing each other. For example, the first contact electrode CNE1 and the second contact electrode CNE2 may be arranged on the first alignment electrode 21 and the second alignment electrode 22, respectively, and spaced apart from each other in the first direction DR1. Each contact electrode CNE1 and CNE2 may form a stripe pattern within the light-emitting region EMA of each sub-pixel PXn.

[0122] Multiple contact electrodes CNE1 and CNE2 can respectively contact the light-emitting element 30. The first contact electrode CNE1 can contact one end of the light-emitting element 30, and the second contact electrode CNE2 can contact the other end of the light-emitting element 30. The light-emitting element 30 can expose a semiconductor layer on both end faces in its extending direction, and each contact electrode CNE1 and CNE2 contacts and electrically connects to the semiconductor layer and electrode layer of the light-emitting element 30. The side of the contact electrodes CNE1 and CNE2 that contacts both ends of the light-emitting element 30 can be arranged on the second insulating layer PAS2. Furthermore, the first contact electrode CNE1 can contact the first alignment electrode 21 through a region in the first insulating layer PAS1 that exposes a portion of the upper surface of the first alignment electrode 21, and the second contact electrode CNE2 can contact the second alignment electrode 22 through a region in the first insulating layer PAS1 that exposes a portion of the upper surface of the second alignment electrode 22.

[0123] The width of each contact electrode CNE1, CNE2 measured along one direction can be smaller than the width of each alignment electrode 21, 22 measured along the same direction. Contact electrodes CNE1, CNE2 can contact one end and the other end of the light-emitting element 30, respectively, and are arranged to cover a portion of the upper surface of the first alignment electrode 21 and the second alignment electrode 22. However, this is not a limitation; contact electrodes CNE1, CNE2 can also be formed with a width greater than that of the alignment electrodes 21, 22, thereby covering both sides of the alignment electrodes 21, 22.

[0124] The contact electrodes CNE1 and CNE2 may contain a transparent conductive material. For example, they may include ITO, IZO, ITZO, aluminum (Al), etc. Light emitted from the light-emitting element 30 can pass through the contact electrodes CNE1 and CNE2 and travel toward the respective alignment electrodes 21 and 22. However, it is not limited to this.

[0125] Although the accompanying drawings illustrate a scenario where two contact electrodes CNE1 and CNE2 are arranged in a sub-pixel PXn, this is not the only possibility. The number of each contact electrode CNE1 and CNE2 can vary depending on the number of alignment electrodes 21 and 22 arranged in each sub-pixel PXn.

[0126] The third insulating layer PAS3 is arranged to cover the first contact electrode CNE1. The third insulating layer PAS3 may include the first contact electrode CNE1 and is arranged to cover one side of the first contact electrode CNE1 arranged relative to the second insulating layer PAS2. For example, the third insulating layer PAS3 may be arranged to cover the first contact electrode CNE1 and the first alignment electrode 21. Such an arrangement can be formed after the insulating material layer constituting the third insulating layer PAS3 is arranged over the entire surface of the light-emitting region EMA, by a process of removing a portion of the insulating material layer to form the second contact electrode CNE2. In this process, the insulating material layer constituting the third insulating layer PAS3 may be removed together with the insulating material layer constituting the second insulating layer PAS2, and one side of the third insulating layer PAS3 may be aligned with one side of the second insulating layer PAS2. One side of the second contact electrode CNE2 may be arranged on the third insulating layer PAS3, and the third insulating layer PAS3 is placed between it and insulated from the first contact electrode CNE1.

[0127] Each of the aforementioned first insulating layer PAS1, second insulating layer PAS2, and third insulating layer PAS3 may comprise an inorganic insulating material or an organic insulating material. For example, the first insulating layer PAS1, second insulating layer PAS2, and third insulating layer PAS3 may comprise materials such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon nitride oxide (SiO)x N y Inorganic insulating materials include aluminum oxide (Al₂O₃), aluminum nitride (AlN), etc. Alternatively, they can include organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene, Cardo resin, siloxane resin, silsesquioxane resin, polymethyl methacrylate, polycarbonate, and polymethyl methacrylate-polycarbonate synthetic resin. However, they are not limited to these.

[0128] Figure 9 This is a schematic perspective view of a light-emitting element according to one embodiment.

[0129] Reference Figure 9 The light-emitting element 30, as a particle-type element, can be a rod or cylindrical shape with a predetermined aspect ratio. The light-emitting element 30 can have dimensions ranging from nanometer (1 nm or more and less than 1 μm) to micrometer (1 μm or more and less than 1 mm). In one embodiment, the diameter and length of the light-emitting element 30 can both be nanometer-scale or micrometer-scale. In several other embodiments, the diameter of the light-emitting element 30 can be nanometer-scale, while the length can be micrometer-scale. In several embodiments, a portion of the light-emitting element 30 may have a nanometer-scale diameter and / or length, while another portion has a micrometer-scale diameter and / or length.

[0130] In one embodiment, the light-emitting element 30 may be an inorganic light-emitting diode. Specifically, the light-emitting element 30 may include a semiconductor layer doped with impurities of any conductivity type (e.g., p-type or n-type). The semiconductor layer may receive electrical signals applied from an external power source and emit light in a specific wavelength band.

[0131] According to one embodiment, the light-emitting element 30 may include a first semiconductor layer 31, a light-emitting layer 36, a second semiconductor layer 32, and an electrode layer 37 stacked sequentially in the longitudinal direction. The light-emitting element 30 may also include an insulating film 38 surrounding the outer surfaces of the first semiconductor layer 31, the second semiconductor layer 32, and the light-emitting layer 36.

[0132] The first semiconductor layer 31 may be an n-type semiconductor. When the light-emitting element 30 emits blue light, the first semiconductor layer 31 may include materials with Al... x Ga y In (1-x-y)The semiconductor material has a composition ratio of N (where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ x + y ≤ 1). For example, it can be any one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with n-type dopant. The first semiconductor layer 31 can be doped with an n-type dopant, such as Si, Ge, Sn, etc. For example, the first semiconductor layer 31 can be n-GaN doped with n-type Si. The length of the first semiconductor layer 31 can be in the range of 1.5 μm to 5 μm, but is not limited thereto.

[0133] The second semiconductor layer 32 is disposed on the light-emitting layer 36, which will be described later. The second semiconductor layer 32 may be a p-type semiconductor. When the light-emitting element 30 emits light in the blue or green wavelength range, the second semiconductor layer 32 may include a semiconductor with Al... x Ga y In (1-x-y) The semiconductor material has a composition ratio of N (where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ x + y ≤ 1). For example, it can be any one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with p-type dopant. The second semiconductor layer 32 can be doped with a p-type dopant, such as Mg, Zn, Ca, Se, Ba, etc. For example, the second semiconductor layer 32 can be p-GaN doped with p-type Mg. The length of the second semiconductor layer 32 can be in the range of 0.05 μm to 0.10 μm, but is not limited thereto.

[0134] Furthermore, although the accompanying drawings illustrate a scenario where the first semiconductor layer 31 and the second semiconductor layer 32 constitute a single layer, the invention is not limited thereto. Depending on the material of the light-emitting layer 36, the first semiconductor layer 31 and the second semiconductor layer 32 may also include a greater number of layers (e.g., a cladding layer or a tensile strain barrier reducing (TSBR) layer).

[0135] A light-emitting layer 36 is disposed between a first semiconductor layer 31 and a second semiconductor layer 32. The light-emitting layer 36 may comprise a material having a single quantum well structure or a multiple quantum well structure. When the light-emitting layer 36 comprises a material with a multiple quantum well structure, it may also be a structure in which multiple quantum layers and well layers are alternately stacked. The light-emitting layer 36 emits light through the recombination of electron-hole pairs based on an electrical signal applied through the first semiconductor layer 31 and the second semiconductor layer 32. When the light-emitting layer 36 emits light in the blue wavelength range, it may comprise materials such as AlGaN and AlGaInN. In particular, when the light-emitting layer 36 is a multiple quantum well structure with alternating quantum layers and well layers, the quantum layers may comprise AlGaN or AlGaInN, and the well layers may comprise materials such as GaN or AlInN. For example, the light-emitting layer 36 may comprise AlGaInN as a quantum layer and AlInN as a well layer, thereby, as described above, the light-emitting layer 36 may emit blue light in the range of 450 nm to 495 nm in the central wavelength band.

[0136] However, this is not the only limitation. The light-emitting layer 36 can also be a structure in which semiconductor materials with larger band gap energies and semiconductor materials with smaller band gap energies are alternately stacked, and it can also include group III to group V semiconductor materials, depending on the wavelength of the emitted light. The light emitted by the light-emitting layer 36 is not limited to blue light; it can also emit red or green light, depending on the situation. The length of the light-emitting layer 36 can range from 0.05 μm to 0.10 μm, but is not limited to this.

[0137] Furthermore, the light emitted from the light-emitting layer 36 can be emitted not only towards the outer surface of the light-emitting element 30 along its length, but also towards both sides. The directionality of the light emitted from the light-emitting layer 36 is not limited to one direction.

[0138] Electrode layer 37 can be an ohmic contact electrode. However, it is not limited to this and can also be a Schottky contact electrode. The light-emitting element 30 may include at least one electrode layer 37. Although Figure 8 The illustration shows a scenario where the light-emitting element 30 includes one electrode layer 37, but is not limited to this. Depending on the situation, the light-emitting element 30 may also include more electrode layers 37, or the electrode layers 37 may be omitted. Even if the number of electrode layers 37 is changed or other structures are further included, the following description of the light-emitting element 30 will still apply equally.

[0139] In a display device 10 according to one embodiment, when the light-emitting element 30 is electrically connected to an electrode or a contact electrode, the electrode layer 37 can reduce the resistance between the light-emitting element 30 and the electrode or contact electrode. The electrode layer 37 may include a conductive metal. For example, the electrode layer 37 may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), ITO, IZO, and ITZO. Furthermore, the electrode layer 37 may also include a semiconductor material doped with n-type or p-type semiconductors. The electrode layer 37 may include the same material, or it may include different materials, and is not limited thereto.

[0140] The insulating film 38 is arranged to surround the outer surfaces of the plurality of semiconductor layers and electrode layers. For example, the insulating film 38 may be arranged to at least surround the outer surface of the light-emitting layer 36 and extend in a direction extending from the light-emitting element 30. The insulating film 38 can perform the function of protecting the aforementioned components. The insulating film 38 may be formed to surround the side portions of the components and may be formed to expose both ends of the light-emitting element 30 in the longitudinal direction.

[0141] Although the accompanying drawings illustrate an insulating film 38 extending along the length of the light-emitting element 30 from the first semiconductor layer 31 to the side of the electrode layer 37, the illustration is not limited to this configuration. The insulating film 38 may cover only a portion of the outer surface of the semiconductor layers, including the light-emitting layer 36, or it may cover only a portion of the outer surface of the electrode layers 37, leaving the outer surfaces of each electrode layer 37 partially exposed. Furthermore, the insulating film 38 may also be formed in a manner where its upper surface is arc-shaped in cross-section in a region adjacent to at least one end of the light-emitting element 30.

[0142] The thickness of the insulating film 38 can range from 10 nm to 1.0 μm, but is not limited thereto. Preferably, the thickness of the insulating film 38 can be around 40 nm.

[0143] The insulating film 38 may include a material with insulating properties (e.g., silicon oxide (SiO2)). x ), silicon nitride (SiN) x ), silicon nitride oxide (SiO) x N y (e.g., aluminum nitride (AlN), aluminum oxide (Al2O3), etc.). Although the accompanying drawings illustrate an example of the insulating film 38 being formed as a single layer, it is not limited thereto. In several embodiments, the insulating film 38 may also be formed as a multilayer structure with multiple layers stacked together. Accordingly, electrical short circuits that may occur when the light-emitting layer 36 is in direct contact with the electrodes that transmit electrical signals to the light-emitting element 30 can be prevented. Furthermore, the insulating film 38 can protect the outer surface of the light-emitting element 30, including the light-emitting layer 36, thus preventing a decrease in luminous efficiency.

[0144] Furthermore, the outer surface of the insulating film 38 can be surface-treated. The light-emitting element 30 can be sprayed onto the electrode in a dispersed state within a predetermined ink and aligned. Here, in order to maintain the dispersed state of the light-emitting element 30 from other adjacent light-emitting elements 30 within the ink, the surface of the insulating film 38 can be treated with a hydrophobic or hydrophilic process. For example, the outer surface of the insulating film 38 can be surface-treated with substances such as stearic acid or 2,3-naphthalene dicarboxylicacid.

[0145] The manufacturing process of the display device 10 will now be described with reference to the other accompanying drawings.

[0146] Figures 10 to 15 This is a cross-sectional view showing a manufacturing method of a display device according to an embodiment.

[0147] Reference Figure 10 A substrate 11 is prepared, in which a first transistor T1, voltage wirings VL1 and VL2, a first conductive pattern CDP, and a first planarization layer 19 are disposed. An inner sidewall IBNL and an outer sidewall EBNL are formed on the first planarization layer 19. The inner sidewall IBNL and the outer sidewall EBNL can be configured as organic materials containing photosensitive substances, and they can be formed by exposure and development after coating the organic material layer. The inner sidewall IBNL and the outer sidewall EBNL can be formed simultaneously using the same masking process.

[0148] Next, refer to Figure 11 Alignment electrodes 21 and 22 are formed on the first planarization layer 19 and the inner embankment IBNL. The alignment electrodes 21 and 22 can be formed using a masking process. The alignment electrodes 21 and 22 can be formed by depositing an electrode material layer on the entire surface of the first planarization layer 19 and the inner embankment IBNL and then patterning it. In the patterning process of the electrode material layer, the first alignment electrode 21 and the second alignment electrode 22 extend in one direction and are formed into shapes that are spaced apart from each other.

[0149] Next, a first insulating layer PAS1 is formed on the substrate 11. The first insulating layer PAS1 can be formed by depositing an insulating material layer on the entire surface of the substrate 11. The first insulating layer PAS1 is formed to cover the alignment electrodes 21, 22 and the outer embankment EBNL. The first insulating layer PAS1 is partially etched to expose one end of each of the alignment electrodes 21, 22. Then, a hydrophobic treatment is performed on the first planarization layer 19, the inner embankment IBNL, the outer embankment EBNL, and the alignment electrodes 21, 22 disposed on the substrate 11. The hydrophobic treatment can prevent ink from overflowing into other adjacent sub-pixels PXn during the ink jetting process described later.

[0150] Then, refer to Figure 12 A light-emitting element 30 is disposed on the first insulating layer PAS1. According to one embodiment, the light-emitting element 30 can be disposed in a dispersed state within ink by an inkjet printing process that jets the ink onto alignment electrodes 21, 22. The ink jetted by the inkjet printing apparatus can be disposed within the area surrounded by the outer dam EBNL. The outer dam EBNL prevents ink from overflowing into adjacent sub-pixels PXn.

[0151] If ink including light-emitting elements 30 is sprayed, an electrical signal is applied to each alignment electrode 21, 22, causing multiple light-emitting elements 30 to be arranged on the first insulating layer PAS1. Applying an electrical signal to the multiple alignment electrodes 21, 22 generates an electric field on the alignment electrodes 21, 22. The light-emitting elements 30 dispersed within the ink can receive dielectric electrophoretic force through the electric field, and the light-emitting elements 30 receiving the dielectric electrophoretic force can change their orientation and position to be positioned on the first insulating layer PAS1.

[0152] Next, a second insulating layer PAS2' is formed on the substrate 11. The second insulating layer PAS2' can be formed by depositing an insulating material layer on the entire surface of the substrate 11. The second insulating layer PAS2' can be formed to cover at least a portion of the second alignment electrode 22, the light-emitting element 30, and the first insulating layer PAS1, and the remaining area can be removed by etching. The second insulating layer PAS2' is formed not to overlap with the first alignment electrode 21 and the outer embankment EBNL.

[0153] Next, refer to Figure 13 A first contact electrode CNE1 is formed on the first insulating layer PAS1. The first contact electrode CNE1 can be formed by depositing a contact electrode material layer on the entire surface of the substrate 11 and then patterning it to be disposed on the first insulating layer PAS1, the second insulating layer PAS2', the first alignment electrode 21, and the light-emitting element 30. Furthermore, a portion of the first contact electrode CNE1 can contact the first alignment electrode 21, and another portion can contact one end of the light-emitting element 30. Although not shown, when the patterning process of the first contact electrode CNE1 is performed, the connection between the first alignment electrode 21 and the second alignment electrode 22 exposed in the cut area CBA is broken.

[0154] Next, refer to Figure 14A third insulating layer PAS3 is formed on the substrate 11. The third insulating layer PAS3 insulates the first contact electrode CNE1 to prevent the first contact electrode CNE1 from connecting with the second contact electrode CNE2. The third insulating layer PAS3 is formed by depositing an insulating material layer on the entire surface of the substrate 11 and then patterning it to cover the first alignment electrode 21, the first contact electrode CNE1, the first planarization layer 19, and the second insulating layer PAS2'. When the third insulating layer PAS3 is patterned, the second insulating layer PAS2' is also patterned, so that the second insulating layer PAS2 disposed on the light-emitting element 30 can be formed simultaneously. Accordingly, one side of the second insulating layer PAS2 can be aligned with one side of the third insulating layer PAS3.

[0155] Next, refer to Figure 15 A second contact electrode CNE2 is formed on the first insulating layer PAS1. The second contact electrode CNE2 can be formed by depositing a contact electrode material layer on the entire surface of the substrate 11 and then patterning it so that it can be arranged on the first insulating layer PAS1, the second insulating layer PAS2, the second alignment electrode 22, and the light-emitting element 30. Furthermore, a portion of the second contact electrode CNE2 can contact the second alignment electrode 22, and another portion can contact the other end of the light-emitting element 30.

[0156] In the manufacturing method of the display device according to the above embodiment, the inner dam IBNL and the outer dam EBNL can be formed simultaneously by a mask process, thereby reducing the mask process and reducing manufacturing costs.

[0157] Figure 16 This is a plan view showing a display device according to another embodiment. Figure 17 This is a plan view showing the outer and inner embankments of a display device according to another embodiment.

[0158] Figure 16 and Figure 17 The embodiment shares the outer embankment with the neighboring sub-pixel PXn as described above. Figure 2 and Figure 7 The embodiments differ. Hereinafter, the outer embankment with differences will be described, and the description of the same structure will be omitted.

[0159] Reference Figure 16 and Figure 17According to another embodiment, the display device 10 may include a plurality of outer embankments EBNL. The plurality of outer embankments EBNL may have a shape extending along a second direction DR2 within each sub-pixel PXn and are arranged to extend toward other sub-pixels PXn adjacent to each other along the second direction DR2. For example, in a plurality of outer embankments EBNL dividing a first sub-pixel PX1, the outer embankment EBNL adjacent to a second sub-pixel PX2 may divide the second sub-pixel PX2 simultaneously with dividing the first sub-pixel PX1.

[0160] In an exemplary embodiment, the second outer embankment EBNL2 may include a second linear portion LA2. The second outer embankment EBNL2 may include a fourth protrusion PR4, a fifth protrusion PR5, and a sixth protrusion PR6 protruding from the second linear portion LA2 toward the inner embankment IBNL of the first sub-pixel PX1, and a seventh protrusion PR7, an eighth protrusion PR8, and a ninth protrusion PR9 protruding toward the inner embankment IBNL of the second sub-pixel PX2. The fourth protrusion PR4 and the seventh protrusion PR7 may be arranged on the same horizontal line, the fifth protrusion PR5 and the eighth protrusion PR8 may be arranged on the same horizontal line, and the sixth protrusion PR6 and the ninth protrusion PR9 may be arranged on the same horizontal line.

[0161] This embodiment differs from the above in that the outer bulge EBNL of the first sub-pixel PX1 and the outer bulge EBNL of the second sub-pixel PX2 are integrated. Figure 2 and Figure 7 The embodiments differ. Although the accompanying drawings illustrate a case where the outer dam EBNL arranged between the first sub-pixel PX1 and the second sub-pixel PX2 is relatively thick, it is not limited to this, and the width of the outer dam EBNL can be formed to be thinner. Accordingly, the area occupied by the outer dam EBNL arranged between the first sub-pixel PX1 and the second sub-pixel PX2 can be reduced, thereby increasing the number of sub-pixels PXn. Furthermore, it makes the patterning of the outer dam EBNL easier to process.

[0162] Figure 18 This is a plan view showing a display device according to yet another embodiment. Figure 19 It is along Figure 18 A cross-sectional view taken from the Q4-Q4' line.

[0163] Figure 18 and Figure 19 The embodiment differs from the one described above in that it includes two first alignment electrodes and the light-emitting elements 30 are arranged in two columns spaced apart along the first direction DR1 within a sub-pixel PXn. Figure 3 and Figure 5 The embodiments differ. Hereinafter, the differences will be described, and the descriptions of the same structures will be omitted.

[0164] Reference Figure 18 and Figure 19 Multiple inner sidewalls IBNL1, IBNL2, multiple outer sidewalls EBNL, multiple alignment electrodes 21, 22, light-emitting elements 30, and multiple contact electrodes CNE1, CNE2 can be arranged on the first planarization layer 19. Furthermore, multiple insulating layers PAS1, PAS2, and PAS3 can be arranged on the first planarization layer 19.

[0165] Specifically, multiple inner sidewalls IBNL1 and IBNL2 and multiple outer sidewalls EBNL can be arranged on the substrate 11. The multiple inner sidewalls IBNL1 and IBNL2 may include first inner sidewalls IBNL1 and second inner sidewalls IBNL2. The second inner sidewalls IBNL2 may be arranged between the first inner sidewalls IBNL1. For example, in a sub-pixel PXn, two first inner sidewalls IBNL1 may be arranged with second inner sidewalls IBNL2 placed between them and spaced apart from each other, and a light-emitting element 30 may be arranged between them.

[0166] Multiple alignment electrodes 21 and 22 are disposed on multiple inner sidewalls IBNL1 and IBNL2 and the first planarization layer 19. The multiple alignment electrodes 21 and 22 may include multiple first alignment electrodes 21 and one second alignment electrode 22. The first alignment electrodes 21 may be disposed with the second alignment electrode 22 spaced apart from each other. For example, the first alignment electrode 21 may be disposed on the first inner sidewall IBNL1, and the second alignment electrode 22 may be disposed on the second inner sidewall IBNL2. The first alignment electrode 21 may contact the first conductive pattern through the first contact hole CT1 and the second contact hole CT2, and the second alignment electrode 22 may contact the second voltage wiring through the third contact hole CT3.

[0167] The first insulating layer PAS1 can be arranged to cover the inner dikes IBNL1 and IBNL2, the outer dike EBNL, and the first alignment electrode 21 and the second alignment electrode 22. The first insulating layer PAS1 can expose at least a portion of each of the first alignment electrode 21 and the second alignment electrode 22. The first insulating layer PAS1 can cover one end of each of the first alignment electrode 21 and both ends of the second alignment electrode 22. The first insulating layer PAS1 can expose the other end of each of the first alignment electrode 21 and a portion of the upper part of the second alignment electrode 22. The exposed other end of each of the first alignment electrode 21 and a portion of the upper part of the second alignment electrode 22 can contact the first contact electrode CNE1 and the second contact electrode CNE2, as described later. The first insulating layer PAS1 can be arranged within the light-emitting region EMA, overlapping the inner dikes IBNL1 and IBNL2 and the light-emitting element 30, and extending along the second direction DR2. The first insulating layer PAS1 can be arranged in an island-shaped pattern.

[0168] The light-emitting element 30 can be disposed on the first insulating layer PAS1 between the first alignment electrode 21 and the second alignment electrode 22. The light-emitting element 30 may include a first light-emitting element 30A and a second light-emitting element 30B. For example, the first light-emitting element 30A and the second light-emitting element 30B disposed between the first inner bank IBNL1 and the second inner bank IBNL2 respectively can be arranged symmetrically to each other with reference to the second inner bank IBNL2.

[0169] The first contact electrode CNE1 can be disposed on the first inner embankment IBNL1, and the second contact electrode CNE2 can be disposed on the second inner embankment IBNL2. One end of the first light-emitting element 30A can contact the first contact electrode CNE1, and the other end can contact the second contact electrode CNE2. One end of the second light-emitting element 30B can contact the first contact electrode CNE1, and the other end can contact the second contact electrode CNE2.

[0170] In the above embodiment, a first light-emitting element 30A and a second light-emitting element 30B separated along a first direction DR1 are included in a sub-pixel PXn. A second inner dam IBNL2 and a second contact electrode CNE2 can be arranged between the first light-emitting element 30A and the second light-emitting element 30B. Therefore, the brightness can be improved by increasing the number of light-emitting elements capable of emitting light in a sub-pixel PXn.

[0171] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, it will be understood by those skilled in the art that the invention can be implemented in other specific forms without altering its technical concept or essential features. Therefore, the embodiments described above should be understood as exemplary in all respects, and not limiting.

Claims

1. A display device, comprising: A planarization layer is disposed on the substrate; Multiple inner dikes and multiple outer dikes are arranged on the planarization layer and extend in one direction; The first alignment electrode and the second alignment electrode are arranged on the plurality of inner embankments and are spaced apart from each other; A light-emitting element is disposed on the first alignment electrode and the second alignment electrode, and is disposed between the first alignment electrode and the second alignment electrode; as well as A first contact electrode and a second contact electrode are provided. The first contact electrode is disposed on the first alignment electrode and contacts one end of the light-emitting element, and the second contact electrode is disposed on the second alignment electrode and contacts the other end of the light-emitting element. The plurality of outer dikes and the plurality of inner dikes are arranged on the same layer, and the plurality of outer dikes place the plurality of inner dikes between them and separate them from each other.

2. The display device according to claim 1, wherein, The plurality of inner dikes and the plurality of outer dikes are connected to the planarization layer. The plurality of inner dikes and the plurality of outer dikes are of the same height.

3. The display device according to claim 1, wherein, The plurality of inner dikes are configured in an island shape, and the plurality of outer dikes are configured in a line shape that extends continuously along the one direction.

4. The display device according to claim 1, wherein, The plurality of outer dikes each include a linear portion parallel to the plurality of inner dikes and a plurality of protruding portions that protrude from the linear portion toward the plurality of inner dikes and are spaced apart from each other.

5. The display device according to claim 4, wherein, The plurality of outer dikes includes a first outer dike and a second outer dike that are adjacent to each other. The plurality of protrusions of the second outer embankment are respectively arranged on a horizontal line passing through each of the plurality of protrusions of the first outer embankment.

6. The display device according to claim 5, wherein, The first alignment electrode and the second alignment electrode are arranged between the plurality of protrusions of the first outer embankment and the plurality of protrusions of the second outer embankment.

7. The display device according to claim 5, wherein, The spacing between each of the plurality of protrusions of the first outer embankment and each of the plurality of protrusions of the opposing second outer embankment may be the same or different from each other.

8. The display device according to claim 5, wherein, The plurality of inner dikes includes a first inner dike and a second inner dike that are adjacent to each other. The interval between each of the plurality of protrusions of the first outer dike and each of the plurality of protrusions of the opposing second outer dike is greater than the distance from one side of the first inner dike to the other side of the second inner dike.

9. The display device according to claim 4, wherein, The spacing between opposing linear sections of the plurality of outer embankments is the same.

10. The display device according to claim 1, wherein, The first alignment electrode and the second alignment electrode overlap with the plurality of inner dikes, but do not overlap with the plurality of outer dikes.

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