Display substrate and display device

Abstract

The application discloses a display substrate and a display device. The display substrate comprises a substrate, a display area, a plurality of sub-pixels, a light shielding layer, a first initialization signal line, a light-emitting control signal line, a first power line, a first data line and a second data line. The plurality of sub-pixels are located in the display area and comprise pixel circuit structures. The plurality of sub-pixels comprise a first sub-pixel and a second sub-pixel adjacent along a first direction. The light shielding layer is located between the pixel circuit structures and the substrate and has a light transmission hole. The first initialization signal line and the light-emitting control signal line extend along the first direction. The first power line extends along a second direction. The first direction intersects the second direction. The first data line extends along the second direction and is connected to the pixel circuit structure of the first sub-pixel. The second data line extends along the second direction and is connected to the pixel circuit structure of the second sub-pixel. The first data line and the second data line are located on two sides of the first power line, respectively. The light transmission hole is located in an area enclosed by the first power line, the second data line, the light-emitting control signal line and the first initialization signal line.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to display substrates and display devices. Background Technology

[0002] With the continuous development of display technology, display devices with under-display fingerprint recognition (such as smartphones) are becoming increasingly popular among users. Under-display fingerprint recognition integrates the fingerprint recognition module inside the display panel; fingerprint recognition is achieved by touching the area corresponding to the fingerprint recognition module on the screen glass cover. However, current display devices with under-display fingerprint recognition still suffer from relatively low fingerprint recognition sensitivity.

[0003] Therefore, display devices with under-display fingerprint recognition still need improvement. Summary of the Invention

[0004] In view of this, in one aspect of the present invention, a display substrate is provided. The display substrate includes: a substrate including a display area; a plurality of sub-pixels located in the display area, each sub-pixel including a pixel circuit structure, the plurality of sub-pixels including a first sub-pixel and a second sub-pixel adjacent along a first direction; a light-shielding layer located between the pixel circuit structure and the substrate, the light-shielding layer having a light-transmitting hole; a first initialization signal line extending along the first direction; a light-emitting control signal line extending along the first direction; a first power line extending along a second direction, the first direction intersecting the second direction; a first data line extending along the second direction, the first data line being connected to the pixel circuit structure of the first sub-pixel; a second data line extending along the second direction, the second data line being connected to the pixel circuit structure of the second sub-pixel, the first data line and the second data line being located on opposite sides of the first power line; wherein the light-transmitting hole is located within the area enclosed by the first power line, the second data line, the light-emitting control signal line, and the first initialization signal line. Therefore, a display device using this display substrate has high fingerprint recognition sensitivity and high resolution.

[0005] Furthermore, the display substrate includes a gate line, a reset control signal line, and a second initialization signal line extending along the first direction. In the second direction, the gate line, the reset control signal line, and the second initialization signal line are arranged sequentially on the side of the light emission control signal line away from the first initialization signal line. The pixel circuit structure of the first sub-pixel and the pixel circuit structure of the second sub-pixel are respectively connected to the second initialization signal line.

[0006] Furthermore, in the first direction, the width of the light-transmitting hole is less than 1 / 3 of the distance between the first data line and the second data line. The pixel circuit structure of the first sub-pixel includes a first light-emitting control transistor and a second light-emitting control transistor. The first electrode of the first light-emitting control transistor is located on the first side of the light-emitting control signal line, and the second electrode of the first light-emitting control transistor is located on the second side of the light-emitting control signal line. The first side and the second side are opposite sides of the light-emitting control signal line, and the light-transmitting hole is located between the first electrode of the first light-emitting control transistor and the second electrode of the second light-emitting control transistor.

[0007] Further, in the first direction, the width of the light-transmitting hole is 1 / 3 to 1 / 2 of the distance between the first data line and the second data line. The light-emitting control signal line includes a first sub-section, a second sub-section, and a third sub-section. The first sub-section is located between the second sub-section and the third sub-section. The first sub-section extends along the first direction, and the second and third sub-sections extend along the second direction. In the first direction, at least a portion of the second sub-section is located between the first power line and the second data line. The pixel circuit structure of the first sub-pixel includes a first light-emitting control transistor and a second light-emitting control transistor. The first electrode of the first light-emitting control transistor is located on the first side of the first sub-section, and the second electrode of the first light-emitting control transistor is located on the second side of the first sub-section. The first side and the second side are opposite sides of the first sub-section. The light-transmitting hole is located in the area enclosed by the first power line, the second sub-section, the second electrode of the second light-emitting control transistor, the first electrode of the first light-emitting control transistor, and the first initialization signal line.

[0008] Furthermore, in the first direction, at least a portion of the third sub-part is located on the side of the first data line away from the first power line, and the second sub-part is located on the side of the second electrode of the second light-emitting control transistor away from the first power line.

[0009] Further, in the first direction, the width of the light-transmitting aperture is greater than 1 / 2 of the distance between the first data line and the second data line. The light-emitting control signal line includes a first sub-part, a second sub-part, and a third sub-part. The first sub-part is located between the second sub-part and the third sub-part. The first sub-part extends along the first direction, and the second and third sub-parts extend along the second direction. In the first direction, at least a portion of the second sub-part is located between the first power line and the second data line. The active layer in the pixel circuit structure of the first sub-pixel is located in the area enclosed by the first initialization signal line, the second initialization signal line, the first data line, and the second data line. The active layer in the first sub-pixel is a first active layer. The orthographic projection of the first active layer on the substrate does not overlap with the orthographic projections of the gate line and the light-emitting control signal line on the substrate. The light-transmitting aperture is located in the area enclosed by the first power line, the first sub-part, the second sub-part, and the first initialization signal line.

[0010] Furthermore, in the first direction, at least a portion of the third sub-section is located between the first data line and the first power line.

[0011] Further, the reset control signal line includes a fourth sub-section extending along the first direction and bent portions located at both ends of the fourth sub-section. At least a portion of the fourth sub-section is located between the first data line and the second data line. The gate line includes a fifth sub-section, a sixth sub-section, and a seventh sub-section. The fifth sub-section is located between the sixth and seventh sub-sections. The fifth sub-section extends along the first direction, and the sixth and seventh sub-sections extend along the second direction. In the first direction, at least a portion of the sixth sub-section is located between the first data line and the second data line. The plurality of sub-pixels includes a third sub-pixel adjacent to the second sub-pixel along the first direction. The third data line extends along the second direction and is connected to the pixel circuit of the third sub-pixel. The components are connected, and the portions of the reset control signal line, the gate line, and the light emission control signal line located between the second data line and the third data line all extend along the first direction. The distance between the fourth sub-part and the fifth sub-part is D1. The spacing between the portion of the reset control signal line located between the second data line and the third data line and the portion of the gate line located between the second data line and the third data line is D2, where D1 is less than D2. The spacing between the fifth sub-part and the first sub-part is D3. The spacing between the portion of the gate line located between the second data line and the third data line and the portion of the light emission control signal line located between the second data line and the third data line is D4, where D3 is less than D4.

[0012] Furthermore, the active layer in the pixel circuit structure of the first sub-pixel is located within the area enclosed by the first initialization signal line, the second initialization signal line, the first data line, and the second data line. The active layer in the pixel circuit structure of the second sub-pixel is located within the area enclosed by the first initialization signal line, the second initialization signal line, the second data line, and the third data line. The active layer in the first sub-pixel is a first active layer, and the active layer in the second sub-pixel is a second active layer. The width of the first active layer is D7, and the width of the second active layer is D8, where D7 is less than D8. The length of the first active layer is L1, and the length of the second active layer is L2, where L1 is less than L2.

[0013] Furthermore, in the first direction, when the width of the light-transmitting hole is 1 / 3 to 1 / 2 of the distance between the first data line and the second data line, the first sub-pixel includes a light-emitting element, which is located on the side of the pixel circuit structure away from the substrate. In the second direction, the anode of the light-emitting element is located on the side of the first sub-pixel away from the second electrode of the second light-emitting control transistor.

[0014] Furthermore, the ratio of the active layer width to the gate length of the thin-film transistor in the pixel circuit structure of the first sub-pixel is consistent with the ratio of the active layer width to the gate length of the thin-film transistor in the pixel circuit structure of the second sub-pixel.

[0015] Furthermore, in the first direction, when the width of the light-transmitting hole is greater than 1 / 2 of the distance between the first data line and the second data line, the first sub-pixel includes a light-emitting element, the light-emitting element is located on the side of the pixel circuit structure away from the substrate, and the anode in the light-emitting element is not in contact with the light-emitting layer.

[0016] Furthermore, the orthographic projection of the first active layer on the substrate has no overlapping area with the orthographic projection of the reset control signal line on the substrate.

[0017] Furthermore, the display substrate includes at least one fingerprint recognition area, and the light-transmitting hole is located within the fingerprint recognition area.

[0018] In another aspect, the present invention provides a display device. The display device includes the display substrate described above. Thus, the display device possesses all the features and advantages of the aforementioned display substrate, which will not be repeated here. In general, the display device has high fingerprint recognition sensitivity and high resolution. Attached Figure Description

[0019] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0020] Figure 1A A top view schematic diagram of a first active layer according to an embodiment of the present invention is shown;

[0021] Figure 1B A top view schematic diagram of a lower electrode plate formed on the side of the first active layer away from the substrate according to an embodiment of the present invention, showing a reset control signal line, a gate line, a light emission control signal line, and a storage capacitor portion.

[0022] Figure 1C A top view schematic diagram of a first initialization signal line, a second initialization signal line, and an upper electrode plate of a storage capacitor portion formed on the side away from the substrate of a lower electrode plate of a reset control signal line, a gate line, a light emission control signal line, and a storage capacitor portion according to an embodiment of the present invention is shown.

[0023] Figure 1D A schematic diagram showing vias provided in a first initialization signal line, a second initialization signal line, a first active layer, an upper electrode plate of a storage capacitor, and a lower electrode plate of a storage capacitor according to an embodiment of the present invention is shown.

[0024] Figure 1E A top view schematic diagram of a first data line, a second data line, and a first power line formed on the side of the upper electrode plate of the first initialization signal line, a second initialization signal line, and a storage capacitor portion away from the substrate is shown according to an embodiment of the present invention.

[0025] Figure 1F A schematic diagram of the structure of a first sub-pixel and a second sub-pixel according to an embodiment of the present invention is shown;

[0026] Figure 1G A top view schematic diagram of a first active layer and a second active layer according to an embodiment of the present invention is shown;

[0027] Figure 2 A top view schematic diagram of a light-shielding layer according to an embodiment of the present invention is shown;

[0028] Figure 3 A schematic diagram of the structure of a display substrate according to an embodiment of the present invention is shown;

[0029] Figure 4 A schematic diagram showing the connection relationship between structures in a sub-pixel according to an embodiment of the present invention is provided.

[0030] Figure 5A A top view schematic diagram of the first active layer according to another embodiment of the present invention is shown;

[0031] Figure 5B A top view schematic diagram of a lower electrode plate formed on the side of the first active layer away from the substrate according to another embodiment of the present invention is shown.

[0032] Figure 5C A top view schematic diagram of a first initialization signal line, a second initialization signal line, and an upper electrode plate of a storage capacitor portion, formed on the side away from the substrate of a lower electrode plate of a reset control signal line, a gate line, a light emission control signal line, and a storage capacitor portion according to another embodiment of the present invention, is shown.

[0033] Figure 5D A schematic diagram showing vias provided in a first initialization signal line, a second initialization signal line, a first active layer, an upper electrode plate of a storage capacitor, and a lower electrode plate of a storage capacitor according to another embodiment of the present invention is shown.

[0034] Figure 5E A top view schematic diagram of a first data line, a second data line, and a first power line formed on the side of the upper electrode plate of the first initialization signal line, the second initialization signal line, and the storage capacitor portion away from the substrate is shown according to another embodiment of the present invention.

[0035] Figure 5F A schematic diagram of the structure of a first sub-pixel and a second sub-pixel according to another embodiment of the present invention is shown;

[0036] Figure 5G A top view schematic diagram of a first active layer and a second active layer according to another embodiment of the present invention is shown;

[0037] Figure 6A A top view schematic diagram of the first active layer according to another embodiment of the present invention is shown;

[0038] Figure 6B A top view schematic diagram showing a reset control signal line, a gate line, and a light emission control signal line formed on the side of the first active layer away from the substrate according to another embodiment of the present invention;

[0039] Figure 6C A top view schematic diagram of a first initialization signal line and a second initialization signal line formed on the side of a reset control signal line, a gate line, and a light emission control signal line away from the substrate, according to another embodiment of the present invention;

[0040] Figure 6D A top view schematic diagram showing a first data line, a second data line, and a first power line formed on the side of the first initialization signal line and the second initialization signal line away from the substrate according to another embodiment of the present invention is shown.

[0041] Figure 6EA schematic diagram of the structure of a first sub-pixel and a second sub-pixel according to another embodiment of the present invention is shown;

[0042] Figure 6F A top view schematic diagram of a first active layer and a second active layer according to another embodiment of the present invention is shown;

[0043] Figure 7 The working principle diagram of the 7T1C pixel compensation circuit is shown;

[0044] Figure 8 A schematic diagram of pixel arrangement according to an embodiment of the present invention is shown. Detailed Implementation

[0045] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0046] In one aspect of the invention, a display substrate is provided. According to an embodiment of the invention, reference is made to... Figure 3 The display substrate includes: a substrate 100, a light-shielding layer 200, and a plurality of sub-pixels 300. Figure 3 Only one sub-pixel is shown in the image. The substrate 100 includes a display area, and a plurality of sub-pixels 300 are located in the display area. Each sub-pixel 300 includes a pixel circuit structure 320. A light-shielding layer 200 is located between the pixel circuit structure 320 and the substrate 100. The light-shielding layer 200 has a light-transmitting hole 210 (see reference). Figure 2 , Figure 3 (The light-transmitting hole is not shown in the image).

[0047] refer to Figure 1F The display substrate includes multiple sub-pixels, including a first sub-pixel 300A and a second sub-pixel 300B adjacent to each other along a first direction. It also includes: a first initialization signal line 160A and a light-emitting control signal line 130 extending along the first direction; a first power line 150, a first data line 140A, and a second data line 140B extending along a second direction. The first and second directions intersect. The first data line 140A is connected to the pixel circuit structure of the first sub-pixel 300A, and the second data line 140B is connected to the pixel circuit structure of the second sub-pixel 300B. The first data line 140A and the second data line 140B are located on opposite sides of the first power line 150. A light-transmitting hole 210 in the light-shielding layer is located within the area enclosed by the first power line 150, the second data line 140B, the light-emitting control signal line 130, and the first initialization signal line 160A. Therefore, a display device using this display substrate has high fingerprint recognition sensitivity and high resolution.

[0048] According to an embodiment of the present invention, the display substrate further includes a fingerprint recognition sensor (not shown in the figure). The fingerprint recognition sensor is disposed on the side of the substrate away from the light-shielding layer, and the orthographic projection of the light-transmitting hole on the substrate at least partially overlaps with the orthographic projection of the fingerprint recognition sensor on the substrate. The fingerprint recognition sensor is used to collect the light signal transmitted through the light-transmitting hole, convert the light signal into an electrical signal, extract fingerprint information, and realize fingerprint recognition after data processing. The present invention, by setting a light-shielding layer in the display substrate and setting a light-transmitting hole in the light-shielding layer, utilizes the pinhole imaging principle. During fingerprint recognition, a portion of the light reflected by the finger can enter the fingerprint recognition sensor through the light-transmitting hole, realizing fingerprint recognition. The light-shielding layer can block light from areas outside the light-transmitting hole, preventing light from other areas from interfering with the fingerprint recognition process. Therefore, the fingerprint recognition sensitivity of the display device using this display substrate can be improved. The specific material of the light-shielding layer is not particularly limited; for example, the light-shielding layer can be formed of a metallic material.

[0049] According to an embodiment of the present invention, reference Figure 3 Sub-pixel 300 includes a light-emitting element 310 and a pixel circuit structure 320. The light-emitting element 310 is located on the side of the pixel circuit structure 320 away from the substrate 100. The light-emitting element 310 is an organic light-emitting diode (OLED), which includes an anode, a light-emitting layer, and a cathode. (Reference) Figure 4The pixel circuit structure 320 may include a storage capacitor section 80 and multiple thin-film transistors (such as a first thin-film transistor 10, a second thin-film transistor 20, a third thin-film transistor 30, a fourth thin-film transistor 40, a fifth thin-film transistor 50, a sixth thin-film transistor 60, and a seventh thin-film transistor 70). The electrodes in the thin-film transistors and the metal traces electrically connecting the thin-film transistors, as well as the two electrode plates of the storage capacitor section 80, are all opaque. In this invention, the orthogonal projection of the light-transmitting hole 210 onto the substrate 100 does not overlap with the orthogonal projection of the opaque portion in the pixel circuit structure 320 onto the substrate 100. Therefore, the opaque portion in the pixel circuit structure will not block the light that needs to enter the light-transmitting hole to achieve fingerprint recognition. Furthermore, in this invention, the orthogonal projection of the light-transmitting hole 210 onto the substrate 100 also does not overlap with the orthogonal projection of the electrodes of the light-emitting element 310 onto the substrate 100. As is well known to those skilled in the art, the anode of an organic light-emitting diode can be formed of a transparent conductive material or a metallic material, and the cathode can be formed of a transparent conductive material or a semi-transparent conductive material. When the electrodes of the light-emitting element are formed of a metallic material or a semi-transparent conductive material, since the orthogonal projections of the light-transmitting aperture and the electrodes of the light-emitting element on the substrate do not overlap, the electrodes of the light-emitting element will not block the light that needs to enter the light-transmitting aperture, thus enabling fingerprint recognition. When the electrodes of the light-emitting element are formed of a transparent conductive material, ensuring that the orthogonal projections of the light-transmitting aperture and the electrodes of the light-emitting element on the substrate do not overlap can prevent stray light from affecting fingerprint recognition. For details regarding the opaque portion in the pixel circuit structure and the specific positional relationship between the electrodes and the light-transmitting aperture in the light-emitting element, please refer to the subsequent description.

[0050] The inventors discovered that as the resolution of display devices continues to increase, the size of subpixels is becoming smaller and smaller. However, the pixel circuit structure within a subpixel includes a storage capacitor and multiple thin-film transistors, and this pixel circuit structure occupies a large area of ​​the subpixel, making the design of the light-transmitting aperture difficult. This invention not only incorporates a light-shielding layer in the display substrate but also optimizes the position of the light-transmitting aperture within the light-shielding layer, enabling under-display fingerprint recognition in high-resolution display devices.

[0051] According to an embodiment of the present invention, reference Figure 1C The display substrate also includes a gate line 120, a reset control signal line 110, and a second initialization signal line 160B extending along a first direction. In a second direction, the gate line 120, the reset control signal line 110, and the second initialization signal line 160B are arranged sequentially on the side of the light-emitting control signal line 130 away from the first initialization signal line 160A. The pixel circuit structure of the first sub-pixel 300A and the pixel circuit structure of the second sub-pixel 300B are respectively connected to the second initialization signal line 160B (see reference). Figure 1FThis allows for reserving an area within the sub-pixel corresponding to the light-transmitting aperture, and the aforementioned traces used for signal application do not obstruct the light that needs to enter the light-transmitting aperture, thus enabling fingerprint recognition. The second direction intersects the first direction; specifically, the second direction is perpendicular to the first direction, but not limited to this.

[0052] It should be noted that, Figure 1A This is a top view of the first active layer 321A. Figure 1B This is a top view of the lower electrode plate 81 of the reset control signal line 110, gate line 120, light emission control signal line 130, and storage capacitor portion formed on the side of the first active layer 321A away from the substrate. Figure 1C This is a top view of the first initialization signal line 160A, the second initialization signal line 160B, and the upper electrode plate 82 of the storage capacitor section, which are formed on the side of the lower electrode plate 81 away from the substrate, including the reset control signal line 110, the gate line 120, the light emission control signal line 130, and the storage capacitor section. Figure 1D A schematic diagram showing vias disposed on the first initialization signal line 160A, the second initialization signal line 160B, the first active layer 321A, the upper electrode plate 82 of the storage capacitor section, and the lower electrode plate 81 of the storage capacitor. Figure 1E This is a top view of the first data line 140A, the second data line 140B, and the first power line 150 formed on the side of the upper electrode plate 82 of the storage capacitor section away from the substrate. Figures 1A-1E The stacking order and positional relationship between the various structures are shown, and to facilitate illustrating the positional relationship of the aforementioned structures, Figures 1A-1E The insulating layers between the various structures are not shown; the stacking relationship between the structures and the insulating layers can be referenced. Figure 3 .

[0053] According to an embodiment of the present invention, reference Figure 3The display substrate further includes a protective layer 400 and a buffer layer 500. The protective layer 400 covers the light-shielding layer 200, and the buffer layer 500 is located between the protective layer 400 and the pixel circuit structure 320. The pixel circuit structure 320 includes an active layer 321, a first insulating layer 322, a first gate metal layer 323, a second insulating layer 324, a second gate metal layer 325, an interlayer dielectric layer 326, a source / drain metal layer 327, and a planarization layer 328, which are sequentially stacked on the side of the buffer layer 500 away from the protective layer 400. A portion of the source / drain metal layer 327 passes through... The vias of the interlayer dielectric layer 326, the second insulating layer 324, and the first insulating layer 322 are connected to the active layer 321 to form the source 327A and drain 327B of the thin-film transistor. The light-emitting element 310 includes an anode 311, a pixel defining layer 312, a light-emitting layer 313, and a cathode 314, which are sequentially stacked on the side of the planarization layer 328 away from the interlayer dielectric layer 326. The anode 311 is connected to the source or drain of the thin-film transistor through a via penetrating the planarization layer 328, and the light-emitting layer 313 is connected to the anode 311 through a via penetrating the pixel defining layer 312. The first gate metal layer 323 is used to form the gate of the thin-film transistor, as well as the reset control signal line, gate line, light-emitting control signal line, and the lower electrode plate of the storage capacitor. The second gate metal layer 325 is used to form the first initialization signal line, the second initialization signal line, and the upper electrode plate of the storage capacitor. The source-drain metal layer 327 is used to form the source, drain, first data line, second data line, and first power line of the thin-film transistor. The specific materials constituting each of the above-mentioned film layers are not particularly limited, and those skilled in the art can design them using commonly used materials. The material constituting the protective layer 400 may include silicon oxide. According to an embodiment of the present invention, refer to... Figure 4 The display substrate also includes a second power line (VSS) 170, and the cathode 314 of the light-emitting element 310 is connected to the second power line 170.

[0054] In this invention, each film layer located on the side of the light-shielding layer away from the substrate has high light transmittance (such as protective layer 400, buffer layer 500, first insulating layer 322, second insulating layer 324, interlayer dielectric layer 326, planarization layer 328, etc.). Therefore, it is only necessary to set light-transmitting holes in the light-shielding layer to ensure the stability of the display substrate while realizing fingerprint recognition.

[0055] According to an embodiment of the present invention, reference Figure 2 The light-shielding layer 200 has multiple light-transmitting holes 210, which are arranged periodically (that is, the distance between any two light-transmitting holes 210 in the light-shielding layer 200 is the same). The orthographic projection of each light-transmitting hole 210 on the substrate 100 is located at the orthographic projection of a sub-pixel 300 on the substrate 100 (e.g., ...). Figure 2Within the range of 220 shown.

[0056] It should be noted that the opening size of the multiple light-transmitting holes in the light-shielding layer is consistent. The shape of the light-transmitting holes is not particularly limited; for example, according to an embodiment of the invention, the opening shape of the light-transmitting holes can be square, thereby improving image quality and obtaining clearer fingerprint information.

[0057] The specific period for the arrangement of the light-transmitting holes is not particularly limited, and those skilled in the art can design it according to specific circumstances. For example, it can be designed based on the product's resolution, the size of the subpixels, the thickness of each film layer on the side of the light-shielding layer away from the substrate, and the dielectric constant. Specifically, a light-transmitting hole can be set in an 8×8 pixel unit array, or a light-transmitting hole can be set in a 12×12 pixel unit array. Within the above period, there is no light-transmitting hole in the second subpixel adjacent to the first subpixel. It should be noted that each pixel unit can include multiple subpixels, and the light-transmitting holes are set in the positions described above.

[0058] According to an embodiment of the present invention, reference Figure 3 The display substrate also includes a connection electrode 327C connected to the light-shielding layer 200. The connection electrode 327C is formed from a portion of the source / drain metal layer 327. The connection electrode 327C is connected to the light-shielding layer 200 through a via penetrating the interlayer dielectric layer 326, the second insulating layer 324, the first insulating layer 322, the buffer layer 500, and the protective layer 400. The connection electrode 327C can be connected to the second power line 170. Figure 3 (Not shown in the image) is connected. This prevents the formation of static electricity in the light-shielding layer.

[0059] The following explanation uses a pixel circuit structure comprising 7 thin-film transistors and 1 storage capacitor (i.e., a 7T1C pixel circuit structure) as an example to illustrate the connection relationship between the thin-film transistors and the storage capacitor:

[0060] refer to Figure 4 The first thin-film transistor 10 and the seventh thin-film transistor 70 are reset control transistors, the second thin-film transistor 20 is a threshold compensation transistor, the third thin-film transistor 30 is a drive transistor, the fourth thin-film transistor 40 is a data write transistor, and the fifth thin-film transistor 50 and the sixth thin-film transistor 60 are light-emitting control transistors.

[0061] refer to Figure 1B The gate 13 of the first thin-film transistor is connected to the reset control signal line 110, reference Figure 1B and Figure 1E The source 11 of the first thin-film transistor is connected to the second initialization signal line 160B via the first trace 1, reference. Figure 1D and Figure 1EThe first trace 1 is connected to the source 11 of the first thin-film transistor through via 14, and the first trace 1 is connected to the second initialization signal line 160B through via 15. (Refer to...) Figure 1B and Figure 1E The drain 12 of the first thin-film transistor is connected to the gate 33 of the third thin-film transistor via the second trace 2, reference Figure 1D and Figure 1E The second trace 2 is connected to the drain 12 of the first thin-film transistor through via 24, and the second trace 2 is connected to the gate 33 of the third thin-film transistor through via 25. (Reference) Figure 1B The gate 73 of the seventh thin-film transistor is connected to the reset control signal line 110, reference... Figure 1B and Figure 1E The source 71 of the seventh thin film transistor is connected to the second initialization signal line 160B through the first trace 1, and the drain 72 of the seventh thin film transistor is connected to the anode 311 of the light-emitting element 310 (not shown in Figure 1).

[0062] refer to Figure 1B The gate 23 of the second thin-film transistor is connected to the gate line 120, reference Figure 1B and Figure 1E The source 21 of the second thin-film transistor is connected to the gate 33 of the third thin-film transistor through the second trace 2, and the drain 22 of the second thin-film transistor is connected to the drain 32 of the third thin-film transistor.

[0063] refer to Figure 1B The gate 43 of the fourth thin-film transistor is connected to the gate line 120, reference... Figure 1E The source 41 of the fourth thin-film transistor is connected to the first data line 140A through via 44, and the drain 42 of the fourth thin-film transistor is connected to the source 31 of the third thin-film transistor (see reference). Figure 1B ).

[0064] refer to Figure 1B The gate 53 of the fifth thin-film transistor is connected to the light-emitting control signal line 130, reference... Figure 1E The source 51 of the fifth thin-film transistor is connected to the first power line 150 through via 54, and the drain 52 of the fifth thin-film transistor is connected to the source 31 of the third thin-film transistor (see reference). Figure 1B (That is, the source of the third thin-film transistor, the drain of the fourth thin-film transistor, and the drain of the fifth thin-film transistor are connected to node N2 (reference) Figure 4 )). refer to Figure 1B The gate 63 of the sixth thin-film transistor is connected to the light-emitting control signal line 130, and the source 61 of the sixth thin-film transistor is connected to the drain 32 of the third thin-film transistor (i.e., the drains of the second and third thin-film transistors and the source of the sixth thin-film transistor are connected to node N3 (reference). Figure 4)),refer to Figure 1E The drain 62 of the sixth thin-film transistor is connected to the anode 311 of the light-emitting element 310 through the via 64.

[0065] refer to Figure 1B and Figure 1E The lower electrode plate 81 of the storage capacitor section 80 (reference) Figure 1B It is connected to the source 21 of the second thin-film transistor via the second trace 2 (in Figure 1E In the middle, the position where the lower electrode plate 81 is connected to the second trace 2 is the position where the gate 33 of the third thin-film transistor is connected to the second trace 2 (that is, the source of the second thin-film transistor, the gate of the third thin-film transistor, and the lower electrode plate of the storage capacitor are connected to node N1 (reference). Figure 4 )),refer to Figure 1C and Figure 1E The upper electrode plate 82 of the storage capacitor section 80 is connected to the first power line 150, and the upper electrode plate 82 can be connected through two vias (such as...). Figure 1D and Figure 1E The vias 84 and 85 shown are connected to the first power line 150 to improve the electrical connection performance between the upper electrode plate and the first power line.

[0066] refer to Figure 4 The reset control signal line is used to apply a Reset signal to the first thin-film transistor 10 and the seventh thin-film transistor 70; the gate line is used to apply a Gate signal to the fourth thin-film transistor 40 and the second thin-film transistor 20; the light emission control signal line is used to apply an EM signal to the fifth thin-film transistor 50 and the sixth thin-film transistor 60; the first data line is used to apply a Vdata signal to the fourth thin-film transistor 40; the first power supply line is used to apply a VDD signal to the fifth thin-film transistor 50; and the second initialization signal line is used to apply a Vint signal to the first thin-film transistor 10 and the second thin-film transistor 70.

[0067] According to an embodiment of the present invention, reference Figure 1C , Figure 1D and Figure 1E The display substrate also includes a connection portion 90, which is connected to the first power line 150 via a via 91. This connection portion prevents the first data line from interfering with the first power line.

[0068] To facilitate understanding, the working principle of the 7T1C pixel compensation circuit will be briefly explained below:

[0069] The 7T1C pixel compensation circuit operates in three phases: a reset phase, a sampling phase, and an emission phase, to compensate for the pixel threshold voltage (Vth). (Reference) Figure 7 :

[0070] In phase t1 (i.e., the reset phase), the Reset signal is low. The first thin-film transistor turns on, and the Vint signal initializes point N1, at which point N1 has a potential of Vint. The third thin-film transistor then turns on. The seventh thin-film transistor turns on, and Vint reduces the voltage difference between the anode and cathode of the light-emitting element, thereby reducing the brightness of the light-emitting element at low gray levels and increasing the pixel contrast.

[0071] During phase t2 (i.e., the sampling phase), the Gate signal is low. The fourth thin-film transistor turns on, and the potential at point N2 is Vdata, with the data signal voltage written to point N2. The second thin-film transistor turns on, sampling the connection to the third thin-film transistor. The potential at point N1 rises to Vdata + Vth, and the third thin-film transistor gradually changes from the on state to the off state, compensating for the threshold voltage of the third thin-film transistor.

[0072] During stage t3 (the light-emitting stage), the EM signal is at a low level. The fifth and sixth thin-film transistors are turned on, and the potential at point N2 is VDD. The third thin-film transistor outputs a drive current, and the light-emitting element emits light.

[0073] During the sampling phase, the threshold voltage of the thin-film transistor is compensated to eliminate the impact of the threshold voltage difference of the driving thin-film transistor (i.e., the third thin-film transistor) of different pixels on the uniformity of display brightness.

[0074] In this invention, the width of the light-transmitting hole 210 in the first direction can be less than 1 / 3 of the distance between the first data line and the second data line; alternatively, the width of the light-transmitting hole 210 in the first direction can be 1 / 3 to 1 / 2 of the distance between the first data line and the second data line; or alternatively, the width of the light-transmitting hole 210 in the first direction can be greater than 1 / 2 of the distance between the first data line and the second data line. Specifically:

[0075] According to some embodiments of the present invention, reference Figure 1EIn the first direction, the width of the light-transmitting aperture 210 can be less than 1 / 3 of the distance between the first data line 140A and the second data line 140B. In this case, the pixel circuit structure of the first sub-pixel 300A includes a first light-emitting control transistor (i.e., the fifth thin-film transistor 50) and a second light-emitting control transistor (i.e., the sixth thin-film transistor 60). The first electrode (e.g., the source 51) of the first light-emitting control transistor is located on the first side of the light-emitting control signal line 130, and the second electrode (e.g., the drain 52) of the first light-emitting control transistor is located on the second side of the light-emitting control signal line 130. The second electrode (e.g., the drain 62) of the second light-emitting control transistor is located on the first side of the light-emitting control signal line 130, and the first electrode (e.g., the source 61) of the second light-emitting control transistor is located on the second side of the light-emitting control signal line 130. The first side and the second side are opposite sides of the light-emitting control signal line 130, and the light-transmitting aperture 210 is located between the first electrode 51 of the first light-emitting control transistor and the second electrode 62 of the second light-emitting control transistor. Therefore, the source and drain of the light-emitting control transistor will not block the light-transmitting aperture. Those skilled in the art will understand that the driving transistor, reset control transistor, threshold compensation transistor, data writing transistor, and storage capacitor are all located on the side of the light-emitting control signal line away from the first initialization signal line, so that the source and drain of the transistor and the storage capacitor will not block the light-transmitting hole.

[0076] refer to Figure 1F The first sub-pixel 300A has a light-transmitting hole 210, while the second sub-pixel 300B does not. When the width of the light-transmitting hole 210 is less than 1 / 3 of the distance between the first data line 140A and the second data line 140B, due to the small size of the light-transmitting hole, the positions of the reset control signal line, gate line, light-emitting control signal line, first data line, first power line, and various components in the pixel circuit structure within the first sub-pixel can be consistent with their positions within the second sub-pixel (see reference). Figure 1F Furthermore, the size of the first active layer 321A is the same as the size of the second active layer 321B, and the position of the first active layer 321A within the first sub-pixel is the same as the position of the second active layer 321B within the second sub-pixel (see reference). Figure 1G ).

[0077] It should be noted that the "first active layer" refers to the active layer within the area enclosed by the second initialization signal line, the first initialization signal line, the first data line, and the second data line; the "second active layer" refers to the second initialization signal line, the first initialization signal line, the second data line, and the third data line 140C (reference). Figure 1F The active layer within the enclosed area. The third data line is a data line extending along the second direction and connected to the pixel circuit structure of the third sub-pixel. The third sub-pixel is a sub-pixel adjacent to the second sub-pixel in the first direction (see reference). Figure 1F(Only the third data line in the third sub-pixel is shown in the figure).

[0078] According to other embodiments of the present invention, reference is made to Figures 5A-5E ,in, Figure 5A This is a top view of the first active layer 321A. Figure 5B This is a top view of the lower electrode plate 81 of the reset control signal line 110, gate line 120, light emission control signal line 130, and storage capacitor portion formed on the side of the first active layer 321A away from the substrate. Figure 5C This is a top view of the first initialization signal line 160A, the second initialization signal line 160B, and the upper electrode plate 82 of the storage capacitor section, which are formed on the side of the lower electrode plate 81 away from the substrate, including the reset control signal line 110, the gate line 120, the light emission control signal line 130, and the storage capacitor section. Figure 5D A schematic diagram showing vias disposed on the first initialization signal line 160A, the second initialization signal line 160B, the first active layer 321A, the upper electrode plate 82 of the storage capacitor section, and the lower electrode plate 81 of the storage capacitor. Figure 5E This is a top view of the first data line 140A, the second data line 140B, and the first power line 150 formed on the side of the upper electrode plate 82 of the storage capacitor section away from the substrate. Figures 5A-5E The stacking order and positional relationship between the various structures are shown, and to facilitate illustrating the positional relationship of the aforementioned structures, Figures 5A-5E The insulating layers between the various structures are not shown; the stacking relationship between the structures and the insulating layers can be referenced. Figure 3 .

[0079] refer to Figure 5E In the first direction, the width of the light-transmitting aperture 210 can be 1 / 3 to 1 / 2 of the distance between the first data line 140A and the second data line 140B. At this time, the reference... Figure 5C and Figure 5EThe light-emitting control signal line 130 includes a first sub-section 131, a second sub-section 132, and a third sub-section 133. The first sub-section 131 is located between the second sub-section 132 and the third sub-section 133. The first sub-section 131 extends along a first direction, and the second sub-sections 132 and 133 extend along a second direction. In the first direction, at least a portion of the second sub-section 132 is located between the first power line 150 and the second data line 140B. The pixel circuit structure of the first sub-pixel 300A includes a first light-emitting control transistor (i.e., a fifth thin-film transistor 50) and a second light-emitting control transistor (i.e., a sixth thin-film transistor 60). The first electrode of the first light-emitting control transistor (… For example, the source 51 is located on the first side of the first sub-part 131, the second electrode of the first light-emitting control transistor (such as the drain 52) is located on the second side of the first sub-part 131, the second electrode of the second light-emitting control transistor (such as the drain 62) is located on the first side of the first sub-part 131, and the first electrode of the second light-emitting control transistor (such as the source 61) is located on the second side of the first sub-part 131. The first side and the second side are opposite sides of the first sub-part 131. The light-transmitting hole 210 is located in the area enclosed by the first power line 150, the second sub-part 132, the second electrode 62 of the second light-emitting control transistor, the first electrode 51 of the first light-emitting control transistor, and the first initialization signal line 160A.

[0080] Further, refer to Figure 5E In the first direction, at least a portion of the third sub-section 133 is located on the side of the first data line 140A away from the first power line 150, and the second sub-section 132 is located on the side of the second electrode 62 of the second light-emitting control transistor away from the first power line 150. Therefore, the source and drain of the light-emitting control transistor will not block the light-transmitting aperture, and consequently, the source and drain of the driving transistor, reset control transistor, threshold compensation transistor, data write transistor, and storage capacitor will also not block the light-transmitting aperture.

[0081] It should be noted that, since the light-emitting control signal line is not disposed on the same layer as the first data line and the first power line, "in the first direction, at least a portion of the third sub-part is located on the side of the first data line away from the first power line" means that the orthographic projection of at least a portion of the third sub-part on the substrate is located on the side of the orthographic projection of the first data line on the substrate away from the orthographic projection of the first power line on the substrate. Similarly, "in the first direction, at least a portion of the second sub-part is located between the first power line and the second data line" means that the orthographic projection of at least a portion of the second sub-part on the substrate is located between the orthographic projection of the first power line on the substrate and the orthographic projection of the second data line on the substrate.

[0082] In this embodiment, the size of the light-transmitting hole can be increased to further improve the sensitivity of fingerprint recognition, and it can be applied to display devices with smaller sub-pixel sizes. Traditional fingerprint recognition display devices typically sacrifice resolution by setting a larger light-transmitting hole in a larger sub-pixel; that is, traditional fingerprint recognition display devices usually have a larger light-transmitting hole in a lower-resolution display device. However, this invention can set a larger light-transmitting hole in a smaller sub-pixel, thus making it applicable to higher-resolution display devices, allowing the display device to balance high resolution and high fingerprint recognition sensitivity.

[0083] For more specific details, please refer to Figure 5F The first sub-pixel 300A has a light-transmitting hole 210, while the second sub-pixel 300B does not have a light-transmitting hole. (See reference...) Figure 5C The reset control signal line 110 includes a fourth sub-section 111 extending along a first direction and bent portions 112 located at both ends of the fourth sub-section 111, as shown in the reference. Figure 5F At least part of the fourth sub-section 111 is located between the first data line 140A and the second data line 140B, see reference. Figure 5C and Figure 5F The gate line 120 includes a fifth sub-section 121, a sixth sub-section 122, and a seventh sub-section 123. The fifth sub-section 121 is located between the sixth sub-section 122 and the seventh sub-section 123. The fifth sub-section 121 extends along a first direction, while the sixth sub-section 122 and the seventh sub-section 123 extend along a second direction. In the first direction, at least a portion of the sixth sub-section 122 is located between the first data line 140A and the second data line 140B. A plurality of sub-pixels include a third sub-pixel (not shown) adjacent to the second sub-pixel 300B along the first direction. The third data line 140C extends along the second direction and is connected to the pixel circuit structure of the third sub-pixel. The portions of the reset control signal line 110, the gate line 120, and the light emission control signal line 130 located between the second data line 140B and the third data line 140C all extend along the first direction (see reference). Figure 5F The distance between the fourth sub-pixel 111 and the fifth sub-pixel 121 is D1. The distance between the portion of the reset control signal line 110 located between the second data line 140B and the third data line 140C and the portion of the gate line 120 located between the second data line 140B and the third data line 140C is D2, where D1 is less than D2. The distance between the fifth sub-pixel 121 and the first sub-pixel 131 is D3. The distance between the portion of the gate line 120 located between the second data line 140B and the third data line 140C and the portion of the light emission control signal line 130 located between the second data line 140B and the third data line 140C is D4, where D3 is less than D4. Thus, by narrowing the spacing between the signal lines within the first sub-pixel, a larger area is reserved to correspond to the light-transmitting aperture.

[0084] Since the spacing between signal lines is reduced, in this embodiment, the area of ​​the storage capacitor in the first sub-pixel must also be smaller than the area of ​​the storage capacitor in the second sub-pixel.

[0085] Further, refer to Figure 5F and Figure 5G The active layer in the pixel circuit structure of the first sub-pixel 300A is located within the area enclosed by the first initialization signal line 160A, the second initialization signal line 160B, the first data line 140A, and the second data line 140B. The active layer in the pixel circuit structure of the second sub-pixel 300B is located within the area enclosed by the first initialization signal line 160A, the second initialization signal line 160B, the second data line 140B, and the third data line 140C. The active layer in the first sub-pixel is the first active layer 321A, and the active layer in the second sub-pixel is the second active layer 321B. The width of the first active layer 321A is D7, and the width of the second active layer 321B is D8, where D7 is less than D8. The length of the first active layer 321A is L1, and the length of the second active layer 321B is L2, where L1 is less than L2 (see reference). Figure 5G Therefore, by reducing the size of the first active layer, the connection between the source and drain of the thin-film transistor and each signal line is ensured.

[0086] It should be noted that in this embodiment, the first sub-pixel 300A emits light normally. Therefore, the narrowing of the spacing between the signal lines and the reduction of the size of the first active layer are both based on the premise that the first sub-pixel 300A emits light normally.

[0087] According to an embodiment of the present invention, due to the reduction in the size of the first active layer, the position of the via 44 connecting the first data line 140A to the source of the fourth thin-film transistor is shifted, and the position of the via 54 connecting the first power line 150 to the source of the fifth thin-film transistor is shifted (see reference). Figure 5F Therefore, the portions of the first data line 140A and the first power line 150 that are connected to the pixel circuit structure of the first sub-pixel 300A may have a bent structure (see reference). Figure 5F For example, the portions of the first data line 140A and the first power line 150 that are connected to the pixel circuit structure of the first sub-pixel 300A are bent toward the side closer to the light-transmitting hole 210, so that the first data line 140A can apply a signal to the fourth thin film transistor 40, and the first power line 150 can apply a signal to the fifth thin film transistor 50.

[0088] According to an embodiment of the present invention, when the width of the light-transmitting aperture 210 is 1 / 3 to 1 / 2 of the distance between the first data line 140A and the second data line 140B, the ratio of the active layer width to the gate length of the thin-film transistor in the first sub-pixel 300A is consistent with the ratio of the active layer width to the gate length of the thin-film transistor in the second sub-pixel 300B. Therefore, the display brightness of the first sub-pixel can be consistent with that of the second sub-pixel, ensuring the uniformity of brightness across the entire display screen. It should be noted that the gate length is the dimension of the gate in its extension direction, and the active layer width is the dimension of the active layer perpendicular to the gate extension direction.

[0089] According to an embodiment of the present invention, when the width of the light-transmitting aperture 210 is 1 / 3 to 1 / 2 of the distance between the first data line 140A and the second data line 140B, in the second direction, the anode 311 of the light-emitting element in the first sub-pixel is located on the side of the first sub-part 131 away from the second electrode 62 of the second light-emitting control transistor (see reference). Figure 5E That is, the light-emitting element in the first sub-pixel 300A is moved away from the light-transmitting hole 210 compared to the light-emitting element in the second sub-pixel 300B, to prevent the electrodes of the light-emitting element from blocking the light-transmitting hole. At this time, the drain 62 of the sixth thin-film transistor in the first sub-pixel 300A is connected to the anode 311 of the light-emitting element through the third trace 3 (see reference). Figure 5E ).

[0090] The emission color of the first sub-pixel described above is not particularly limited. For example, the first sub-pixel can be a red-emitting sub-pixel, or a green-emitting sub-pixel, or a blue-emitting sub-pixel. That is to say, when the width of the light-transmitting aperture does not exceed 1 / 2 of the sub-pixel width, the light-transmitting aperture can be set in the region of the light-shielding layer corresponding to the red-emitting sub-pixel, or in the region of the light-shielding layer corresponding to the green-emitting sub-pixel, or in the region of the light-shielding layer corresponding to the blue-emitting sub-pixel.

[0091] According to other embodiments of the present invention, reference is made to Figures 6A-6D ,in, Figure 6A This is a top view of the first active layer 321A. Figure 6B This is a top view schematic diagram of the reset control signal line 110, gate line 120, and light emission control signal line 130 formed on the side of the first active layer 321A away from the substrate. Figure 6C This is a top view showing the first initialization signal line 160A and the second initialization signal line 160B formed on the side of the reset control signal line 110, gate line 120, and light emission control signal line 130 away from the substrate. Figure 6DThis is a top view of the first data line 140A, the second data line 140B, and the first power line 150 formed on the side of the first initialization signal line 160A, the second initialization signal line 160B away from the substrate. Figures 6A-6D The stacking order and positional relationship between the various structures are shown, and to facilitate illustrating the positional relationship of the aforementioned structures, Figures 6A-6D The insulating layers between the various structures are not shown; the stacking relationship between the structures and the insulating layers can be referenced. Figure 3 .

[0092] refer to Figure 6D In the first direction, the width of the light-transmitting hole 210 can be greater than 1 / 2 of the distance between the first data line 140A and the second data line 140B. At this time, the reference... Figure 6C and Figure 6D The light-emitting control signal line 130 includes a first sub-section 131, a second sub-section 132, and a third sub-section 133. The first sub-section 131 is located between the second sub-section 132 and the third sub-section 133. The first sub-section 131 extends along a first direction, while the second sub-section 132 and the third sub-section 133 extend along a second direction. In the first direction, at least a portion of the second sub-section 132 is located between the first power line 150 and the second data line 140B. (Reference) Figure 6A and Figure 6E The active layer in the pixel circuit structure of the first sub-pixel 300A is located within the area enclosed by the first initialization signal line 160A, the second initialization signal line 160B, the first data line 140A, and the second data line 140B. The active layer in the first sub-pixel 300A is the first active layer 321A. (Refer to...) Figure 6B The orthographic projection of the first active layer 321A on the substrate has no overlapping area with the orthographic projection of the gate line 120 and the light-emitting control signal line 130 on the substrate (that is, part of the first active layer 321A is disconnected and discontinuous; in other words, the pixel circuit structure of the first sub-pixel 300A does not have a light-emitting control transistor or a driving transistor). The light-transmitting hole 210 is located in the area enclosed by the first power line 150, the first sub-part 131, the second sub-part 132, and the first initialization signal line 160A.

[0093] Further, refer to Figure 6D In the first direction, at least a portion of the third sub-pixel 133 is located between the first data line 140A and the first power line 150. This allows for a larger area within the first sub-pixel to correspond to the light-transmitting aperture.

[0094] Since a pixel circuit structure needs to be set in the first sub-pixel, when the width of the light-transmitting hole is greater than half the distance between the first and second data lines, the remaining area of ​​the first sub-pixel is no longer sufficient to set up a complete pixel circuit structure. Therefore, in this embodiment, the first sub-pixel can be used as a dummy sub-pixel, that is, the first sub-pixel does not emit light, in order to reduce the setting of thin-film transistors, or even eliminate the setting of thin-film transistors, to ensure that a larger area is reserved in the first sub-pixel to correspond to the light-transmitting hole. In this embodiment, the opening size of the light-transmitting hole is larger, which can further improve the sensitivity of fingerprint recognition, and can be applied to display devices with smaller sub-pixel sizes. That is, this embodiment can set a light-transmitting hole with a larger opening size in a smaller sub-pixel, thereby making it suitable for display devices with higher resolution, so that the display device can balance high resolution and high fingerprint recognition sensitivity.

[0095] In this embodiment, the orthographic projection of the first active layer 321A in the first sub-pixel onto the substrate 100 can also have no overlapping area with the orthographic projection of the reset control signal line 110 onto the substrate 100. This eliminates the need for a reset control transistor, a light-emitting control transistor, a threshold compensation transistor, a data writing transistor, and a driving transistor in the pixel circuit structure of the first sub-pixel, reducing leakage current. In this embodiment, the fabrication of the lower electrode plate of the storage capacitor section can be omitted, simplifying the process and reserving a larger area corresponding to the light-transmitting hole. Furthermore, this invention retains a portion of the first active layer, a portion of the source / drain metal layers, and a portion of the upper electrode plate of the storage capacitor section (see reference). Figure 6C This helps maintain the uniformity of the etching process during the manufacturing of the display substrate, and it can also...

[0096] According to an embodiment of the present invention, when the width of the light-transmitting hole 210 is greater than 1 / 2 of the distance between the first data line 140A and the second data line 140B, the anode in the light-emitting element of the first sub-pixel does not contact the light-emitting layer. Since the first sub-pixel does not emit light, the process of drilling a hole in the pixel defining layer can be eliminated by ensuring that the anode of the light-emitting element does not contact the light-emitting layer.

[0097] According to an embodiment of the present invention, when the width of the light-transmitting aperture 210 is greater than 1 / 2 of the distance between the first data line 140A and the second data line 140B, the reference... Figure 6E The first sub-pixel 300A has a light-transmitting hole 210, while the second sub-pixel 300B does not. In this case, the following conditions are also met: D1 < D2, D3 < D4, D7 < D8, L1 < L2 (refer to...). Figure 6E and Figure 6F (This will not be elaborated upon here.)

[0098] It should be noted that, in this embodiment, since the first sub-pixel 300A does not emit light, the distance between two adjacent signal lines can be further reduced (compared to the scheme where the width of the light-transmitting hole is 1 / 3 to 1 / 2 of the distance between the first data line and the second data line), so that a larger area can be reserved in the first sub-pixel 300A to correspond to the light-transmitting hole.

[0099] In this embodiment, the plurality of sub-pixels includes a fourth sub-pixel (not shown in the figure) adjacent to the first sub-pixel 300A along the second direction. The fourth sub-pixel is a normally emitting sub-pixel, and the material of the light-emitting layer in the fourth sub-pixel is the same as the material of the light-emitting layer in the first sub-pixel. Since the first sub-pixel does not emit light, making the material of the light-emitting layer of the fourth sub-pixel the same as the material of the light-emitting layer of the first sub-pixel allows for brightness compensation through the fourth sub-pixel, ensuring that the display performance of the display device does not significantly decrease.

[0100] For example, taking the red, green, and blue (RGB) three-primary-color scheme as an example, refer to Figure 8 ( Figure 8 (Only some sub-pixels are shown). In the row direction, each row is arranged with a red sub-pixel (R), two green sub-pixels (G) and a blue sub-pixel (B) arranged in the column direction. In the column direction, the red sub-pixel is located in the row corresponding to the area between the green and blue sub-pixels in the previous row, the green sub-pixel is located in the row corresponding to the area between the blue and red sub-pixels in the previous row, and the blue sub-pixel is located in the row corresponding to the area between the red and green sub-pixels in the previous row (i.e., the sub-pixels are staggered in the column direction). This pixel arrangement allows the red and blue sub-pixels to be shared by two adjacent pixel units. For example, B1, R1, and G1 constitute one pixel unit, while B1, R1, and G2 constitute another pixel unit. Furthermore, the aforementioned pixel arrangement ensures that there is another green sub-pixel (e.g., G3) adjacent to the green sub-pixel (e.g., G2). When the width of the light-transmitting aperture in the first direction is greater than half the distance between the first data line and the second data line, the light-transmitting aperture is placed in a green sub-pixel, such as in G2 (i.e., the first sub-pixel 300A is the green sub-pixel G2). In this case, G2 does not emit light. The light emission of the pixel unit composed of B1, R1, and G1 is unaffected, but the light emission of the pixel unit composed of B1, R1, and G2 is affected. In this situation, by increasing the brightness of G3, the brightness of the green light in the pixel unit composed of B1, R1, and G2 can be compensated, alleviating the display performance degradation caused by G2's lack of light emission. Furthermore, the pixel unit composed of B2, R2, and G3 can also emit light normally, resulting in good overall display performance for the display device. The inventors also discovered that when the light-transmitting aperture is placed in a red or blue sub-pixel, noticeable black spots appear during display.

[0101] According to embodiments of the present invention, the display substrate may include at least one fingerprint recognition area, and the fingerprint recognition area has a light-transmitting hole as described above. For example, the display substrate may have one fingerprint recognition area, and during fingerprint recognition, the finger needs to press a specific area (i.e., the fingerprint recognition area) to achieve fingerprint recognition. Alternatively, the display substrate may have multiple fingerprint recognition areas, such as any area within the entire display area of ​​the display substrate can be a fingerprint recognition area, and during fingerprint recognition, the finger can press any area to achieve fingerprint recognition.

[0102] In another aspect, the present invention provides a display device. According to an embodiment of the invention, the display device includes the display substrate described above. Thus, the display device possesses all the features and advantages of the display substrate described above, which will not be repeated here. In general, the display device has high fingerprint recognition sensitivity and high resolution.

[0103] In the description of this invention, the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and are not intended to require that this invention be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0104] In the description of this specification, references to terms such as "one embodiment," "another embodiment," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples, without contradiction. Additionally, it should be noted that in this specification, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0105] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A display substrate, comprising: Substrate, including the display area; Multiple sub-pixels are located in the display area. Each sub-pixel includes a pixel circuit structure. The multiple sub-pixels include a first sub-pixel and a second sub-pixel that are adjacent along a first direction. A light-shielding layer is located between the pixel circuit structure and the substrate, and the light-shielding layer has light-transmitting holes. The display substrate also includes a protective layer and a buffer layer. The protective layer covers the light-shielding layer, and the buffer layer is located between the protective layer and the pixel circuit structure. The substrate further includes a connection electrode connected to the light-shielding layer. The connection electrode is formed from a portion of the source / drain metal layer. The connection electrode passes through a via of the interlayer dielectric layer, the second insulating layer, the first insulating layer, the buffer layer, and the protective layer. The connection electrode is connected to the light-shielding layer and to the second power line. The first initialization signal line extends along the first direction; The light emission control signal line extends along the first direction; A first power line extends along a second direction, and the first direction intersects the second direction; A first data line extends along the second direction and is connected to the pixel circuit structure of the first sub-pixel. The second data line extends along the second direction and is connected to the pixel circuit structure of the second sub-pixel. The first data line and the second data line are located on both sides of the first power line. The light-transmitting hole is located within the area enclosed by the first power line, the second data line, the light-emitting control signal line, and the first initialization signal line, and the light-transmitting hole is located in the first sub-pixel; The pixel circuit structure of the first sub-pixel is different from that of the pixel circuit structure of the second sub-pixel in terms of layout. The spacing between at least one signal line is smaller in the first sub-pixel than in the second sub-pixel. The size of the active layer in the pixel circuit structure of the first sub-pixel is smaller than the size of the active layer in the pixel circuit structure of the second sub-pixel.

2. The display substrate according to claim 1, comprising a gate line, a reset control signal line, and a second initialization signal line extending along the first direction, wherein in the second direction, the gate line, the reset control signal line, and the second initialization signal line are arranged sequentially on the side of the light emission control signal line away from the first initialization signal line, and the pixel circuit structure of the first sub-pixel and the pixel circuit structure of the second sub-pixel are respectively connected to the second initialization signal line.

3. The display substrate according to claim 2, wherein, In the first direction, the width of the light-transmitting hole is less than 1 / 3 of the distance between the first data line and the second data line. The pixel circuit structure of the first sub-pixel includes a first light-emitting control transistor and a second light-emitting control transistor. The first electrode of the first light-emitting control transistor is located on the first side of the light-emitting control signal line, and the second electrode of the first light-emitting control transistor is located on the second side of the light-emitting control signal line. The second electrode of the second light-emitting control transistor is located on the first side of the light-emitting control signal line, and the first electrode of the second light-emitting control transistor is located on the second side of the light-emitting control signal line. The first side and the second side are opposite sides of the light-emitting control signal line. The light-transmitting hole is located between the first electrode of the first light-emitting control transistor and the second electrode of the second light-emitting control transistor.

4. The display substrate according to claim 2, wherein, In the first direction, the width of the light-transmitting hole is 1 / 3 to 1 / 2 of the distance between the first data line and the second data line. The light emission control signal line includes a first sub-section, a second sub-section, and a third sub-section. The first sub-section is located between the second sub-section and the third sub-section. The first sub-section extends along a first direction, and the second and third sub-sections extend along a second direction. In the first direction, at least a portion of the second sub-section is located between the first power line and the second data line. The pixel circuit structure of the first sub-pixel includes a first light-emitting control transistor and a second light-emitting control transistor. The first electrode of the first light-emitting control transistor is located on a first side of the first sub-part, and the second electrode of the first light-emitting control transistor is located on a second side of the first sub-part. The second electrode of the second light-emitting control transistor is located on a first side of the first sub-part, and the first electrode of the second light-emitting control transistor is located on a second side of the first sub-part. The first side and the second side are opposite sides of the first sub-part. The light-transmitting hole is located within the area enclosed by the first power line, the second sub-section, the second electrode of the second light-emitting control transistor, the first electrode of the first light-emitting control transistor, and the first initialization signal line.

5. The display substrate according to claim 4, wherein, In the first direction, at least a portion of the third sub-section is located on the side of the first data line away from the first power line, and the second sub-section is located on the side of the second electrode of the second light-emitting control transistor away from the first power line.

6. The display substrate according to claim 2, wherein, In the first direction, the width of the light-transmitting hole is greater than 1 / 2 of the distance between the first data line and the second data line. The light emission control signal line includes a first sub-section, a second sub-section, and a third sub-section. The first sub-section is located between the second sub-section and the third sub-section. The first sub-section extends along a first direction, and the second and third sub-sections extend along a second direction. In the first direction, at least a portion of the second sub-section is located between the first power line and the second data line. The active layer in the pixel circuit structure of the first sub-pixel is located within the area enclosed by the first initialization signal line, the second initialization signal line, the first data line, and the second data line. The active layer in the first sub-pixel is the first active layer. The orthographic projection of the first active layer on the substrate has no overlapping area with the orthographic projections of the gate line and the light-emitting control signal line on the substrate, and the light-transmitting hole is located in the area enclosed by the first power line, the first sub-section, the second sub-section and the first initialization signal line.

7. The display substrate according to claim 6, wherein, In the first direction, at least a portion of the third sub-section is located between the first data line and the first power line.

8. The display substrate according to claim 6, wherein, The reset control signal line includes a fourth sub-section extending along the first direction and bent portions located at both ends of the fourth sub-section, with at least a portion of the fourth sub-section located between the first data line and the second data line. The gate line includes a fifth sub-section, a sixth sub-section, and a seventh sub-section. The fifth sub-section is located between the sixth and seventh sub-sections. The fifth sub-section extends along a first direction, and the sixth and seventh sub-sections extend along a second direction. In the first direction, at least a portion of the sixth sub-section is located between the first data line and the second data line. The plurality of sub-pixels includes a third sub-pixel adjacent to the second sub-pixel along the first direction. A third data line extends along the second direction and is connected to the pixel circuit structure of the third sub-pixel. The portions of the reset control signal line, the gate line, and the light emission control signal line located between the second data line and the third data line all extend along the first direction. The distance between the fourth sub-part and the fifth sub-part is D1. The distance between the portion of the reset control signal line located between the second data line and the third data line and the portion of the gate line located between the second data line and the third data line is D2. D1 is less than D2. The spacing between the fifth sub-part and the first sub-part is D3, and the spacing between the portion of the gate line located between the second data line and the third data line and the portion of the light emission control signal line located between the second data line and the third data line is D4, wherein D3 is smaller than D4.

9. The display substrate according to claim 8, wherein, The active layer in the pixel circuit structure of the first sub-pixel is located within the area enclosed by the first initialization signal line, the second initialization signal line, the first data line, and the second data line. The active layer in the pixel circuit structure of the second sub-pixel is located within the area enclosed by the first initialization signal line, the second initialization signal line, the second data line, and the third data line. The active layer in the first sub-pixel is a first active layer, and the active layer in the second sub-pixel is a second active layer. The width of the first active layer is D7, and the width of the second active layer is D8, where D7 is smaller than D8. The length of the first active layer is L1, and the length of the second active layer is L2, wherein L1 is less than L2.

10. The display substrate according to any one of claims 3 or 4, wherein, In the first direction, when the width of the light-transmitting hole is 1 / 3 to 1 / 2 of the distance between the first data line and the second data line, the first sub-pixel includes a light-emitting element, which is located on the side of the pixel circuit structure away from the substrate. In the second direction, the anode of the light-emitting element is located on the side of the first sub-pixel away from the second electrode of the second light-emitting control transistor.

11. The display substrate according to claim 10, wherein, The ratio of the active layer width to the gate length of the thin-film transistor in the pixel circuit structure of the first sub-pixel is consistent with the ratio of the active layer width to the gate length of the thin-film transistor in the pixel circuit structure of the second sub-pixel.

12. The display substrate according to claim 9, wherein, In the first direction, when the width of the light-transmitting hole is greater than 1 / 2 of the distance between the first data line and the second data line, The first sub-pixel includes a light-emitting element, which is located on the side of the pixel circuit structure away from the substrate, and the anode in the light-emitting element is not in contact with the light-emitting layer.

13. The display substrate according to claim 12, wherein, The orthographic projection of the first active layer on the substrate has no overlapping area with the orthographic projection of the reset control signal line on the substrate.

14. The display substrate according to claim 1, wherein, The display substrate includes at least one fingerprint recognition area, and the fingerprint recognition area has the light-transmitting hole.

15. A display device comprising the display substrate according to any one of claims 1-14.

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