Display device

Abstract

According to an exemplary embodiment of the present disclosure, there is provided a display device including a display panel divided into a display area and a non-display area and including a substrate, a pixel cell transistor disposed above the substrate and disposed in the display area, a gate-in-panel (GIP) transistor disposed in the non-display area, a conductive pattern disposed below the substrate and disposed in an edge area of the display area and the non-display area, and the conductive pattern being grounded, and a barrier film disposed below the conductive pattern and the substrate. By so doing, edge burn-in due to polarization can be improved.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0111155, filed with the Korean Intellectual Property Office on September 1, 2020, the disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of displays, and more specifically, to display devices such as rollable display devices. Background Technology

[0004] As display devices used as monitors for computers, televisions, or cell phones, there are organic light-emitting display devices (OLEDs) that are self-emissive and liquid crystal display devices (LCDs) that require a separate light source.

[0005] The applications of display devices have diversified to personal digital assistants and monitors for computers and televisions, and research is underway on display devices with large display areas and reduced size and weight.

[0006] Recently, rollable display devices have attracted attention as the next generation of display devices. These rollable display devices are manufactured by forming display elements and wiring on a flexible substrate made of a plastic material such as polyimide (PI) as a flexible material, so that images can be displayed even when the display device is rolled up. Summary of the Invention

[0007] One objective of this disclosure is to provide a display device that can improve edge aging in display devices such as flexible display devices based on polyimide substrates.

[0008] Another objective of this disclosure is to provide a display device that can suppress drive failures of gate in-plate (GIP) cells in a display device, such as a flexible display device based on a polyimide substrate.

[0009] The purpose of this disclosure is not limited to the above-mentioned purposes, and other purposes not mentioned above will be clearly understood by those skilled in the art through the following description.

[0010] To achieve the above objectives, according to one aspect of this disclosure, a display device includes: a display panel divided into a display area and a non-display area and including a substrate; a pixel unit transistor disposed above the substrate and disposed in the display area; a gate-in-plate (GIP) transistor disposed in the non-display area; a conductive pattern disposed below the substrate and disposed in the edge area of ​​the display area and the non-display area, and the conductive pattern being grounded; and a barrier film disposed below the substrate and the conductive pattern.

[0011] To achieve the above objectives, according to another aspect of this disclosure, a display device includes: a display panel divided into a display area and a non-display area and including a substrate; a pixel unit transistor disposed above the substrate and disposed in the display area; a gate-in-plate (GIP) transistor disposed in the GIP area of ​​the non-display area; a conductive pattern disposed on a side surface of the substrate and disposed in the edge area of ​​the display area and the non-display area, and the conductive pattern being grounded; and a barrier film disposed below the substrate and the conductive pattern.

[0012] To achieve the above objectives, according to another aspect of this disclosure, a display device includes: a display panel divided into a display area and a non-display area and including a substrate; a GIP transistor disposed above the substrate and in the GIP area of ​​the non-display area; a recess disposed in the substrate and below the GIP transistor; and a filling layer disposed in the recess.

[0013] Further details of the exemplary implementation are included in the detailed implementation and the accompanying drawings.

[0014] According to this disclosure, edge spots caused by polarization can be improved by counteracting the positive charge in the substrate (e.g., polyimide substrate) in the edge region of the display panel.

[0015] In addition, according to this disclosure, the fluctuation of the threshold voltage Vth of the transistor in the gate in-board (GIP) region is improved, and the drop of the high-potential power supply voltage is improved, thereby improving the reliability of the drive circuit.

[0016] The effects of this disclosure are not limited to those illustrated above, and this specification includes many more effects. Attached Figure Description

[0017] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1A and Figure 1B This is a perspective view of a display device according to a first exemplary embodiment of the present disclosure;

[0019] Figure 2 This is a plan view of a display device according to a first exemplary embodiment of the present disclosure;

[0020] Figure 3 It is along Figure 2 A cross-sectional view taken from line II-II;

[0021] Figure 4This is a schematic plan view of a display panel according to a first exemplary embodiment of the present disclosure;

[0022] Figure 5A and Figure 5B yes Figure 4 A magnified view of region A;

[0023] Figure 6 This is a schematic cross-sectional view of a display panel according to a first exemplary embodiment of the present disclosure;

[0024] Figure 7 This is a cross-sectional view of a portion of a sub-pixel according to a first exemplary embodiment of the present disclosure;

[0025] Figure 8 This is a schematic cross-sectional view of a display panel according to a second exemplary embodiment of the present disclosure;

[0026] Figure 9 This is a schematic cross-sectional view of a display panel according to a third exemplary embodiment of the present disclosure;

[0027] Figure 10 This is a schematic cross-sectional view of a display panel according to a fourth exemplary embodiment of the present disclosure;

[0028] Figure 11 This is a schematic cross-sectional view of a display panel according to a fifth exemplary embodiment of the present disclosure;

[0029] Figure 12 This is a schematic plan view of a display panel according to the sixth illustrative embodiment of the present disclosure;

[0030] Figure 13 This is a cross-sectional view of a portion of the GIP region according to the sixth exemplary embodiment of this disclosure;

[0031] Figure 14A , Figure 14B and Figure 14C It is illustrated in sequence. Figure 13 A cross-sectional view of the manufacturing method of the structure;

[0032] Figure 15 This is a cross-sectional view of a portion of the GIP region according to the seventh exemplary embodiment of this disclosure;

[0033] Figure 16A , Figure 16B and Figure 16C It is illustrated in sequence. Figure 15 A cross-sectional view of the manufacturing method of the structure;

[0034] Figure 17 This is a schematic plan view of a display panel according to the eighth exemplary embodiment of the present disclosure; and

[0035] Figure 18 This is a schematic plan view of a display panel according to the ninth exemplary embodiment of the present disclosure. Detailed Implementation

[0036] The advantages and features of this disclosure, as well as methods for achieving such advantages and features, will become clear from the exemplary embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided by way of example only so that those skilled in the art can fully understand the disclosure and scope of this disclosure. Therefore, this disclosure will be limited only by the scope of the appended claims.

[0037] The shapes, dimensions, ratios, angles, numbers, etc., shown in the accompanying drawings used to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the specification, similar reference numerals generally denote similar elements. Furthermore, in the following description of this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Any reference to the singular may include the plural unless explicitly stated otherwise.

[0038] Even without explicit explanation, components are interpreted as including the normal tolerance range.

[0039] When using terms such as “on,” “above,” “below,” and “next to” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless these terms are used with the terms “immediately following” or “directly.”

[0040] When a component or layer is placed "on" another component or layer, the component or layer may be placed directly on the other component or layer, or other components or layers may be placed in between.

[0041] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, in the technical concept of this disclosure, the first component mentioned below can be the second component.

[0042] Throughout the manual, the same reference numerals usually indicate the same components.

[0043] For ease of description, the dimensions and thickness of each component shown in the accompanying drawings are illustrated, and this disclosure is not limited to the dimensions and thickness of the components shown.

[0044] Features of the various embodiments of this disclosure may be attached to or combined with each other in part or in whole, and may be interlocked and operated in various technical ways, and these embodiments may be performed independently of each other or in association with each other.

[0045] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0046] First, a rollable display device can also be described as a display device that can display images even when rolled up. Compared to general display devices in related technologies, rollable display devices can be highly flexible. The shape of the rollable display device can be freely changed depending on whether it is used. Specifically, when not in use, the rollable display device is rolled up and stored in a reduced volume. Conversely, when in use, the rolled-up display device is unfolded for use.

[0047] However, this disclosure is not limited to rollable display devices, but can be applied to all plastic-based display devices, such as foldable display devices. In the following description, for ease of description, rollable display devices will be used as an example of display devices.

[0048] Figure 1A and Figure 1B This is a perspective view of a display device according to a first exemplary embodiment of the present disclosure.

[0049] Reference Figure 1A and Figure 1B The display device 100 according to a first exemplary embodiment of the present disclosure includes a display unit DP and a housing unit HP.

[0050] A display unit (DP) is a configuration for displaying images to a user, and for example, display elements and circuits, wiring, components, etc. for driving the display elements can be set in the display unit (DP).

[0051] As described above, the display device 100 according to the first exemplary embodiment of this disclosure is a rollable display device 100, and the display unit DP can be configured to be rolled up and unfolded. For example, the display unit DP according to the first exemplary embodiment of this disclosure can be formed of a display panel and a back cover, both of which are flexible enough to be rolled up or unfolded. Reference will be made below. Figure 2 and Figure 3 The display unit (DP) is described in more detail.

[0052] The housing unit HP is a casing that houses the display unit DP. The display unit DP can be rolled up to be housed in the housing unit HP, and the display unit DP can be unfolded to be positioned outside the housing unit HP.

[0053] The housing unit HP has an opening HPO to allow the display unit DP to move inside and outside the housing unit HP. The display unit DP can move vertically by passing through the opening HPO of the housing unit HP.

[0054] The display unit DP of the display device 100 can switch from a fully unfolded state to a fully rolled-up state or vice versa.

[0055] Figure 1A The following is an example of a fully extended display unit DP of a display device 100, wherein in the fully extended state, the display unit DP of the display device 100 is disposed outside the housing unit HP. That is, in order for a user to view an image through the display device 100, the fully extended state can be defined as when the display unit DP is extended to be disposed outside the housing unit HP as much as possible and cannot be extended further.

[0056] Figure 1B The illustration shows a fully rolled-up display unit DP of a display device 100 as an example. In the fully rolled-up state, the display unit DP of the display device 100 is housed within the housing unit HP and cannot be rolled up further. That is, from an aesthetic point of view, it is advantageous for the display unit DP not to be located outside the housing unit HP when the user is not viewing an image through the display device 100. Therefore, when the display unit DP is rolled up to be housed within the housing unit HP, it is defined as the fully rolled-up state.

[0057] When the display unit DP is in a fully rolled-up state to be housed in the housing unit HP, the size of the display device 100 is reduced and the display device 100 can be easily carried.

[0058] To switch the display unit DP to a fully extended or fully rolled-up state, a drive unit that causes the display unit DP to roll up or roll down can be configured.

[0059] Figure 2 This is a plan view of a display device according to a first exemplary embodiment of the present disclosure.

[0060] Figure 3 It is along Figure 2 The cross-sectional view taken from line II-II.

[0061] Reference Figure 2 and Figure 3 The display unit DP according to the first exemplary embodiment of the present disclosure includes a back cover 110, a display panel 120, a flexible film 130, and a printed circuit board 140.

[0062] Display panel 120 is a panel used to display images to the user.

[0063] Display panel 120 may include display elements for displaying images, driving elements for driving the display elements, and wiring for transmitting various signals to the display elements and driving elements. The display elements can be defined in different ways depending on the type of display panel 120. For example, when display panel 120 is an organic light-emitting display panel, the display element may be an organic light-emitting diode (OLED) including an anode, an organic light-emitting layer, and a cathode. For example, when display panel 120 is a liquid crystal display panel, the display element may be a liquid crystal display element. In the following, although it is assumed that display panel 120 is an organic light-emitting display panel, display panel 120 is not limited to organic light-emitting display panels. Furthermore, since the display device 100 according to the first exemplary embodiment of this disclosure is a rollable display device, display panel 120 can be implemented as a flexible display panel to be rolled onto or unrolled from a roller.

[0064] The display panel 120 includes a display area AA and a non-display area NA.

[0065] Display area AA is the area in display panel 120 where images are displayed.

[0066] Within the display area AA, multiple sub-pixels constituting multiple pixels and circuitry for driving these sub-pixels can be arranged. The multiple sub-pixels are the smallest units constituting the display area AA, and display elements can be disposed in each of the multiple sub-pixels. The multiple sub-pixels can constitute a pixel. For example, an organic light-emitting diode (OLED) including an anode, an organic light-emitting layer, and a cathode can be disposed in each of the multiple sub-pixels, but is not limited thereto. Furthermore, the circuitry for driving the multiple sub-pixels can include driving elements, wiring, etc. For example, the circuitry can be composed of thin-film transistors, storage capacitors, gate lines, data lines, etc., but is not limited thereto.

[0067] The non-display area NA is the area where no image is displayed.

[0068] In the non-display area NA, various wiring, circuits, etc., are provided for driving the organic light-emitting diodes in the display area AA. For example, in the non-display area NA, link lines that transmit signals to multiple sub-pixels and circuits in the display area AA, or driver ICs such as gate driver ICs or data driver ICs, may be provided, but it is not limited to these.

[0069] The flexible film 130 is a film in which various components are disposed on a base film with elasticity. Specifically, the flexible film 130 is a film that provides signals to multiple sub-pixels and circuits of the display area AA and is electrically connected to the display panel 120. The flexible film 130 is disposed at one end of the non-display area NA of the display panel 120 to provide power supply voltage or data voltage to the multiple sub-pixels and circuits of the display area AA. Although Figure 2 Four flexible membranes 130 are shown, but the number of flexible membranes 130 can vary depending on the design and is not limited thereto.

[0070] Simultaneously, driver ICs, such as gate driver ICs or data driver ICs, can be disposed on the flexible film 130. The driver IC is a component that processes data for displaying images and drive signals for processing that data. Depending on the mounting method, the driver IC can be disposed as a chip-on-glass (COG), chip-on-film (COF), tape-on-carrier (TCP), etc. However, for ease of description, the driver IC is described as being mounted on the flexible film 130 as a chip-on-film, but it is not limited to this.

[0071] A printed circuit board 140 is disposed at one end of the flexible film 130 for connection to the flexible film 130. The printed circuit board 140 is a component that provides signals to the driver IC. The printed circuit board 140 provides various signals to the driver IC, such as drive signals or data signals. For example, a data driver that generates data signals can be mounted in the printed circuit board 140, and the generated data signals can be provided to multiple sub-pixels and circuits of the display panel 120 through the flexible film 130. Meanwhile, although... Figure 2 A printed circuit board 140 is shown, but the number of printed circuit boards 140 can vary depending on the design and is not limited to this.

[0072] A flexible printed circuit board can also be provided connected to the printed circuit board 140. For example, the printed circuit board 140 can be referred to as the source printed circuit board S-PCB on which a data driver is mounted, and the flexible printed circuit board connected to the printed circuit board 140 can be referred to as the control printed circuit board C-PCB on which a timing controller is mounted. For example, the flexible printed circuit board can be disposed in the roller, or disposed outside the roller and in the receiving unit HP, or disposed in direct contact with the printed circuit board 140.

[0073] A rear cover 110 is disposed on the rear surface of the display panel 120, the flexible film 130, and the printed circuit board 140 to support the display panel 120, the flexible film 130, and the printed circuit board 140. Therefore, the size of the rear cover 110 can be larger than the size of the display panel 120. Thus, the rear cover 110 can protect other configurations of the display unit DP from external influences. Although the rear cover 110 is formed of a rigid material, at least a portion of the rear cover 110 can be flexible to be rolled or unfolded together with the display panel 120. For example, the rear cover 110 can be formed of a metallic material such as stainless steel (SUS) or Invar, or a plastic. However, various materials can be used, and are not limited to these, as long as the material of the rear cover 110 meets physical conditions such as thermal strain, radius of curvature, and stiffness.

[0074] Reference Figure 3 The display panel 120 includes a substrate 121, a buffer layer 122, a pixel unit 123, an encapsulation layer 124, an encapsulation substrate 125, a blocking film 126, and a polarizing plate 127.

[0075] The substrate 121 is a base component that supports various parts of the display panel 120 and may be made of an insulating material. The substrate 121 may be formed of a flexible material to allow the display panel 120 to be rolled up or unrolled, and may be formed, for example, of a plastic material such as polyimide (PI).

[0076] The buffer layer 122 can suppress the diffusion of moisture and / or oxygen that permeates from the outside of the substrate 121. The buffer layer 122 can be composed of a single layer or a double layer of silicon oxide (SiOx) and silicon nitride (SiNx), but is not limited thereto.

[0077] Pixel unit 123 includes a plurality of organic light-emitting diodes (OLEDs) and a pixel driving circuit for driving the OLEDs. Pixel unit 123 may be a region corresponding to display area AA. The OLED may include an anode, an organic light-emitting layer, and a cathode.

[0078] The anode can provide holes to the organic light-emitting layer and is formed of a conductive material with a high work function. For example, the anode can be formed of tin oxide (TO), indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (ITZO), etc., but is not limited to these.

[0079] The organic light-emitting layer is provided with holes from the anode and electrons from the cathode to emit light. Depending on the color of the light emitted from the organic light-emitting layer, it can be formed as a red, green, blue, or white organic light-emitting layer. When the organic light-emitting layer is white, color filters of various colors can be additionally provided.

[0080] The cathode can provide electrons to the organic light-emitting layer and is formed of a conductive material with a low work function. For example, the cathode can be formed of any or more metals selected from the group consisting of, but not limited to, magnesium (Mg), silver (Ag), and aluminum (Al) and their alloys.

[0081] Depending on the emission direction of the light emitted from the organic light-emitting diode, the display panel 120 can be configured as a top-emitting type or a bottom-emitting type.

[0082] According to the top-emitting type, light emitted from the organic light-emitting diode is directed onto the upper part of the substrate 121 on which the organic light-emitting diode is formed. In the case of the top-emitting type, a reflective layer can be formed below the anode to allow light emitted from the organic light-emitting diode to travel towards the upper part of the substrate 121, i.e., towards the cathode.

[0083] According to the bottom-emitting type, light emitted from the organic light-emitting diode is directed to the lower part of the substrate 121 on which the organic light-emitting diode is formed. In the case of the bottom-emitting type, the anode can be formed only of a transparent conductive material, and the cathode can be formed of a metallic material with high reflectivity to allow light emitted from the organic light-emitting diode to travel to the lower part of the substrate 121.

[0084] In the following description, for ease of description, the display device 100 according to the first exemplary embodiment of the present disclosure will be described by assuming that it is a bottom-emitting display device, but is not limited thereto.

[0085] The circuitry for driving the organic light-emitting diodes is disposed in the pixel unit 123. This circuitry can be formed by thin-film transistors, storage capacitors, gate lines, data lines, power lines, etc., but it can vary in various forms depending on the design of the display device 100.

[0086] An encapsulation layer 124 covering the pixel unit 123 is disposed above the pixel unit 123. The encapsulation layer 124 seals the organic light-emitting diode of the pixel unit 123. The encapsulation layer 124 can protect the organic light-emitting diode of the pixel unit 123 from external moisture, oxygen, and impact. The encapsulation layer 124 can be formed by alternately stacking multiple inorganic layers and multiple organic layers. For example, the inorganic layers can be formed of inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), and aluminum oxide (AlOx), and the organic layers can be formed of epoxy resin or acrylic polymer, but they are not limited thereto.

[0087] An encapsulation substrate 125 is disposed above the encapsulation layer 124. Together with the encapsulation layer 124, the encapsulation substrate 125 protects the organic light-emitting diode (OLED) of the pixel unit 123. The encapsulation substrate 125 protects the OLED of the pixel unit 123 from external moisture, oxygen, and impact. The encapsulation substrate 125 can be formed from a metallic material with high corrosion resistance and easy processing into foil or thin film form, such as aluminum (Al), nickel (Ni), chromium (Cr), and alloys of iron (Fe) and nickel. Therefore, since the encapsulation substrate 125 is formed from a metallic material, it can be implemented as an ultrathin film and has high resistance to external impacts and scratches.

[0088] The first adhesive layer AD1 may be disposed between the encapsulation layer 124 and the encapsulation substrate 125. The first adhesive layer AD1 can bond the encapsulation layer 124 and the encapsulation substrate 125 to each other. The first adhesive layer AD1 is formed of an adhesive material and may be a thermosetting adhesive or a self-curing adhesive. For example, the first adhesive layer AD1 may be formed of optically transparent adhesive (OCA), pressure-sensitive adhesive (PSA), etc., but is not limited thereto.

[0089] Simultaneously, the first adhesive layer AD1 can be configured to surround the encapsulation layer 124 and the pixel unit 123. That is, the pixel unit 123 can be sealed by the buffer layer 122 and the encapsulation layer 124, and the encapsulation layer 124 and the pixel unit 123 can be sealed by the buffer layer 122 and the first adhesive layer AD1. The first adhesive layer AD1, together with the encapsulation layer 124 and the encapsulation substrate 125, can protect the organic light-emitting diode of the pixel unit 123 from external moisture, oxygen, and impact. The first adhesive layer AD1 may also include an absorbent. The absorbent can be hygroscopic particles that can absorb moisture and oxygen from the outside to minimize the penetration of moisture and oxygen into the pixel unit 123.

[0090] A barrier film 126 is disposed on the lower surface of the substrate 121. The barrier film 126 protects the display panel 120 from external impacts, moisture, and heat. The barrier film 126 may be made of a polymer resin with lightweight and shatter-resistant properties. For example, the barrier film 126 may be made of a cyclic olefin polymer (COP), but is not limited thereto, and may also be made of materials such as polyimide (PI), polycarbonate (PC), and polyethylene terephthalate (PET).

[0091] The polarizing plate 127 is disposed on the lower surface of the blocking film 126.

[0092] The polarizer 127 is configured to suppress the reflection of external light incident on the display device 100 so that it becomes visible. For example, the polarizer 127 may include a surface layer 127f, a first protective layer 127e, a polarization layer 127d, a second protective layer 127c, a phase retardation layer 127b, and an adhesive layer 127a.

[0093] A surface layer 127f is disposed on the outermost side of the polarizing plate 127 to enhance the mechanical strength of the polarizing plate 127 and suppress glare and reflection, thereby improving the visibility of the display device 100. The surface layer 127f may be formed by a layer or film formed by surface treatment methods such as anti-glare (Ag), semi-glare (SG), low reflection (LR), and anti-glare and low reflection (AGLR), but is not limited thereto.

[0094] An adhesive layer 127a is disposed on the uppermost side of the polarizing plate 127 to bond the polarizing plate 127 to the blocking film 126. The adhesive layer 127a may be formed of, for example, pressure-sensitive adhesive (PSA), but is not limited thereto.

[0095] The phase retardation layer 127b can have a transmission axis of -45 degrees or +45 degrees relative to the polarization angle of external light passing through the polarizing layer 127d. Therefore, external light incident on the phase retardation layer 127b passes through the phase retardation layer 127b and becomes circularly polarized.

[0096] The polarizing layer 127d can linearly polarize light incident from the outside of the display device 100. Therefore, the polarizing layer 127d can be formed by an oriented film formed from a polymer film based on polyvinyl alcohol (PVA) containing iodine or dichroic dyes, but is not limited thereto.

[0097] A first protective layer 127e and a second protective layer 127c can be disposed on both surfaces of the polarizing layer 127d. The polarizing layer 127d is formed of a moisture-absorbing polyvinyl alcohol-based material, such that the first protective layer 127e and the second protective layer 127c are disposed on both surfaces of the polarizing layer 127d. Therefore, damage to the polarizing layer 127d due to heat or moisture can be suppressed. The first protective layer 127e and the second protective layer 127c can be formed of a material without phase difference so as not to affect the polarization state of the polarizing layer 127d. For example, the first protective layer 127e and the second protective layer 127c can be formed of a material such as triacetyl cellulose (TAC), but are not limited thereto.

[0098] The back cover 110 may be disposed above the encapsulation substrate 125. The back cover 110 is configured to contact the encapsulation substrate 125 of the display panel 120 to protect the display panel 120. In order to protect the display panel 120, the back cover 110 may be formed of a rigid material.

[0099] Meanwhile, the back cover 110 may include multiple openings 111.

[0100] Multiple openings 111 allow the back cover 110 to be flexible. The multiple openings 111 can deform flexibly and allow the back cover 110 to be rolled around or unfolded from the roller together with the display panel 120.

[0101] The second adhesive layer AD2 can be disposed between the encapsulation substrate 125 and the back cover 110. The second adhesive layer AD2 can bond the encapsulation substrate 125 and the back cover 110 to each other. The second adhesive layer AD2 is formed of an adhesive material and can be a thermosetting adhesive or a self-curing adhesive. For example, the second adhesive layer AD2 can be formed of optically transparent adhesive (OCA), pressure-sensitive adhesive (PSA), etc., but is not limited thereto.

[0102] Despite Figure 3 The diagram shows that the multiple openings 111 of the back cover 110 are not filled with the second adhesive layer AD2, but the second adhesive layer AD2 may fill some or all of the multiple openings 111. If the second adhesive layer AD2 fills the multiple openings 111 of the back cover 110, the contact area between the second adhesive layer AD2 and the back cover 110 is increased, thereby preventing separation.

[0103] According to this disclosure, in a display device such as a flexible display device based on a polyimide substrate, a conductive pattern is formed in the edge region of the display panel to counteract positive charges in the substrate, such as the polyimide substrate. This improves edge aging. Additionally, according to this disclosure, a portion of the substrate, such as the polyimide substrate, below the transistors in the gate-in-the-panel (GIP) cells is removed or a light-shielding layer is formed to suppress drive failures in the GIP region, as will be described in detail with reference to the accompanying drawings.

[0104] Figure 4 This is a schematic plan view of a display panel according to a first exemplary embodiment of the present disclosure.

[0105] Figure 5A and Figure 5B yes Figure 4 A magnified view of region A.

[0106] Figure 6 This is a schematic cross-sectional view of a display panel according to a first exemplary embodiment of the present disclosure.

[0107] Figure 7 This is a cross-sectional view of a portion of a sub-pixel according to a first exemplary embodiment of the present disclosure.

[0108] Figure 5AAs an example, a portion of a display panel according to a comparative embodiment, excluding the conductive pattern 150 of this disclosure, is shown, and Figure 5B As an example, a display panel including the conductive pattern 150 of this disclosure is shown as part of a first exemplary embodiment.

[0109] exist Figure 6 For ease of description, the polarizing plate is not shown.

[0110] Despite Figure 7 The diagram shows a first transistor T1, a second transistor T2, and a third transistor, but is not limited to these. Additionally, in Figure 7 In the diagram, for ease of description, only a portion of the third transistor and the second transistor T2 are shown.

[0111] Reference Figure 4 The display panel 120 according to the first exemplary embodiment of the present disclosure may include a display area AA and a non-display area NA.

[0112] The display area AA is the area in the display panel 120 where the image is displayed, and a portion of the edge of the display area AA can be defined as the edge area EA.

[0113] The edge region EA can be 5mm wide from the edge of the display region AA, but is not limited to this. The width can vary depending on the pixel design, and a width of 5mm can correspond to the width of approximately ten subpixels.

[0114] The edge region EA corresponds to the edge of the display region AA.

[0115] The non-display area NA is the area where no image is displayed, and the non-display area NA may include a GIP area in which a gate driver is provided.

[0116] The non-display area AA can be adjacent to one or more side surfaces of the display area AA.

[0117] exist Figure 4 The image shows a rectangular display area AA surrounded by a non-display area NA, as an example. However, the shape of the display area AA and the shape and arrangement of the non-display area NA adjacent to the display area AA are not limited to this. Figure 4 The example shown. The display area AA and the non-display area NA can have shapes suitable for the design of an electronic device including the display device 100. Therefore, exemplary shapes of the display area AA can include pentagons, hexagons, circles, ellipses, etc.

[0118] Each pixel in the display area AA may include pixel driving circuitry. Pixel driving circuitry may include one or more switching transistors and one or more driving transistors. Additionally, pixel driving circuitry may include one or more sensing transistors. Each pixel driving circuit may be electrically connected to gate lines and data lines to communicate with gate drivers and data drivers located in the non-display area NA.

[0119] The gate driver and data driver can be implemented by thin-film transistors (TFTs) in the non-display area NA. This type of driver is called a GIP. In addition, some components, such as the data driver IC, can be mounted on separate printed circuit boards and can be coupled to connection interfaces (pads, bumps, or pins) located in the non-display area NA by means of circuit films such as flexible printed circuit boards (FPCBs), chip-on-film (COF), or tape-on-carrier packages (TCPs).

[0120] The display device 100 may also include various additional components to generate various signals or drive pixels in the display area AA. Additional components for driving pixels may include inverter circuits, multiplexers, electrostatic discharge circuits, etc. The display device 100 may also include additional components associated with functions other than pixel driving functions. For example, the display device 100 may include additional components providing touch sensing functions, user authentication functions (e.g., fingerprint recognition), multi-level pressure sensing functions, haptic feedback functions, etc. These additional components may be located in external circuitry connected to the non-display area NA and / or connection interfaces.

[0121] Meanwhile, the display device 100 according to the first exemplary embodiment of the present disclosure forms a conductive pattern 150 in the edge region EA of the display panel 120 to improve edge aging.

[0122] That is, the conductive pattern 150 according to the first exemplary embodiment is formed under the substrate 121 and in the edge region EA and the non-display region NA, and is grounded to cancel the positive charge in the substrate 121. Therefore, edge aging is improved.

[0123] For example, the conductive pattern 150 according to the first exemplary embodiment of this disclosure may be provided in a strip shape on the left and right sides of the display panel 120 where the GIP area is provided, but is not limited thereto. The conductive pattern 150 of this disclosure may be provided in the form of a rectangular frame along the entire edge of the display panel 120.

[0124] Specifically, in flexible display devices, such as those using polyimide as a substrate, edge aging of the display panel becomes a problem. For example, in rollable display devices, polyimide is used as a substrate to ensure rollability.

[0125] Polyimides are essentially composed of solvents and solids, and after curing, mobile charges are generated due to chemical bonds. (See reference...) Figure 5A An electric field is applied (driving) to the display panel, causing the moving charges of the polyimide to move. In the display device, the presence of the light-shielding layer LS between the display area AA and the non-display area NA structurally creates a difference in the electric field. That is, referring to... Figure 7 When the display panel 120 is driven, a (+) electric field can be formed on the light-shielding layer LS below the first transistor T1, and polarized mobile charges are formed on the surface of the polyimide substrate 121 due to this electric field. (-) charges (i.e., negative charges) accumulate on the surface of the substrate 121 below the light-shielding layer LS, and conversely, (+) charges (i.e., positive charges) accumulate in other areas. Conversely, no light-shielding layer or less is provided in the GIP area of ​​the non-display area NA, and (+) and (-) signals are applied alternately.

[0126] During initial and long-term operation, (-) charges move to the area beneath the light-shielding layer LS, which has a strong electric field, while (+) charges are trapped in other areas. Compared to the edge area EA, the entire display panel 120 achieves an electrical equilibrium state through the strong electric fields of the other display areas AA, thus preventing edge aging. For ease of explanation and reference, "other display areas AA" refers to the display areas AA excluding the edge area EA.

[0127] However, in the case of re-driving after driving is complete, the (+) charge trapped in the edge region EA is canceled out (neutralized) by the (-) charge generated during re-driving, and the regenerated (+) charge moves near the lower part of the light-shielding layer LS. This results in a negative shift in Vth of the second transistor T2 to identify aging caused by the brightness difference between the edge region EA and other display regions AA.

[0128] Therefore, in accordance with this disclosure, refer to Figure 6 A conductive pattern 150 is formed below the substrate 121 of the edge region EA of the display panel 120, and the conductive pattern 150 is grounded to cancel the (+) charge trapped in the edge region EA.

[0129] Reference Figure 6 The conductive pattern 150 of the first exemplary embodiment of this disclosure may be formed under the substrate 121 and in the edge region EA and the non-display region NA.

[0130] The conductive pattern 150 can be composed of conductive strips, but is not limited to this.

[0131] After the laser lift-off (LLO) process, conductive strips can be laminated onto the outer periphery of the display panel 120. Subsequently, a barrier film 126 can be laminated.

[0132] That is, the display panel 120 according to the first exemplary embodiment of the present disclosure may include a substrate 121 on which thin film transistors T1 and T2 and an organic light-emitting diode 160 are disposed, an encapsulation substrate 125, a barrier film 126, etc.

[0133] The substrate 121 can be a glass or plastic substrate. When the substrate is a plastic substrate, a polyimide-based or polycarbonate-based material is used, allowing the substrate to be flexible. Specifically, polyimide can be used in high-temperature processes and can be coated, therefore polyimide is frequently used in plastic substrates.

[0134] Buffer layer 122 is a functional layer that protects the transistor from impurities such as alkali ions, moisture, and / or oxygen leaking from substrate 121 or its underlying layers. Buffer layer 122 may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. Buffer layer 122 may include multiple buffer layers and / or active buffer layers. Multiple buffer layers may be constructed by alternating layers of silicon oxide (SiOx) and silicon nitride (SiNx) and perform the function of delaying the diffusion of moisture and / or oxygen penetrating into substrate 121. Active buffer layers perform the following functions: protecting the active layers ACT1, ACT2, and ACT3 of transistors T1 and T2 and blocking various types of defects flowing out from substrate 121.

[0135] Pixel unit 123 includes an organic light-emitting diode 160 and a pixel driving circuit for driving the organic light-emitting diode 160. Pixel unit 123 may be an area corresponding to display area AA.

[0136] The organic light-emitting diode 160 may include an anode 161, an organic layer 162, and a cathode 163.

[0137] At least one first transistor T1, a second transistor T2, and a third transistor may be disposed on the buffer layer 122. The first transistor T1 may be a driving transistor, the second transistor T2 may be a sensing transistor, and the third transistor may be a switching transistor, but is not limited thereto.

[0138] The first transistor T1 may include a first active layer ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1.

[0139] The second transistor T2 may include a second active layer ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode.

[0140] The third transistor may include a third active layer ACT3, a third gate electrode, a third source electrode, and a third drain electrode.

[0141] The light-shielding layer LS can be set on the buffer layer 122.

[0142] The light-shielding layer LS is configured to overlap with the first active layer ACT1 of the first transistor T1 to protect the first transistor T1 from externally introduced light or moisture, thereby minimizing the deformation of the device characteristics of the first transistor T1. Although in Figure 7 The diagram shows that the light-shielding layer LS is electrically connected to the first drain electrode DE1, but the light-shielding layer LS can be floating, and is therefore not limited to this.

[0143] The first insulating layer 115a can be disposed on the light-shielding layer LS.

[0144] The first insulating layer 115a can be configured as a single layer or multiple layers of silicon nitride SiNx or silicon oxide SiOx.

[0145] The first active layer ACT1, the second active layer ACT2, and the third active layer ACT3 can be disposed on the first insulating layer 115a. The first active layer ACT1, the second active layer ACT2, and the third active layer ACT3 can be formed of an oxide semiconductor material.

[0146] However, it is not limited to this, so the first active layer ACT1, the second active layer ACT2 and the third active layer ACT3 can be formed of amorphous silicon a-Si or various organic semiconductor materials such as pentacene.

[0147] The gate insulating layer 115b is disposed on the first active layer ACT1 and the second active layer ACT2, and the first gate electrode GE1 and the second gate electrode GE2 can be disposed on the gate insulating layer 115b.

[0148] The gate insulating layer 115b can be configured as a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx).

[0149] The first gate electrode GE1 and the second gate electrode GE2 can be formed from various conductive materials, such as magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), gold (Au), or alloys thereof, but are not limited thereto.

[0150] The second insulating layer 115c can be disposed on the first gate electrode GE1 and the second gate electrode GE2.

[0151] The second insulating layer 115c is an interlayer insulating layer and can be formed of an insulating inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx) or an insulating organic material. The second insulating layer 115c and / or the first insulating layer 115a are selectively removed to form a contact hole through which the source and drain regions of the light-shielding layer LS, the second gate electrode GE2, and the first active layer ACT1 are exposed.

[0152] The first source electrode SE1 and the first drain electrode DE1 can be disposed on the second insulating layer 115c. The first source electrode SE1 and the first drain electrode DE1, which are spaced apart from each other, can be electrically connected to the first active layer ACT1. In addition, the first drain electrode DE1 can also be electrically connected to the light-shielding layer LS.

[0153] The second source electrode SE2 can be disposed on the second insulating layer 115c. The second source electrode SE2 can be electrically connected to the second gate electrode GE2 and the third active layer ACT3.

[0154] The third insulating layer 115d can be disposed on the first source electrode SE1, the first drain electrode DE1, and the second source electrode SE2.

[0155] The third insulating layer 115d is a planarization layer used to protect transistors T1 and T2 and to planarize their upper parts. The third insulating layer 115d can be formed in various forms, such as an organic insulating layer of benzocyclobutene (BCB) or acrylic, or an inorganic insulating layer of silicon oxide (SiOx) or silicon nitride (SiNx), or it can be formed as a single layer, double layer, or multiple layers.

[0156] The organic light-emitting diode 160 can be disposed on the third insulating layer 115d.

[0157] The organic light-emitting diode 160 may include an anode 161, an organic layer 162 formed on the anode 161, and a cathode 163 formed on the organic layer 162.

[0158] The organic light-emitting diode 160 can be configured to have a single light-emitting layer structure that emits only a single light, or it can be configured to have a structure consisting of multiple light-emitting layers to emit white light. When the organic light-emitting diode 160 emits white light, a color filter can also be provided. The organic light-emitting diode 160 can be disposed in the middle of the substrate 101 corresponding to the display area AA.

[0159] The anode 161 can be disposed on the third insulating layer 115d. The anode 161 can be electrically connected to the first drain electrode DE1 of the first transistor T1 through a contact hole.

[0160] Anode 161 provides holes to the light-emitting layer, so the anode can be formed of a conductive material with a high work function. For example, anode 161 can be formed of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO), but is not limited thereto.

[0161] The display device 100 can be implemented as either a top-emitting or bottom-emitting type. When the display device is a top-emitting type, a reflective layer formed of a metallic material with excellent reflectivity, such as aluminum (Al) or silver (Ag), can be added below the anode 161. Therefore, light emitted from the light-emitting layer is reflected from the anode 161 and directed upwards, i.e., towards the cathode 163. Conversely, when the display device 100 is a bottom-emitting type, the anode 161 can be formed solely of a transparent conductive material.

[0162] The organic layer 162 can be disposed between the anode 161 and the cathode 163.

[0163] The organic layer 162 is a region that emits light through the coupling of electrons and holes supplied from the anode 161 and the cathode 163.

[0164] Meanwhile, various organic light-emitting diode (OLED) structures were proposed to improve the efficiency and lifespan of OLEDs and reduce power consumption, thereby improving the quality and productivity of organic light-emitting display devices.

[0165] Therefore, in addition to organic light-emitting diodes employing a single stack, i.e., a single electroluminescent unit (EL unit), an organic light-emitting diode having a series structure using multiple stacks, i.e., multiple electroluminescent units, is proposed to achieve improved efficiency and lifetime characteristics. However, this disclosure is not limited to the series structure. Hereinafter, for ease of description, a series structure will be used as an example.

[0166] In an organic light-emitting diode (OLED) with a dual-stacked structure, i.e., using a stack of first and second electroluminescent units, a light-emitting region that emits light through the recombination of electrons and holes is disposed in each of the first and second electroluminescent units. Therefore, compared to an OLED with a single-stacked structure, light emitted from the first light-emitting layer of the first electroluminescent unit and the second light-emitting layer of the second electroluminescent unit induces constructive interference to provide higher brightness.

[0167] The stacked structure may include a charge-generating layer disposed between an anode 161 and a cathode 163, a first stack disposed between the charge-generating layer and the anode 161, and a second stack disposed between the cathode 163 and the charge-generating layer. The charge-generating layer is disposed between the first stack and the second stack to generate charge. The charge-generating layer may be formed by a structure in which a p-type charge-generating layer and an n-type charge-generating layer are stacked. That is, the charge-generating layer may consist of a p-type charge-generating layer and an n-type charge-generating layer that generate positive and negative charges in two directions and essentially serve as electrodes.

[0168] Each of the first stack and the second stack includes at least one light-emitting layer, and may include a common layer between the light-emitting layers.

[0169] The embankment 115e can be positioned above the anode 161 and the third insulating layer 115d.

[0170] Dike 115e is an insulating layer disposed between multiple sub-pixels to divide the multiple sub-pixels.

[0171] The dam 115e may include an opening that exposes a portion of the anode 161. The dam 115e may be an organic insulating material configured to cover the edge or boundary of the anode 161. For example, the dam 115e may be formed of a polyimide resin, an acrylic resin, or a benzocyclobutene (BCB) resin, but is not limited thereto.

[0172] Organic layer 162 may be disposed on anode 161. Organic layer 162 may include a light-emitting layer disposed in each of the plurality of sub-pixels and a common layer disposed in the plurality of sub-pixels. The light-emitting layer is an organic layer that emits light of a specific color, and different light-emitting layers are disposed in the first sub-pixel, the second sub-pixel, and the third sub-pixel, respectively. However, this disclosure is not limited thereto; for example, multiple light-emitting layers may be disposed in all sub-pixels to emit white light.

[0173] The common layer is an organic layer configured to improve the luminous efficiency of the light-emitting layer. The common layer can be formed on top of multiple sub-pixels; that is, the common layers of multiple sub-pixels are connected and integrally formed. The common layer may include, but is not limited to, hole injection layers, hole transport layers, electron transport layers, electron injection layers, and charge generation layers.

[0174] The cathode 163 is disposed on the organic layer 162.

[0175] The cathode 163 is an electrode that provides electrons to the organic light-emitting diode 160.

[0176] The cathode 163 can be formed of a material with a low work function. The cathode 163 may include a transparent conductive material. For example, the cathode 163 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc. Alternatively, the cathode 163 may include any of the group consisting of metallic materials such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), magnesium (Mg), palladium (Pd), copper (Cu), and alloys thereof. For example, the cathode 163 may be formed of an alloy of magnesium (Mg) and silver (Ag). Alternatively, the cathode 163 may be constructed by stacking layers formed of a transparent conductive layer such as ITO, IZO, or IGZO and layers formed of metallic materials such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), magnesium (Mg), palladium (Pd), copper (Cu), or alloys thereof, but is not limited thereto.

[0177] Cathode 163 is electrically connected to a low-potential power line to be supplied with a low-potential power signal.

[0178] The encapsulation layer 124 can be disposed on the cathode 163. The encapsulation layer 124 can be disposed above the dam 115e and the organic light-emitting diode 160. The encapsulation layer 124 can block oxygen and moisture from penetrating into the display device 100 from the outside. For example, when the display device 100 is exposed to moisture or oxygen, pixel shrinkage occurs, resulting in a reduction in the light-emitting area, or bad pixels are generated in the light-emitting area. The encapsulation layer 124 can block oxygen and moisture to protect the display device 100.

[0179] The encapsulation layer 124 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer.

[0180] The first encapsulation layer is disposed on the cathode 163 and inhibits the permeation of moisture or oxygen. The first encapsulation layer may be formed of an inorganic material such as silicon nitride (SiNx), silicon oxynitride (SiNxOy), or aluminum oxide (AlyOz), but is not limited thereto.

[0181] A second encapsulation layer is disposed on the first encapsulation layer to planarize the surface. Furthermore, the second encapsulation layer can cover foreign matter or particles that may be generated during the manufacturing process of the display device. The second encapsulation layer can be formed of organic materials such as silicon oxide carbon (SiOxCz), acrylic, or epoxy resin, but is not limited to these.

[0182] The third encapsulation layer is disposed on the second encapsulation layer and, like the first encapsulation layer, inhibits the penetration of moisture or oxygen. The third encapsulation layer may be formed of inorganic materials such as silicon nitride (SiNx), silicon oxynitride (SiNxOy), silicon oxide (SiOx), or aluminum oxide (AlyOz), but is not limited thereto.

[0183] The packaging substrate 125 is disposed on the packaging layer 124.

[0184] The encapsulation substrate 125, together with the encapsulation layer 124, protects the organic light-emitting diode 160. The encapsulation substrate 125 protects the organic light-emitting diode 160 of the pixel unit 123 from external moisture, oxygen, and impact. The encapsulation substrate 125 can be formed from a metallic material with high corrosion resistance and easy processing into foil or thin film form, such as aluminum (Al), nickel (Ni), chromium (Cr), and alloys of iron (Fe). Therefore, since the encapsulation substrate 125 is formed from a metallic material, it can be implemented as an ultrathin film and has high resistance to external impacts and scratches, but is not limited thereto.

[0185] As described above, according to a first exemplary embodiment of this disclosure, a conductive pattern 150 is disposed below the substrate 121 and in the edge region EA and the non-display region NA, for example, in a portion of the upper part of the barrier film 126, and the conductive pattern 150 is grounded to provide (-) charge. By doing so, the (+) charge trapped in the substrate 121 is canceled out and thus edge aging can be improved.

[0186] Furthermore, according to the first exemplary embodiment of this disclosure, as an example, the conductive pattern 150 is formed by a conductive strip, but is not limited thereto. According to this disclosure, the conductive pattern can be formed by a silver paste (Ag) coating, which will be described in detail below by a second exemplary embodiment of this disclosure.

[0187] Figure 8 This is a schematic cross-sectional view of a display panel according to a second exemplary embodiment of the present disclosure.

[0188] and Figure 6 Compared to the 120 display panel, Figure 8 The display panel 220 according to the second exemplary embodiment of this disclosure differs only in the configuration of the conductive pattern 250, but the other configurations are substantially the same, so redundant descriptions will be omitted. The same configurations will be indicated by the same reference numerals.

[0189] Reference Figure 8 The display panel 220 according to the second exemplary embodiment of the present disclosure may include a display area AA and a non-display area NA.

[0190] A portion of the edge of the display area AA can be defined as the edge area EA.

[0191] The edge area EA can extend inward from the edge of the display area AA by 5mm, but is not limited to this.

[0192] According to a second exemplary embodiment of the present disclosure, a conductive pattern 250 is formed in the edge region EA of the display panel 220.

[0193] That is, the conductive pattern 250 according to the second exemplary embodiment of the present disclosure can be formed under the substrate 121 and in the edge region EA and the non-display region NA, and the conductive pattern 250 can be grounded.

[0194] For example, the conductive pattern 250 may be arranged as a stripe pattern on one side, left side, or right side of the display panel 220 where the GIP area is provided, but this disclosure is not limited thereto. The conductive pattern 250 of this disclosure may be arranged in the form of a rectangular frame along the entire edge of the display panel 220.

[0195] The conductive pattern 250 can be disposed below the substrate 121 and in the edge region EA and the non-display region NA, specifically, between the substrate 121 and the barrier film 226. For example, after the laser lift-off (LLO) process, silver paste is applied to the periphery of the display panel 220 and on the rear surface of the substrate 121 to form the conductive pattern 250, and the barrier film 226 can be laminated on the rear surface of the substrate 121 including the conductive pattern 250.

[0196] The conductive pattern 250 can be formed by brushing with silver paste, but is not limited to this.

[0197] Meanwhile, in the first and second exemplary embodiments of this disclosure, as examples, conductive patterns 150 and 250 are disposed on the periphery of display panels 120 and 220, but this disclosure is not limited thereto. According to this disclosure, the conductive layer can be disposed on the entire rear surface of the substrate, which will be described in more detail with reference to the following third exemplary embodiment of this disclosure.

[0198] Figure 9 This is a schematic cross-sectional view of a display panel according to a third exemplary embodiment of the present disclosure.

[0199] and Figure 6 and Figure 8 Compared to the 120 and 220 display panels, Figure 9 The display panel 320 according to the third exemplary embodiment of this disclosure differs only in the configuration of the conductive layer 350, but the other configurations are substantially the same. Therefore, redundant descriptions will be omitted.

[0200] Reference Figure 9 The display panel 320 according to the third exemplary embodiment of the present disclosure may include a display area AA and a non-display area NA.

[0201] According to a third exemplary embodiment of this disclosure, a conductive layer 350 is formed on the entire display panel 320.

[0202] That is, the conductive layer 350 according to the third exemplary embodiment of this disclosure can be formed on the entire display panel 320, i.e., on the entire rear surface of the substrate 121, and the conductive layer 350 can be grounded. The conductive layer 350 can be formed in the barrier film 326. The conductive layer 350 can be formed on the surface of the barrier film 326 by adding a conductive material to the barrier film 326. As the added material, conductive balls may be included, and the conductive layer may be formed of tin oxide (TO), indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (ITZO), etc.

[0203] Furthermore, according to the first, second, and third exemplary embodiments, as examples, conductive patterns 150 and 250 or conductive layer 350 are formed between substrate 121 and barrier films 126, 226, and 326, but this disclosure is not limited thereto. According to this disclosure, conductive patterns may be disposed at the periphery of the display panel and on the side surface of the substrate, which will be described in detail below by the fourth and fifth exemplary embodiments of this disclosure.

[0204] Figure 10 This is a schematic cross-sectional view of a display panel according to a fourth exemplary embodiment of the present disclosure.

[0205] and Figure 6 and Figure 8 Compared to the 120 and 220 display panels, Figure 10 The display panel 420 according to the fourth exemplary embodiment of this disclosure differs only in the configuration of the substrate 421 and the conductive pattern 450, but the other configurations are substantially the same. Therefore, redundant descriptions will be omitted.

[0206] Reference Figure 10 The display panel 420 according to the fourth exemplary embodiment of the present disclosure may include a display area AA and a non-display area NA.

[0207] A portion of the edge of the display area AA can be defined as the edge area EA.

[0208] The edge area EA can extend inward from the edge of the display area AA by 5mm, but is not limited to this.

[0209] According to a fourth exemplary embodiment of the present disclosure, a conductive pattern 450 is formed in the edge region EA of the display panel 420. That is, the conductive pattern 450 according to the fourth exemplary embodiment of the present disclosure can be formed on the side surface of the substrate 421 and in the edge region EA and the non-display region NA, and the conductive pattern 450 can be grounded.

[0210] For example, the conductive pattern 450 may be arranged in a strip shape on one side, left side, or right side of the display panel 420 where the GIP area is provided, but this disclosure is not limited thereto. The conductive pattern 450 of this disclosure may be arranged in the form of a rectangular frame along the entire edge of the display panel 420.

[0211] The conductive pattern 450 can be formed on the side surface of the substrate 421 and in the edge region EA and the non-display region NA. That is, for example, the substrate 421 is formed by etching the side surface of the substrate 421 in the non-display region NA and the edge region EA or selectively coating polyimide in the area of ​​the display panel 420 other than the non-display region NA and the edge region EA, and then a conductive material is deposited on the side surface of the substrate 421 to form the conductive pattern 450.

[0212] As conductive materials, tin oxide (TO), indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (ITZO), etc. can be used.

[0213] Subsequently, a barrier film 426 can be laminated on the back surface of the substrate 421 and the conductive pattern 450.

[0214] Figure 11 This is a schematic cross-sectional view of a display panel according to a fifth exemplary embodiment of the present disclosure.

[0215] and Figure 10 Compared to the 420 display panel, Figure 11 The configuration of only the conductive pattern 550 of the display panel 520 according to the fifth exemplary embodiment of this disclosure differs, but other configurations are substantially the same. Therefore, redundant descriptions will be omitted.

[0216] Reference Figure 11 The display panel 520 according to the fifth exemplary embodiment of the present disclosure may include a display area AA and a non-display area NA.

[0217] A portion of the edge of the display area AA can be defined as the edge area EA.

[0218] The edge area EA can extend inward from the edge of the display area AA by 5mm, but is not limited to this.

[0219] According to a fifth exemplary embodiment of the present disclosure, a conductive pattern 550 is formed in the edge region EA of the display panel 520. Specifically, the conductive pattern 550 according to the fifth exemplary embodiment of the present disclosure is formed on the side surface of the substrate 521 and in the edge region EA and the non-display region NA, and extends along the side surface of the display panel 520 to the upper part, and the conductive pattern 550 is grounded.

[0220] According to the fifth exemplary embodiment of this disclosure, the conductive pattern 550 may be disposed on one side, left and right sides of the display panel 520 in which the GIP area is disposed, or disposed in the form of a rectangular frame along the entire edge of the display panel 520.

[0221] Furthermore, according to a fifth exemplary embodiment of this disclosure, the substrate 521 is formed by etching the side surfaces of the substrate 521 in the non-display area NA and the edge area EA, or by selectively coating polyimide in areas of the display panel 520 other than the non-display area NA and the edge area EA. Thereafter, a conductive material is sprayed onto the side surfaces of the display panel 520, including the side surfaces of the substrate 521, to form a conductive pattern 550.

[0222] Subsequently, a barrier film 526 is stacked on the back surface of the substrate 521 and the conductive pattern 550.

[0223] Simultaneously, when a negative bias is applied to the GIP region to perform a turn-off drive on the transistor, an active back channel is formed by the charge accumulated on the surface of the polyimide substrate. That is, during gate drive, charge accumulates on the surface of the polyimide substrate due to the negative bias, causing polarization. This forms an active back channel, resulting in a shift in the transistor's threshold voltage Vth. This creates a short current path, resulting in a voltage drop, and abnormal operation of the Qb node, which may lead to drive failure.

[0224] Therefore, according to this disclosure, a portion of the polyimide substrate beneath the transistor in the GIP region is removed or a shielding layer is formed to suppress drive faults in the GIP region. By doing so, the threshold voltage offset of the transistor in the GIP region is improved, and the high-potential power supply voltage drop is reduced, thereby enhancing the reliability of the drive circuit.

[0225] Figure 12 This is a schematic plan view of a display panel according to a sixth exemplary embodiment of the present disclosure.

[0226] Figure 13 This is a cross-sectional view of a portion of the GIP region according to a sixth exemplary embodiment of this disclosure.

[0227] exist Figure 12 In this illustration, for ease of description, as an example, the transistor T in the GIP region GA and the recess H below it are arranged regularly in rows and columns, but this disclosure is not limited thereto. Figure 13 For ease of description, a cross-section of the GIP region GA, including a transistor T, is shown as an example. For example, in... Figure 13 In this document, some configurations, including those above the second insulating layer 615b, are omitted.

[0228] Reference Figure 12 and Figure 13 The display panel 620 according to the sixth exemplary embodiment of the present disclosure may include a display area AA and a non-display area NA.

[0229] Display area AA is the area in display panel 620 where images are displayed.

[0230] The non-display area NA is the area where no image is displayed, and it can be adjacent to one or more side surfaces of the display area AA.

[0231] The non-display area NA may include the GIP area GA in which a gate driver is provided.

[0232] The GIP area (GA) can be located on at least one side of the display panel 620, but is not limited to this. Figure 12 The image shows, as an example, the GIP area GA settings on the left and right sides of the display panel 620, but is not limited to this.

[0233] Meanwhile, the display device according to the sixth exemplary embodiment of the present disclosure forms a groove H by removing a portion of the substrate (e.g., a polyimide substrate) 621 below the transistor T in the GIP region GA of the display panel 620, and fills the groove H with predetermined filling layers 670 and 675.

[0234] Specifically, substrate 621 can be a glass or plastic substrate. When the substrate is a plastic substrate, a polyimide-based material or a polycarbonate-based material is used, allowing the substrate to be flexible. Specifically, polyimide can be applied in high-temperature processes and can be coated, therefore polyimide is frequently used in plastic substrates.

[0235] Buffer layers 622a and 622b are functional layers that protect the transistor from impurities such as alkali ions, moisture, and / or oxygen leaking from the substrate 621 or its underlying layers. Buffer layers 622a and 622b may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but are not limited thereto. Buffer layers 622a and 622b may include multiple buffer layers 622a and / or an active buffer layer 622b. Multiple buffer layers 622a may be constructed by alternating layers of silicon oxide (SiOx) and silicon nitride (SiNx), and perform the function of delaying the diffusion of moisture and / or oxygen penetrating into the substrate 621. The active buffer layer 622b protects the active layer ACT of the transistor T and performs the function of blocking various types of defects flowing out from the substrate 621.

[0236] At least one transistor T may be disposed on buffer layers 622a and 622b.

[0237] A transistor T may include an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0238] The active layer ACT can be set on buffer layers 622a and 622b.

[0239] The active layer ACT can be formed from an oxide semiconductor material. However, it is not limited to this; for example, the active layer ACT can be formed from amorphous silicon (a-Si), polycrystalline silicon, or various organic semiconductor materials such as pentacene.

[0240] The first insulating layer 615a is disposed on the active layer ACT, and the gate electrode GE, the source electrode SE, and the drain electrode DE can be disposed on the first insulating layer 615a, but this disclosure is not limited thereto, and the source electrode SE and the drain electrode DE can be disposed on a different layer than the gate electrode GE.

[0241] The first insulating layer 615a can be configured as a single layer or multiple layers of silicon nitride SiNx or silicon oxide SiOx.

[0242] The gate electrode GE, source electrode SE, and drain electrode DE can be formed from various conductive materials, such as magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), gold (Au), or their alloys, but are not limited thereto.

[0243] The second insulating layer 615b can be disposed above the gate electrode GE, the source electrode SE, and the drain electrode DE.

[0244] The second insulating layer 615b can be formed of insulating inorganic materials such as silicon oxide (SiOx) or silicon nitride (SiNx) or insulating organic materials.

[0245] In this design, the substrate 621 is completely removed below the transistor T in the GIP region GA, and a groove H is formed. That is, the substrate 621 below the active layer ACT of the transistor T is completely removed to fundamentally suppress the charge and voltage drop accumulated on the surface of the substrate 621.

[0246] The groove H may have a shape similar to, but not limited to, the planar shape of the transistor T. The groove H may have a rectangular shape that includes the transistor T.

[0247] The groove H is the portion of the substrate 621 below the transistor T in the GIP region GA where the substrate 621 is completely removed, and the groove H may be filled with filler layers 670 and 675.

[0248] Filler layers 670 and 675 may include a first filler layer 670 in contact with the multi-buffer layer 622a and a second filler layer 675 in contact with the first filler layer 670.

[0249] The first filling layer 670 can be configured as a single layer or multiple layers of silicon oxide SiOx, silicon nitride SiNx or silicon oxynitride SiON.

[0250] The second filler layer 675 may be formed from at least one selected from acrylic, acrylic oligomers, epoxy resins and urethane, but is not limited thereto.

[0251] The process of forming the groove H and the fill layers 670 and 675 on the substrate 621 will be described in more detail below with reference to the accompanying drawings.

[0252] Figures 14A to 14C It is illustrated in sequence. Figure 13 A cross-sectional view of the manufacturing method of the structure.

[0253] First, refer to Figure 14A A substrate 621 can be formed on a support substrate 681, wherein a sacrificial layer 682 is present.

[0254] The substrate 621 is a base component supporting various parts of the display panel and can be made of an insulating material. The substrate 621 can be formed of a flexible material to allow the display panel to be rolled or unfolded, and for example, the substrate 621 can be formed of a plastic material such as polyimide (PI). That is, to realize a flexible display device, the flexibility of the substrate 621 needs to be ensured. Currently, to ensure the flexibility of the substrate, a flexible plastic substrate 621 can be used instead of the glass substrate of related technologies.

[0255] When the substrate 621 is formed of a flexible material such as polyimide, the support substrate 681 can be attached to the lower part of the substrate 621 to facilitate subsequent processes.

[0256] The support substrate 681 may be made of glass, but is not limited to it.

[0257] The support substrate 681 can be separated from the substrate 621 by releasing the sacrificial layer 682 through a laser release process. The sacrificial layer 682 can be formed of amorphous silicon (a-Si) or silicon nitride (SiNx) film.

[0258] Next, a predetermined photoresist pattern PR can be formed on the substrate 621.

[0259] The photoresist pattern PR is patterned by a photolithography process, and, for example, when using positive photoresist, the portion of the GIP region where the transistor is located, i.e. the portion to which the groove is to be formed, is exposed for removal, but this disclosure is not limited thereto.

[0260] Next, refer to Figure 14B A portion of the substrate 621 is etched using a photoresist pattern PR to form a groove H in the portion of the transistor where the GIP region is to be formed.

[0261] The groove H can be formed by completely removing the substrate 621 to expose the sacrificial layer 682 beneath the substrate 621.

[0262] Next, a second filling layer 675 is formed in the groove H with a predetermined thickness.

[0263] The second filler layer 675 may be formed from at least one selected from acrylic, acrylic oligomers, epoxy resins and urethane, but is not limited thereto.

[0264] The second filler layer 675 can be used to suppress buckling of the substrate 621 when the support substrate 681 is released.

[0265] Next, refer to Figure 14C The first filling layer 670 is filled into the groove H that is filled with the second filling layer 675.

[0266] The first filling layer 670 can be configured as a single layer or multiple layers of silicon oxide SiOx, silicon nitride SiNx or silicon oxynitride SiON.

[0267] The first filler layer 670 can be used to enhance the adhesion between the second filler layer 675 and the layer formed on the substrate 621.

[0268] Figure 15 This is a cross-sectional view of a portion of the GIP region according to the seventh exemplary embodiment of this disclosure.

[0269] and Figure 13 Compared to the sixth exemplary implementation, Figure 15 The seventh exemplary embodiment of this disclosure differs only in the configuration of the groove H and the light-shielding layer 777, while other configurations are substantially the same. Therefore, redundant descriptions will be omitted. Identical configurations will be denoted by the same reference numerals.

[0270] Similar to the sixth exemplary embodiment of this disclosure described above, in Figure 15 For ease of description, a cross-section of the GIP region GA, including a transistor T, is shown as an example. For example, in Figure 15 In this document, some configurations, including those above the second insulating layer 615b, are omitted.

[0271] Reference Figure 15 According to the seventh exemplary embodiment of the present disclosure, the display device forms a groove H by removing a portion of the thickness of the substrate (e.g., a polyimide substrate) 721 below the transistor T in the GIP region GA, and fills the groove H with a predetermined light-shielding layer 777.

[0272] A portion of the thickness of the substrate 721 beneath the transistor T in the GIP region GA is removed to form a groove H, and a light-shielding layer 777 is used to fill the groove H to suppress the formation of an electric field between the active layer ACT and the substrate 721. Therefore, the charge and voltage drop accumulated on the surface of the substrate 721 can be suppressed.

[0273] The groove H may have a shape similar to, but not limited to, the planar shape of the transistor T. The groove H may have a rectangular shape that includes the transistor T.

[0274] The groove H is the portion of the substrate 721 below the transistor T in the GIP region GA where the thickness is partially removed, and the groove H may be filled with a light-shielding layer 777.

[0275] The light-shielding layer 777 can contact the multiple buffer layer 622a.

[0276] The light-shielding layer 777 can be formed of tin oxide (TO), indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (ITZO), etc., to suppress the formation of an electric field between the active layer ACT and the substrate 721, but is not limited to these.

[0277] Figures 16A to 16C It is illustrated in sequence. Figure 15 A cross-sectional view of the manufacturing method of the structure.

[0278] First, refer to Figure 16A A substrate 721 is formed on a support substrate 681, wherein a sacrificial layer 682 is provided.

[0279] Next, a predetermined photoresist pattern PR can be formed on the substrate 721.

[0280] Next, refer to Figure 16B The substrate 721 is etched with a portion of its thickness using a photoresist pattern PR to form a recess H in the portion of the transistor to which the GIP region is to be formed.

[0281] Next, refer to Figure 16C Use a light-shielding layer 777 to fill the groove H.

[0282] The light-shielding layer 777 can be formed of tin oxide (TO), indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (ITZO), etc., but is not limited to these.

[0283] The groove H disclosed herein can be provided individually for a transistor T below the GIP region GA, but is not limited thereto. For example, the groove H can be formed to correspond to multiple transistors T or to correspond to the entire GIP region GA.

[0284] Figure 17This is a schematic plan view of a display panel according to the eighth exemplary embodiment of the present disclosure.

[0285] Figure 18 This is a schematic plan view of a display panel according to the ninth exemplary embodiment of the present disclosure.

[0286] and Figure 12 Compared to the 620 display panel, Figure 17 and Figure 18 The display panels 820 and 920 differ only in the configuration of the recess H, but the other configurations are essentially the same. Therefore, redundant descriptions will be omitted. Identical configurations will be indicated by the same reference numerals.

[0287] Reference Figure 17 and Figure 18 The display panels 820 and 920 according to the eighth and ninth exemplary embodiments of this disclosure may include a display area AA and a non-display area NA.

[0288] The non-display area NA may include the GIP area GA in which a gate driver is provided.

[0289] The GIP area (GA) is located on at least one side of display panels 820 and 920, but is not limited thereto. Figure 17 and 18 The images show, as examples, the GIP (Gateway Area) GA settings on the left and right sides of display panels 820 and 920, but are not limited to this.

[0290] In this embodiment of the display device, a recess H is formed by removing a portion of the substrate (e.g., a polyimide substrate) beneath a plurality of transistors T in the GIP region GA of the display panel 820, and the recess H is filled with predetermined filling layers 870 and 875.

[0291] According to the eighth exemplary embodiment of this disclosure, the groove H can be formed corresponding to a plurality of transistors T, and the groove H can be filled with filler layers 870 and 875. That is, the groove H can be disposed over a wide area of ​​the GIP region GA occupied by the plurality of transistors T.

[0292] The groove H according to the eighth exemplary embodiment of this disclosure can be formed by completely removing the substrate in the GIP region GA occupied by the plurality of transistors T, but is not limited thereto, and the groove H can be formed by removing only a portion of the thickness of the substrate.

[0293] Furthermore, the display device according to the ninth exemplary embodiment of this disclosure forms a groove H by removing a substrate (e.g., a polyimide substrate) corresponding to the entire GIP region GA of the display panel 920, and fills the groove H with predetermined filling layers 970 and 975.

[0294] According to the ninth exemplary embodiment of this disclosure, the groove H can be formed to correspond to the entire GIP region GA, and the groove H can be filled with filler layers 970 and 975.

[0295] The groove H according to the ninth exemplary embodiment of this disclosure can be formed by completely removing the substrate corresponding to the entire GIP region GA, but this disclosure is not limited thereto, and the groove H can be formed by removing only a portion of the thickness of the substrate.

[0296] The filling layers 870, 970 and 875, 975 may include first filling layers 870 and 970 in contact with the multi-buffer layer 622a and second filling layers 875 and 975 in contact with the first filling layers 870 and 970.

[0297] The first filling layers 870 and 970 can be configured as a single layer or multiple layers of silicon oxide SiOx, silicon nitride SiNx or silicon oxynitride SiON.

[0298] The second filler layers 875 and 975 may be formed from at least one selected from acrylic, acrylic oligomers, epoxy resins and urethane, but are not limited thereto.

[0299] When the groove H is formed by removing only a portion of the substrate thickness, the groove H can be filled with a predetermined light-shielding layer.

[0300] The light-shielding layer can be formed of tin oxide (TO), indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (ITZO), etc., to suppress the formation of an electric field between the active layer ACT and the substrate 721, but is not limited to these.

[0301] Exemplary embodiments of this disclosure can also be described as follows:

[0302] According to one aspect of this disclosure, a display device is provided. The display device includes: a display panel divided into a display area and a non-display area and including a substrate; a pixel unit transistor disposed above the substrate and disposed in the display area; a gate-in-plate (GIP) transistor disposed in the non-display area; a conductive pattern disposed below the substrate and disposed in the edge area of ​​the display area and the non-display area, and the conductive pattern is grounded; and a barrier film disposed below the substrate and the conductive pattern.

[0303] According to another aspect of this disclosure, a display device is provided. The display device includes: a display panel divided into a display area and a non-display area and including a substrate; pixel unit transistors disposed above the substrate and in the display area; gate-in-panel (GIP) transistors disposed in the GIP area of ​​the non-display area; a conductive pattern disposed on a side surface of the substrate and in the edge area of ​​the display area and the non-display area, and the conductive pattern being grounded; and a barrier film disposed below the conductive pattern and the substrate.

[0304] The display device may also include a rear cover disposed on the rear surface of the display panel and rollers connected to the rear cover to allow the rear cover and the display panel to be wound or unfolded.

[0305] The substrate can be made of polyimide.

[0306] Conductive patterns can be formed in the shape of strips on at least one side of the display panel.

[0307] Conductive patterns can be formed in the form of rectangular frames along the entire edge of the display panel.

[0308] A light-shielding layer can be placed below the pixel unit transistor, but a light-shielding layer may not be placed below the GIP transistor. Depending on the arrangement of the light-shielding layer, the grounded conductive pattern cancels out the (+) charge captured in the edge area of ​​the display area by the irregularity of the electric field.

[0309] The conductive pattern can be configured to extend from the edge of the display area to the non-display area.

[0310] Conductive patterns can be made of conductive strips or silver paste (Ag paste).

[0311] The conductive pattern can be set on the entire lower surface of the substrate and can be made of tin oxide (TO), indium tin oxide (ITO), indium zinc oxide (IZO) or indium zinc tin oxide (ITZO).

[0312] Conductive patterns can extend along the side surface of the display panel to the top of the display panel.

[0313] According to another aspect of this disclosure, a display device is provided. The display device includes: a display panel divided into a display area and a non-display area and including a substrate; a GIP transistor disposed above the substrate and in the GIP area of ​​the non-display area; a recess disposed in the substrate and below the GIP transistor; and a fill layer disposed in the recess.

[0314] The substrate can be made of polyimide.

[0315] The groove can be formed by completely removing the portion of the substrate corresponding to the GIP transistor.

[0316] The groove can be formed by removing a portion of the thickness of the substrate corresponding to the GIP transistor.

[0317] The groove can have a planar shape that corresponds to the planar shape of the GIP transistor.

[0318] The filling layer may consist of a first filling layer in contact with the buffer layer and a second filling layer in contact with the first filling layer. The first filling layer may be configured as a single layer or multiple layers of silicon oxide SiOx, silicon nitride SiNx or silicon oxynitride SiON, and the second filling layer may be composed of at least any one selected from acrylic, acrylic oligomer, epoxy resin and urethane.

[0319] The filler layer can be made of tin oxide (TO), indium tin oxide (ITO), indium zinc oxide (IZO) or indium zinc tin oxide (ITZO) to form a light-shielding layer.

[0320] The groove can have a planar shape corresponding to multiple GIP transistors.

[0321] The groove can have a planar shape corresponding to the entire GIP area.

[0322] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within the equivalent scope of the appended claims should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: The display panel is divided into a display area and a non-display area and includes a substrate; A pixel unit transistor is disposed above the substrate and in the display area; An in-board gate transistor is disposed in the non-display area; A conductive pattern is disposed below the substrate and in the edge region of the display area and the non-display area, and the conductive pattern is grounded to counteract the positive charge trapped in the substrate at the edge of the display panel; as well as A barrier film is disposed below the substrate and the conductive pattern and closer to the viewing side of the display panel than to the substrate.

2. The display device according to claim 1, wherein, The conductive pattern is disposed on the entire lower surface of the substrate, and the conductive pattern is made of tin oxide, indium tin oxide, indium zinc oxide, or indium zinc tin oxide.

3. A display device, comprising: The display panel is divided into a display area and a non-display area and includes a substrate; A pixel unit transistor is disposed above the substrate and in the display area; An in-board gate transistor is disposed in the in-board gate region of the non-display area; A conductive pattern is disposed on the side surface of the substrate and in the edge region of the display area and the non-display area, and the conductive pattern is grounded to counteract the positive charge trapped in the substrate at the edge of the display panel; as well as A barrier film is disposed below the substrate and the conductive pattern and closer to the viewing side of the display panel than to the substrate.

4. The display device according to claim 1 or 3, further comprising: A rear cover is disposed on the rear surface of the display panel; as well as A roller, which is connected to the back cover, to allow the back cover and the display panel to be wound or unfolded.

5. The display device according to claim 4, wherein, The substrate is made of polyimide.

6. The display device according to claim 4, wherein, The conductive pattern is formed in a strip shape on at least one side of the display panel.

7. The display device according to claim 4, wherein, The conductive pattern is formed in the form of a rectangular frame along the entire edge of the display panel.

8. The display device according to claim 4, wherein, A light-shielding layer is disposed below the pixel unit transistor, but not below the in-plate gate transistor, and according to the arrangement of the light-shielding layer, the grounded conductive pattern cancels out the positive charge captured in the edge region of the display area by the irregularity of the electric field.

9. The display device according to claim 4, wherein, The conductive pattern is configured to extend from the edge of the display area to the non-display area.

10. The display device according to claim 4, wherein, The conductive pattern is composed of conductive strips or silver paste.

11. The display device according to claim 3, wherein, The conductive pattern extends along the side surface of the display panel to the top of the display panel.

12. A display device, comprising: The display panel is divided into a display area and a non-display area and includes a substrate; An in-board gate transistor is disposed above the substrate and in the in-board gate region of the non-display area; A groove is provided in the substrate and below the in-plate gate transistor to remove at least a portion of the substrate located below the in-plate gate transistor, thereby suppressing the charge accumulated on the surface of the substrate below the in-plate gate transistor. as well as A filling layer is disposed in the groove.

13. The display device according to claim 12, wherein, The substrate is made of polyimide.

14. The display device according to claim 12, wherein, The groove is formed by completely removing the portion of the substrate corresponding to the gate transistor within the substrate.

15. The display device according to claim 12, wherein, The groove is formed by removing a portion of the thickness of the substrate corresponding to the gate transistor within the plate.

16. The display device according to claim 12, wherein, The groove has a planar shape corresponding to the planar shape of the gate transistor in the plate.

17. The display device according to claim 12, wherein, The filling layer consists of a first filling layer in contact with a buffer layer disposed below the gate transistor in the board and a second filling layer in contact with the first filling layer. The first filling layer is configured as a single layer or multiple layers of silicon oxide, silicon nitride or silicon oxynitride, and the second filling layer is composed of at least one selected from acrylic, acrylic oligomer, epoxy resin and urethane.

18. The display device according to claim 12, wherein, The filler layer is made of tin oxide, indium tin oxide, indium zinc oxide, or indium zinc tin oxide to form a light-shielding layer.

19. The display device according to claim 12, wherein, The groove has a planar shape corresponding to a plurality of in-plate gate transistors.

20. The display device according to claim 12, wherein, The groove has a planar shape corresponding to the entire gate region within the board.

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