Devices for increasing operating voltage

Abstract

This disclosure relates to devices for increasing operating voltage. An apparatus (100) includes: a substrate (101-106) having an upper semiconductor layer, a buried semiconductor layer, and a DTI structure (107-108) defining an active device region; a virtual LDMOS device (121) in the active device region, the virtual LDMOS device (121) including: a ground drain (D1) in a drift region (105), a source (S1, S2) in a body region (109) extending to contact the buried semiconductor layer, a gate electrode (G1-G4) formed such that at least a portion of the source and gate electrodes are connected to the body injection region, and a buffer semiconductor layer portion (104) adjacent to the DTI structure; and one or more active LDMOS devices (122) positioned in the active device region, the one or more active LDMOS devices (122) being separated from the DTI structure by the virtual LDMOS device (121), the virtual LDMOS device (121) reducing the electric field on the sidewall insulating layer (107) in the DTI structure.

Description

Technical Field

[0001] This invention generally relates to integrated circuit devices and methods for manufacturing integrated circuit devices. In one aspect, the invention relates to the manufacture and use of laterally diffused metal-oxide-semiconductor (LDMOS) transistor devices. Background Technology

[0002] High-voltage integrated circuit applications, such as high-voltage smart power applications, consist of integrated circuit MOS field-effect transistor devices that must be able to maintain a high voltage (e.g., 45 volts or greater) between the source and drain terminals of the transistor device. Laterally diffused metal-oxide-semiconductor (LDMOS) transistor devices are typically used to provide high-voltage operation for such high-voltage applications. However, these LDMOS devices typically require thick, lightly doped epitaxial layers, making them difficult to integrate with low-voltage circuitry on the same chip. To improve integration density and electrical isolation robustness when integrating LDMOS devices with low-voltage circuitry on the same chip, deep trench isolation (DTI) structures are included to isolate and separate the LDMOS devices. Some types of DTI structures are constructed to include heavily doped n-type polysilicon plugs surrounded by an insulating dielectric layer. In semiconductor-on-insulator (SOI) technology, the polysilicon plug typically acts as a substrate connection and is therefore always grounded. Therefore, a large electric field may exist on the insulating dielectric layer between the polysilicon plug and the high-voltage end of the adjacent DTI structure. Because process technologies can provide DTI (Dielectric Transmission Insulation) structure designs optimized for operation at the highest first voltage level (e.g., 98V), existing DTI structure designs may fail to maintain higher operating voltages for certain high-voltage applications (e.g., to 106V, 114V, and further to 122V), leading to time-dependent dielectric breakdown (TDDB) failure of the insulating dielectric layer in the DTI structure. While this problem can be addressed by increasing the thickness of the insulating dielectric layer in the DTI structure, such changes in the process module typically require long development cycles and may cause other process issues. Although examples of dummy gate layout designs exist, where the drain of the dummy gate device is shorted to the drain of the active device to improve matching and uniformity, such dummy gate devices are typically designed identically to the active devices and implemented by placing two, four, or more dummy gates, which can occupy a significant area.

[0003] As seen above, existing solutions for integrating LDMOS devices can be extremely difficult in practice due to the challenges of balancing applicable performance, design, complexity, and cost constraints in providing higher operating voltages for LDMOS devices without altering process steps or otherwise degrading other critical device characteristics. High-voltage transistor devices and manufacturing processes are also needed to overcome these challenges, as outlined above. Further limitations and disadvantages of conventional processes and techniques will become apparent to those skilled in the art after reviewing the remainder of this application with reference to the accompanying drawings and detailed description. Summary of the Invention

[0004] This document provides a laterally diffused MOS semiconductor device and a method for manufacturing the same. The disclosed semiconductor device includes a semiconductor substrate (which may be an SOI substrate) comprising an upper semiconductor layer having an upper surface and a first conductivity type, and a second buried semiconductor layer or region having a second, opposite conductivity type. In selected embodiments, the first conductivity type is p-type, and the second, opposite conductivity type is n-type. In other embodiments, the upper semiconductor layer is an epitaxial p-type layer, and the second buried semiconductor layer is a lightly doped n-type buried layer formed between the epitaxial p-type layer and a buried insulating layer. The semiconductor device also includes a deep trench isolation structure having conductive contact structures or layers and sidewall insulators formed in the semiconductor substrate to extend from the upper surface of the semiconductor substrate into the semiconductor substrate, thereby defining an active device region disposed on the upper surface of the semiconductor substrate on one side of the deep trench isolation structure. In selected embodiments, the conductive contact layer of the deep trench isolation structure is grounded to bias the underlying substrate. Additionally, the semiconductor device includes a first dummy laterally diffused metal-oxide-semiconductor (LDMOS) device positioned within the active device region. As formed, the first virtual LDMOS device includes a drain region located in a drift region of an upper semiconductor layer and connected to a predetermined reference voltage (e.g., ground). The first virtual LDMOS device also includes a source region located in a body region extending through the upper semiconductor layer to contact a second buried semiconductor layer. Additionally, the first virtual LDMOS device includes a gate electrode formed over the upper semiconductor layer between the drain and source regions, wherein at least a portion of the gate electrode is directly electrically connected to the source region (and thus the body region), for example, by using a metal wire or interconnect that connects the gate electrode (partially) to the source region. In a selected embodiment, the gate electrode in the first virtual LDMOS device is a split gate electrode, including a first gate portion positioned over a channel region in the body region and a second gate flap portion positioned over a shallow trench isolation region formed in a drift region of the upper semiconductor layer. In other embodiments, the gate electrode in the first virtual LDMOS device is a single continuous polysilicon electrode. The first virtual LDMOS device also includes a buffer portion of the semiconductor layer at an upper surface of the semiconductor substrate, the buffer portion being adjacent to a deep trench isolation structure. The semiconductor device further includes one or more active LDMOS devices located in the active device region, said one or more active LDMOS devices being isolated from the deep trench isolation structure by a first dummy LDMOS device, which reduces the electric field on the sidewall insulating layer of the deep trench isolation structure. In a selected embodiment, the deep trench isolation structure and the first dummy LDMOS device are formed as a concentric ring to surround the one or more active LDMOS devices located in the active device region.In a selected embodiment, the dimensions of the first gate portion and the second gate flap portion of the gate electrode in the first dummy LDMOS device differ from the dimensions of the split gate electrode in one or more active LDMOS devices. In other embodiments, the first gate portion and the second gate flap portion of the gate electrode in the first dummy LDMOS device have the same device geometry as the split gate electrode in one or more active LDMOS devices. In a selected embodiment, the first gate portion and the second gate flap portion of the split gate electrode are connected to the source / body of one or more active LDMOS devices. In other embodiments, the first gate portion of the split gate electrode is connected to the source / body of one or more active LDMOS devices, and the second gate flap portion of the split gate electrode is connected to the gate terminal of one or more active LDMOS devices.

[0005] In another form, a semiconductor device and a method for manufacturing the same are provided herein. In the disclosed method, a semiconductor substrate is formed including an upper semiconductor layer having an upper surface and a first conductivity type, and a second buried semiconductor layer having a second, opposite conductivity type. In a selected embodiment, the upper semiconductor layer is an epitaxial p-type layer, and the second buried semiconductor layer is a lightly doped n-type buried layer. A deep trench isolation structure is formed around an active device region disposed at the upper surface of the semiconductor substrate, the deep trench isolation structure including a conductive contact layer surrounded by sidewall insulators formed in the semiconductor substrate, extending from the upper surface of the semiconductor substrate into the semiconductor substrate. Additionally, a dummy laterally diffused metal-oxide-semiconductor (LDMOS) device is formed at a peripheral location positioned within the active device region, the peripheral location adjacent to the deep trench isolation structure to surround one or more active LDMOS devices positioned within the active device region. In a selected embodiment, the deep trench isolation structure and the dummy LDMOS device are formed as concentric rings to surround one or more active LDMOS devices positioned within the active device region. In forming a virtual LDMOS device, a dopant of a second conductivity type is selectively implanted into the upper surface of a semiconductor substrate to form a first body region and a second body region in contact with a second buried layer, thereby defining: a peripheral buffer zone located between a deep trench isolation structure and the first body region in the upper semiconductor layer, and a drift region located between the first body region and the second body region in the upper semiconductor layer. Forming the virtual LDMOS device further includes: forming a first shallow trench isolation structure in the upper surface of the semiconductor substrate to cover the peripheral buffer zone, and forming at least a second shallow trench isolation structure in the upper surface of the semiconductor substrate to cover a portion of the drift region—excluding the central drain region opening. Forming the virtual LDMOS device further includes: forming a first gate electrode and a second gate electrode above the semiconductor substrate, wherein the first gate electrode covers a first portion of the drift region and at least a portion of the first body region to define a first channel region within the first body region, and wherein the second gate electrode covers a second portion of the drift region and at least a portion of the second body region to define a second channel region within the second body region. In a selected embodiment, the first gate electrode has a first gate portion positioned above the first channel region and a second gate flap portion positioned above at least a portion of the second shallow trench isolation structure, and the second gate electrode has a third gate portion positioned above the second channel region and a fourth gate flap portion positioned above at least a portion of the second shallow trench isolation structure. In other embodiments, the first gate electrode has a first single continuous polycrystalline electrode positioned above the first channel region and above at least a portion of the second shallow trench isolation structure, and the second gate electrode has a second single continuous polycrystalline electrode positioned above the second channel region and above at least a portion of the second shallow trench isolation structure.Forming a virtual LDMOS device further includes selectively implanting a dopant of a first conductivity type into the upper surface of a semiconductor substrate to simultaneously form a drain region in a central drain region, a first source region in a first body region adjacent to a first gate electrode, and a second source region in a second body region adjacent to a second gate electrode. In selected embodiments, the method includes forming an interconnect assembly over the semiconductor substrate, including a first interconnect assembly for connecting the drain region of the virtual LDMOS device to a ground voltage and a second interconnect assembly for connecting a first gate electrode and a second gate electrode to the first source region and the second source region, respectively. In other embodiments, the method includes forming an interconnect assembly over the semiconductor substrate, including a first interconnect assembly for connecting the drain region of the virtual LDMOS device to a ground voltage, a second interconnect assembly for connecting a first gate portion and a third gate portion to the source / body of one or more active LDMOS devices, and a third interconnect assembly for connecting a second gate flap portion and a fourth gate flap portion to the gate terminals of one or more active LDMOS devices. In other embodiments, the method includes forming an interconnect assembly over a semiconductor substrate to include a first interconnect assembly for connecting the drain region of a virtual LDMOS device to a ground voltage, and a second interconnect assembly for connecting a first gate electrode and a second gate electrode to the source / body of one or more active LDMOS devices. Attached Figure Description

[0006] The invention and its many objectives, features and advantages will be understood when the following detailed description is considered in conjunction with the following figures.

[0007] Figure 1 This is a simplified cross-sectional view of a high-voltage laterally diffused metal-oxide-semiconductor (LDMOS) virtual device for amplifying the operating voltage of a main high-voltage PLDMOS device according to a selected embodiment of the present disclosure.

[0008] Figure 2 This is a graph showing the analog current in the source and drain of the main high-voltage PLDMOS and the current from the ground terminal in the high-voltage LDMOS dummy device during a low-side breakdown event according to a selected embodiment of the present disclosure.

[0009] Figure 3 This illustrates the simulated deep trench isolation sidewall potential under low-side bias conditions according to a selected embodiment of the present disclosure, as a function of the source-to-drain voltage V. SD The curve that changes.

[0010] Figure 4 This is a graph showing the analog current in the source and drain of the main high-voltage PLDMOS and the current at the ground terminal of the high-voltage LDMOS virtual device during high-side bias conditions according to a selected embodiment of the present disclosure.

[0011] Figure 5 This illustrates the simulated deep trench isolation sidewall potential under high side bias conditions according to a selected embodiment of the present disclosure, as a function of the source-to-drain voltage BV. DSS The curve that changes.

[0012] Figure 6 This is a simplified schematic flowchart illustrating a method for manufacturing an apparatus according to a selected embodiment of the present invention.

[0013] It should be understood that, for the sake of simplicity and clarity, the elements shown in the drawings are not necessarily drawn to scale. For example, for the purpose of promoting and improving clarity and understanding, the dimensions of some elements are enlarged relative to other elements. In addition, where deemed appropriate, reference numerals have been repeated in the drawings to indicate corresponding or similar elements. Detailed Implementation

[0014] High-voltage virtual P-channel laterally diffused MOS (LDMOS) transistors and buffered p-type epitaxial layers are described for use with high-voltage (e.g., approximately 50-200V) smart power applications by positioning the virtual PLDMOS transistor and buffered p-type epitaxial layer between a main PLDMOS transistor array and a surrounding deep trench isolation (DTI) structure to amplify the operating voltage of the main PLDMOS transistor array. Formed as a ring adjacent to the DTI structure, the virtual PLDMOS transistor and buffered p-type epitaxial layer are positioned and connected to reduce the electric field on the DTI sidewalls by connecting the gate, source, and body of the virtual PLDMOS transistor to the source and body of the PLDMOS transistor array, and connecting the drain of the virtual PLDMOS transistor to ground. In this configuration, the virtual PLDMOS transistor is always off. In selected embodiments, the disclosed virtual PLDMOS transistor and main PLDMOS transistor can be similarly constructed and have similar breakdown voltages, but the virtual PLDMOS transistor can have gate flaps with different arrangements, sizes, and structures to achieve high breakdown voltages. As disclosed herein, a “virtual” PLDMOS transistor refers to the limited functionality of a device compared to an active PLDMOS transistor generated by electrical connections at the terminals of a virtual PLDMOS transistor, wherein the characteristic geometry of virtual and active PLDMOS transistors are otherwise identical.

[0015] Various illustrative embodiments of the invention will now be described in detail with reference to the accompanying drawings. While various details are set forth in the following description, it should be understood that the invention can be practiced without these specific details, and many implementation-specific decisions can be made regarding the invention described herein to achieve specific objectives of the device designer, such as compliance with process technology or associated design constraints that vary from implementation to implementation. While this development effort may be complex and time-consuming, it is merely a routine task of daily work for those of ordinary skill in the art who will benefit from this disclosure. For example, selected aspects are depicted with reference to simplified cross-sectional views of a semiconductor device, but not including every device feature or geometry, so as not to limit or obscure the invention. Such descriptions and representations are generally used by those skilled in the art to describe and convey the gist of their work to others skilled in the art. Additionally, although specific example materials are described herein, those skilled in the art will recognize that other materials having similar properties can be substituted without loss of functionality. It should also be noted that throughout this detailed description, certain materials will be formed and removed to fabricate the semiconductor structure. Unless specific processes for forming or removing such materials are described in detail below, it will be contemplated that techniques conventional to those skilled in the art will be used to grow, deposit, remove, or otherwise form such layers to an appropriate thickness. Such details are well known and are not to be considered necessary to teach those skilled in the art how to make or use the present invention.

[0016] To provide additional details for a better understanding of selected embodiments of this disclosure, reference is now made to... Figure 1 The diagram depicts a simplified cross-sectional view 100 of a high-voltage horizontally diffused metal-oxide-semiconductor (LDMOS) virtual device 121 positioned between deep trench isolation structures 107-108 and a main high-voltage PLDMOS device 122 to amplify the operating voltage of the main high-voltage PLDMOS device 122 by reducing the electric field generated on the DTI insulator 107 during high-voltage operation. The depicted LDMOS virtual device 121 and main device 122 are formed of different semiconductor materials having P-type and N-type conductivity. For the P-type material, the dopant concentration varies between the lowest dopant concentration (P-), higher dopant concentration (P), higher dopant concentration (P+), and highest dopant concentration (P++). Similarly, the dopant concentration of the N-type material varies between the lowest dopant concentration (N), higher dopant concentration (N+), and highest dopant concentration (N++).

[0017] For example, the depicted LDMOS virtual device 121 and main device 122 may be p-type LDMOS devices formed on or as part of an SOI wafer 101-113, or formed on or as part of a bulk semiconductor substrate or other substrate, wherein one or more additional semiconductor layers and / or well regions are formed using epitaxial semiconductor growth and / or selective doping techniques, as described more fully below. For example, SOI wafer substrates 101-113 may include an n-type wafer substrate 101, a buried oxide or insulating layer 102, a lightly doped n-type buried layer (LNA) 103, and a p-type semiconductor epitaxial substrate layer consisting of a p-type epitaxial layer 104 and p-type drift layers 105, 106. An n-type wafer substrate 101 can be provided as a processed wafer layer (e.g., n-type wafer substrate 101) formed of a material with impurities of a first conductivity type, at a predetermined doping level and depth, using any suitable dopant type and / or concentration. During the processing of the wafer substrate 101, an insulating layer 102 and a thin substrate semiconductor seed layer can be formed to provide a seed layer for the thick epitaxial growth of p-type semiconductor substrate layers 104-106, followed by implantation of a lightly doped n-type buried layer (LNBL) 103, thereby forming the initial SOI substrate structure 101-106. In another embodiment, a lightly doped n-type buried layer (LNBL) 103 is formed on the buried oxide layer 102 using an n-type seed layer and any suitable epitaxial growth process, followed by the formation of the p-type semiconductor substrate layers 104-106 using a second epitaxial growth process. Alternatively, the SOI wafer substrate structure 101-106 can be formed by bonding a donor wafer to the processed wafer. Using this technique, at least a portion of an n-type wafer substrate 101 and a buried dielectric layer 102 is provided as a processing wafer, which is bonded to or otherwise attached to a donor wafer comprising a portion of the buried dielectric layer 102, an LNBL layer 103, and p-type semiconductor layers 104-106 that may be wholly or partially formed as p-type epitaxial layers. Alternatively, and depending on the type of transistor being manufactured, the semiconductor substrate can be implemented as a bulk silicon substrate, (doped or undoped) single-crystal silicon, an SOI substrate, or any semiconductor material including, for example, Si, SiC, SiGe, SiGeC, Ge, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors or any combination thereof. For a selected bulk silicon substrate embodiment, the buried insulating layer 102 can be formed by implanting some material (e.g., oxygen) into the substrate 101 at a predetermined energy and depth, followed by an oxidation process.

[0018] In SOI wafer substrates 101-106, isolation structures surrounding active device regions, either alone or in combination with patterned shallow trench isolation (STI) structures 110-113, include deep trench isolation (DTI) structures 107, 108 and / or buried insulating layer 102. As will be understood, trench openings can be etched using any desired technique and the trench openings can be at least partially filled using one or more dielectric (and semiconductor) materials. For example, deep trench isolation structures 107, 108 can be formed in SOI wafer substrates 101-106 to surround and isolate various well regions and active regions in integrated circuit device 100. In selected embodiments, deep trench openings are etched through the underlying p-type epitaxial layers 104-106, LNBL layer 103, and buried insulating layer 102 using one or more etch masks (e.g., by applying anisotropic etching to a patterned trench etch mask layer) to reach the underlying n-type wafer substrate 101, thereby forming deep trench isolation structures 107, 108. Once the deep trench openings are formed, they are typically lined with one or more insulating layers 107 (e.g., oxide), and then the center is filled with heavily doped n-type polysilicon 108 to provide a conductive contact path from the surface to the underlying substrate 101. Similarly, shallow trench isolation (STI) structures 110-113 can be formed by patterning and etching shallow trench openings in the upper surface of p-type epitaxial layers 104-106, filling the openings with one or more insulating dielectric layers, and then polishing or planarizing the filling layers to the substrate surface to form the STI structures 110-113.

[0019] Whether before or after the formation of the STI structure 110 / 113, n-type bulk wells or body regions 109A, 109B are formed in the SOI wafer substrate 101-106 to contact the LNBL layer 103, so that the subsequently formed source and gate regions of the HV LDMOS virtual device 121 can be connected to the n-type body 109B of the active HV PLDMOS device 122 through the n-type body 109A and the LNBL layer 103. The n-type bulk wells or body regions 109A, 109B can be formed by selectively diffusing or implanting n-type impurities into the lower p-type epitaxial layers 104-106 using an implantation mask to achieve a predetermined implantation energy and dopant concentration, so that they are located in the upper portion of the p-type epitaxial layers 104-106. During formation, the n-type sump pit or main body regions 109A and 109B define a buffer p-type epitaxial layer 104 adjacent to the DTI structure 107 / 108, and p-type drift regions 105 and 106 that are surrounded on the sides by the n-type main body injection regions 109A and 109B and in the lower layer by the LNBL layer 103.

[0020] Whether before or after forming the DTI structures 107 / 108 and / or STI structures 110 / 113, additional gate electrodes and wells, source / drains, and contact regions can be formed in the SOI wafer substrates 101-113 using any suitable deposition, patterning, masking, etching, and / or implantation steps. For example, a gate dielectric layer and a conductive polysilicon layer can be formed sequentially, followed by selective masking, patterning, and etching to form gate electrodes (G1-G6) over the SOI wafer substrates 101-113. Alternatively, one or more insulating layers can be deposited over the gate electrodes (G1-G6) and the SOI wafer substrates 101-113, followed by selective masking, patterning, and etching to form sidewall implantation masks (SW1-3) and split gate separators (INS1-3) adjacent to the gate electrodes (G1-G6). After forming the gate electrodes (G1-G6), sidewall implantation masks (SW1-3), and split gate separators (INS1-3), additional processing steps are performed, which may include one or more additional masks to selectively implant the indicated p+, n+ source / drain regions, n+ body contact regions, and lightly doped drain (LDD) regions in the SOI wafer substrates 101-113.

[0021] After forming doped regions and isolation structures in SOI wafers 101-113, electrical interconnects are formed above the wafer surface to connect gate electrodes G1-G6 to source / drain contact regions, as shown in the figure. It should be understood that the electrical interconnects may be defined silicide layers and connection metallized conductors (MC1-MC3) formed of one or more metal materials or layers, including, for example, ohmic metal layers, transition layers, and conductive layers. Specifically, the first connection metallized conductor MC1 connects gate electrodes G1 and G2 to a first split gate electrode, while the second connection metallized conductor MC2 connects gate electrodes G3 and G4 to the second split gate electrode of the virtual HV PLDMOS device 121. Similarly, the third connection metallized conductor MC3 connects gate electrodes G5 and G6 to the third split gate electrode of the main HV PLDMOS device 122. Formed within a dielectric layer stack (not shown), a metal layer electrically connects the conductive DTI polycrystalline contact 108 (and wafer substrate 101) to a ground reference potential (GND) and also electrically connects the drain D1 of the dummy HV PLDMOS device 121 to the ground reference potential (GND). Additionally, a metal interconnect layer provides conductive paths to the terminals of the dummy HV PLDMOS 121 (including the first source terminal S1, split gate electrodes G1 / G2, G3 / G4, and the second source terminal S2) and the terminals of the main HV PLDMOS 122 (including the shared second source terminal S2, split gate electrodes G5 / G6, and the second drain terminal D2). As disclosed herein, circuitry and connectivity elements may be included in a packaged integrated circuit device to provide functionality and electrical characteristics to a customer. Although Figure 1 A split-gate embodiment is shown, but it should be understood that this disclosure also covers the use of conventional continuous single polycrystalline gate structures to achieve the benefits provided herein.

[0022] Utilizing the depicted connection between the virtual HV PLDMOS 121 and the main HV PLDMOS 122, the operating voltage of the main HV PLDMOS 122 is increased by positioning and connecting the virtual HV PLDMOS 121 to reduce the potential near the buried insulator layer in the integrated circuit, such as the DTI insulator layer 107 and / or the SOI insulator layer 102. For this purpose, the n-type wafer substrate 101 is grounded via a heavily doped n-type polysilicon plug 108 in the center of the DTI structure 107 / 108. To provide electrical isolation from adjacent devices, each of the main PLDMOS devices 122 is surrounded by and included within the DTI structure 107 / 108 and the buried oxide (BOX) layer 102. Additionally, the main PLDMOS device 122 is surrounded and enclosed by a virtual HV PLDMOS structure 121, which has a similar design to the active HV PLDMOS structure 122 and is positioned adjacent to the DTI structures 107 / 108. Below the virtual and main HV PLDMOS structures 121, 122, an LNBL layer 103 is disposed over the entire structure and coupled to the host potential via one or more n-type host injection regions 109A / B. Furthermore, the p-type drift regions 105, 106 are surrounded laterally by the n-type host injection regions 109A / B and, in the lower layer, by the LNBL layer 103.

[0023] In situations where the device breakdown voltage is typically determined by the vertical pn junction between the p-type drift regions 105, 106 and the LNBL layer 103, a split-gate design can be employed to achieve a high breakdown voltage and reduce the impact of silicon defects along the shallow trench isolation (STI) sidewalls 110-113 on device performance. For the split-gate design, a first gate (e.g., G1) is positioned above a portion of the channel region of the n-type body implantation region (e.g., 109A), while a second gate or "polycrystalline fold" (e.g., G2) is positioned above the STI (e.g., STI111). The polycrystalline folds G2, G3, and G6 in the dummy device 121 and the active device 122 can be optimized individually to achieve a high breakdown voltage. To enhance protection against potential near the DTI sidewall insulator 107, a buffer p-type epitaxial layer 104 is positioned between the DTI structure 107 / 108 and the n-type body 109A of the dummy HV PLDMOS device 121, having a minimum specified width dimension W1 (e.g., 0.1-10 micrometers). To physically and / or electrically connect the dummy HV PLDMOS device 121 to a single protective structure surrounding the main HV PLDMOS device 122 array, the dummy HV PLDMOS device 121 may be positioned adjacent to the DTI structure 107 / 108 and connected together in a connection or surround design arranged around the main HV PLDMOS device 122 array.

[0024] In the disclosed dummy HV PLDMOS device 121, the p+ source / body S1 and gate terminals G1 / G2 are connected to the p+ source / body terminal of the main HV PLDMOS device 122 via the N-type body injection region 109 and the LNBL layer 103, while the drain terminal D1 in the dummy HV PLDMOS device 121 is connected to the ground rail (GND). Using this arrangement, different V values ​​are applied to the main HV PLDMOS 122. SD The bias voltage will generate different electrostatic potentials in the LNBL layer 103, such as the electrostatic potential depletion line V. SD1 -V SD3 As shown.

[0025] For example, under the condition that the drain D2 of the main HV PLDMOS 122 is grounded and active, or the source / body S2 and gate G5 / G6 of the main HV PLDMOS 122 are scanned upwards to a high voltage low-side bias, the depletion line V is depleted. SD1 -V SD3 The simulated electrostatic potentials of the disclosed virtual HV PLDMOS 121 and master HV PLDMOS 122 under different low-side bias conditions are shown. Specifically, with depletion line V SD1 =40V indicates the simulated electrostatic potential of the disclosed virtual HV PLDMOS 121 and main HV PLDMOS 122 under a first source-drain voltage low bias condition (e.g., Vsd = 40V). Under the first source-drain voltage low bias condition, the depletion line V SD1 =40V marks the boundary of the depletion region. Therefore, it can be seen that there is no significant depletion at the n-type host injection region 109A / B, LNBL layer 103 and barrier p-type epitaxial layer 104 (including the region adjacent to DTI structure 107 / 108). This means that the potential at the DTI sidewall 107 follows the source voltage at S1 / S2.

[0026] However, when the source-drain voltage bias condition Vsd exceeds a critical value, the LNBL layer 103 begins to deplete. This is for a second, intermediate source-drain voltage low bias condition (e.g., Vsd = 80V) with the simulated electrostatic depletion line V of the disclosed virtual HV PLDMOS 121 and main HV PLDMOS 122. SD2 =80V is shown. At the depletion line V SD2 With 80V indicating the boundary of the depletion region under this intermediate bias condition, it can be seen that there is no significant depletion at the n-type host injection region 109A / B. However, the central portion of the LNBL layer 103 is completely depleted. In addition, the peripheral portions of the LNBL layer 103 and the barrier p-type epitaxial layer 104 adjacent to the DTI structures 107 / 108 are partially depleted.

[0027] Additionally, with the exhaustion line V SD3 =120V indicates the simulated electrostatic potential of the disclosed virtual HVPLDMOS 121 and main HVPLDMOS 122 under a high bias condition of the third source-drain voltage (e.g., Vsd = 120V). At the depletion line V SD3 =120V indicates the boundary of the depletion region under this bias condition. It can be seen that there is no significant depletion at the n-type host injection region 109A / B, while the LNBL layer 103 and the barrier p-type epitaxial layer 104 adjacent to the DTI structure 107 / 108 are completely depleted. This means that there is a voltage drop in the barrier p-type epitaxial layer 104 that reduces the potential near the DTI sidewall 107.

[0028] As should be understood, the metallized conductors MC1-MC3 enable the split gate electrodes G1 / G2 and G3 / G4 to be directly electrically connected to the p+ source regions S1 and S2, respectively, for example, using metal wires or interconnects. Conversely, the p+ source regions S1 and S2 are directly electrically connected to the n-type body region 109. However, in other embodiments, portions of the split gate electrodes are individually connected to different potentials. In this case, the metallized conductors MC1-MC3 are modified or removed to allow such individual electrical connections. For example, in embodiments where gate electrode portions G1 / G4 are connected or directly electrically connected to the p+ source regions S1 and S2, and gate electrode flap portions G2 / G3 are connected or directly electrically connected to the gate terminal of the main device or to another bias voltage (e.g., a logic power supply), the metallized conductors MC1-MC3 may be removed or not formed.

[0029] To provide additional details for a better understanding of selected embodiments of this disclosure, reference is now made to... Figure 2 It depicts the events during a low-side breakdown event. Figure 1 The graph 200 shows the simulated source, drain, and ground currents of a simulated structure with a main high-voltage PLDMOS device protected by a high-voltage LDMOS dummy device. The plotted graph shows the source (I) current during a low-side breakdown event at a breakdown voltage of 147V. S )201, Grounding (-I GND )202 and drain (-I D The analog current at terminal 203, where the source current I of the main HV PLDMOS device is... S Flow to drain I D and grounding terminal I GND .exist Figure 1 In the simulation domain, there are two virtual gate fingers (G1 / G2 and G3 / G4) and one active gate finger (G5 / G6) in the simulation structure, simulating the ground terminal current (-I). GND )202 is higher than the drain current (-I) D)203, and the simulated low-side breakdown voltage of this novel device is approximately 147V.

[0030] To provide additional details for a better understanding of selected embodiments of this disclosure, reference is now made to... Figure 3 It depicts the simulated deep trench isolation sidewall potential (V0) under low side bias conditions. DTI_Sidewall With the source-to-drain voltage V SD The curve 300 shows the change. As shown in the curve of the DTI sidewall potential, there are two different slopes. In the first part 301, when Vsd is less than 75V, the DTI sidewall potential exactly follows the source voltage and the slope of the curve is 1. However, after the inflection point 302, when Vsd exceeds 75V, the increase of the DTI sidewall potential slows down and the slope of the curve 303 is less than 1. Therefore, the DTI sidewall potential is lower than the source-to-drain voltage. At a breakdown voltage of 147V, the DTI sidewall potential is below 98V, thus effectively eliminating the DTI structure as a limiting factor. (See also...) Figure 1 When the LNBL layer 103 is at a higher source-to-drain voltage V SD When depletion occurs, a specific voltage drop appears in the buffer p-type epitaxial layer 104 between the n-type body 109A of the virtual device and the DTI structure 107 / 108 to reduce the potential near the DTI sidewall 107, thereby enabling Figure 3 The slope 303 in the middle decreases.

[0031] To provide additional details for a better understanding of selected embodiments of this disclosure, reference is now made to... Figure 4 It depicts, for example, during a high-side breakdown event. Figure 1 The simulated source, drain, and ground current curves 400 show the simulated source, drain, and ground currents of the simulated structure, which has a main high-voltage PLDMOS device protected by a high-voltage PLDMOS dummy device. The plotted curves show the source (I... S 401, Grounding (-I) GND )402 and drain (I D The analog current at terminal 403 is determined by the gate voltage (V) applied to gate electrodes G5 / G6. G ), source voltage at source terminal S2 (V S ) and the drain voltage (V) at the drain terminal D2 of the main HV PLDMOS device 122 D The high-potential bias is applied. In the simulation curve 400, the simulated source current (I) is... S )401 and grounding current (-I GND The current exceeds the drain current (I) D Together they share a common trace to provide high-side capability up to 120V.

[0032] To provide additional details for a better understanding of selected embodiments of this disclosure, reference is now made to... Figure 5 It depicts the simulated deep trench isolation sidewall potential (V0) under high side bias conditions. DTI_Sidewall (V) as the source / body voltage V S The curve 500 shows the change. As shown in the curve of DTI sidewall potential, there are two different slopes, including when the source / body voltage V... S The first part, 501, occurs when the voltage is less than 80V, where the DTI sidewall potential exactly follows the source voltage and the slope of the curve is 1. However, after the inflection point 502, when the source / body voltage V... S Above 80V, the increase in DTI sidewall potential slows down and the slope of curve 503 is less than 1. Due to depletion in the buffered p-type epitaxial layer, a voltage drop exists between the virtual PLDMOS body and DTI, which effectively reduces the DTI sidewall potential to below 98V, even when the source / body voltage V... S The same applies when increasing to 120V. Therefore, the disclosed HV PLDMOS expands the operating voltage to 106V or even 114V without any process changes. This enhancement is achieved by employing a "always-off" dummy PLDMOS device to generate sufficient potential drop across the DTI structure. While the dummy PLDMOS device does require a small additional silicon area, this increased footprint is justifiable in many applications where higher voltage blocking capability is needed, but the utilization rate of this high-voltage device is relatively low, thus it cannot be justified by the significant development costs and / or cycle time for a new technology with a more competitive BV / Rdson quality factor. In most applications, power devices are typically used to deliver larger currents, which usually require larger device sizes (i.e., larger device widths and multiple fingers). In this case, the increase in device size due to the peripheral dummy device will be minimal.

[0033] To provide additional details for a better understanding of selected embodiments of this disclosure, reference is now made to... Figure 6 It depicts a simplified flowchart illustrating a semiconductor device including an LDMOS device with an extended operating voltage. After the process begins at step 602, a series of manufacturing steps are performed in step 604 to provide or manufacture a semiconductor-on-insulator (SOI) wafer substrate on which a p-type epitaxial layer is formed over a buried n-type layer and a buried insulating layer, wherein the buried insulating layer separates the underlying n-type semiconductor substrate from the p-type epitaxial layer and the buried n-type layer.

[0034] Regarding manufacturing step 604, there may be several preliminary steps involving the preparation of a wafer substrate for subsequent processing. Any bulk or composite substrate can be used as the starting material, but in selected embodiments, the SOI wafer substrate is fabricated to include a lower wafer substrate, a buried insulator layer, and an epitaxial semiconductor layer. In selected embodiments, the epitaxial semiconductor layer is formed having a first, lightly doped n-type layer over the buried insulator layer, followed by epitaxial formation of a second, p-type epitaxial layer over the first, lightly doped n-type layer. Alternatively, the epitaxial semiconductor layer can be formed as a p-type epitaxial layer over the buried insulator layer, followed by implantation of n-type impurities to form a lightly doped n-type buried layer.

[0035] In step 606, an active device region is defined and depicted in the epitaxial semiconductor layer by forming shallow trench isolation and deep trench isolation structures in the SOI substrate, including conductive contacts through the deep trench isolation structures to the underlying n-type semiconductor substrate. Specifically, the deep trench isolation structures are formed to extend downward from the surface of the SOI wafer substrate to the underlying wafer substrate. To form each deep trench isolation (DTI) structure, a deep trench opening is formed by selectively masking and etching through the p-type epitaxial layer, the buried n-type layer, and the buried insulating layer using any suitable sequence of steps, for example, by using a patterned mask with one or more anisotropic etching steps. The DTI is filled with a highly doped polysilicon plug surrounded by one or more dielectric layers. If desired, one or more processing steps may be applied to planarize the deep trench isolation structure from the remainder of the SOI substrate, for example, by applying a polishing step to the surface of the SOI substrate. It should be understood that the deep trench isolation structures may be formed and positioned to surround and protect a first active device region, in which a high-voltage PLDOS transistor device will subsequently be formed. In the active device region, one or more shallow trench isolation (STI) structures can be formed by patterning and etching shallow trench openings in the upper surface of the SOI substrate, filling the openings with one or more insulating dielectric layers, and then polishing or planarizing the filling layers to the substrate surface to form the shallow trench isolation structure.

[0036] Beginning at step 608, additional steps are performed to fabricate additional well regions, gate electrodes, and associated source / drain regions in the active region on the surface of the SOI wafer substrate. Specifically, the body contact region can be formed by selectively implanting n-type dopants at the surface of the SOI substrate extending downward to contact the buried n-type layer. It should be understood that any suitable sequence of steps can be used to form each body contact region, for example, by patterning an implantation or diffusion mask with openings above the desired body contact region, followed by implanting or diffusing n-type impurities with a predetermined dopant concentration and implantation energy. By positioning the n-type body contact region within the p-type epitaxial layer, a peripheral p-type epitaxial region, drift region, and RESURF structure are defined for the virtual HV PLDMOS structure at the periphery of the active HV PLDMOS region. Specifically, the first n-type body contact region can be positioned adjacent to but spaced apart from the DTI structure by a minimum specified width dimension W1 (e.g., 0.1-10 micrometers) to create a buffered p-type epitaxial layer that enhances protection of the potential near the DTI sidewall insulator. To physically and / or electrically connect the subsequently formed dummy HV PLDMOS devices to a single protective structure surrounding the main HV PLDMOS device array, a buffer p-type epitaxial layer is positioned adjacent to the DTI structure and the subsequently formed dummy HV PLDMOS devices in a connection or surround design arranged around the subsequently formed main HV PLDMOS device array. If desired, additional well regions can be formed by doping the epitaxial semiconductor substrate using any suitable dopant implantation process to define n-type or p-type well regions.

[0037] In step 610, a gate electrode structure is formed over the SOI structure, at least in the active device region surrounded and enclosed by the deep trench isolation structure. While any suitable sequence of steps can be used to form the gate electrode structure, an example fabrication sequence includes, for example, forming or depositing one or more gate dielectric layers over the SOI substrate by depositing a doped polysilicon layer over the SOI substrate, followed by forming one or more conductive gate electrode layers over the gate dielectric layers. The gate electrode structure is then formed over the active region by subsequently patterning an etch mask, followed by applying one or more selective etch steps to the conductive gate electrode layers and the gate dielectric layers. As formed, the gate electrode structure is positioned to define the dummy gate electrodes (e.g., G1 / G2 and G3 / G4) of the dummy HV PLDMOS device and the active gate electrodes (e.g., G5 / G6) of the main HV PLDMOS device.

[0038] In step 612, source and drain regions are formed in the upper surface of the SOI substrate, at least in the active device region. It should be understood that any suitable sequence of steps can be used to form the source / drain regions, for example, by patterning a source / drain implantation or diffusion mask with openings above the desired source / drain regions, followed by implanting or diffusing p-type impurities with a predetermined dopant concentration and implantation energy to form p+ source / drain regions. It should be understood that the implantation or diffusion mask may include one or more sidewall implantation masks formed on the sidewalls of the gate electrode, for example, by forming an insulating layer above the gate electrode structure, which is then anisotropically etched to leave the sidewall implantation mask. Depending on the desired location and type of source / drain regions, the implantation or diffusion mask may also include additional patterned implantation masks. For example, an injection mask can be formed before forming a sidewall injection mask to protect all or part of the barrier p-type epitaxial layer and p-type drift region from the source / drain injection step. This allows one or more lightly doped drain (LDD) regions to be selectively formed on one side of the gate electrode structure via a first source / drain injection. A sidewall injection mask is then formed for use with a second source / drain injection to form P+ source / drain regions positioned to be fully contained within the n-type body region and P+ drain regions positioned in the p-type drift region and spaced apart from the n-type body region. After forming the source / drain regions, the active device region includes a high-voltage dummy PLDMOS transistor and a buffer p-type epitaxial layer formed by an adjacent deep trench isolation (DTI) structure to protect the array of high-voltage main PLDMOS transistors formed at the protected locations within the active device region. Formed as a ring adjacent to the DTI structure, a dummy PLDMOS transistor and a buffer p-type epitaxial layer are positioned and connected to reduce the electric field on the DTI sidewalls by connecting the gate, source, and body of the dummy PLDMOS transistor to the source and body of the PLDMOS transistor array, and connecting the drain of the dummy PLDMOS transistor to ground. In this configuration, the dummy PLDMOS transistor is always off. In selected embodiments, the disclosed dummy PLDMOS transistor and main PLDMOS transistor can be similarly constructed and have similar breakdown voltages, but the dummy PLDMOS transistor may include a split-gate design, wherein the arrangement and size of the gate electrodes are controlled or optimized to achieve a high breakdown voltage.

[0039] After forming the gate electrode structure and doped source / region, end contacts are formed in step 614 for the gate, source, drain, and deep trench isolation contact regions. It should be understood that any suitable contact formation sequence can be used to form the end contacts, for example, by selectively forming a silicide layer with a patterned mask such that a deposited metal layer is formed to contact the gate, source, drain, and DTI contact regions, followed by annealing to form the silicide layer for subsequent electrical connection to metallized conductors formed in an interconnect stack over the SOI substrate.

[0040] In step 616, a metal interconnect structure is formed over the SOI substrate, which connects the source / body and gate terminals of the dummy HV PLDMOS structure to the source / body terminals of an adjacent active HV PLDMOS device and connects the drain terminal of the dummy HV PLDMOS structure to ground. The process at step 616 may include sequentially forming an intermediate dielectric layer and patterned metal interconnect conductors for direct electrical connection to the gate, source, drain, and DTI terminals.

[0041] At step 618, the manufacturing method ends. At this point, the fabrication of the semiconductor device can continue with individual dicing into separate integrated circuit dies and additional packaging steps. Of course, the order of the actions described above can be altered to form the specific device regions and features required for any particular integrated circuit application. It should be understood that additional processing steps will be used to fabricate the semiconductor device described herein, such as nitride banding, the preparation and formation of one or more sacrificial oxide layers, shallow trench isolation regions, and the formation of various buried wells or regions. Additionally, other circuit features, such as capacitors, diodes, etc., can be formed on the wafer structure. For example, one or more sacrificial oxide formations, stripping, isolation region formation, well region formation, gate dielectric and electrode formation, extended implantation, halogen implantation, spacer layer formation, source / drain implantation, thermally driven or annealed steps, and polishing steps can be performed, as well as conventional back-end processing (not depicted), typically including the formation of multi-level interconnects for connecting transistors in the desired manner to achieve the desired function. Therefore, depending on process and / or design requirements, the specific sequence of steps used to complete the fabrication of the semiconductor structure can be varied.

[0042] While the exemplary embodiments described herein relate to various isolated LDMOS transistors and methods of fabrication thereof, the invention is not necessarily limited to the exemplary embodiments, which illustrate inventive aspects applicable to various transistor fabrication processes and / or structures. Therefore, the specific embodiments disclosed above are merely illustrative and should not be considered as limiting the invention, as the invention can be modified and practiced in different but equivalent ways, which will be apparent to those skilled in the art who benefit from the teachings herein. For example, although the various devices shown herein are for P-channel LDMOS transistor devices, etc., this is for ease of explanation and not intended to be limiting, and those skilled in the art should understand that the principles taught herein are applicable to devices of any conductivity type. Furthermore, the body contact region is described as being formed by implanting an n-type dopant into a p-type upper semiconductor layer, but alternatively, the reverse method can be used to form a p-type buffer and drift region by implanting a p-type dopant into an n-type upper semiconductor layer, thereby making the body contact region an unimplanted portion of the n-type upper semiconductor layer. Therefore, the designation of specific regions as N-type or P-type is by way of illustration only and not limitation, and regions of opposite conductivity types can be substituted to form devices of opposite conductivity types. Furthermore, the thickness and doping concentration of the described layers can be adjusted as needed for the desired application. Therefore, the foregoing description is not intended to limit the invention to the specific forms set forth, but rather is intended to cover such alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims, so that those skilled in the art will understand that they can make various changes, substitutions, and variations in its broadest form without departing from the spirit and scope of the invention.

[0043] The benefits, other advantages, and solutions to the problem have been described above with respect to specific embodiments. However, these benefits, advantages, solutions to the problem, and any elements that may make any benefit, advantage, or solution occur or become more apparent should not be construed as essential, necessary, or fundamental features of any or all of the elements of the claims. As used herein, the terms “comprises” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements does not necessarily include only those elements, but may include other elements not expressly listed or not inherent to such process, method, article, or apparatus.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor substrate, the semiconductor substrate comprising an upper semiconductor layer having an upper surface and a first conductivity type and a second buried semiconductor layer having a second conductivity type opposite to the first conductivity type; A deep trench isolation structure includes a conductive contact structure and a sidewall insulator formed in the semiconductor substrate to extend from the upper surface of the semiconductor substrate into the semiconductor substrate, thereby defining an active device region disposed on the upper surface of the semiconductor substrate on one side of the deep trench isolation structure. A first virtual transversely diffused metal-oxide-semiconductor (LDMOS) device is located in the active device region, the first virtual LDMOS device comprising: A drain region having the first conductivity type, the drain region being located in the drift region of the upper semiconductor layer and connected to a predetermined reference voltage, the drift region having the first conductivity type; A source region having the first conductivity type, the source region being located in a body region extending through the upper semiconductor layer to contact the second buried semiconductor layer, the body region having the second conductivity type; and A gate electrode is formed above the upper semiconductor layer between the drain region and the source region, wherein at least a portion of the gate electrode is electrically connected to the source region. A buffer portion of the upper semiconductor layer at the upper surface of the semiconductor substrate, the buffer portion being adjacent to the deep trench isolation structure; and One or more active LDMOS devices are positioned in the active device region, the one or more active LDMOS devices being isolated from the deep trench isolation structure via a first virtual LDMOS device, the first virtual LDMOS device reducing the electric field on the sidewall insulating layer in the deep trench isolation structure; each of the one or more active LDMOS devices includes: A drain region having the first conductivity type, the drain region being located in the drift region of the upper semiconductor layer, the drift region having the first conductivity type; A source region having the first conductivity type, the source region being located in a body region extending through the upper semiconductor layer to contact the second buried semiconductor layer, the body region having the second conductivity type; and A gate electrode is formed above the upper semiconductor layer between the drain region and the source region of the active LDMOS device.

2. The semiconductor device according to claim 1, characterized in that, The deep trench isolation structure and the first virtual LDMOS device are formed as a concentric ring to surround the one or more active LDMOS devices located in the active device region.

3. The semiconductor device according to claim 1, characterized in that, The gate electrode in the first virtual LDMOS device is a split gate electrode comprising the following: A first gate portion, the first gate portion being positioned above the channel region in the body region, and The second gate flap portion is positioned above the shallow trench isolation region formed in the drift region of the upper semiconductor layer.

4. The semiconductor device according to claim 3, characterized in that, The first gate portion is connected to the source / body of the one or more active LDMOS devices, and the second gate flap portion is connected to the gate terminal of the one or more active LDMOS devices.

5. The semiconductor device according to claim 1, characterized in that, The semiconductor substrate includes a semiconductor-on-insulator (SOI) substrate, wherein the upper semiconductor layer and the second buried semiconductor layer are formed above the lower substrate and are isolated from the lower substrate by the buried insulating layer.

6. A method for manufacturing a semiconductor device, characterized in that, This includes performing the following operations in any order: A semiconductor substrate is formed, the semiconductor substrate comprising an upper semiconductor layer having an upper surface and a first conductivity type and a second buried semiconductor layer having a second conductivity type opposite to the first conductivity type; A deep trench isolation structure adjacent to an active device region is formed in the semiconductor substrate, the active device region being disposed on the upper surface of the semiconductor substrate, the deep trench isolation structure including a conductive contact structure and a sidewall insulator formed in the semiconductor substrate, extending from the upper surface of the semiconductor substrate into the semiconductor substrate; as well as A virtual laterally diffused metal-oxide-semiconductor (LDMOS) device is formed at a peripheral location within the active device region, the peripheral location being adjacent to the deep trench isolation structure and adjacent to one or more active LDMOS devices located within the active device region, in the following manner: A dopant of the second conductivity type is selectively implanted into the upper surface of the semiconductor substrate to form a first host region and a second host region to contact the second buried layer, thereby defining: The upper semiconductor layer is positioned in the outer buffer zone between the deep trench isolation structure and the first main body region, and The drift region in the upper semiconductor layer is located between the first main region and the second main region, and the drift region has the first conductivity type; A first gate electrode and a second gate electrode are formed above the semiconductor substrate. The first gate electrode covers a first portion of the drift region and at least a portion of the first body region to define a first channel region within the first body region, and the second gate electrode covers a second portion of the drift region and at least a portion of the second body region to define a second channel region within the second body region. as well as Dopant of the first conductivity type is selectively implanted into the upper surface of the semiconductor substrate to simultaneously form a drain region in the central drain region, a first source region in the first body region adjacent to the first gate electrode, and a second source region in the second body region adjacent to the second gate electrode. as well as Provide one or more active LDMOS devices in the active device region, each of the one or more active LDMOS devices comprising: A drain region having the first conductivity type is provided, the drain region being located in a drift region of the upper semiconductor layer, the drift region having the first conductivity type; Provide a source region having the first conductivity type, the source region being located in a body region extending through the upper semiconductor layer to contact the second buried semiconductor layer, the body region having the second conductivity type; and A gate electrode is provided, the gate electrode being formed above the upper semiconductor layer between the drain region and the source region of the active LDMOS device.

7. The method according to claim 6, characterized in that, Forming the first gate electrode and the second gate electrode includes: A first gate electrode is formed above at least a portion of a first single continuous polycrystalline electrode positioned above the first channel region and within the drift region; and The second gate electrode is formed above at least a portion of a second single continuous polycrystalline electrode positioned above the second channel region and in the drift region.

8. The method according to claim 6, characterized in that, Additionally, it includes forming an interconnect assembly over the semiconductor substrate, the interconnect assembly including a first interconnect assembly for connecting the drain region of the virtual LDMOS device to a reference voltage and a second interconnect assembly for connecting the first gate electrode and the second gate electrode to the first source region and the second source region, respectively.

9. The method according to claim 6, characterized in that, Forming the first gate electrode and the second gate electrode includes: A first gate electrode is formed having a first gate portion positioned above the first channel region and a second gate flap portion positioned above at least a portion of a shallow trench isolation structure positioned in the drift region; and A second gate electrode is formed having a third gate portion positioned above the second channel region and a fourth gate flap portion positioned above at least a portion of a shallow trench isolation structure positioned in the drift region.

10. The method according to claim 9, characterized in that, The method further includes forming an interconnect assembly over the semiconductor substrate, the interconnect assembly comprising: A first interconnect set used to connect the drain region of the virtual LDMOS device to a reference voltage; A second interconnect set for connecting the first gate portion and the third gate portion to the source / body of the one or more active LDMOS devices; and A third interconnect set for connecting the second gate fold portion and the fourth gate fold portion to the gate terminals of the one or more active LDMOS devices.

Images