Semiconductor structure and method for providing body ties to cascode transistors

Abstract

Semiconductor structures and methods for providing a body tie to a cascode transistor are disclosed. Systems, methods, and apparatus for improved body-tied structures are described. The improved body-tied structures are configured to have a lower resistance body tie when the transistor is "off" (Vg is approximately 0 volts). When the transistor is "on" (Vg > Vt), the resistance to the body tie is much higher, thereby reducing the performance penalty associated with the presence of a body tie. Spatially efficient body-tied structures suitable for cascode configurations are also described.

Description

[0001] This invention application is a divisional application of patent application No. 201680085521.9 entitled "Matching Body Contact for SOI Transistors", filed on June 29, 2016, with international application number PCT / US2016 / 040193, and entered the Chinese national phase on November 8, 2018.

[0002] Cross-reference to related applications

[0003] This application relates to U.S. Application No. 14 / 945,323, filed November 18, 2015, the entire disclosure of which is incorporated herein by reference. Technical Field

[0004] The various embodiments described herein generally relate to systems, methods, and apparatus for suppressing the buoyancy effect in semiconductor devices. Background Technology

[0005] Floating-body silicon-on-insulator (SOI) transistors are limited in terms of operating voltage and power due to the accumulation of hot carriers—which can increase the potential of the body region of the SOI transistor. Body-tied SOI transistors, in contrast, have been shown to extend voltage and power handling capabilities.

[0006] For drain-source voltages greater than approximately 3.2 volts (Vds), floating-body SOI transistors have been shown to exhibit non-conductive hot carrier drift (e.g., a decrease in threshold voltage and an increase in drain current in the non-conductive state). Body-connected devices have been shown not to experience this mechanism.

[0007] When a floating-body transistor is conducting, the corresponding floating effect can cause a sudden decrease in the transistor's output impedance under moderate bias at various levels of drain-source voltage. This can, in turn, reduce the transistor's analog gain and increase the complexity of modeling the corresponding device. Body-connected devices (transistors) suppress the decrease in output impedance and, for higher drain-source voltages, extend the range of higher output impedances.

[0008] Body connections on wide (large gate width) transistors with conventional (H-gate, T-gate) body connection structures become less effective at suppressing device degradation due to high resistance and increased parasitic capacitance, which reduces the ability to control the floating body effect. In particular, for large transistor widths, conventional body connection devices (e.g., H-gate, T-gate) are less effective at suppressing such degradation, and the increased drain-gate capacitance associated with conventional body connection devices can degrade performance in applications using such transistors, such as radio frequency (RF) amplifiers.

[0009] Although body connections can improve the voltage handling capability of a transistor, the conductivity of the transistor in the on-state may be reduced. Summary of the Invention

[0010] It may be desirable to extend the voltage and power handling capabilities of semiconductor devices, such as RF integrated circuits (ICs), by providing improved body interconnect structures. Such semiconductor devices may include metal-oxide-semiconductor (MOS) field-effect transistors (FETs), complementary metal-oxide-semiconductor (CMOS) FETs, and particularly MOSFETs and CMOSFETs fabricated on silicon-on-insulator (SOI) and silicon-on-sapphire (SOS) substrates. Such semiconductor devices equipped with improved body interconnect structures according to various teachings of this disclosure can, for example, be used in radio frequency (RF) amplifiers, including but not limited to RF power amplifiers and cellular RF power amplifiers operating under various operating categories, including but not limited to switching categories D, E, and F, saturation categories B and C, and linear categories A and A / B.

[0011] According to a first aspect of this disclosure, a semiconductor structure is provided, comprising: a first gate polysilicon structure defining a first body region having a first conductivity type; a second gate polysilicon structure defining a second body region having a first conductivity type; a first drain region adjacent to the first body region having a second conductivity type; a first source region adjacent to the first body region having a second conductivity type; a second source region adjacent to the second body region having a second conductivity type; a second drain region adjacent to the second body region having a second conductivity type; the first source region and the second drain region defining a first common source / drain region having a second conductivity type; and a first non-conductive barrier. The system comprises: a separation region configured to form an interruption in the second body region to divide the second body region into two separate second body regions; at least one first body contact region having a first conductivity type, the at least one first body contact region being formed in the first common source / drain region, separate from the first body region and the second body region and abutting a first non-conductive isolation region; and at least one first body tab having a first conductivity type, the at least one first body tab extending across the first common source / drain region and contacting the first body region and the at least one first body contact region, wherein the first non-conductive isolation region, the at least one first body contact region, and the at least one first body tab define a first butted body connection structure.

[0012] According to a second aspect of this disclosure, a semiconductor structure comprising a plurality of transistors is described, the semiconductor structure comprising: an insulating layer; a silicon layer covering the insulating layer; an active region formed in the silicon layer, the active region extending through the silicon layer to contact the insulating layer, the active region comprising a body region, a source region, and a drain region of one or more fingers of each of the plurality of transistors, the plurality of transistors being configured as a cascode stack arranged from top to bottom, wherein, for every two successive transistors in the cascode stack, the source region of the finger of the top transistor and the drain region of the finger of the bottom transistor are formed in a common source / drain region of the silicon layer; and at least one mating body connection structure associated with the top finger, comprising: i) a non-conductive isolation region; ii) a body contact region formed in the common source / drain region of the fingers of two successive transistors, separated from the body region of the fingers and abutting the isolation region of the non-conductive isolation region; and iii) a body protrusion region formed in the silicon layer, contacting the body region of the fingers of the top transistor and the body contact region, wherein at least one non-conductive isolation region is configured to: form an interruption in the region of the silicon layer defining the body region of the fingers of the bottom transistor to divide the body region into separate body regions, and extend the interruption in the region of the silicon layer defining the body region of the fingers of one or more successive transistors adjacent to the bottom transistor and the common source / drain region to divide the region into separate regions.

[0013] According to a third aspect of this disclosure, a method is provided for providing a body connection to a transistor arranged in a cascode configuration, the cascode configuration comprising: a first gate polysilicon structure defining a first body region having a first conductivity type; a second gate polysilicon structure defining a second body region having a first conductivity type; a first drain region adjacent to the first body region having a second conductivity type; a first source region adjacent to the first body region having a second conductivity type; a second source region adjacent to the second body region having a second conductivity type; a second drain region adjacent to the second body region having a second conductivity type; the first source region and the second drain region defining a first common source / drain region. The domain has a second conductivity type; the method includes: forming an interruption in a second body region through a first non-conductive isolation region to divide the second body region into two separate second body regions; forming at least one first body contact region having a first conductivity type in a first common source / drain region, the at least one first body contact region being separate from the first body region and the second body region and abutting against the first non-conductive isolation region; and forming at least one first body protrusion having a first conductivity type, the at least one first body protrusion extending across the first common source / drain region and contacting the first body region and the at least one first body contact region, wherein the first non-conductive isolation region, the at least one first body contact region, and the at least one first body protrusion define a first mating body connection structure. Attached Figure Description

[0014] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one or more embodiments of this disclosure and, together with the description of exemplary embodiments, serve to illustrate the principles and implementation of this disclosure.

[0015] Figure 1A A top view of an N-type MOSFET transistor device is shown.

[0016] Figure 1B It shows Figure 1A A cross-sectional view of the transistor device along line A.

[0017] Figure 1C It shows Figure 1A A schematic representation of a transistor device.

[0018] Figure 2A A top view of an N-type MOSFET transistor device with a T-gate body connection according to an embodiment of the prior art is shown.

[0019] Figure 2B It shows Figure 2A A schematic representation of a transistor device.

[0020] Figure 2C A top view of an N-type MOSFET transistor device with an H-gate body connection according to an embodiment of the prior art is shown.

[0021] Figure 3A A top view of an N-type MOSFET transistor device with a source-body connection according to an embodiment of the prior art is shown.

[0022] Figure 3B It shows Figure 3A A schematic representation of a transistor device.

[0023] Figure 4A A top view of an N-type MOSFET transistor having a mating body contact according to an embodiment of the present disclosure is shown.

[0024] Figure 4B It shows Figure 4A A cross-sectional view of the transistor device along line B.

[0025] Figure 5A A top view of an N-type MOSFET transistor having a mating body contact according to an alternative embodiment of the present disclosure is shown.

[0026] Figure 5B It shows Figure 5A A cross-sectional view of the transistor device along line C.

[0027] Figure 5C It shows Figure 4A and Figure 5A A schematic representation of a transistor device.

[0028] Figure 6 A top view of an N-type MOSFET transistor with mating body contacts according to an alternative embodiment of the present disclosure is shown, wherein the body contacts are provided via a plurality of different body protrusions.

[0029] Figure 7A and Figure 7B It shows Figure 6 A top view of an alternative embodiment to the one shown.

[0030] Figure 8A A top view of two adjacent fingers of a transistor device having mating body contacts according to an embodiment of the present disclosure is shown, wherein corresponding polysilicon protrusions are created in a common source region.

[0031] Figure 8B It shows Figure 8A An alternative embodiment of the embodiment shown is in which the corresponding polysilicon protrusions are joined.

[0032] Figures 8C to 8H A top view of stacked transistors having mating body contacts according to various embodiments of the present disclosure is shown.

[0033] Figure 8I schematic representation Figure 8C and Figure 8D Stacked transistors.

[0034] Figure 8J schematic representation Figure 8E Stacked transistors.

[0035] Figure 8K schematic representation Figure 8F Stacked transistors.

[0036] Figure 9A A top view of a transistor with isolated docking body contacts is shown.

[0037] Figure 9B It shows Figure 9A A cross-sectional view of the transistor device along line F.

[0038] Figure 9C A top view of two adjacent fingers of a transistor device with isolated mating body contacts is shown.

[0039] Figure 9D It shows Figures 9A to 9B A schematic representation of a transistor device.

[0040] Figure 10A A diagram showing the resistance of the docking body connection (contact) relative to the gate bias voltage and the width of the body protrusion.

[0041] Figure 10B A graph comparing the drain-source currents in the off-state of two floating transistors and two transistors having docking body connections according to various embodiments of the present disclosure is shown.

[0042] Figure 11A and Figure 11B The diagram shows the drain-source current versus drain-source voltage of a transistor device having a docking body connection according to an embodiment of the present disclosure and a transistor device otherwise identical without a body connection.

[0043] Figures 12A to 12C A graph is shown illustrating the effect of the number of body protrusions of the docking body connected transistor according to the present invention on the drain-source current and drain-source voltage response of the same transistor device.

[0044] Figure 12DA diagram is shown illustrating the output conductance of the docking body-connected transistor device and the number of body protrusions according to various embodiments of the present invention.

[0045] Figure 13 A graph showing the effect of hot carrier injection on floating body transistors is shown.

[0046] Figure 14 A diagram illustrating the effect of the docking body connection according to the invention on hot carrier injection is shown.

[0047] Figure 15A and Figure 15B A comparison diagram is shown, representing the total gate capacitance and drain-gate capacitance of the same transistor with various body connections and without body connections.

[0048] Figures 16A to 16B The diagram illustrates f, representing the docking body connection to the transistor according to the present invention. T frequency and f max A comparison chart of the effects of frequency.

[0049] Figure 17 A comparative graph is shown illustrating the effect of the docking body connection according to the present invention on the adjacent channel leakage ratio performance of an RF power amplifier.

[0050] Figure 18 A comparative graph is shown illustrating the effect of the docking body connection according to the present invention on the gain and output power (Pout) of a transistor under the same bias at a relatively high voltage bias.

[0051] Figure 19 A comparative graph is shown, illustrating the effect of the docking body connection according to the invention on the bias current (Ibias) for a given output power of an RF power amplifier.

[0052] Figure 20A A schematic representation of a cascode configuration including two stacked transistors is shown.

[0053] Figure 20B A schematic representation of a cascode configuration comprising three stacked transistors is shown.

[0054] Figure 21A This illustrates the case where a transistor with a cascode configuration has a finger. Figure 20A The top transistor T in the cascode configuration is shown. B The docking body connection according to the embodiments of this disclosure.

[0055] Figure 21B and Figure 21D This illustrates the case where each transistor in a cascode configuration has a single finger. Figure 20A The top transistor T in the cascode configuration is shown. B The spatially effective docking body connection according to the embodiments of this disclosure.

[0056] Figure 21C and Figure 21E The following are examples of methods for targeting different situations in the context of... Figure 21B and Figure 21D The method described in the text for creating a contact area between docking bodies is used to connect them.

[0057] Figure 22 This illustrates the provision for the case where each transistor in a cascode configuration has two fingers. Figure 20A The top transistor T in the cascode configuration is shown. B The spatially effective docking body connection according to the embodiments of this disclosure. Figure 22 It shows the transistor T provided to the top. B Each finger-shaped component has such a spatially effective docking body connection.

[0058] Figure 23 This illustrates the provision for the case where each transistor in a cascode configuration has two fingers. Figure 20B The top transistor T in the cascode configuration is shown. E The spatially effective docking body connection according to the embodiments of this disclosure. Figure 23 It shows the transistor T provided to the top. E Each finger-shaped component has such a spatially effective docking body connection.

[0059] Figure 24 This illustrates the provision for the case where each transistor in a cascode configuration has two fingers. Figure 20B The top transistor T in the cascode configuration is shown. E The docking body connection of the finger-shaped member according to the embodiments of this disclosure.

[0060] Figure 25 It shows the result of Figure 20A This represents a portion of a common-source, common-gate configuration, which has according to Figure 8B and Figure 22 It provides docking body connections for various finger-shaped elements of transistors with common source and common gate configurations.

[0061] Figure 26 It shows the result of Figure 20B This represents a portion of a common-source, common-gate configuration, which has according to Figure 8B , Figure 22 as well as Figure 23 It provides docking body connections for various finger-shaped elements of transistors with common source and common gate configurations.

[0062] Figure 27 It shows the result of Figure 20B The representation shows the full-width structure of a cascode configuration, which has according to Figure 8B , Figure 22 , Figure 23 as well as Figure 24 It provides docking body connections for various finger-shaped elements of transistors with common source and common gate configurations.

[0063] Figure 28 It shows the result of Figure 20B The representation shows the full-width structure of a cascode configuration, which has according to Figure 8B , Figure 22 as well as Figure 23 It provides docking body connections for various finger-shaped elements of transistors with common source and common gate configurations.

[0064] Figure 29A A schematic representation of a cascode configuration comprising four stacked transistors is shown.

[0065] Figure 29B It shows the result of Figure 29A The representation has the characteristics shown in Figure 8. Figure 22 , Figure 23 as well as Figure 24 The docking body connects to the full-width structure of the cascode configuration, wherein the topmost transistor T of the cascode configuration is connected. E The docking body connection is based only on Figure 24 The docking body connection. Detailed Implementation

[0066] Throughout this specification, embodiments and variations are described for the purpose of illustrating the use and implementation of the inventive concept. These illustrative descriptions should be understood as presenting examples of the inventive concept and not as limiting the scope of the concept disclosed herein.

[0067] This disclosure describes an apparatus that provides all the benefits of conventional body-connected semiconductor devices, such as H-gate MOSFET devices and T-gate MOSFET devices, without the limitations and degradation associated with these configurations. Methods for manufacturing and using such an apparatus are also described.

[0068] According to various embodiments of this disclosure, mating body contacts in semiconductor devices can improve the operational performance of semiconductor devices. As used herein, the expressions "matting body contact," "matting body connection," and "matting body connected" are equivalent, and these expressions relate to various methods and apparatuses for providing a body connection to a semiconductor device, as described below with reference to various corresponding figures, based on this disclosure. In an exemplary case of a transistor device, such a mating body connection can be provided by "connecting" a body region of the transistor device to a source region of the transistor device via a conductive path having a desired conductivity (e.g., resistivity). Alternatively, the mating body connection can be configured to connect a body region of the transistor device to an open contact provided at any desired external potential, the open contact being resistively connected to the body region of the transistor device via a conductive path having a desired conductivity.

[0069] The docking body connection according to various embodiments of this disclosure can be achieved by providing some additional structure to the semiconductor device, such as by... Figure 5B The "body protrusion" exemplified by item (512) is composed of... Figure 5A The "polysilicon protrusion" exemplified in item (510) and the part made of Figure 5A and Figure 5B The term (540) in the document exemplifies the "ontology contact area". Such a structure, as well as any other structures related to the implementation of docking ontology links according to this disclosure, will be further described in the following paragraphs.

[0070] As used herein, a body protrusion (e.g., Figure 5B Item (512) is related to the gate polysilicon structure of semiconductor devices (e.g., Figures 5A to 5B The ontology region below item (110) (e.g., Figure 5B Item (112) (i.e., transistor body, transistor channel, transistor conductive channel) has regions of the same type of doping, the body protrusion branching out from and adjacent to the body region below the gate polysilicon structure of the semiconductor device, and extending to or through the source region of the semiconductor device (e.g., Figures 5A to 5B The item (120) in the middle) or the drain region. In one exemplary embodiment of this disclosure, such a body protrusion may utilize a corresponding polysilicon protrusion branching from the gate polysilicon structure of the device (e.g., Figure 5A The protrusion is created by the term (510) and can therefore be part of the gate polysilicon structure. The polysilicon protrusion is used as a mask to prevent doping of the semiconductor region beneath the polysilicon protrusion, thereby creating the body protrusion.

[0071] As used herein, the body contact area (e.g., Figures 5A to 5B Item (540) in the text is related to the ontology region (e.g., Figure 5B The item (112) has a region with the same type of doping, and this body contact region is used to provide a low resistivity conductive path to the desired potential to be applied to the body region of the device. Therefore, the body protrusion (e.g., Figure 5B Item (512) in the middle provides a first resistivity (e.g., Figure 5C A conductive path between the body region (R1) and the body contact region, and the body contact region provides a second resistivity (e.g., Figure 5C The conductive path from R2 in the desired body connection potential.

[0072] As presented in the following sections of this disclosure, mating body contacts according to various embodiments of this disclosure can be provided by connecting one or more body protrusions to the body region of the device. According to various embodiments of this disclosure described later, such body protrusions contact a body contact region having the same type of doping as the body region beneath the gate polysilicon structure. According to various embodiments of this disclosure, the doping in the body contact region may have an associated concentration similar to, less than, or greater than the associated doping concentration of the body region. According to various embodiments of this disclosure described later, the body contact region may be created in a source region adjacent to the gate polysilicon structure, or in a region adjacent to the source region adjacent to the gate polysilicon structure. Alternative embodiments where the body contact region is located within the drain region of the semiconductor device are also possible.

[0073] The embodiments described herein are illustrated using an N-type MOSFET device. By applying different doping schemes as appropriate, those skilled in the art will readily apply the inventive concepts disclosed herein to other types of semiconductor devices, such as P-type MOSFET devices. Embodiments according to the invention can also be applied to extended drain devices, such as laterally diffused metal-oxide-semiconductor (LDMOS) devices, and other gate-controlled transistors or devices.

[0074] According to various embodiments of this disclosure, a semiconductor device having a mating body contact may include a semiconductor device comprising a field-effect transistor (FET) formed on silicon-on-insulator (SOI). The FET device may include complementary metal-oxide-semiconductor (CMOS), metal-oxide-semiconductor field-effect transistor (MOSFET), and other types of field-effect transistor (FET) devices. In embodiments, silicon-on-insulator (SOI) may include silicon-on-sapphire (SOS).

[0075] As used herein, the MOSFET P-body (e.g., Figure 5B Item (112)), P-body, P-body region, and body region refer to the gate polysilicon structure (e.g., Figures 5A to 5B The P-doped silicon below item (110) provides a conductive channel to the MOSFET during operation. The body region and body protrusions (e.g., Figure 5B Item (512) in the gate polysilicon structure and polysilicon protrusion (e.g., Figures 5A to 5B A continuous P-doped region is created below item (510) in the middle.

[0076] In one embodiment according to this disclosure, the P-doped silicon (body away from the gate polysilicon structure) below the distal end of the polysilicon protrusion contacts a P+ doped region (body contact region) of the semiconductor device. As mentioned above, such a P+ doped region defining the body contact region is a region having the same type of doping as the body region below the gate polysilicon structure, and can have any doping concentration, not limited to P+ doping.

[0077] In one exemplary embodiment according to this disclosure, the body contact region may have a square or rectangular shape. As will be described later in this disclosure, the body contact region may provide a low-resistivity conductive path to a desired body connection potential via a metal contact or via a low-resistivity layer, such as a silicide layer, on top of the contact region. Furthermore, the body contact region may contact the source region of a semiconductor device to provide a source-body connection, or be isolated from any active region of the device (e.g., source / drain region) to enable any potential to be supplied to the body (decoupled from the source potential).

[0078] In one embodiment according to this disclosure, multiple polysilicon protrusions (branching from the gate polysilicon) may be provided for the same gate polysilicon structure, wherein corresponding body protrusions (P-doped regions beneath the polysilicon protrusions) are connected to different and separate body contact regions (e.g., described later). Figure 7A ).

[0079] In another embodiment according to this disclosure, a plurality of polysilicon protrusions are provided for the same gate polysilicon, and the corresponding body protrusions may be connected to the same continuous body contact region (e.g., described later). Figure 7B ).

[0080] In one embodiment according to the present disclosure, the body protrusion contacts the body contact region at the distal end of the body region of the body protrusion, which is away from the gate.

[0081] In one embodiment of the present disclosure, the MOSFET transistor includes a plurality of fingers having associated plurality of gate polysilicon structures, wherein corresponding polysilicon protrusions are connected to each gate polysilicon structure (e.g., described later). Figures 8A to 8B ).

[0082] In another embodiment of this disclosure, the body protrusion corresponding to the polysilicon gate of the adjacent finger can be connected to the same continuous P+ doped region (e.g., as described later). Figure 8B ).

[0083] In another embodiment of this disclosure, polysilicon protrusions branching from the polysilicon gates of adjacent fingers can be joined (e.g., as described later). Figure 8B ).

[0084] According to some embodiments of this disclosure, a body contact region connected to the distal end of the body protrusion (away from the body region) is created within the source region of the MOSFET transistor, thereby creating a P+ doped region within the N+ doped source region. According to another embodiment of this disclosure, such a body contact region is created in a region adjacent to and in contact with the source region of the MOSFET transistor. It should be noted that although the body contact region is described as a P+ doped region, this should not be considered as limiting the scope of the inventor's invention, as various doping levels of the body contact region, including doping similar to that of the body region, can also be used in the body contact invention.

[0085] Further description of the above embodiments according to this disclosure will be provided in the following sections with reference to the accompanying drawings.

[0086] Figure 1A A top view of an N-type SOI MOSFET device (100) is shown. A gate finger (110) is shown located between the source region (120) and the drain region (130). The gate finger (110) has a length L. G and width W G On one hand, the gate fingers can be fabricated via a gate polysilicon structure (110) that blocks the implantation of dopant ions for doping adjacent source and drain regions of the MOSFET. Those skilled in the art will readily recognize that a multi-finger SOI device can have multiple such fingers, each of which may include a corresponding gate polysilicon structure (110), a drain region (130) with a corresponding drain contact (155), and a source region (120) with a corresponding source contact (145). In some embodiments, adjacent fingers may share a corresponding drain region and / or source region.

[0087] Figure 1B It shows Figure 1A A cross-sectional view along line A of the N-type SOI MOSFET device (100). In one aspect, a gate polysilicon structure (110) is shown disposed on an insulating gate oxide layer (115). In another aspect, the body region (112) beneath the gate polysilicon structure (110) is doped with P-type dopant (P-body), and the source region (120) and drain region (130) are heavily implanted with N-type dopant (N+). Figure 1B As shown in the cross-sectional view, the regions (112, 120, 130) of the SOI MOSFET device are created on top of a buried oxide (BOX) layer (150) formed on a semiconductor substrate (160). Therefore, due to the insulating properties of the BOX layer (150), Figure 1A and Figure 1B The SOI MOSFET depicted in this paper does not provide a conductive path between regions (112, 120, 130) and the semiconductor substrate (body). Those skilled in the art will readily recognize that regions (112, 120, 130) of the SOI MOSFET device (100) can be formed in a thin silicon layer (180) covering an insulating layer (150), such regions (112, 120, 130) extending through the depth of the thin silicon layer (180) to reach the insulating layer (150). Therefore, and as is known in the art, the SOI MOSFET device (100) can be referred to as a thin-film SOI MOSFET, where the thin film refers to the thin silicon layer (180). It should be noted that the various embodiments according to this disclosure described below can be implemented in thin-film SOI MOSFET devices.

[0088] Figure 1A and Figure 1B The SOI MOSFET device (100) depicted in the figure does not provide a body connection, which, as those skilled in the art know, is a connection between the P body and a reference (fixed) potential, such as the source region of the device. Figure 1C The SOI device schematically represented in the diagram is a floating device and is therefore susceptible to the disadvantages discussed above in this disclosure.

[0089] Figure 2A This is a top view showing an N-type MOSFET transistor (200) with a T-gate body connection structure according to a prior art embodiment. Figure 2AIn the illustrated prior art embodiment, the gate polysilicon structure (110) is extended to include a structure (210) that complements the conventional structure (110) for creating the conductive channel (i.e., the body region, the channel region) of the device (200). Thus, the T-shaped polysilicon structure (110, 210) allows for the formation of a corresponding P-body region beneath the polysilicon, which contacts a P+ region (240). The latter P+ region (240) allows for low-resistance contact with the P- region beneath the polysilicon extension (210), and therefore allows for low-resistance contact with the transistor body beneath the polysilicon region (110). The P-body region beneath the polysilicon region (210) also allows for isolation of the source region (120) from the drain region (130) relative to the heavily doped region (240). Those skilled in the art will understand that the T-gate body-connect structure of the prior art body-connected transistor (200) allows the P+ region (240) to make electrical contact with a constant voltage node to provide a conductive path for floating charge in the channel region of the transistor (200). According to some implementations, the P+ region (240) may be in contact with an overlay metal layer that is connected to a constant voltage. Such a constant voltage may be a voltage applied to the source terminal of the transistor, or a reference potential such as ground or a fixed (negative) voltage. Those skilled in the art will understand that... Figure 2A The top view depicted is a simplified top view of the transistor (200) because only structures / elements relevant to the description of the (prior art) implementation are shown. Those skilled in the art will understand that other structures / elements, such as drain / source contacts, are omitted from such a drawing for clarity. Generally, the same approach is used when presenting the various figures that form part of this disclosure.

[0090] The T-gate body connection structure used in the N-type transistor (200) can reduce Figure 1A The floating body effect exists in the transistor (100). However, the T-gate body connected between the gate and source of the transistor (200) via an extended polysilicon structure (210) adjacent to the drain and source regions (130, 120) provides increased parasitic capacitance (C). SG ), and provides an increased parasitic capacitance (C) between the gate and drain of the transistor (200). DG Such parasitic capacitance (C) SG C DG They do not have a constant capacitance value because their value can change depending on the voltage applied to the transistor terminals. The latter is a parasitic capacitance (C). SG C DG )exist Figure 2B As shown in the diagram (as a variable capacitor), Figure 2BA transistor (200) is schematically represented, which includes a body contact providing a desired potential for connection. Those skilled in the art will readily recognize the adverse effects of such parasitic capacitance on the performance of the transistor (200), particularly reducing the switching speed of the transistor and lowering the characteristic operating frequency f of transistors (200) using T-gate body connections. T and f max Due to parasitic capacitance (C) SG C DG The non-constant nature of capacitance can also negatively affect the linearity of existing transistors (200).

[0091] Alternative implementations of the T-gate body connection known to those skilled in the art, such as Figure 2C The H-gate body interconnect described in the diagram also provides the benefit of reducing the floating body effect, but at the cost of increased parasitic capacitance, which can degrade the device's RF performance (e.g., lower f-value). T and f max ). Figure 2C The prior art implementation of the H-gate body connection depicted in the figure has the following advantages: it allows for transistors with a large width (W). G In the case of T-gate body connection, the increased parasitic capacitance (C) is discussed. SG C DG At the cost of these and related negative effects, more efficient (e.g., symmetrical) body connections are provided. However, for large transistor widths, H-gate or T-gate cannot provide efficient body connections to the transistor because providing body connections at the far end of the transistor channel would result in higher resistance relative to the middle of the channel width.

[0092] Figure 3A This is a top view showing an N-type MOSFET transistor (300) with a source-body connection structure according to a prior art embodiment. Figure 3A In the illustrated prior art embodiment, a body contact is provided by adding a P+ region (340) in the source region (120), the P+ region (340) connecting the P-body region below the gate polysilicon structure (110) to the source region (120). In other words, the P+ region (340) provides a low-resistance path between the source region (120) and the P-body region below the gate polysilicon structure (110), such as Figure 3B It is depicted illustratively.

[0093] and Figure 2A The situation is the same as that of the T-gate body connection structure. Figure 3A The source-body connection structure used in the N-type transistor (300) can reduce Figure 1AThe floating body effect exists in the transistor (100). Furthermore, since there is no extended gate polysilicon structure (110) provided, for example, in the T-gate (and H-gate) structure, Figure 3A The source-body connection structure does not provide additional parasitic capacitance.

[0094] Figure 3A The region (340) in the transistor must link the source region (120) to the P-body region associated with the gate polysilicon structure (110). Therefore, the region (340) must have a non-zero overlap (Δ) with the P-body region (see “MITTL Low-Power FDSOI CMOS Process”, revised June 2006, 2006: 1, the entire contents of which are incorporated herein by reference). This overlap may locally alter the characteristics of the conductive channel of the transistor (300) in the overlapping region, and may therefore negatively affect the transistor's performance, for example, by causing nonlinear responses of the transistor (300) (e.g., IV characteristic curves).

[0095] If passed Figure 3A The source body connection configuration provided by the prior art implementation may also introduce increased manufacturing complexity, including aligning the P+ region (340) relative to the gate polysilicon region (110). The accuracy associated with this latter alignment step is affected because any variation in alignment can directly impact the linearity of the transistor and the consistency of its IV characteristic curves, and also affects the cost and yield of manufacturing such a transistor.

[0096] Figure 4A This is a top view showing an N-type MOSFET transistor (400) having a mating body contact according to an embodiment of the present disclosure. According to an embodiment of the present disclosure, the MOSFET transistor device (400) may be a thin-film SOI device, comprising a layer formed on a covering insulating layer (…). Figure 4B 150) thin silicon layer ( Figure 4BThe active regions (e.g., 120, 130) in the transistor (180) extend through the depth of the thin silicon layer to reach the insulating layer. The transistor (400) includes a polysilicon protrusion (410) that branches off from the gate polysilicon structure (110), passes through the source region (120), and extends beyond the source region (120) to the body contact region (440) adjacent to the source region (120). Since the polysilicon protrusion (410) is a structure adjacent to the gate polysilicon structure (110) (e.g., forming a single structure), a corresponding body protrusion is created below the polysilicon protrusion (410) having the same type (doped) as the P-body region below the gate polysilicon structure (110) (because the polysilicon protrusion (410) prevents N+ from being injected into the P-body during the implantation phase associated with, for example, the doping of the adjacent drain region (130) and source region (120). Depend on Figure 4B As can be seen, such a body protrusion connects the P-body region below the gate polysilicon structure (110) to the body contact region (440) adjacent to the source region (120). Figures 4A to 4B (The region shown is designated as P+). According to various embodiments of this disclosure, the body contact region has the same type of doping as the P body region, and the body contact region may have the same concentration (e.g., P-) or a higher concentration (e.g., P+) compared to the concentration of the P body region.

[0097] Further reference Figures 4A to 4B During operation of the transistor (400), the body contact region (440) and the body protrusion (412) can provide a conductive path for charge carriers between the transistor body (112) and the N+ source region (120), which provides a final extraction node for the floating charge previously contained in the transistor body (112).

[0098] Figure 4B It shows Figure 4A The N-type MOSFET transistor (device) (400) with mating body contact according to an embodiment of the present invention is shown in the figure. Figure 4A A cross-sectional view of line B. (From...) Figure 4B As can be seen from the cross-sectional view, the transistor body region (112) below the gate polysilicon structure (110) is adjacent to the P-body region (412), which is formed below the polysilicon protrusion (410) and is referred to herein as the body protrusion. The transistor (400) along... Figure 4A The cross-sectional view of line A in the previous discussion can be found in the following. Figure 1B I saw it in the middle.

[0099] Figure 5AA top view of an N-type MOSFET transistor (500) with a mating body contact according to another embodiment of the present disclosure is shown. The transistor (500) includes a polysilicon protrusion (510) branching from the gate polysilicon structure (110) into the source region (120) and extending into a P+ region (540) created within the source region (120), i.e., the body contact region. Since the polysilicon protrusion (510) is adjacent to the gate polysilicon structure (110), a corresponding body protrusion is created beneath the polysilicon protrusion (510) having the same type (doping) as the P-body region beneath the gate polysilicon structure (110). Figure 4B As can be seen, such a body protrusion connects the P-body region under the gate polysilicon structure (110) to the body contact region (540) formed in the source region (120).

[0100] Figure 5B It shows Figure 5A The N-type MOSFET transistor (device) with mating body contact shown in the embodiment of the present invention is shown along... Figure 5A A cross-sectional view of line C. (From...) Figure 5B As can be seen in the cross-sectional view, the body region (112) below the gate polysilicon structure (110) is adjacent to the P-body region (512) (body protrusion) formed below the polysilicon protrusion (510). Furthermore, the body protrusion (512) contacts a body contact region (540) created within the source region (120) at its distal end. The transistor (500) along... Figure 5A The cross-sectional view of line A in the previous discussion can be found in the following. Figure 1B I saw it in the middle.

[0101] As is known to those skilled in the art, a low resistivity layer, such as a silicide layer, can be present on top of exposed silicon regions of a semiconductor device. Such a low resistivity layer can provide a low-resistivity conductive path between all points in the underlying silicon region. For example, refer to… Figure 5B A continuous silicide layer (not shown) deposited on top of regions (120) and (540) can provide a low resistivity conductive path between any point in two adjacent regions (120) and regions (540).

[0102] Further reference Figures 4A to 5B , Figure 4A and Figure 5AThe body protrusions (412, 512) of the transistors (400, 500) depicted according to embodiments of the present disclosure can provide a first resistive (conductive) path between the body region (112) and the body contact region (440, 540), and a continuous low resistivity layer, such as a silicide layer, deposited on top of the body contact region (440, 540) and the source region (120) can provide a second resistive path between the body protrusions (412, 512) and the source region (120). Those skilled in the art will readily understand that, based on the doping type and concentration of these regions, the resistance (R1) associated with the first resistive path can be substantially greater than the resistance (R2) associated with the second resistive path. Figure 5C This is a schematic representation of an N-type MOSFET transistor (400, 500), wherein a body protrusion (412, 512) and a body contact region (440, 540) provide a resistive connection between the transistor's body and source (a first resistive path and a second resistive path, respectively, with equivalent resistances R1 and R2). This resistive connection is formed by... Figure 5C The connection between the source S of the transistor and the resistor R (=R1+R2) is represented.

[0103] A second resistive path between the body protrusions (412, 512) and the source region (120) can be provided using alternative methods of conductive (silicide layer) discussed above. According to embodiments of this disclosure, metal contacts associated with different regions can be used to provide the second resistive path. For example, a second low-resistivity path can be created by bridging metal contacts on top of the body contact regions (440, 540) to metal contacts (145) on top of the source region (120) via metal.

[0104] Further reference Figure 5C In some cases, it may be desirable to provide different resistance values ​​R to achieve the desired effect of the provided body connection. Since the resistance R2 provided by the second resistance path is very small (essentially zero) compared to the resistance R1 provided by the first resistance path, resistance R2 cannot be used to substantially modify the resistance of resistor R. According to various embodiments of this disclosure, different resistance values ​​of resistor R can be provided by adjusting the value of resistance R1 via parameters of the body protrusions (412, 512).

[0105] According to the implementation of this disclosure, Figure 5CThe resistance value of resistor R1, and therefore the resistance value of resistor R, can be adjusted via the width and / or length of the polysilicon protrusions (410, 510) associated with the body protrusions (412, 512). Those skilled in the art will understand that modifying the width and / or length of the polysilicon protrusions (410, 510), and thus correspondingly modifying the width and / or length of the body protrusions (412, 512), can modify resistor R1 and thus modify the resistivity of the first resistive path (between region (112) and region (440, 540)).

[0106] According to another embodiment of this disclosure, the number of polysilicon protrusions (510, 410) in a given gate polysilicon structure can be more than one, for example, two, three, four or more (e.g., as described later). Figures 6 to 7B The relative spacing of the polysilicon protrusions and the width and / or length of the polysilicon protrusions (410, 510) can be used to adjust the resistance value R1 of the resistance path between the body region (112) and the body contact region (440, 540), thereby adjusting the resistance value of the resistor R.

[0107] According to another exemplary embodiment of this disclosure, the polysilicon protrusions (410, 510) may be created during a manufacturing step different from the step for manufacturing the gate polysilicon structure (110). Although such an exemplary embodiment may introduce complexity to the overall manufacturing process, it remains a possible alternative embodiment for providing the mating body contact of the present invention.

[0108] Further reference Figure 4A and Figure 5A Those skilled in the art will recognize that, with Figure 2A Compared to existing technical embodiments, the embodiments according to this disclosure reduce parasitic capacitance. Furthermore, unlike such existing technical embodiments, the embodiments of this disclosure do not introduce gate-drain parasitic capacitance C. DG Furthermore, due to... Figure 2A Compared to the polysilicon region (210) in the prior art embodiments, the size (width and / or length) of the polysilicon protrusions (410, 510) is relatively reduced, therefore Figure 4A and Figure 5A The gate-source parasitic capacitance C depicted in the embodiment according to this disclosure SG Less than Figure 2A C of the prior art implementation SG .

[0109] According to some embodiments of this disclosure, the polysilicon protrusions (410, 510) are constituent elements of the gate polysilicon structure (110) and are created using the same mask. Since they are constituent elements of the gate polysilicon structure (110), for example... Figure 3A The prior art transistor shown presents an alignment problem requiring the creation of polysilicon protrusions (410, 510) and associated body protrusions (412, 512) relative to the gate polysilicon (110) and the associated P-body (112). Given the previously discussed... Figure 3A As will be recognized by those skilled in the art from existing technical implementations, the docking body connection method described herein provides the elimination of such alignment steps and a simpler manufacturing process.

[0110] As indicated in the preceding paragraphs of this disclosure, when combined with (for example, Figure 2A , Figure 3A Compared to the body linking of existing technical implementations, for example... Figures 4A to 5C The docking body connections described in the various embodiments according to this disclosure offer the following advantages: simpler manufacturing process, adjustable body connection impedance (e.g., resistance), and reduced parasitic capacitance. Therefore, integrated circuits using transistor devices with docking body connections according to the present invention can outperform integrated circuits with similar functions using transistor devices without body connections or with body connections according to prior art embodiments. The following description... Figures 10A to 19 Comparative data graphs are shown illustrating additional performance advantages of the docking body contact (connection) according to the present invention.

[0111] As mentioned in the preceding paragraphs, according to some embodiments of this disclosure, a mating body connection can be provided to the gate polysilicon of a transistor via more than one polysilicon protrusion. Such embodiments of this disclosure... Figure 6 The description in the middle, Figure 6 yes Figure 4A An extension of the implementation methods described herein. For example... Figure 6 As shown, multiple polysilicon protrusions (610) branch out from the gate polysilicon structure (110), pass through the source region (120), and extend beyond the source region (120) to... Figure 6 The P+ region and the body contact region (440) adjacent to the source region (120) are used to form a single polysilicon structure. Such different polysilicon protrusions (610) allow for the creation of corresponding different body protrusions that provide a resistive conductive path between the P-body and the body contact region (440) below the polysilicon gate structure (110), and thus provide a resistive conductive path to the source region (110). Figure 6The cross-sectional views of the N-type MOSFET transistor (600) shown along lines A and B can be respectively... Figure 1B and Figure 4B This is obtained from the transistor width W. G In large cases, multiple polysilicon protrusions (610) may be desired. Although in Figure 6 In the exemplary embodiment of the present disclosure depicted, different polysilicon protrusions reach a common, continuous body contact region (440). However, according to an alternative embodiment of the present disclosure, such a body contact region may include one or more distinct and separate P+ regions, each such P+ region adjacent to a source region (120). Those skilled in the art will readily understand how based on… Figure 6 The exemplary structural layout described herein is used to obtain such an alternative embodiment. It should be noted that the polysilicon protrusion (610) extends along the width of the body region (via W... G The position of (definition) can be based on Figure 6 The desired design goals of the docking body connection transistor (600) are determined by this. According to an exemplary embodiment of this disclosure, such as... Figure 6 The polysilicon protrusions (610) depicted are arranged symmetrically along the width of the body region, wherein the polysilicon protrusions (610) are positioned relative to the center line of the width of the body region. Figure 6 (represented by B in the text) arranged symmetrically. According to another exemplary embodiment of this disclosure, such as... Figure 6 As depicted, polysilicon protrusions (610) are arranged at equidistant positions along the width of the body region, wherein the distance between any two consecutive polysilicon protrusions (610) along the width W G The distance is constant.

[0112] With Figure 6 The method described herein is similar to the one provided, and can be used for... Figure 5A The docking body connection embodiment described in this disclosure is extended to provide more than one polysilicon protrusion (510) branching from the gate polysilicon structure (110). For example... Figure 7A As shown, each such polysilicon protrusion (510) can reach a region within the source region (120) that includes a P+ region associated with the body contact region (540). Figure 7A As depicted in the exemplary embodiment of this disclosure, such body contact regions (540) may be different and separate, and have a one-to-one relationship with each polysilicon protrusion (510). Other embodiments of this disclosure, such as... Figure 7BThe P+ regions depicted, associated with different body contact regions (540), may be merged into one or more larger P+ regions (540), each of which may be used as a body contact region for more than one polysilicon protrusion (510).

[0113] As mentioned above, the gate polysilicon (110) can be part of the fingers of a larger device, wherein such a device may include multiple such fingers. Each such finger may be part of a separate transistor, which is combined with other transistors to create a larger device. The larger device may include multiple transistors connected in series or in parallel or a combination of series and parallel connections. As those skilled in the art know, in some cases, adjacent fingers may share the same continuous source region. According to embodiments of this disclosure, one, more than one, or all of the fingers of the larger device may have according to Figures 4A to 7B The structure provided in the document is the docking body connection structure of the structural layout.

[0114] Figure 8A An embodiment of a transistor device according to this disclosure is shown in which two adjacent fingers share a common source region (120). Each finger has an associated length L. G1 and L G2 The corresponding gate polysilicon structure (110), in some embodiments, has a length L G1 and L G2 They can be equal to each other. Each gate polysilicon structure (110) may have a corresponding polysilicon protrusion (510) branching from the gate polysilicon structure (110) into the common source region (120) and extending to the body contact region (540), which in some exemplary embodiments is a P+ region. Figure 8A The exemplary embodiment of the present disclosure depicted in the figure shows a polysilicon protrusion (510) in each gate polysilicon structure (110) that merges into the body contact region (540) at its distal end. This limitation should not be construed as limiting the scope of the invention as understood by the inventors of this application, but is merely an exemplary embodiment of the invention. As described in the above paragraphs and regarding… Figures 4A to 7BAs discussed, many different structural layouts of the mating body contacts according to this disclosure are possible, and are within the capabilities of those skilled in the art based on the teachings of this disclosure. For example, in one embodiment, the body contact region (540) may be located at the same distance from the corresponding gate polysilicon structure (110). In another embodiment, the body contact region (540) may be located at different distances relative to the corresponding gate polysilicon structure (110).

[0115] A gate polysilicon structure (110) connecting two adjacent fingers is expected. This is typically accomplished via the extension and bonding of the gate polysilicon structure outside the active region of the device (e.g., a region separated from the drain and source regions of the device). According to embodiments of this disclosure, such as Figure 8B As depicted, two adjacent gate polysilicon structures can be joined via a common polysilicon protrusion between the two adjacent gate polysilicon structures. Figure 8B In the implementation described herein, there is a component consisting of L G1 and L G2 Two gate polysilicon structures (110) of corresponding associated gate lengths are connected via a polysilicon protrusion (510) shared by the two structures (110). This allows, for example, a gate voltage provided at a gate contact associated with one gate polysilicon structure to be provided to an adjacent gate, and thus allows for a simpler and more streamlined monolithic gate polysilicon structure.

[0116] Figure 8B The public polysilicon protrusion (510) of the exemplary embodiment of the present disclosure described herein can, while being coupled to the corresponding gate polysilicon structure (110) as described above, extend to the body contact region (540) via its connection. Figure 8B The two transistor devices shown provide a docking body connection. Figure 8B The described implementation provides a mechanism and reference for docking body connection. Figures 4A to 7B The described mechanism is similar, wherein the body protrusion associated with the polysilicon protrusion (510) resistively connects the P-body region below the gate polysilicon to the common source region (120) via a body contact region (540), the body contact region (540) providing a (second) low-resistivity conductive path to the source region (540) as described above. It should be noted that, although... Figure 8B The P+ region (540) appears to be centrally located between the two gate polysilicon structures (110), but the position of such a region can be determined by... Figure 8BThe desired body connection performance requirements for each of the two devices depicted vary. Similarly, the width of the segment of the polysilicon protrusion associated with one gate polysilicon structure between the body contact regions (540) may differ from the width of the segment associated with the other gate polysilicon structure.

[0117] exist Figures 8A to 8B In the exemplary embodiments depicted according to this disclosure, a corresponding associated gate length L is provided. G1 and L G2 The adjacent fingers can be the same device or part of two discrete devices. According to another embodiment of this disclosure, adjacent fingers can correspond to, for example, the fingers of discrete devices electrically connected in a cascode configuration. In such a cascode configuration, such as... Figures 8C to 8K As depicted, the source of the first device is electrically connected to the drain of the second (later) device. Although Figures 8C to 8E and Figures 8I to 8J The exemplary configuration shown in this disclosure uses two common-source cascode transistor devices; however, those skilled in the art will understand that, as Figure 8F and Figure 8K The stacking size described herein, which includes more than two, such as three, four, five, ..., ten or more stacked devices, is also possible.

[0118] Figure 8C It shows Figure 8I The diagram shows a schematic top view of a common-source, common-gate docking configuration (800C) according to this disclosure. It should be noted that... Figure 8I The top transistor, schematically represented in the diagram, corresponds to Figure 8C The gate length L depicted in the figure and associated with it G1 The first component of the identification, and Figure 8I The bottom transistor, schematically represented in the diagram, corresponds to... Figure 8C The gate length L depicted in the figure and associated with it G2 The second device identified. (By) Figure 8C As can be seen, due to the associated gate length L G1 The source region (120) of the first device is represented by the associated gate length L. G2 The drain region (130) of the second device is shared, thereby electrically connecting such a source region and a drain region.

[0119] like Figure 8C As shown, a docking body connection to the second device can be provided via a polysilicon protrusion (510): the polysilicon protrusion (510) is connected to (via L) G2The gate polysilicon structure (110) of the second device (identified) extends over the source region (120) of the second device to a body contact region (540) formed within the source region (120) of the second device (e.g., P+ doped). As combined Figures 4A to 7B As described, such a polysilicon protrusion (510) can be used to create a corresponding body protrusion beneath the polysilicon protrusion (510), which can provide an adjustable resistive conductive path between the body region and the body contact region (540) of the second device. Since there is no body connection, therefore (via L...) G1 The first transistor (identified) is as follows: Figure 8I The three-terminal transistor shown (the top transistor in the figure).

[0120] according to Figure 8D Another exemplary embodiment of the present disclosure described herein may be provided via two polysilicon protrusions (510). Figure 8D The description in (by L) G2 The identification of the second device's docking body connection: The two polysilicon protrusions (510) are connected to the gate polysilicon structure (110) of the second device and extend over and across the source region (120) of the second device to a body contact region (440) adjacent to the source region (120) of the second device (e.g., P+ doped). Thus, as described above, such polysilicon protrusions (510) can provide corresponding body protrusions to resistively connect the body region of the second device to the body contact region (440). Figure 8D The schematic representation of the docking body connection common source common gate configuration is also by Figure 8I To provide, where (through L) G1 The first transistor (identified) is as follows: Figure 8I The three-terminal transistor shown (the top transistor in the figure).

[0121] According to some implementations of this disclosure, such as Figure 8E What is meant can also be expressed to Figures 8C to 8D (through L) G1 The first device (identified) provides one or more docking bodies for connection. For example... Figure 8E As shown, a docking body connection to the first device can be provided via a first polysilicon protrusion (510): the first polysilicon protrusion (510) is connected to (via L) G1 The gate polysilicon structure (110) of the first device (identified) extends over the common drain / source region (130 / 120) of the two cascode devices to a body contact region (540) formed within the common drain / source region (130 / 120) (e.g., P+ doped). As combined Figures 4A to 7B As described, such a polysilicon protrusion (510) can be used to create a corresponding body protrusion below the polysilicon protrusion (510), which can provide an adjustable resistive conductive path between the body region of the first device and the body contact region (540). Figure 8E A schematic representation of the common-source, common-gate configuration of the docking body connection is provided by Figure 8J To represent, where (through L) G1 and L G2 The two transistors (marked) are four-terminal transistors, each with a mating body connection.

[0122] Those skilled in the art will understand that, regarding Figures 4A to 7B Various combinations of the described structures for providing a mating body connection to either the first and second devices (or more devices for a larger stack size) in the cascode configuration discussed above according to this disclosure are feasible. For example, the first device may be provided with a mating body connection according to... Figures 4A to 5A and Figures 7A to 7B The docking body connection of any structure represented herein, and the second (later) device may be provided independently of the docking body connection provided to the first device. Figures 4A to 7B The docking body connection of any structure represented in the diagram.

[0123] Figure 8F and Figure 8K express Figure 8C and Figure 8E The extension of the exemplary embodiment according to this disclosure is depicted in the figure, wherein the common-source cascode configuration includes n transistor devices connected in series, and the source (120) and drain (130) of two adjacent devices are as follows: Figure 8C The implementation methods described herein are merged as such. It should be noted that, in accordance with this disclosure and in... Figures 8C to 8K In the cascode configuration shown in the figure, only the last device (e.g., Figure 8C The second device, and Figure 8F The nth device can be configured according to Figure 6 The structure represents the docking body connection.

[0124] According to another embodiment of this disclosure, the stack can be optimized by providing different or the same body connection structures to the different devices in the stack (e.g., Figures 8C to 8K The desired performance is achieved by providing different or the same resistance between the body and the contact for each of the stacked devices. This is described later. Figures 10A to 19 This indicates the performance of an individual device related to the body's interconnection structure.

[0125] According to some implementations, not all stacked devices are provided with a docking body structure, and therefore, for example... Figures 8C to 8D and Figures 8I to 8J As described herein, the stack may include a combination of three-terminal devices and four-terminal devices. Figure 8G and Figure 8H A further exemplary embodiment is provided in which some of the stacked (four-terminal) devices are provided with a mating body connection structure according to the present teaching, while other (three-terminal) devices are not provided with a mating body connection. Figure 8G The exemplary cascode configuration depicted in the image, only the last one (via L) Gn The device (identified) is equipped with a docking body connection according to this instruction, and according to Figure 8H The exemplary common-source cascode configuration depicted in the figure is only (via L) G2 The second device (identified) and (via L) Gn The last device (identified) is provided with a docking body connection according to this teaching. It should be understood that such exemplary embodiments should not be considered as limiting the scope of the invention, as variations of such embodiments of stacked devices having docking body connections according to this disclosure are entirely within the capabilities of those skilled in the art in light of this teaching.

[0126] The above embodiments of this disclosure describe the electrical connection between the body (channel) region and the corresponding source region of a transistor device, thereby providing an electrical connection to the potential present at the source terminal of the device. According to another embodiment of this disclosure, a docking body connection can be provided that is decoupled from the potential at the corresponding source terminal. Such an embodiment allows the docking body connection to be coupled to a potential independent of the potential at the source terminal of the corresponding device. Figure 9A and Figure 9B The corresponding structure is described in the text, and Figure 9D The corresponding schematic representation is depicted in the text.

[0127] Figure 9A A top view is depicted of a docking body connection device (900A) according to an embodiment of the present disclosure, which can be used to resistively connect the body region of a device to any potential. The transistor device (900A) (e.g., a thin-film SOI device) includes features for providing, as described above... Figure 5AThe described docking body connection has a similar structure, except that the body contact region (540) is now isolated from the source region (120) via an isolation P-region created beneath the polysilicon structure (910) connected to the polysilicon protrusion (510). Similar to the polysilicon protrusion (510), the polysilicon structure (910) allows for the creation of a corresponding isolation P-region (912) beneath the polysilicon structure (910), which is adjacent to the body protrusion created via the polysilicon protrusion (510) and thus electrically connected to the body region beneath the gate polysilicon structure (110). The isolation P-region (912) surrounds the body contact region (540) within the source region (120) as... Figure 9B The cross-sectional view depicted in the figures does not provide any contact between regions (540) and (120). Note that similar reference numerals (reference numerals) in the figures denote similar items, and therefore further description can be made with respect to other figures of this disclosure.

[0128] Figure 9B It shows Figure 9A A cross-sectional view along line F of the docking body connector (900A). Figure 9B As can be seen, the source region (120) is isolated from the body contact region (540) via an isolation P-region (912) associated with the polysilicon structure (910) and the BOX layer (150), and the BOX layer (150) extends to all active regions of the device—including Figure 9B The area (120, 912, 540) shown in the cross-sectional view provides a common foundation.

[0129] Those skilled in the art will understand that, due to isolation from the source region (120), the body contact region (540) can be coupled to any desired potential during operation of the mating body connection device (900A) of the present invention, while providing a conductive path with adjustable resistivity to the body region of the device. Such coupling of the isolated body contact region (540) to the desired potential can be provided, for example, via a metal contact connected on top of the region (540).

[0130] According to another embodiment of the present invention, such as Figure 9C What is described in the text is similar to Figure 9A and Figure 9B The relevant instruction can be extended to adjacent finger members, wherein, through (L) G1 L G2The fingers of the shared common source region (120) can provide an isolated docking body connection within the common source region (120) to allow contact with the body at any desired potential. Those skilled in the art will understand that, due to its isolation relative to adjacent regions, the body contact region (540) can be provided in any active region of the device (900C) that is different from the body region—including in the drain region (130).

[0131] It should be noted that, based on this disclosure and the previously described drawings (e.g., Figures 4A to 8H Any configuration of the docking body connected to the source pole as described in the diagram can be set as follows: Figures 9A to 9D The example illustrates an equivalent isolated docking body connection. Therefore, Figures 8C to 8K The stacked transistor structure depicted may also be provided with isolated body connection structures as needed. Those skilled in the art can further extend the teachings according to this disclosure to include configurations including isolated docking body connections from the source and combinations of docking body connections.

[0132] When the transistor is in a non-conducting state (the opposite of when the transistor is in a conducting state), the docking body connection according to the various embodiments described above can provide a lower resistance (the first resistance described above) between the transistor channel and the body contact region (e.g., regions (440, 540)). When the gate voltage Vg of a transistor having a docking body connection according to various embodiments of this disclosure is close to or lower than the transistor body voltage (threshold voltage Vt), thereby placing the transistor in a cutoff / non-conducting state, the doping in the body protrusion provides a resistive conductive path from the body contact region to the transistor body region below the gate polysilicon. The body protrusion is conductive from the surface of the silicon through the entire depth of the silicon. When the gate voltage Vg of such a transistor is close to or higher than the transistor threshold voltage Vt, thereby placing the transistor in a conducting / conducting state, there is a region of mobile charge depletion in the body protrusion. This region starts from the top surface of the active silicon layer and extends into the silicon. This depletion region becomes non-conductive, thus reducing the cross-section of the conductive silicon in the body protrusion (and thus increasing the resistivity). Therefore, compared to the case where the transistor is non-conductive, when the transistor is in a conductive state (Vg>Vt), the docking body connection according to various embodiments of this disclosure can provide a higher resistance between the transistor channel and the body connection (located at the body contact region). This higher resistance allows for reduced loss of RF characteristic performance of the transistor due to the provision of the body connection. Those skilled in the art are fully aware of the loss of RF characteristic performance of the transistor associated with providing a body connection to the transistor, and therefore can appreciate the benefits of the docking body connection according to this disclosure.

[0133] Figure 10A A graph showing the (effective) docking body connection resistance Reff versus the gate bias voltage Vg and the body protrusion width (in μm). From Figure 10A As can be seen from the figure, for a given body protrusion width (the width along the gate width), the body connection resistance increases with the gate bias voltage Vg. Specifically, for the case where the gate bias voltage Vg = -0.3V (transistor is not conducting), the effective body connection resistance is 1MΩ, and for the case where the gate bias voltage Vg = 1V (transistor is conducting), the effective body connection resistance is greater than 1000MΩ. Furthermore, from... Figure 10A As can be seen from the figure, for a given gate bias voltage Vg, the effective resistance decreases as the width of the body protrusion increases.

[0134] Transistors having docking body connections according to various embodiments of the present disclosure can exhibit performance advantages compared to transistors without body connections (floating bodies) or transistors with conventional (H-gate, T-gate) body connections. Such performance advantages include, but are not limited to, improved control of majority carriers and potential in the body region of the transistor without the disadvantages of conventional (H-gate, T-gate) body connection transistors.

[0135] Compared to floating transistors, the docking body connection according to the present invention provides: higher breakdown voltage, lower drain-source current (Ids) in the off state (non-conductive state) under elevated drain-source voltage (Vds), less reduction in output impedance with increasing Vds in the on state (conductive state), and improved HCI (hot carrier injection) performance for RF applications.

[0136] Compared to conventional (H-gate, T-gate) body-connected transistors, the mating body connection according to the present invention provides: less total gate parasitic capacitance (the sum of all capacitances attached to the gate), less drain-gate capacitance (not increased compared to floating-body transistors), and higher f (due to the reduced drain-gate capacitance). max Furthermore, there are no restrictions on the channel width to maintain the characteristics of the body-connected devices. Additionally, with... Figure 3A Compared with the existing source-body connection structure shown in the figure, the present docking body connection invention provides a simpler manufacturing process, lower manufacturing cost and higher process yield.

[0137] In addition to benefiting from all other applications with improved output impedance and breakdown voltage, the above-mentioned features of the docking body connection according to the invention enable higher peak power increase efficiency (PAE) for RF power amplifier applications.

[0138] Figure 10B This shows the effect of two floating body transistors (T) 1AT 1B ) and two transistors (T) connected to a docking body according to various embodiments of this disclosure. 2A T 2B A graph comparing the drain-source current (Ids) of transistor T in the off state (e.g., gate-source voltage Vgs = 0). 1A With transistor T 2A The same (e.g., the same gate length), and transistor T 1B With transistor T 2B Same (e.g., same gate length). Figure 10B The diagram clearly shows that for a transistor (T) with a docking body connection... 2A T 2B In the case of [missing information], the cutoff-state current Ids (leakage current) is lower at the point where the drain-source voltage Vds increases. Furthermore, based on [missing information]... Figure 10B The diagram also clearly shows that for transistors (T) with docking body connections... 2A T 2B In the case of ), the effective breakdown voltage (the voltage Vds when the current Ids reaches a certain level) is higher because at all points on the curve, (T) 2A T 2B The Ids current is lower than (T) 1A T 1B The Ids current.

[0139] Figure 11A and Figure 11B Plots of Ids and Vds for the same transistor devices with and without a body connection are shown, where the gate-source voltage Vgs is varied in 25mV steps. As can be seen from these plots, the transistor with the body connection exhibits a smooth Ids vs. Vds curve regardless of the Vgs voltage, and does not show the characteristic curves seen elsewhere. Figure 11B The well-known warping (kink) is a characteristic of floating-body transistors. Figure 11B The location of the visible warpage depends on the Vgs voltage applied to the floating-body transistor. As those skilled in the art will know, such warpage represents a sudden drop in the transistor's output impedance (Vds / Ids), and is undesirable in many RF applications and low-frequency analog applications. Figure 11B As can be seen, depending on the applied Vgs voltage, warping occurs at Vds voltages between 0.6V and 0.8V.

[0140] Figures 12A to 12C A graph is shown illustrating the effect of the number of body protrusions of the docking body connected transistor according to the invention on the Ids vs. Vds response of the same transistor device (e.g., the same channel length and channel width). Figure 12A The docking body connection device (shown in the figure) has a polysilicon protrusion (branching out from the corresponding gate polysilicon structure). Figure 12B The docking body connector in the middle has four polysilicon protrusions, and Figure 12C The docking body connector has seven polysilicon protrusions, each connected to a corresponding body contact area. For example, from... Figures 12A to 12C As can be seen from the figure, increasing the number of polysilicon protrusions on the docking body connector improves the output conductivity and breakdown voltage. Figure 12D The diagram shows a fixed gate width W for a fixed gate bias voltage Vg = 0.6V. G The output conductance g of the docking body connection device ds A diagram showing the number of protrusions on the body.

[0141] Figure 13 and Figure 14 A graph is shown illustrating the effect of a docking body connection relative to hot carrier injection on the same transistor device with a body connection over the lifetime of the transistor when used in RF applications. This is measured by monitoring the change in bias current at a fixed bias input voltage for the same transistor operating as an amplifier output transistor under RF power stress, with and without a docking body connection. Figure 13 The diagram shows the decrease in bias current over time due to hot carrier injection for a transistor without a body connection (a floating transistor). Figure 13 As the graph shows, hot carrier injection causes the bias current to gradually drift and decrease over time. This, in turn, can lead to undesirable performance in RF amplifiers using such transistor devices. In contrast, Figure 14 The figure illustrates that identical transistors with body connections (identical transistors) do not exhibit a change in bias current over time when operating under the same conditions. This result demonstrates that the docking body connection of the present invention provides an effective outlet for minority carrier charges generated over time within the transistor channel due to hot carrier injection. Those skilled in the art will understand that... Figure 14 The superior performance of the docking body connection according to this disclosure is shown, and it will be understood that such a curve is important for the reliability and design capability of the docking body connection transistor.

[0142] Figure 15A The diagram shows the transistor width W for a gate bias voltage Vg = 0.5 volts. G =10μm, a graph showing the normalized total gate capacitance Cgg of a transistor with a body-connected junction (T2) and the same transistor (T1) without a body connection (floating body). Figure 15B It shows the indication for and Figure 15A The same transistor / condition measurement normalized Cdg plot is shown in the attached figure. Figure 15A and Figure 15B As can be seen, with the addition of body connections, the total capacitance increases only slightly, and the measured Cdg is actually lower.

[0143] Figures 16A to 16B The diagram illustrates the docking body connection to the transistor according to this disclosure. T frequency and f max A comparison chart of the effects of frequency. Figure 16A This shows f for a floating body transistor. T Data diagram (top diagram) and f for three different configurations of the docking body connection transistor. T The data diagram shows that the floating-body transistor and the docking-body interconnect transistor are identical in other respects (e.g., the same channel length and width). As shown by... Figure 16A As can be seen from the figure, f is observed. T A slight decrease in frequency. This can be attributed to, for example, Figure 15A and Figure 15B The increased C obtained by the visible docking body connection configuration GS capacitance. Figure 16B It shows the correspondence with Figure 16A The data graph shows the same transistor / condition f. max Data chart. (As shown by...) Figure 16B As can be seen from the data chart, f max follow Figure 16A f is visible in the figure T It decreased without further deterioration.

[0144] Figure 17 A comparative graph illustrating the impact of the docking body connection according to the invention on RF power amplifier applications is shown. As those skilled in the art know, a quality factor of an RF power amplifier is the peak power increase efficiency (PAE) at a given level, also known as ACLR (adjacent channel leakage ratio). Linearity and frequency requirements in RF applications do not allow the use of conventional T-gate or H-gate transistors. However, the docking body connection configuration according to the invention can be used because, as can be seen from the previous graph, it does not increase the drain-gate capacitance C. DG Furthermore, it also increases the total gate capacitance C by a small amount. GG Therefore, by Figure 17 As can be seen from the figure, the ACLR of transistors with docking body connections is sufficiently low before it increases due to the transistors reaching compression. Figure 17Typical ACLR curves are shown for the same floating body device and docking body connection device. Note that both transistors have an ACLR of less than -40 dBc until it increases rapidly due to compression. For a wide range of device sizes and bias conditions, both the floating body configuration and the docking body connection configuration provide an ACLR of less than -40 dBc (dB relative to the corresponding RF carrier).

[0145] A higher bias voltage allows the transistor to operate at a higher output power Pout until the transistor reaches compression. Therefore, by connecting the transistor to the docking body, a higher breakdown voltage can be provided to enable operation of the transistor at a higher bias voltage and thus at a higher Pout. Figure 18 This diagram shows the gain versus Pout of the same floating-body transistor and docked-body transistor under the same bias at a relatively high voltage bias. Figure 18 As can be seen from the data graph, the docking body connection device can operate at a higher power before entering compression, which is represented by a decrease in gain (droop).

[0146] As is well known to those skilled in the art, a lower bias current (Ibias) reduces the power lost in the transistor, which is wasted power and thus reduces transistor efficiency. When operating at high bias voltages and high RF power, the voltage in the body region of the transistor can increase due to the generated charge carriers. For floating-body devices, as discussed above... Figure 11B As shown by the warping, the body potential increases. In the case of the docking body connection device according to the invention, these generated charge carriers are cleared via the conductive channel provided by the body protrusion. For RF applications, due to the increase in the body potential of the floating body transistor, the bias current can increase with increasing power, especially for operating conditions that cause transient operation in the region shown to be affected by the increased body potential (warping), while for the docking body connection transistor, the bias current still performs well. This is in Figure 19 It is shown in the middle.

[0147] Exemplary and non-limiting applications of transistor devices using docking body connections according to various embodiments of this disclosure may include: general-purpose analog circuits with body connections, power amplifiers (PA), low-noise amplifiers (LNA), analog-to-digital converters (ADC), voltage-controlled oscillators (VCO), and voltage reference circuits with frequencies ranging from DC to 100 GHz and higher.

[0148] Using the teachings according to this disclosure, the gate length can be further optimized (the gate length can be made shorter). For example, as previously described... Figure 10BIt is evident that, compared to floating-body transistors, a larger breakdown voltage can be obtained using the body-connected transistor according to this disclosure. Therefore, Figure 10B The docking body connects the transistor (T) 2,A T 2,B ) and floating body transistor (T 1,A T 1,B Compared to being able to achieve higher V DS It operates safely at higher voltages because at higher V DS Higher I associated with floating transistors at voltage DS Current could damage the transistor. As is known to those skilled in the art, the transistor (T) can be controlled by changing its gate length. 1,A T 1,B This type of breakdown, in which a larger gate length allows for a higher breakdown voltage of the transistor and therefore a higher operating voltage V0. DS In other words, floating body transistors (T... 1,A T 1,B The expected breakdown voltage is obtained via the transistor (T) connected to the docking body. 2,A T 2,B This is provided by a larger gate length compared to [previous type]. Furthermore, compared to [other types]... Figure 3A Compared to the body connection of the prior art described herein, the requirement for the overlapping area between regions (110) and (340) can specify a larger gate length.

[0149] As mentioned above Figures 8C to 8F The docking body connection of the present invention, as discussed, can be provided to a cascode configuration comprising a plurality of stacked transistors. Figure 20A This schematically represents two stacked transistors (T) A T B ) common source cascode configuration (2000A), Figure 20B This schematically represents three stacked transistors (T). C T D T E The cascode configuration (2000B) of the transistor. As discussed above, this relates to transistors (e.g., T). B T D T E The docking body connection can be provided through a body contact region arranged in the source region of the transistor, which is shared with the drain region of the adjacent transistor in a cascode configuration. Throughout this document, T is used. A To T E These definitions are used to represent, for example... Figure 20A and Figure 20B The transistors in the circuit layout shown. This is in Figure 21A It is shown in the middle, Figure 21A Described to Figure 20A transistor T B The ontology link is based on the content of this disclosure.

[0150] like Figure 21A As shown, connected to transistor T B The polysilicon protrusion (510B) of the gate polysilicon structure (110B) in the transistor (T) B T A The common source / drain region (120B / 130A) extends to the body contact region (540B) formed within the common source / drain region (120B / 130A) (e.g., P+ doped). In some cases, due to the desired physical size of the polysilicon protrusion (510B) and the desired physical size of the body contact region (540B), the transistor (T) A T B The spacing between the corresponding gate polysilicon structures (110A, 110B) may be large, and therefore the spacing of the corresponding body regions defined by such gate polysilicon structures may also be large. This is in Figure 21A As shown in the diagram, a common source / drain region is created with transistor T. B The drain region (130B) and transistor T A The source region is wider than the common region to provide spacing for the docking body connections (510B, 540B). This wider region results in two transistors (T... A T B The large spacing between the gate polysilicon structures (110A, 110B) may therefore lead to Figure 20A The overall physical size of the cascode configuration (2000A) is increased. According to embodiments of this disclosure, the overall physical size of the cascode configuration (2000A) can be reduced while providing docking body connections (e.g., the desired physical size of structures (510B, 540B)) having the same desired physical size discussed above. It should be noted that in Figure 21A In the following figures, various structures for implementing various docking body connection configurations according to this disclosure are represented by corresponding top view structures, wherein, given the relationship with Figures 1 to 2010, the ... Figure 9D Based on the above discussion, those skilled in the art can readily understand the corresponding alternative views of such various structures.

[0151] According to the implementation of this disclosure, such as Figure 21B As shown, it can be achieved by placing a transistor T at the bottom. A In the gate polysilicon structure (110A), an disconnect region is created to reduce the size of the transistor T at the top. BThe total physical dimensions of the common source cascade configuration (2000A) for docking body connection. Figure 21B In the docking body connection (2100B), the presence of the break region allows the polysilicon protrusion (510B) to extend through the break region and across the region that typically contains the gate polysilicon structure (110A), and thus allows for a smaller spacing between the two gate polysilicon structures (110A) and (110B) while maintaining the desired physical dimensions of the polysilicon protrusion (510B) and the contact region (540B). Specifically, in order to isolate the source region (120A) from the common source / drain region (120B / 130A), an isolation region (2090) is formed around the break region, and the isolation region (2090) extends to the transistor (T). B T A In the common source / drain region (120B / 130A) of the transistor, and extending to transistor T A In the source region (120A). Figure 21D In another embodiment of the present disclosure, as depicted, the isolation region (2090) extends completely through the source region (120A) to reach the boundary (2090) of such a region, and thus divides the source region (120A) into two distinct (separate left and right) source regions (120A), each of which is isolated from a common source / drain region (120B / 130A). Figure 21B , Figure 21D The isolation region (2090) can be formed by removing silicon from the region (e.g., etching, oxidation, etc.) to form a non-conductive region.

[0152] Further reference Figure 21B , Figure 21D The disconnection of the gate polysilicon structure (110A) provides a gap for the polysilicon protrusion (510B) to extend beyond a distance corresponding to the gap between the gate polysilicon structures (110A) and (110B), and the disconnection of the source region (120A) formed by the isolation region (2090) provides a conductive channel for the body protrusion defined by the polysilicon protrusion (510B), which extends over the silicon region that normally belongs to the source region (120A). Additionally, as Figure 21B , Figure 21D As depicted, the body contact region (540B) is formed in the region of the abutment isolation region (2090) to provide contact with the transistor T. B (via 110) B 120 B 130 B(Limited) Provides a docking body connection (2100B) according to this teaching. A body contact region (540B) contacts the body protrusion at the distal end of the body protrusion defined by the polysilicon protrusion (510B), the distal end being away from the transistor T. B The gate is defined by the body region of the gate polysilicon structure (110B). Figure 21B The silicon region and polysilicon (gate and body protrusions) depicted in the embodiments according to this disclosure are shaped such that a transistor T is formed. A The drain (130A) and transistor T B The silicon region of the source (120B) and transistor T A The source (120A) is separated, but the transistor T is... B The body protrusion and the transistor T therein B The body protrusion extends into the area within the body contact region (540B) to provide a continuous silicon region.

[0153] Figure 21C , Figure 21E An exemplary method for creating a (P+ doped) bulk contact region (540B) using a target (2120) for implanting a P-type dopant is shown according to this disclosure. Creating a polysilicon protrusion (510B) as a barrier layer for dopant implantation and an isolation region without silicon means that only the common area between regions 120B / 130A and the target (2120) is doped, thereby creating… Figure 21B The body contact area (540B) is depicted in the diagram. According to this teaching, the body contact area (540B) can be created using any other method known to those skilled in the art.

[0154] Figure 22 Transistor T is shown for a cascode configuration (2000A). A and T B Each includes more than one finger (e.g., two fingers, for example, via...). Figure 22 The docking body connection implementation (2200) according to another embodiment of the present disclosure, as defined by the corresponding gate polysilicon structure (110A, 110B). Those skilled in the art will understand that... Figure 22 The docking body connection configuration (2200) depicted in this disclosure is for transistors (T) A T B The extension of the teachings of the embodiments (2100B, 2100D) shown in Figures (21B, 21D) for each of the cases having more than one finger. Figure 22 It shows information about transistor T A The center line C of the source electrode (120A) LThe two transistors (T) in the mirrored cascode configuration (2000A) A T B Each of the two fingers in the transistor has a source (120A) that serves as the common source for the two fingers. Figure 22 It can be seen that transistor T A Having around the center line C L Two mirrored fingers (each finger is identified by a separate discontinuous region (110A), wherein each separate discontinuous region (110A) is broken at a region defined by an isolation region (2090), each finger having a center line C about the stack. L Similar mirrored regions (110A, 120A, 130A), centerline C L Crossing the center of area (120A). Further away from centerline C. L Furthermore, regarding the centerline mirror image, transistor T is arranged. B The fingers, each having similar regions (110B, 120B, 130B), wherein region (120B) corresponds to transistor T. A The region (130A) is shared. Transistor T B The region (130E) terminates at the region marked by line (2095).

[0155] according to Figure 22 The implementation described in the figure (2200) can be achieved by using a bottom transistor T A Disconnect regions are created in the gate polysilicon structure (110A) of each finger to reduce the number of transistors with top T. B The total physical dimensions of the common source cascode configuration (2000A) for docking body connection, such as Figure 22 As shown in the diagram. The disconnect region allows transistor T to... B Each finger's polysilicon protrusion (510B) extends through the break region, across the area typically containing the transistor T. A The region of the gate polysilicon structure (110A) of the adjacent finger members, and therefore the disconnected region in maintaining the region for transistor T B Each finger provides the desired physical dimensions of the polysilicon protrusion (510B) and contact region (540B) for docking body connection, while allowing for a smaller spacing between the two gate polysilicon structures (110A) and (110B) of adjacent fingers. Therefore, as Figure 22 The depicted top transistor T BEach finger (defined by the gate polysilicon structure (110B)) is provided with a mating body connection defined by structures (510B, 540B), which, according to an embodiment of the present disclosure, can be positioned around the centerline C of the structure (2200). L Arranged symmetrically. It should be noted that... Figure 22 Only the top transistor T in the cascode configuration (2000A) is shown. B The finger-like components are connected to the docking body. For example... Figures 25 to 29B As can be seen, the finger-shaped connections to the transistors in the cascode stack, excluding the top transistor, are docking with the main body.

[0156] Further reference Figure 22 The docking body connection (2200) is in order to connect (by...) Figure 20A (Schematic representation) Bottom transistor T in cascode configuration A The source region (120A) of each finger (110A) (which is common to both fingers) is isolated from each common source / drain region (120B / 130A), forming an isolation region (2090) around the two disconnected regions, which isolates the transistor T A The source region (120A) shared by the two fingers (110A) is broken into two different (separate) source regions (120A), each of which is isolated from the two common source / drain regions (120B / 130A). The isolation region (2090) can be formed by removing silicon from the region (e.g., etching, oxidation, etc.) to form a non-conductive region.

[0157] Continue to refer to Figure 22 The disconnection of the gate polysilicon structure (110A) provides a gap for the polysilicon protrusion (510B) to extend beyond a distance corresponding to the gap between adjacent gate polysilicon structures (110A) and (110B), and the disconnection of the source region (120A) formed by the isolation region (2090) provides a conductive channel for the body protrusion defined by the polysilicon protrusion (510B), which extends over the silicon region that normally belongs to the source region (120A). Additionally, a body contact region (540B) is formed in the region abutting the isolation region (2090) to provide a conductive channel to the transistor T. B Each finger provides a mating body connection according to this teaching. A body contact region (540B) contacts the body protrusion at the distal end of the body protrusion defined by two polysilicon protrusions (510B), the distal end being away from the transistor T. B The gate is defined by the body region of the gate polysilicon structure (110B).

[0158] Depend on Figure 22 The configuration (2200) is visible. Figure 22 The silicon region and polysilicon structure (gate and body protrusions) depicted in the embodiments according to this disclosure are formed such that for transistor T A Each finger and transistor T B The corresponding adjacent fingers form a transistor T. A The drain of the finger-shaped device (130A) and transistor T B The silicon region of the source (120B) of the adjacent finger and the transistor T A The source (120A) (for T) A The two fingers (which are common) are separate, but simultaneously supply power to transistor T. B The body protrusion of the finger and the region in which the body protrusion extends into the body contact area (540B) provide a continuous silicon region.

[0159] like Figure 21B and Figure 22 The docking body connections (2100B, 2200) depicted according to this teaching can be extended to cascode configurations with more than two, such as three, four and more stacks, wherein the disconnection of the gate polysilicon structure coupled to the isolation region (2090) as discussed above can be used to provide docking body connections to the transistors / fingers of the cascode stack.

[0160] Figure 23 Showing the target Figure 20B The three transistors (T) depicted in the text C T D T E A docking body connection implementation (2300) according to another embodiment of the present disclosure of the common source cascode configuration (2000B), wherein each transistor has at least two fingers. Figure 23 This shows information about the (bottom) transistor T. C The center line C of the source electrode (120C) L The three transistors (T) in the mirrored cascode configuration (2000B) C T D T E Each of the two fingers in the transistor (120C) is a source transistor T. C The common source of the two finger-shaped elements is interrupted by an isolation region (2090) at the center of the source (120C). Figure 23 It can be seen that transistor T C Having around the center line C LTwo mirrored fingers (each finger is identified by a separate non-contiguous region (110C), wherein each separate non-contiguous region (110C) is broken at a region defined by an isolation region (2090), each finger having a center line C about the stack. L Mirror-image similar regions (110C, 120C, 130C) (the centerline passes through the center of region (120C) along the width of the region). Further away from the centerline C L And regarding centerline C L The mirror image is of transistor T (in the middle). D The fingers (each finger is identified by a separate non-contiguous region (110D)) are arranged on the (bottom) transistor T, wherein each separate non-contiguous region (110D) is broken at a region defined by an isolation region (2090). C With (top) transistor T E Between the fingers, each finger has a similar region (110D, 120D, 130D), wherein region (120D) is similar to transistor T. C The area (130C) is shared. Additionally, at a distance C from the centerline... L At the farthest point and mirrored about the center line is the transistor T. D The finger-shaped adjacent (top) transistor T E The fingers (each finger is identified by a separate, consecutive region (110E)) each have similar regions (110E, 120E, 130E), wherein region (120E) corresponds to transistor T. D The area (130D) is shared, and the area (130E) terminates at the area marked by line (2095).

[0161] according to Figure 23 The docking body connection implementation method (2300) depicted in the figure can be achieved by using transistor T C and T D Disconnect regions are created in the gate polysilicon structure (110C, 110D) of each finger to reduce the number of transistors connected to the top transistor T. E The total physical dimensions of the common source cascode configuration (2000B) for docking body connections, such as... Figure 23 As shown. Transistor T D The disconnected region in the finger allows transistor T E The polysilicon protrusion (510E) of the finger extends through the break region and across the area that typically contains the transistor T. D The region of the gate polysilicon structure (110D) of the adjacent finger members. The disconnected region maintains the connection to the transistor T. EEach finger provides the desired physical dimensions for the polysilicon protrusion (510E) and contact region (540E) of the mating body connection, while allowing for a smaller spacing between the two gate polysilicon structures (110E) and (110D) of adjacent fingers. Figure 23 It can be seen that the disconnected regions in the polysilicon gate structures (110D) and (110C) are located at essentially the same position along the width of the finger and have essentially the same size along the width.

[0162] Further reference Figure 23 In order to place the bottom transistor T C Each finger (110C) of (T) C The shared source region (120C) of the two fingers is isolated from each common source / drain region (120E / 130D) and (120D, 130C), forming an isolation region (2090) around the four disconnected regions, thereby disconnecting the source region (120C) from the common source / drain region (120D / 130C). This can... Figure 23 As seen in the diagram, the isolation region (2090) separates each common source / drain region (120D / 130C) and the common source region (120C) into two distinct (and isolated) regions (one on each side of the isolation region (2090)), each distinct region being isolated from all other source and / or drain regions of the other fingers in the stack. Although Figure 23 Not shown, but those skilled in the art will recognize that, when necessary, this can be achieved by disconnecting parts of the region (e.g., as by...). Figure 6 The contacts 154 and 155 (illustrated in the diagram) and the metal layer for jumpering such contacts provide electrical continuity between regions disconnected by the isolation region (2090). Furthermore, it should be noted that it is not necessary to provide disconnection across regions not connected to external signals—such as disconnected common source / drain regions (120D / 130C) (see reference 1590). Figure 20B The electrical continuity of the common source and common gate configuration is due to the fact that the disconnected region cannot prevent the current from flowing across the length of the corresponding finger.

[0163] Continue to refer to Figure 23 The disconnection of the gate polysilicon structure (110D) provides a gap for the polysilicon protrusion (510E) to extend beyond a distance corresponding to the gap between adjacent gate polysilicon structures (110E) and (110D), and the disconnection of the common source / drain region (120D / 130C) formed by the isolation region (2090) and the disconnection of the common source region (120C) are for communication with transistor T. EEach polysilicon protrusion (510E) associated with each finger provides a conductive channel to a body protrusion, wherein the body protrusion extends over a silicon region that typically belongs to the common source / drain region (120D / 130C). Finally, a body contact region (540E) isolated from regions (120D / 130C) and (120C) is formed in a region abutting the isolation region (2090) to provide a conductive channel to transistor T. E Each finger provides a mating body connection according to this teaching. A body contact region (540E) contacts the body protrusion at the distal end of the body protrusion defined by two polysilicon protrusions (510E), the distal end being away from the transistor T. E The gate is defined by the body region of the gate polysilicon structure (110E).

[0164] Depend on Figure 23 The docking body connection configuration (2300) can be seen. Figure 23 The silicon region and polysilicon structure (gate and body protrusions) depicted in the embodiments according to this disclosure are formed such that for transistor T C T D and T E The center line C of the configuration (2300) L The finger-like components on the same side form a transistor T. D The drain region of the finger-shaped device (130D) and the transistor T E The silicon region of the source region (120E) of the finger-shaped device forms the transistor T. C The drain region of the finger-shaped device (130C) and the transistor T D The silicon region of the source region (120D) of the finger-shaped device and the formation of the transistor T C of (T) C The silicon regions of the source region (120C) shared by the two fingers are separated from each other, but simultaneously supply silicon to the transistor T. E The body protrusion of the finger (defined by the polysilicon protrusion (510E)) and the region in which the body protrusion extends into the body contact region (540E) provide a continuous silicon region.

[0165] Further reference Figure 23Because the disconnection of the gate polysilicon structure (110C) creates an isolated gate body region, a vertical polysilicon structure (2320) can be used to bond adjacent gate polysilicon structures on each side of the disconnection and within the isolation region (2090). According to some embodiments of this disclosure, such a vertical polysilicon structure (2320) can be fabricated wide enough to engage with contacts to a metal layer (not shown) used (e.g., via jumpers at the contacts) to restore the continuity of the disconnected gate polysilicon structure, thereby restoring transistor T. C A continuous gate channel. Those skilled in the art will readily understand the various methods and structures used to create such contacts to the metal layer.

[0166] Figure 24 Showing the target Figure 20B The three transistors (T) depicted in the text C T D T E The top transistor T in the cascode configuration (2000B) E The docking ontology connection implementation method (2400) according to another embodiment of the present disclosure. Figure 24 The diagram shows transistor T (at the top). E The center line C of the drain region (130E) L The three transistors (T) in the mirrored cascode configuration (2000B) C T D T E Each of the two fingers in the ) has a drain region (130E) that is transistor T E The common drain region of the two finger-shaped elements. Figure 24 It can be seen that transistor T E It has two fingers (each finger is identified by a corresponding area (110E)), each finger has a centerline C. L Mirror-image similar regions (110E, 120E, 130E) (the centerline passes through the center of region (130E) along the width of the region). Further away from the centerline C L And regarding centerline C L The mirror image is of the (middle) transistor T. D The arrangement of transistor T at the bottom C and (top) transistor T E The fingers are connected by fingers, each finger having a similar region (110D, 120D, 130D), wherein region (130D) is connected to transistor T. E The area (120E) is shared. Finally, at a distance C from the centerline... L The farthest point and the one mirrored about the center line is the (bottom) transistor T.C With transistor T D The adjacent fingers each have similar regions (110C, 120C, 130C), wherein region (130C) is adjacent to transistor T. D The area (120D) is shared, and the area (120C) terminates at the area marked by line (2095). It should be noted that... Figure 24 Only the top transistor T in the cascode configuration (2000B) is shown. E The finger-like components are connected to the mating body. This can be, for example, as described above. Figures 21A to 21E , Figure 22 as well as Figures 25 to 29B As seen in the image, the finger-shaped connectors of the transistors, excluding the top transistor, are connected to the main body of the transistors in the cascode configuration.

[0167] Figure 24 The docking body connection (2400) depicted in the present disclosure is a transistor T. E The body region of the finger-like element provides a common contact area (2450) (e.g., P+ doped). [The text abruptly ends here, likely due to an incomplete sentence or missing information.] Figure 24 As can be seen, the two gate polysilicon structures (110E) do not each extend through the silicon region and cross the boundary of the silicon region (defined by the outline (2095)) into region (2490). Instead, they are joined within the silicon region by a vertical polysilicon structure (2410), which defines a common body region below the two body regions defined by the structure (110E). A horizontal polysilicon protrusion (2420) is then formed at (or near) the midpoint of the structure (2410) and extends horizontally toward the edge of the silicon region (the region contained within the outline (2095)) to form a lower region doped with the same type as the body region. Similar to the body protrusion discussed above, the horizontal polysilicon protrusion (2420) provides a low-resistivity conductive path (e.g., the body protrusion) between the body region below the gate polysilicon region (110E) and the body contact region (2450). According to an exemplary embodiment of this disclosure, a silicon region surrounding a horizontal polysilicon protrusion (2420) is extended near the boundary of a silicon region defined by a contour (2095) to provide an extended region (2460), wherein a body contact region (2450) is formed. Figure 24 As can be seen, the body contact area (2450) is formed at the far end of the extension area (2460) and abuts against the non-silicon area defined by the contour (2095), while contacting the body protrusion defined by the horizontal polysilicon protrusion (2420). Figure 24 The dashed line on one side of the extended region defines the normal boundary of the silicon region without the extended region (2460).

[0168] Although the docking body connection discussed above according to this teaching is described as a connection to the top transistor in a cascode configuration of stacked transistors—for example… Figure 20A transistor T B and Figure 20B transistor T E —(the finger-like element) provides a mating body connection, but such a mating body connection can also be used together for the same cascode configuration of stacked transistors comprising two, three, four or more stacked transistors (e.g., Figures 8I to 8K as well as Figures 20A to 20B In, as described below Figures 25 to 29B The description describes providing mating body connections to the fingers of the lower stacked transistors. In cases where the transistors in a cascode stack include more than one finger, one or more fingers of the same transistor may be provided with such mating body connections, and / or one or more fingers of the same transistor may not be provided with mating body connections. The teachings of this disclosure provide methods and structures for forming such mating body connections using standard manufacturing procedures known in the art, which those skilled in the art can use to meet their design requirements. Where space efficiency is required, [the following methods can be used]. Figures 21B to 24 The docking body connections (2100B, 2200, 2300, 2400) depicted in this disclosure reduce the spacing between adjacent finger members.

[0169] Figure 25 This illustrates a stack of two transistors with a common-source, common-gate connection according to the teachings described above (e.g., Figure 20A Part of ). Figure 25 This shows information about the (bottom) transistor T. A The transistor T, mirrored by the center line of the source region A and T B Each of them has two finger-like parts. (By...) Figure 25 As can be seen from the description above... Figure 22 The docking body connection (2200) is provided to the top transistor T. B The fingers (defined by the gate polysilicon structure (110B)) are connected to the body via structures (510B, 540B, 2090). As previously described, structure (510B) defines a doped (low resistivity) conductive region identical to the body region of the fingers, which electrically connects the body region of the fingers to the body contact region (540B). Figure 8B The docking body connection (800B) is provided to the bottom transistor T of the cascode stack. AThe docking body connection is defined by the structure (510A, 540A).

[0170] Figure 26 A three-transistor cascode stack with the docking body connection described above according to this teaching is shown (e.g., Figure 20B Part of ). Figure 26 This shows information about the (bottom) transistor T. C The transistor T, mirrored by the center line of the source region C T D and T E Each of them has two finger-like parts. (By...) Figure 26 As can be seen from the description above... Figure 23 The docking body connection (2300) is provided to the top transistor T. E The fingers (defined by the gate polysilicon structure (110E)) are connected to the body contact (2300) by structures (510E, 540E, 2090). As previously described, structure (510E) defines a doped (low resistivity) conductive region identical to the body region of the fingers, which electrically connects the body region of the fingers to the body contact region (540E). Figure 22 The docking body connection (2200) is provided to the intermediate transistor T. D The finger-shaped members, connecting to the main body (2200), are formed by structures (510D, 540D, 2090). Finally, according to the above description... Figure 8B The docking body connection (800B) is provided to the bottom transistor T of the common-gate common-source stack of three transistors. C The docking body connection (800B) is defined by the structure (510C, 540C).

[0171] Figure 27 It shows Figure 20B The full-width structure (2700) of a three-transistor cascode stack is equipped with docking body connections according to various teachings of this disclosure to reduce the physical size of the cascode stack. Figure 27 The diagram shows transistor T (at the top). E The center line of the drain region of the mirrored transistor T C T D and T E Each of the four fingers has a top transistor defined by a gate polysilicon region (110E). Figure 27 It can be seen that transistor T C T D and T E The two finger-like components at the top further relate to the bottom transistor T. CThe source region is a centerline mirror image of the source region, which is contained within the bottom transistor T. C Within the region defined by the two gate polysilicon structures (110C), and transistor T C T D and T E The two finger-like components at the bottom further relate to the bottom transistor T. C The source region is a centerline mirror image of the source region, which is contained within the bottom transistor T. C Within the region defined by the two gate polysilicon structures (110C).

[0172] Further reference Figure 27 The top transistor T of the cascode stack E Each finger (defined by structure 110E) is provided with a docking body connection structure (2300), with the transistor T in the middle. D Each finger (defined by structure 110D) is provided with two docking body connection structures (2200), and the bottom transistor T C Each finger (defined by structure 110C) is provided with four docking body connection structures (800B), wherein, as shown above... Figure 26 Details of the docking body connection structure (800B, 2200, 2300) are provided.

[0173] Continue to refer to Figure 27 The above reference Figure 24 The docking body connection (2400) discussed in accordance with the teachings of this disclosure is provided to the top transistor T. E The finger-like element defines the finger-like element. Figure 27 The centerline of the drain region of the (cascode) structure (2700). Such a docking body connection (2400) includes the above reference. Figure 24 The described structures are (2410, 2420, 2450, 2460). Therefore, the top transistor T... E The finger-shaped part of the center line of the defined drain region has a mating body connection structure (2300) at the midpoint of the width of the structure (2700) and two mating body connection structures (2400) at the opposite ends of the width.

[0174] Figure 28 It shows the relationship with Figure 27 The same full-width structure, except that the docking body connection structure (2400) is removed, thus allowing the top transistor T to... E Each of the finger-shaped components has a single docking body connection structure (2300).

[0175] Figure 29B It shows Figure 29AThe full-width structure (2900B) of a four-transistor cascode stack (2900A) is equipped with body connections according to various teachings of this disclosure to reduce the physical size of the cascode stack. Figure 29B The diagram shows transistor T (at the top). E The center line C of the drain region L Mirrored transistor T B T C T D And T E Each of the four fingers has a top transistor defined by a gate polysilicon region (110E). Figure 29B It can be seen that transistor T B T C T D And T E The two finger-like components at the top further relate to the bottom transistor T. B The source region is a centerline mirror image of the source region, which is contained within the bottom transistor T. B Within the region defined by the two gate polysilicon structures (110B), and transistor T B T C T D And T E The two finger-like components at the bottom further relate to the bottom transistor T. B The source region is a centerline mirror image of the source region, which is contained within the bottom transistor T. B Within the region defined by the two gate polysilicon structures (110B).

[0176] Further reference Figure 29B The top transistor T of the cascode stack E Each finger (defined by structure 110E) is provided with a docking body connection structure (2400), transistor T D Each finger (defined by structure 110D) is provided with a docking body connection structure (2300), transistor T C Each finger (defined by structure 110C) is provided with two docking body connection structures (2200), and the bottom transistor T B Each finger (defined by structure 110B) is provided with four docking body connection structures (800B), wherein, as shown above... Figure 26 and Figure 24 Details of the docking body connection structure (800B, 2200, 2300, 2400) are provided. (This is consistent with the description above.) Figure 27 The full-width structure (2700) depicted in the middle is relative to, Figure 29BThe full-width structure (2900B) depicted in the diagram provides only one type of docking body connection structure (structure 2400) to the top transistor of the cascode stack, in contrast to two docking body connection structures (2300, 2400) that provide connection to the top transistor of the stack corresponding to structure (2700).

[0177] Depend on Figure 27 , Figure 28 and Figure 29B As can be seen, to transistors (e.g., T) E T D The protruding part of the body of the docking body connection structure of the finger-shaped member (e.g., such as) Figures 22 to 23 The body protrusions (510B, 510E) of the body connection structure (2200, 2300) shown are connected by the next (lower) transistor (e.g., T). D T C An interrupt is formed in the gate polysilicon structure of the adjacent finger to provide this. Then, to the next transistor (e.g., T...) D The docking body of the protruding part of the body (e.g., 510D) is connected to the next (lower) transistor (e.g., T). C Interruptions are formed in the gate polysilicon structure of adjacent fingers to provide this, and so on. Therefore, for each level, starting from the top transistor of the cascode stack of multiple transistors and going down to the bottom transistor of the cascode stack, the number of body protrusions in the fingers of the cascode stacked transistors doubles because each segment of the disconnected gate polysilicon structure (110D, ..., 110C) can be provided with one body protrusion (with mating body connection) that may require an interruption in the adjacent gate polysilicon structure. This in Figure 28 An example is provided, in which the top transistor T E The finger-shaped component is provided with a docking body connection structure (2300), the body protrusion (510E) of which is located next to the lower transistor T. D The gate polysilicon structure (110D) of the finger is formed in the disconnected region, thereby forming two different gate polysilicon structures (110D) on each side of the disconnection, each gate polysilicon structure subsequently having a mating body connection structure (2200). Intermediate transistor T D The two mating bodies of the finger-like component (2200) are connected, which in turn causes the gate polysilicon structure (110C) to break, thereby affecting the lower transistor T. CThe fingers, together with the disconnections formed through the body protrusion (510E), form four distinct (disconnected) gate polysilicon structures (110C). Those skilled in the art will recognize that, for cases with large cascode stack heights, the number of disconnections in the gate polysilicon structures of the fingers of the lower and upper transistors in the stack can differ significantly. If necessary, for example, regarding the above... Figure 21A As described, this large difference can be reduced by inserting a docking body connection without breaking in the adjacent gate polysilicon structure, which effectively resets the doubling of the number of body protrusions for each transistor level described above.

[0178] Finally, those skilled in the art will understand that the various semiconductor structures depicted in the figures above can be physically arranged in various patterns, some of which may include symmetry with respect to various axes, such as the symmetry discussed above. Figures 22 to 24 , Figure 27 , Figure 28 and the centerline C of 29B L The symmetry. According to some exemplary embodiments of this disclosure, such as... Figure 29B As depicted, such a semiconductor structure can also be positioned relative to the centerline C'. L Symmetrical, center line C' L The finger extends along the length of the finger through the central region of the cascode transistor.

[0179] Those skilled in the art will recognize that, as described above, Figures 20A to 28 The smaller spacing allowed by the various docking body connections described herein results in a cost advantage due to the reduced physical size of the cascode configuration. This reduction in physical size can also provide performance advantages for RF circuits. For applications requiring a large number of transistor fingers, the closer spacing of the fingers allows for shorter interconnect lengths to connect them. Excessive interconnect lengths required to connect a large number of transistor fingers can introduce parasitic capacitance, resistance, and inductance, which can degrade RF performance.

[0180] Such semiconductor devices, including those with the common-source cascode configuration discussed above and equipped with improved body interconnect structures according to various teachings of this disclosure, can be used, for example, as radio frequency (RF) amplifiers, including but not limited to RF power amplifiers and cellular RF power amplifiers operating under various operating categories, including but not limited to switching categories D, E and F, saturation categories B and C, and linear categories A and A / B.

[0181] It should be noted that although the exemplary case of an N-type SOI MOSFET is used to provide various exemplary embodiments according to this disclosure, such exemplary cases are provided primarily for clarity. Various embodiments of the docking body connection according to the invention are equally suitable for other transistor types and other transistor technologies, particularly where the source and / or drain regions extend down to an insulating layer such as the “BOX” layer of an SOI device.

[0182] The term "MOSFET" technically refers to a metal-oxide-semiconductor; another synonym for MOSFET is "MISFET," which stands for metal-insulating-semiconductor-FET. However, "MOSFET" has become the common label for most types of insulated-gate FETs ("IGFETs"). Nevertheless, it is well known that the term "metal" in the names MOSFET and MISFET is now often misused because the previously used metal gate material is now typically a polycrystalline silicon layer (polysilicon). Similarly, "oxide" in the name MOSFET may be misused because a different dielectric material is used in order to achieve a strong channel at a lower applied voltage. Therefore, the term "MOSFET" as used herein should not be understood to be literally limited to metal-oxide-semiconductor, but rather, alternatively, generally includes IGFETs.

[0183] As will be apparent to those skilled in the art, various embodiments of the present invention can be implemented to meet a wide variety of specific requirements. Unless otherwise stated above, the selection of appropriate component values ​​is a matter of design choice, and various embodiments of the present invention can be implemented using any suitable IC technology (including, but not limited to, MOSFET and IGFET structures). Integrated circuit implementations can be fabricated using any suitable substrate and process—including, but not limited to, standard bulk silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), GaAs pHEMT, and MESFET technologies. However, the inventive concepts described above are particularly useful for SOI-based fabrication processes (including SOS) and fabrication processes with similar characteristics. Fabrication in CMOS on SOI or SOS enables low power consumption, good linearity, and high-frequency operation (above approximately 10 GHz, particularly above approximately 20 GHz) due to the ability of the FET stack to withstand high power signals during operation. Monolithic IC implementation is particularly useful because, with careful design, parasitic capacitance can typically be kept low.

[0184] Voltage levels or voltage polarities and / or logic signal polarities can be adjusted or reversed according to specific specifications and / or implementation technologies (e.g., NMOS, PMOS, or CMOS, and enhancement-mode or depletion-mode transistor devices). Component voltage, current, and power handling capabilities can be adjusted as needed, for example, by adjusting device size, "stacking" components (especially FETs) in series to handle higher voltages, and / or using multiple components in parallel to handle larger currents. Additional circuit components can be added to enhance the capabilities of the disclosed circuit and / or to provide additional functionality without significantly altering the function of the disclosed circuit.

[0185] Applications of novel devices and systems, which may include various implementations, include electronic circuits used in high-speed computers, communication and signal processing circuits, modems, single-processor or multi-processor modules, single or multiple embedded processors, data switches, and application-specific modules including multi-layer, multi-chip modules. Such devices and systems may also be included as sub-components within various electronic systems—such as televisions, cellular phones, personal computers (e.g., laptops, desktops, handhelds, tablets, etc.), workstations, radios, video players, audio players (e.g., MP3 players), vehicles, medical devices (e.g., heart monitors, blood pressure monitors, etc.). Some implementations may include numerous methods.

[0186] The actions described herein can be performed in any order other than the order described. The various actions described with respect to the methods proposed herein can be performed repeatedly, sequentially, or in parallel.

[0187] The accompanying drawings, which form part of this invention, illustrate, by way of illustration and not limitation, specific embodiments in which the subject matter can be practiced. The illustrated embodiments are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments can be utilized and derived therefrom, allowing for structural and logical substitutions and changes without departing from the scope of this disclosure. Therefore, these specific embodiments should not be considered limiting, and the scope of the various embodiments is defined only by the appended claims and the full scope of their equivalents.

[0188] In this document, for convenience, these embodiments of the inventive subject matter may be referred to individually or generally by the term "invention" only, and are not intended to voluntarily limit the scope of this application to any single invention or inventive concept if more than one invention or inventive concept is actually disclosed. Therefore, although specific embodiments have been illustrated and described herein, any arrangement calculated to achieve the same purpose may replace the specific embodiments shown. This disclosure is intended to cover any and all modifications or variations of the various embodiments. After reading the above description, combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art.

[0189] An abstract of this disclosure is provided to conform to 37 C. FR § 1.72(b), which requires that the abstract enable the reader to quickly determine the nature of the technical disclosure. The abstract is submitted and should be understood not to construe as limiting the scope or meaning of the claims. In the foregoing detailed description, various features are combined in a single embodiment for the purpose of simplifying the disclosure. This approach of the disclosure should not be construed as requiring more features than expressly recited in each claim. Rather, the inventive subject matter can be found in fewer features than in a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim is itself a separate embodiment.

[0190] In addition, this technology can also be configured as follows:

[0191] (1) A semiconductor structure comprising:

[0192] A first gate polysilicon structure defines a first body region, the first body region having a first conductivity type;

[0193] A second gate polysilicon structure defines a second body region having the first conductivity type;

[0194] The first drain region adjacent to the first body region has a second conductivity type;

[0195] A first source region adjacent to the first body region has the second conductivity type;

[0196] A second source region adjacent to the second body region has the second conductivity type;

[0197] The second drain region adjacent to the second body region has the second conductivity type.

[0198] The first source region and the second drain region define a first common source / drain region, which has the second conductivity type;

[0199] A first non-conductive isolation region is configured to form an interruption in the second body region to divide the second body region into two separate second body regions.

[0200] At least one first body contact region having the first conductivity type, the at least one first body contact region being formed within the first common source / drain region, separate from the first body region and the second body region, and abutting the first non-conductive isolation region; and

[0201] The device has at least one first body protrusion of the first conductivity type, the at least one first body protrusion extending across the first common source / drain region and contacting the first body region and the at least one first body contact region.

[0202] The first non-conductive isolation region, the at least one first body contact region, and the at least one first body protrusion define a first docking body connection structure.

[0203] (2) According to the semiconductor structure of (1), wherein the first non-conductive isolation region is further configured to extend the silicon region of the first common source / drain region to provide a continuous silicon region for the at least one first body contact region and the at least one first body protrusion.

[0204] (3) The semiconductor structure according to (1) or (2), wherein the first non-conductive isolation region is further configured to form an interrupt in the second source region to divide the source region into two separate second source regions.

[0205] (4) The semiconductor structure according to (1) or (2), wherein the length of the at least one first body protrusion is greater than the length defined by the interval between the first body region and the second body region.

[0206] (5) The semiconductor structure according to (1), wherein the first body protrusion extends in a direction perpendicular to the direction defined by the first body region and the second body region along the width of the body region.

[0207] (6) The semiconductor structure according to (1) further includes:

[0208] At least one second body contact region having the first conductivity type, which is separate from the first body region and the second body region; and

[0209] At least one second body protrusion having the first conductivity type extends into the second source region and contacts one of the two separate second body regions and the at least one second body.

[0210] (7) The semiconductor structure according to (6) further includes:

[0211] A second body contact region having the first conductivity type, which is separate from the first body region and the second body region; and

[0212] An additional second body protrusion having the first conductivity type extends into the second source region and contacts another of the two separate second body regions.

[0213] (8) The semiconductor structure according to (6) or (7), wherein the at least one second body contact region is formed in the second source region and is laterally surrounded by the second source region.

[0214] (9) The semiconductor structure according to (6) or (7), wherein the at least one second body contact region abuts against the second source region.

[0215] (10) The semiconductor structure according to (9), wherein the at least one second body contact region and the other second body contact region form a continuous silicon region.

[0216] (11) The semiconductor structure according to any one of (1), (2) or (6), wherein the first gate polysilicon structure and the second gate polysilicon structure define the fingers of the first transistor and the second transistor arranged in a common-source, common-gate configuration, respectively.

[0217] (12) The semiconductor structure according to (11) further includes:

[0218] The other first finger of the first transistor;

[0219] The second transistor has another second finger; and

[0220] The other first docking body connection structure includes:

[0221] i) The other first body contact area;

[0222] ii) The additional first body protrusion; and

[0223] iii) The first non-conductive isolation region,

[0224] The additional first finger, the additional second finger, and the additional first docking body connection structure are mirror images of the first finger, the second finger, and the first docking body connection structure around the center line of the semiconductor structure, wherein the center line is defined by the central region of the second source region along the width of the second source region, and the second source region is the common source region of the second finger and the additional second finger.

[0225] (13) The semiconductor structure according to (1) further includes:

[0226] A third gate polysilicon structure defines a third body region having the first conductivity type;

[0227] A third drain region adjacent to the third body region, having the second conductivity type, the third drain region and the second source region defining a second common drain / source region, the second common drain / source region having the second conductivity type; and

[0228] A third source region adjacent to the third body region has the second conductivity type;

[0229] The first non-conductive isolation region is further configured to form an interruption in the third body region and the second common source / drain region, so as to divide the third body region and the second common source / drain region into two separate third body regions and two separate second common source / drain regions, respectively.

[0230] (14) The semiconductor structure according to (13) further includes a second docking body connection configuration, the second docking body connection configuration including:

[0231] A second non-conductive isolation region is configured to form an interruption in one of the two separate third body regions;

[0232] A second body contact region having the first conductivity type, formed within the region of the second common source / drain region, separate from the second body region and the third body region, and abutting the second non-conductive isolation region; and

[0233] A second body protrusion having the first conductivity type extends across a region of the second common source / drain region and contacts one of the two separate second body regions and the second body contact region.

[0234] Wherein, the region of the second common source / drain region is one of the two separate second common source / drain regions that is adjacent to one of the two separate second body regions.

[0235] (15) According to the semiconductor structure of (14), wherein the second non-conductive isolation region is further configured to extend the silicon region of the second common source / drain region to provide a continuous silicon region for the second body contact region and the second body protrusion.

[0236] (16) The semiconductor structure according to (14) or (15), wherein the second non-conductive isolation region is further configured to form an interrupt in the third source region to divide the source region into two separate third source regions.

[0237] (17) The semiconductor structure according to (14) or (15), wherein the length of the at least one second body protrusion is greater than the length defined by the interval between the second body region and the third body region.

[0238] (18) The semiconductor structure according to (14), wherein the second body protrusion extends in a direction perpendicular to the direction defined by the second body region and the third body region.

[0239] (19) The semiconductor structure according to (14) further includes an additional second docking body connection configuration associated with another of the two separate second body regions.

[0240] (20) The semiconductor structure according to (19), wherein the additional second docking body connection includes:

[0241] An additional second non-conductive isolation region is configured to form an interruption in another of the two separate third body regions;

[0242] A further second body contact region having the first conductivity type, formed within the region of the second common source / drain region, separate from the second body region and the third body region, and abutting the further second non-conductive isolation region; and

[0243] An additional second body protrusion having the first conductivity type extends across a region of the second common source / drain region and contacts another of the two separate second body regions and the additional second body contact region.

[0244] Wherein, the region of the second common source / drain region is one of the two separate second common source / drain regions that is adjacent to the other of the two separate second body regions.

[0245] (21) The semiconductor structure according to (20) wherein the additional second non-conductive isolation region is further configured to extend the silicon region of the second common source / drain region to provide a continuous silicon region for the additional second body contact region and the additional second body protrusion.

[0246] (22) The semiconductor structure according to (20) or (21), wherein the additional second non-conductive isolation region is further configured to form an interrupt in the third source region to further divide the source region into further separated source regions.

[0247] (23) The semiconductor structure according to (20) or (21), wherein the length of the additional second body protrusion is greater than the length defined by the interval between the second body region and the third body region.

[0248] (24) The semiconductor structure according to (20), wherein the additional second body protrusion extends in a direction perpendicular to the direction defined by the second body region and the third body region.

[0249] (25) The semiconductor structure according to (19) further includes at least one third docking body connection structure associated with one of the separate third body regions, the at least one third docking body connection structure comprising:

[0250] A third body contact region having the first conductivity type, which is separate from the second body region and the third body region; and

[0251] A third body protrusion having the first conductivity type extends across the third source region and contacts one of the separate third body regions and the third body contact region.

[0252] (26) The semiconductor structure according to (25) further includes a plurality of third docking body connection structures, each third docking body connection structure being associated with a different third body region in the separate third body regions.

[0253] (27) The semiconductor structure according to (25) or (26), wherein the third body contact region is formed in the third source region and is laterally surrounded by the third source region.

[0254] (28) The semiconductor structure according to (26) wherein at least one of the plurality of third docking body connection structures has a third body contact region abutting the third source region.

[0255] (29) The semiconductor structure according to (28) wherein two or more third body contact regions in the plurality of third docking body connection structures form a continuous silicon region.

[0256] (30) The semiconductor structure according to any one of (14), (19), (25) and (26), wherein the first gate polysilicon structure, the second gate polysilicon structure and the third gate polysilicon structure respectively define the fingers of the first transistor, the second transistor and the third transistor arranged in a common source and common gate configuration.

[0257] (31) The semiconductor structure according to (30) further includes:

[0258] The other first finger of the first transistor;

[0259] The second transistor has another second finger;

[0260] The additional third finger of the third transistor;

[0261] At least one additional first docking body connection structure, including:

[0262] i) The other first body contact area;

[0263] ii) The additional first body protrusion; and

[0264] iii) the first non-conductive isolation region; and

[0265] At least one additional second docking body connection structure, including:

[0266] iv) Another second body contact area;

[0267] v) The additional second body protrusion; and

[0268] vi) The second non-conductive isolation region;

[0269] The additional first finger, the additional second finger, the additional third finger, the additional first docking body connection structure, and the additional second docking body connection structure are mirror images of the first finger, the second finger, the third finger, the first docking body connection structure, and the second docking body connection structure around the center line of the semiconductor structure, wherein the center line is defined by the central region of the third source region along the width of the third source region, and the third source region is the common source region of the third finger and the additional third finger.

[0270] (32) A semiconductor structure comprising:

[0271] According to at least two instances of the semiconductor structure described in (12), the at least two instances are mirror images of a centerline around a centerline of the first drain region of the first finger of the at least two instances, the centerline being along the width of the first drain region defining a common first drain region, the semiconductor structure further comprising:

[0272] A first vertical polysilicon structure is joined at a first end of the first gate polysilicon structure in the at least two instances, the first vertical polysilicon structure defining a common body region below the first body region in the at least two instances; and

[0273] A first horizontal polysilicon structure extends from the midpoint of the first vertical polysilicon structure through a first edge of the silicon region of the semiconductor structure, the first horizontal polysilicon structure extending the lower common body region to the first edge of the silicon region.

[0274] (33) The semiconductor structure according to (32) further includes:

[0275] A second vertical polysilicon structure is joined to the first gate polysilicon structure at a second end of the first gate polysilicon structure in the at least two instances, the second vertical polysilicon structure defining a common body region below the first body region in the at least two instances; and

[0276] A second horizontal polysilicon structure extends from the midpoint of the second vertical polysilicon structure through a second edge of the silicon region of the semiconductor structure opposite to the first edge, the second horizontal polysilicon structure extending the lower common body region to the second edge of the silicon region.

[0277] (34) A semiconductor structure comprising:

[0278] According to at least two instances of the semiconductor structure described in (31), the at least two instances are mirror images of a centerline around a centerline of the first drain region of the first finger of the at least two instances, the centerline being along the width of the first drain region defining a common first drain region, the semiconductor structure further comprising:

[0279] A first vertical polysilicon structure is joined at a first end of the first gate polysilicon structure in the at least two instances, the first vertical polysilicon structure defining a common body region below the first body region in the at least two instances; and

[0280] A first horizontal polysilicon structure extends from the midpoint of the first vertical polysilicon structure through a first edge of the silicon region of the semiconductor structure, the first horizontal polysilicon structure extending the lower common body region to the first edge of the silicon region.

[0281] (35) The semiconductor structure according to (34) further includes:

[0282] A second vertical polysilicon structure is joined to the first gate polysilicon structure at a second end of the first gate polysilicon structure in the at least two instances, the second vertical polysilicon structure defining a common body region below the first body region in the at least two instances; and

[0283] A second horizontal polysilicon structure extends from the midpoint of the second vertical polysilicon structure through a second edge of the silicon region of the semiconductor structure opposite to the first edge, the second horizontal polysilicon structure extending the lower common body region to the second edge of the silicon region.

[0284] (36) According to the semiconductor structure described in (11), wherein the transistor in the common-source, common-gate configuration is a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0285] (37) The semiconductor structure according to (36), wherein the transistor is manufactured using a technology according to one of the following: a) silicon-on-insulator (SOI) technology and b) silicon-on-sapphire (SOS) technology.

[0286] (38) The semiconductor structure according to (30) wherein the transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0287] (39) The semiconductor structure according to (38) wherein the transistor is manufactured using a technology according to one of the following: a) silicon-on-insulator (SOI) technology and b) silicon-on-sapphire (SOS) technology.

[0288] (40) The semiconductor structure according to (36) is suitable for use as an amplifier in applications selected from the group consisting of: a) radio frequency (RF) amplifiers, b) RF power amplifiers, c) cellular RF power amplifiers, d) switched RF power amplifiers, e) CMOS (complementary metal-oxide-semiconductor) RF power amplifiers, and f) cellular CMOS RF power amplifiers.

[0289] (41) According to the semiconductor structure of (40), wherein the operating category of the amplifier is one or more of the following categories: i) linear category A, ii) linear category A / B, iii) saturation category B, iv) saturation category C, v) switching category D, vi) switching category E, and vii) switching category F.

[0290] (42) The semiconductor structure described in (38) is suitable for use as an amplifier in applications selected from the group consisting of: a) radio frequency (RF) amplifiers, b) RF power amplifiers, c) cellular RF power amplifiers, d) switched RF power amplifiers, e) CMOS (complementary metal-oxide-semiconductor) RF power amplifiers, and f) cellular CMOS RF power amplifiers.

[0291] (43) According to the semiconductor structure described in (42), wherein the operating category of the amplifier is one or more of the following categories: i) linear category A, ii) linear category A / B, iii) saturation category B, iv) saturation category C, v) switching category D, vi) switching category E, and vii) switching category F.

[0292] (44) A semiconductor structure comprising a plurality of transistors, the semiconductor structure comprising:

[0293] Insulating layer;

[0294] A silicon layer covering the insulating layer;

[0295] An active region formed in the silicon layer, the active region extending through the silicon layer to contact the insulating layer, the active region including a body region, a source region, and a drain region of one or more fingers of each of the plurality of transistors, the plurality of transistors being configured as a cascode stack arranged from top to bottom, wherein, for every two successive transistors in the cascode stack, the source region of the finger of the top transistor and the drain region of the finger of the bottom transistor are formed in a common source / drain region of the silicon layer; and

[0296] At least one docking body connection structure associated with the top finger includes:

[0297] i) Non-conductive isolation region;

[0298] ii) A body contact region formed in the common source / drain region of the fingers of two successive transistors, separated from the body region of the fingers and abutting the isolation region of the non-conductive isolation region; and

[0299] iii) A body protrusion region formed in the silicon layer, which contacts the body region of the finger of the top transistor and the body contact region.

[0300] Wherein, at least one of the non-conductive isolation regions is configured as follows:

[0301] An interruption is formed in the region of the body region of the finger defining the bottom transistor in the silicon layer to divide the body region into separate body regions.

[0302] The interruption in such a region of the silicon layer is extended to divide the region into separate regions, wherein the regions define the body region of the fingers of one or more successive transistors adjacent to the bottom transistor and a common source / drain region.

[0303] (45) The semiconductor structure according to (44) further includes:

[0304] Additional docking body connection structures associated with the bottom fingers, wherein the body protrusion region of each of the additional docking body connection structures contacts a separate body region of the fingers of the bottom transistor.

[0305] (46) The semiconductor structure according to (45), wherein:

[0306] Each finger of the transistors in the plurality of transistors includes a number of associated docking body connection structures equal to the number of separate body regions of each finger, and

[0307] The protruding body region of each of the associated docking body connection structures contacts the separate body region of each finger.

[0308] (47) The semiconductor structure according to (44) or (45), wherein:

[0309] The common-source, common-gate stack includes a first top transistor and a last bottom transistor.

[0310] Each of the plurality of transistors in the cascode stack includes two or more fingers; and

[0311] The regions of any two fingers of each transistor are mirrored around a center line defined by the width of a common source region, which is the source region of the two fingers of the last bottom transistor.

[0312] (48) The semiconductor structure according to (47), wherein the semiconductor structure is symmetrical with respect to the center line.

[0313] (49) The semiconductor structure according to (47) wherein each finger of the first top transistor includes one and only one associated docking body connection structure.

[0314] (50) The semiconductor structure according to (47) wherein each finger of the transistor adjacent to the first top transistor includes one and only one associated docking body connection structure.

[0315] (51) The semiconductor structure according to (50), wherein the regions of any two fingers of each transistor are further mirrored around a centerline defined by the width of a common drain region, the common drain region being the drain regions of the two fingers of the first top transistor, the two fingers including a first top finger and a second top finger, the semiconductor structure further comprising:

[0316] A vertical polysilicon structure, which joins the gate polysilicon structures of the first top finger and the second top finger, the vertical polysilicon structure defining a common body region below the body regions of the first top finger and the second top finger; and

[0317] A horizontal polysilicon structure extends from the midpoint of the vertical polysilicon structure through the edge of the silicon region of the semiconductor structure, the horizontal polysilicon structure extending the lower common body region to the edge of the silicon region.

[0318] (52) The semiconductor structure according to (51), wherein the semiconductor structure is symmetrical with respect to a centerline passing through the center of the one or more fingers of each of the plurality of transistors along the length of the one or more fingers.

[0319] (53) The semiconductor structure according to (48) wherein the semiconductor structure is symmetrical with respect to a centerline passing through the center of the one or more fingers of each of the plurality of transistors along the length of the one or more fingers.

[0320] (54) The semiconductor structure according to (49) wherein the semiconductor structure is symmetrical with respect to a centerline passing through the center of the one or more fingers of each of the plurality of transistors along the length of the one or more fingers.

[0321] (55) A method for providing a body connection to a transistor arranged in a common-source, common-gate configuration, the common-source, common-gate configuration comprising:

[0322] A first gate polysilicon structure defines a first body region, the first body region having a first conductivity type;

[0323] A second gate polysilicon structure defines a second body region having the first conductivity type;

[0324] The first drain region adjacent to the first body region has a second conductivity type;

[0325] A first source region adjacent to the first body region has the second conductivity type;

[0326] A second source region adjacent to the second body region has the second conductivity type;

[0327] A second drain region adjacent to the second body region, having the second conductivity type, and

[0328] The first source region and the second drain region define a first common source / drain region, which has the second conductivity type;

[0329] The method includes:

[0330] An interruption is formed in the second body region by a first non-conductive isolation region to divide the second body region into two separate second body regions;

[0331] At least one first body contact region having the first conductivity type is formed within the first common source / drain region, the at least one first body contact region being separate from the first body region and the second body region and abutting against the first non-conductive isolation region; and

[0332] At least one first body protrusion having the first conductivity type is formed, the at least one first body protrusion extending across the first common source / drain region and contacting the first body region and the at least one first body contact region.

[0333] The first non-conductive isolation region, the at least one first body contact region, and the at least one first body protrusion define a first docking body connection structure.

Claims

1. A transistor device, comprising: Electrical insulation layer; A first region having a first conductivity type; A second region having the first conductivity type; A conductive channel between the first region and the second region, the conductive channel having a second conductivity type; At least one body contact region having the second conductivity type, the at least one body contact region being separated from the conductive channel, the body contact region being wholly or partially contained within the first region; The body protrusion having at least one body protrusion of the second conductivity type is in contact with the conductive channel and the at least one body contact region; An isolation region having the second conductivity type, the isolation region isolating the at least one body contact region from the first region; A first structure is formed on the conductive channel and defines the length and width of the conductive channel; as well as A second structure is formed on the at least one body protrusion and defines the length and width of the at least one body protrusion. in: The first region, the second region, the conductive channel, the at least one body contact region, the at least one body protrusion, and the isolation region are formed on the electrical insulating layer, thereby contacting the electrical insulating layer. The length and width of the at least one body protrusion are such that the at least one body protrusion provides a desired resistance path between the conductive channel and the at least one body contact region, and The at least one body protrusion extends across the common source / drain region of the transistor device and another transistor device, and extends through a break region formed in the gate polysilicon structure of the other transistor device, wherein the break region is configured to form a body separation region that divides the body region of the other transistor device into two separate body regions.

2. The transistor device according to claim 1, wherein, The at least one body protrusion is configured to connect the at least one body contact region resistively to the conductive channel with a resistance value depending on the operating mode of the transistor device.

3. The transistor device according to claim 1, wherein, The isolation provided by the isolation region to the at least one body contact region is configured to achieve coupling of a potential with the body contact region, the potential being different from the potential coupled to the first region.

4. The transistor device according to claim 1, wherein, The transistor device is a silicon-on-insulator (SOI) transistor device manufactured using silicon-on-insulator (SOI) technology.

5. The transistor device according to claim 4, wherein, The silicon layer of the SOI transistor device is a thin-film silicon layer.

6. The transistor device according to claim 5, further comprising: A third structure is formed on the isolation region and defines the shape of the isolation region.

7. The transistor device according to claim 6, wherein, The shape of the isolation area follows the outline of at least one body contact area in the first area.

8. The transistor device according to claim 7, wherein: The second structure contacts the first structure at one end and the third structure at the other end. The third structure includes a plurality of segments arranged at a second end of the second structure, the plurality of segments defining the shape of the isolation region.

9. The transistor device according to claim 7, wherein: The at least one body contact area is partially contained within the first area, and The shape of the isolated area follows an open outline.

10. The transistor device according to claim 7, wherein: The at least one body contact area is completely contained within the first area, and The shape of the isolated area follows a closed contour.

11. The transistor device according to claim 6, wherein: The second structure contacts the first structure at one end and the third structure at the other end. The third structure includes two segments arranged at the second end of the second structure on opposite sides of the second structure, the two segments extending longitudinally along the longitudinal direction of the second structure and in a direction opposite to the first structure.

12. The transistor device according to claim 11, wherein: The third structure includes additional third and fourth segments that connect the two segments to the second structure, respectively.

13. The transistor device according to claim 11, wherein: The at least one body contact area is partially contained within the first area, and The two segments extend through the first region into a region adjacent to the first region.

14. The transistor device of claim 11, wherein: The at least one body contact area is completely contained within the first area, and The third structure includes an additional segment that joins the two ends of the two segments away from the second end of the second structure.

15. The transistor device according to claim 6, wherein, The first structure, the second structure, and the third structure form a single integral structure.

16. A field-effect transistor (FET), comprising: Drain region having a first conductivity type; A source region having the first conductivity type; A gate polysilicon structure defining a body region, the body region having a second conductivity type; At least one body contact region having the second conductivity type, the at least one body contact region being separate from the body region, the body contact region being wholly or partially contained within the source region; The at least one body protrusion having the second conductivity type is in contact with the body region and the at least one body contact region, and the at least one body protrusion is configured to electrically connect the at least one body contact region to the body region. as well as An isolation region having the second conductivity type, the isolation region isolating the at least one body contact region from one of the source region and the drain region. The gate polysilicon structure is formed on the body region and defines the length and width of the body region. The field-effect transistor (FET) further includes at least one polysilicon protrusion formed on the at least one body protrusion and defining the length and width of the at least one body protrusion such that the at least one body protrusion provides a desired resistive path between the body region and the at least one body contact region. The at least one body protrusion extends across the common source / drain region of the field-effect transistor FET and another field-effect transistor FET, and extends through a disconnect region formed in the gate polysilicon structure of the other field-effect transistor FET, wherein the disconnect region is configured to form a body separation region that divides the body region of the other field-effect transistor FET into two separate body regions.

17. The field-effect transistor (FET) of claim 16, further comprising: At least one isolation polysilicon structure is configured to define the isolation region.

18. The field-effect transistor (FET) of claim 17, wherein, The at least one polysilicon protrusion, the gate polysilicon structure, and the isolation polysilicon structure form a single polysilicon structure.

19. The field-effect transistor FET of claim 16, wherein... The FET is a silicon-on-insulator (SOI) FET manufactured using silicon-on-insulator (SOI) technology.

20. The field-effect transistor (FET) of claim 19, further comprising: Insulating layer; as well as The silicon layer covering the insulating layer, The drain region, the source region, the body region, the at least one body contact region, the at least one body protrusion, and the isolation region are formed in the silicon layer and extend through the silicon layer to reach the insulating layer.

21. A semiconductor structure, comprising: a) A plurality of transistors configured as a cascode stack arranged from top to bottom, each transistor in the cascode stack comprising: Drain region having a first conductivity type; A source region having the first conductivity type; A gate polysilicon structure defining a body region, the body region having a second conductivity type; Specifically, for two successive transistors in the cascode stack, the source region of the top transistor and the drain region of the bottom transistor are formed in a common source / drain region. b) having at least one body contact region of the second conductivity type, the at least one body contact region being contained within the source region of at least one transistor in the cascode stack, the body contact region being separate from the body region of the transistor; c) Having at least one body protrusion of the second conductivity type, the at least one body protrusion contacting the body region of the at least one transistor and the at least one body contact region, the at least one body protrusion being configured to electrically connect the at least one body contact region to the body region. The gate polysilicon structure is formed on the body region and defines the length and width of the body region. The semiconductor structure further includes at least one polysilicon protrusion formed on the at least one body protrusion and defining the length and width of the at least one body protrusion such that the at least one body protrusion provides a desired resistive path between the body region and the at least one body contact region. in: The at least one transistor is the top transistor of the two successive transistors, and The semiconductor structure further includes a non-conductive isolation region formed in the common source / drain region of the two successive transistors, wherein the at least one non-conductive isolation region is configured to: i) An interrupt is formed in a region of the body region of the bottom transistor to divide the body region into separate body regions, and ii) Extending the interrupt to the source region of the bottom transistor of the two successive transistors, and The at least one body contact area abuts against the non-conductive isolation area.

22. The semiconductor structure according to claim 21, further comprising: The additional one or more body contact regions having the second conductivity type are contained within the source regions of the corresponding one or more transistors in the cascode stack, and the additional one or more body contact regions are separate from the body regions of the corresponding one or more transistors. as well as The device has one or more additional body protrusions of the second conductivity type, which contact the body region of the corresponding one or more transistors and the additional one or more body contact regions. The additional one or more body protrusions are configured to electrically connect the additional one or more body contact areas to the body areas of the corresponding one or more transistors.

23. The semiconductor structure according to claim 21, wherein: The common-source, common-gate stack includes a first top transistor and a last bottom transistor, and The semiconductor structure also includes: A last body contact region having the second conductivity type, the last body contact region being completely contained within the region abutting the source region of the last bottom transistor; and A last body protrusion having the second conductivity type contacts the body region of the last bottom transistor and the last body contact region, the last body protrusion being configured to electrically connect the last body contact region to the body region of the last bottom transistor.

24. The semiconductor structure according to claim 21, further comprising: The transistor has one or more additional body protrusions of the second conductivity type, which are in contact with the body region and the at least one body contact region of the transistor.

25. The semiconductor structure according to claim 24, wherein: The at least one body contact area includes two or more body contact areas.

26. The semiconductor structure according to claim 21, wherein: The at least one body contact region is completely contained within the source region of the at least one transistor in the common-source, common-gate stack.

27. The semiconductor structure according to claim 21, further comprising: Conductive contact portion on a portion of the at least one body contact area.

28. The semiconductor structure according to claim 21, further comprising: An isolation region having the second conductivity type isolates the at least one body contact region from the source region of the at least one transistor.

29. The semiconductor structure according to claim 28, wherein: The at least one body contact region is partially contained within the source region of the at least one transistor in the cascode stack.

30. The semiconductor structure according to claim 21, wherein: The interrupt divides the source region of the bottom transistor into separate source regions.

31. The semiconductor structure according to claim 30, wherein: The source region of the bottom transistor is shared with the drain region of the transistor adjacent to the bottom transistor.

32. The semiconductor structure according to claim 21, wherein: Each transistor in the cascode stack is a silicon-on-insulator (SOI) transistor device manufactured using silicon-on-insulator (SOI) technology.

33. The semiconductor structure according to claim 32, wherein: The silicon layer of the silicon-on-insulator (SOI) transistor device is a thin-film silicon layer.

34. The semiconductor structure according to claim 32, further comprising: Insulating layer; as well as The silicon layer covering the insulating layer, In this embodiment, the drain region, source region, and body region of each transistor in the cascode stack, the at least one body contact region, and the at least one body protrusion are formed in the silicon layer and extend through the silicon layer to reach the insulating layer.

35. The semiconductor structure according to claim 21, wherein: The at least one polysilicon protrusion and the gate polysilicon structure form a single polysilicon structure.

36. An amplifier circuit comprising the semiconductor structure according to claim 21.

37. A method for providing a body contact to a cascode stack, the method comprising: Fabricate a plurality of transistors configured to be arranged in a cascode stack from top to bottom, each transistor in the cascode stack comprising: Drain region having a first conductivity type; A source region having the first conductivity type; A gate polysilicon structure defining a body region, the body region having a second conductivity type; Fabricate at least one body contact region having the second conductivity type, the at least one body contact region being contained within the source region of at least one transistor in the cascode stack, the body contact region being separate from the body region of the transistor; Manufacture at least one body protrusion having the second conductivity type, the at least one body protrusion contacting the body region and the at least one body contact region of the at least one transistor; and Based on the manufacturing process, the at least one body contact area is electrically connected to the body region via the at least one body protrusion. The gate polysilicon structure is formed on the body region and defines the length and width of the body region. At least one polysilicon protrusion is formed on the at least one body protrusion, and defines the length and width of the at least one body protrusion such that the at least one body protrusion provides a desired resistive path between the body region and the at least one body contact region. in: The at least one transistor is the top transistor of the two successive transistors in the cascode stack, and A non-conductive isolation region is formed in the common source / drain region of the two successive transistors, wherein the at least one non-conductive isolation region is configured as follows: i) An interrupt is formed in the body region of the bottom transistor of the two successive transistors to divide the body region into separate body regions, and ii) Extending the interrupt to the source region of the bottom transistor of the two successive transistors, and The at least one body contact area abuts against the non-conductive isolation area.

38. The method of claim 37, further comprising: A conductive contact is formed on a portion of the at least one body contact area to provide an external electrical connection to the body area.

39. The method of claim 37, further comprising: For two successive transistors in the cascode stack, the source region of the top transistor and the drain region of the bottom transistor are formed in the common source / drain region.

40. An amplifier, comprising: A first transistor and a second transistor, each defined by a corresponding first body region and a second body region, are connected in series such that the source region of the first transistor and the drain region of the second transistor define a first common source / drain region. The first body region is defined by a first gate polysilicon structure, and the second body region is defined by a second gate polysilicon structure, the second gate polysilicon structure including a disconnect region configured to form a body separation region that divides the second body region into two separate second body regions. A first non-conductive isolation region is formed to surround the body separation region and is configured to isolate the first common source / drain region from the source region of the second transistor. as well as At least one first body protrusion contacts the first body region and extends across the first common source / drain region to contact at least one first body contact region abutting the first non-conductive isolation region.

41. The amplifier according to claim 40, wherein, The at least one first body contact region is formed within the first common source / drain region and is separate from the first body region and the second body region.

42. The amplifier according to claim 40, wherein, The first non-conductive isolation region is configured such that the silicon region of the first common source / drain region extends into the silicon region through the two separate body regions.

43. The amplifier according to claim 42, wherein, The at least one first body protrusion contacts the at least one first body contact region in the extended continuous silicon region of the first common source / drain region.

44. The amplifier according to claim 40, wherein, The first non-conductive isolation region divides the source region of the second transistor into two separate source regions.

45. The amplifier according to claim 40, wherein, The length of at least one first body protrusion is greater than the length defined by the interval between the first body region and the second body region.

46. ​​The amplifier according to claim 40, wherein, The first body protrusion extends in a direction perpendicular to the direction defined by the first body region and the second body region along the width of the body region.

47. The amplifier of claim 40, further comprising: At least one second body protrusion contacts one of the two separate body regions and extends into the source region of the second transistor to contact at least one second body contact region.

48. The amplifier of claim 47, further comprising: The additional second body protrusion contacts another body region in the two separate body regions and extends into the source region of the second transistor to contact another second body contact region.

49. The amplifier according to claim 47, wherein, The at least one second body contact region is formed in the source region of the second transistor, such that the contact region is laterally surrounded by the source region.

50. The amplifier according to claim 47, wherein, The at least one second body contact region abuts against the source region of the second transistor.

51. The amplifier according to claim 40, wherein, The first transistor and the second transistor are arranged in a common-source, common-gate configuration.

52. The amplifier of claim 51, further comprising one or more additional transistors connected in series with the first transistor and the second transistor, wherein the first transistor, the second transistor, and the other one or more transistors are arranged in a common-source, common-gate configuration.

53. The amplifier according to claim 51, wherein, The transistor configured with a common source and common gate is a metal-oxide-semiconductor field-effect transistor (MOSFET).

54. The amplifier according to claim 53, wherein, The transistor is manufactured using one of the following techniques: a) silicon-on-insulator (SOI) technology and b) silicon-on-sapphire (SOS) technology.

55. The amplifier according to claim 53, wherein, The amplifier is suitable for use as a radio frequency (RF) amplifier.

56. The amplifier according to claim 55, wherein, The radio frequency (RF) amplifier includes an RF power amplifier.

57. The amplifier according to claim 56, wherein, The amplifier is adapted to be used as an RF power amplifier selected from the group consisting of: cellular RF power amplifiers, switched RF power amplifiers, and complementary metal-oxide-semiconductor (CMOS) RF power amplifiers.

58. The amplifier according to claim 56, wherein, The amplifier is suitable for use as a cellular complementary metal-oxide-semiconductor CMOS RF power amplifier.

59. The amplifier according to claim 57 or 58, wherein, The amplifier's operating category is one or more of the following categories: i) linear category A, ii) linear category A / B, iii) saturation category B, iv) saturation category C, v) switching category D, vi) switching category E, and vii) switching category F.

60. An electronic module comprising the amplifier according to claim 40.

61. An electronic system comprising the electronic module of claim 60, the electronic system being configured to operate as: a) a television, b) a cellular telephone, c) a personal computer, d) a workstation, e) a wireless device, f) a video player, g) an audio player, h) a vehicle, i) a medical device, and j) other electronic systems.

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