Thin film transistor, array substrate and display panel

Abstract

The present disclosure provides a thin film transistor, an array substrate and a display panel, wherein the thin film transistor comprises: an active layer, a gate insulating layer and a gate electrode, wherein the active layer comprises a channel region and a source region and a drain region located on both sides of the channel region; the gate insulating layer is located on one side of the active layer; the gate electrode is located on the side of the gate insulating layer away from the active layer, and the gate electrode comprises a first region close to the drain region, a second region close to the source region and a third region located between the first region and the second region; wherein, under the same level signal of the gate electrode, the electric field strength of the third region acting on the channel region is greater than the electric field strength of the first region acting on the channel region. The thin film transistor provided by the present disclosure can reduce the leakage of the thin film transistor.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a thin film transistor, an array substrate and a display panel. Background Art

[0002] Thin Film Transistor (TFT) is a key component for active driving of display devices such as Liquid Crystal Display (LCD) and Organic Light-Emitting Diode (OLED), and plays an important role.

[0003] Depending on the materials that form the active layer (Active) structure, thin film transistors include amorphous silicon thin film transistors (a-Si TFT), oxide thin film transistors (Oxide TFT) and low-temperature polycrystalline silicon thin film transistors (LTPS TFT). Compared with amorphous silicon thin film transistors and oxide thin film transistors, low-temperature polycrystalline silicon thin film transistors have the advantages of high mobility and are suitable for small and medium-sized display technologies with high PPI and multi-system integration (such as GOA).

[0004] However, due to the existence of defects such as grain boundaries, the leakage of low-temperature polysilicon thin-film transistors is much higher than that of amorphous silicon and oxide semiconductors.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] The purpose of the embodiments of the present disclosure is to provide a thin film transistor, an array substrate and a display panel, which can reduce the leakage of the thin film transistor.

[0007] According to one aspect of an embodiment of the present disclosure, there is provided a thin film transistor, the thin film transistor comprising:

[0008] An active layer, comprising a channel region and a source region and a drain region located on both sides of the channel region;

[0009] A gate insulating layer, located on one side of the active layer;

[0010] A gate, located at a side of the gate insulating layer away from the active layer, the gate comprising a first region close to the drain region, a second region close to the source region, and a third region between the first region and the second region;

[0011] Wherein, under the same level signal of the gate, the electric field strength of the third region acting on the channel region is greater than the electric field strength of the first region acting on the channel region.

[0012] In an exemplary embodiment of the present disclosure, when the gate is at the same level of signal, the electric field strength of the third region acting on the channel region is greater than the electric field strength of the second region acting on the channel region.

[0013] In an exemplary embodiment of the present disclosure, a thickness of the gate insulating layer between the first region of the gate and the active layer is greater than a thickness of the gate insulating layer between the third region of the gate and the active layer.

[0014] In an exemplary embodiment of the present disclosure, a thickness of the gate insulating layer between the second region of the gate and the active layer is greater than a thickness of the gate insulating layer between the third region of the gate and the active layer.

[0015] In an exemplary embodiment of the present disclosure, it further includes:

[0016] A buffer layer is located on a side of the active layer away from the gate insulating layer; the thickness of the buffer layer corresponding to the third region is greater than the thickness corresponding to the first region, so that the thickness of the gate insulating layer between the first region of the gate and the active layer is greater than the thickness between the third region of the gate and the active layer.

[0017] In an exemplary embodiment of the present disclosure, the thickness of the buffer layer corresponding to the third region is greater than the thickness corresponding to the second region, so that the thickness of the gate insulation layer located between the second region of the gate and the active layer is greater than the thickness between the third region of the gate and the active layer.

[0018] In an exemplary embodiment of the present disclosure, a first hollow portion is formed on the gate on the first region.

[0019] In an exemplary embodiment of the present disclosure, a second hollow portion is formed on the gate on the first region.

[0020] In an exemplary embodiment of the present disclosure, a third hollow portion is formed on the gate on the third region.

[0021] In an exemplary embodiment of the present disclosure, the first hollow portion, the second hollow portion and the third hollow portion are strip-shaped hollow structures, and a length extension direction of the strip-shaped hollow structure intersects with a length direction of the channel region.

[0022] In an exemplary embodiment of the present disclosure, the first hollow portion is connected to the second hollow portion and the third hollow portion, and the gate forms an interdigitated finger structure.

[0023] In an exemplary embodiment of the present disclosure, in a direction from the gate toward the drain region, a width of the first region is 0.001 μm to 50 μm.

[0024] In an exemplary embodiment of the present disclosure, the thickness of the gate insulating layer between the first region of the gate and the active layer is 1 μm to 50 μm greater than the thickness between the third region of the gate and the active layer.

[0025] In an exemplary embodiment of the present disclosure, the gate insulating layer includes:

[0026] A first sub-insulating layer, located between the active layer and the gate;

[0027] The second sub-insulating layer is located between the first sub-insulating layer and the gate, and a selective etching ratio of the second sub-insulating layer to the first sub-insulating layer is greater than 10:1.

[0028] In an exemplary embodiment of the present disclosure, a material of the gate insulating layer includes at least one of silicon oxide and a high-K material.

[0029] According to another aspect of the embodiments of the present disclosure, an array substrate is provided. The array substrate includes the above-mentioned thin film transistor.

[0030] According to another aspect of the embodiments of the present disclosure, a display panel is provided, which includes the above-mentioned array substrate.

[0031] In the thin film transistor provided by the present disclosure, under the same level signal of the gate, the electric field strength of the third region acting on the channel region is greater than the electric field strength of the first region acting on the channel region; that is, for example, when the thin film transistor is switched from a high level signal to a low level signal and is in an off state, the electric field strength at the first region of the channel region close to the drain region is relatively small, which is equivalent to a resistor being connected in series in the channel region, thereby generating an uneven electric field in the channel region, suppressing the concentration of the electric field at the drain end, and thus reducing the leakage of the thin film transistor.

[0032] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0034] Figure 1 A schematic diagram of a thin film transistor provided for an embodiment of the present disclosure;

[0035] Figure 2 A schematic diagram of a thin film transistor provided for another embodiment of the present disclosure;

[0036] Figure 3 A schematic diagram of a thin film transistor provided in accordance with another embodiment of the present disclosure;

[0037] Figure 4 A schematic diagram of a gate hollow portion provided in accordance with an embodiment of the present disclosure;

[0038] Figure 5 A schematic diagram of a gate hollow portion provided in another embodiment of the present disclosure;

[0039] Figure 6 A schematic diagram of a gate hollow portion provided in yet another embodiment of the present disclosure;

[0040] Figure 7 A schematic diagram of a mask for forming a hollow portion of a gate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more comprehensive and complete and will fully convey the concept of the example embodiments to those skilled in the art.

[0042] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other components, devices, etc. may be adopted. In other cases, known components, device implementations or operations are not shown or described in detail to avoid blurring the various aspects of the present disclosure.

[0043] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0044] The terms "a", "an", "the", and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second", etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0045] At present, compared with NMOS (N-type metal oxide semiconductor field effect transistor), since the working carriers in PMOS (P-type metal oxide semiconductor field effect transistor) are holes, its effective mobility is lower, and the relative leakage will be smaller, so it is currently widely used. The leakage mechanism of LTPS (low temperature polysilicon) is mainly the generation-recombination (GR) of carriers, and there are two main sub-mechanisms: the thermal generation mechanism and the field enhancement (the field-enhanced generation). The common technology to reduce leakage current is the lightly doped drain LDD (Lightly Doped Drain) technology, but there is an offset area between the channel and the source and drain, and self-alignment cannot be used. The LDD area is narrow and difficult to control, and it will lead to a decrease in the turn-on current.

[0046] The present disclosure mainly focuses on the field enhancement mechanism to avoid the electric field concentration phenomenon existing at the drain end of the TFT, and provides a thin film transistor, such as Figure 1-Figure 3 As shown, the thin film transistor includes: an active layer 310, a gate insulating layer 321 and a gate 351. The active layer 310 includes a channel region and a source region and a drain region located on both sides of the channel region; the gate insulating layer 321 is located on one side of the active layer 310; the gate 351 is located on the side of the gate insulating layer 321 away from the active layer 310, and the gate 351 includes a first region A1 close to the drain region, a second region A2 close to the source region, and a third region A3 located between the first region A1 and the second region A2. Among them, under the same level signal of the gate 351, the electric field strength of the third region A3 acting on the channel region is greater than the electric field strength of the first region A1 acting on the channel region.

[0047] In the thin film transistor provided by the present disclosure, under the same level signal of the gate, the electric field strength of the third area A3 acting on the channel area is greater than the electric field strength of the first area A1 acting on the channel area; that is, for example, when the thin film transistor is switched from a high level signal to a low level signal and is in an off state, the electric field strength in the first area A1 of the channel area close to the drain area is relatively small, which is equivalent to a resistor being connected in series in the channel area, generating an uneven electric field in the channel area, suppressing the concentration of the electric field at the drain end, thereby reducing the leakage (off-state current) of the thin film transistor.

[0048] In one embodiment of the present disclosure, under the same level signal of the gate, the electric field strength of the third region A3 acting on the channel region is greater than the electric field strength of the second region A2 acting on the channel region. That is, for example, when the thin film transistor is switched from a high level signal to a low level signal and is in an off state, the electric field strength at the second region A2 of the channel region close to the drain region is relatively small, which is equivalent to a resistor connected in series at this point in the channel region, generating an uneven electric field in the channel region, and suppressing the concentration of the electric field at the source end.

[0049] In one embodiment of the present disclosure, Figure 1 As shown, the thickness of the gate insulating layer 321 between the first area A1 of the gate 351 and the active layer 310 is greater than the thickness between the third area A3 of the gate 351 and the active layer 310, that is, the distance between the first area A1 of the active layer 310 and the channel area is greater than the distance between the third area A3 and the channel area, so that under the same level signal of the gate 351, the electric field strength of the third area A3 acting on the channel area is greater than the electric field strength of the first area A1 acting on the channel area, which is equivalent to connecting a resistor in series in the channel area, generating an uneven electric field in the channel area, suppressing the concentration of the electric field at the drain end, and thus reducing the leakage of the thin film transistor.

[0050] Further, the thickness of the gate insulating layer 321 between the second region A2 of the gate 351 and the active layer 310 is greater than the thickness between the third region A3 of the gate 351 and the active layer 310, that is, the distance between the second region A2 of the active layer 310 and the channel region is greater than the distance between the third region A3 and the channel region, so that under the same level signal of the gate 351, the electric field strength of the third region A3 acting on the channel region is greater than the electric field strength of the second region A2 acting on the channel region, which is equivalent to a resistor connected in series in the channel region, generating an uneven electric field in the channel region, and suppressing the concentration of the electric field at the source end. In addition, the gate insulating layer 321 is set thicker at the positions corresponding to the first region A1 and the second region A2, which facilitates the formation of the gate insulating layer 321 and reduces the process difficulty.

[0051] For example, in the direction from the gate 351 to the drain region, the width of the first region A1 is 0.001 μm to 50 μm, such as 0.001 μm, 0.01 μm, 0.1 μm, 1 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, etc., which are not listed here. Of course, the width of the first region A1 may also be less than 0.001 μm or greater than 50 μm, which is not limited in the present disclosure. The width of the first region A1 is set to 0.001 μm to 50 μm, which can balance the on-state current while reducing the leakage of the thin film transistor, and avoid excessive influence on the on-state current.

[0052] For example, in the direction from the gate 351 to the drain region, the width of the second region A2 may be 0.001 μm to 50 μm, such as 0.001 μm, 0.01 μm, 0.1 μm, 1 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, etc., which are not listed here. Of course, the width of the second region A2 may also be less than 0.001 μm or greater than 50 μm, which is not limited in the present disclosure. Among them, the width of the second region A2 may be the same as the width of the first region A1.

[0053] For example, the thickness of the gate insulating layer 321 between the first region A1 of the gate 351 and the active layer 310 is greater than the thickness between the third region A3 of the gate 351 and the active layer 310 by 1 μm to 50 μm, for example, 1 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, etc., which are not listed here in the present disclosure. Of course, the thickness of the gate insulating layer 321 between the first region A1 of the gate 351 and the active layer 310 is greater than the thickness between the third region A3 of the gate 351 and the active layer 310, and may be less than 1 μm or greater than 50 μm, which is not limited in the present disclosure.

[0054] For example, the thickness of the gate insulating layer 321 between the second region A2 of the gate 351 and the active layer 310 is greater than the thickness between the third region A3 of the gate 351 and the active layer 310 by 1 μm to 50 μm, for example, 1 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, etc., which are not listed here in the present disclosure. Of course, the thickness of the gate insulating layer 321 between the second region A2 of the gate 351 and the active layer 310 is greater than the thickness between the third region A3 of the gate 351 and the active layer 310, and may be less than 1 μm or greater than 50 μm, which is not limited in the present disclosure. Among them, the thickness of the gate insulating layer 321 between the second region A2 and the first region A1 of the gate 351 and the active layer 310 may be the same.

[0055] For example, Figure 1As shown, the gate insulating layer 321 includes: a first sub-insulating layer 3211 and a second sub-insulating layer 3212, that is, the gate insulating layer 321 is a stacked structure. The first sub-insulating layer 3211 is located between the active layer 310 and the gate 351, and the second sub-insulating layer 3212 is located between the first sub-insulating layer 3211 and the gate 351, and the selective etching ratio of the second sub-insulating layer 3212 to the first sub-insulating layer 3211 is greater than 10:1. For example, 10:1, 20:1, 50:1, 100:1, etc. By selecting the selective etching ratio of the second sub-insulating layer 3212 to the first sub-insulating layer 3211, the second sub-insulating layer 3212 can be etched to form a depression in the middle part of the gate insulating layer 321, so that the thickness of the gate insulating layer 321 between the first area A1 and the second area A2 of the gate 351 and the active layer 310 is greater than the thickness between the third area A3 of the gate 351 and the active layer 310.

[0056] Among them, the material of the first sub-insulating layer 3211 is silicon oxide, and the material of the second sub-insulating layer 3212 is silicon nitride. The etching selectivity of silicon oxide and silicon nitride is relatively high, which is more conducive to the uniformity of the recessed depth of the gate insulating layer 321, that is, the electrical uniformity is basically not affected. Of course, the gate insulating layer 321 can be a single-layer structure, for example, formed of materials such as silicon oxide, silicon nitride, and silicon oxynitride, and the present disclosure does not limit this.

[0057] In one embodiment of the present disclosure, Figure 2 As shown, the thin film transistor further includes: a buffer layer 200. The buffer layer 200 is located on the side of the active layer 310 away from the gate insulating layer 321; the thickness of the buffer layer 200 corresponding to the third region A3 is greater than the thickness corresponding to the first region A1, so that the thickness of the gate insulating layer 321 between the first region A1 of the gate 351 and the active layer 310 is greater than the thickness between the third region A3 of the gate 351 and the active layer 310, that is, the distance between the first region A1 of the active layer 310 and the channel region is greater than the distance between the third region A3 and the channel region, so that under the same level signal of the gate 351, the electric field strength of the third region A3 acting on the channel region is greater than the electric field strength of the first region A1 acting on the channel region, which is equivalent to a resistor connected in series in the channel region, generating an uneven electric field in the channel region, suppressing the concentration of the electric field at the drain end, and thus reducing the leakage of the thin film transistor.

[0058] Further, the thickness of the buffer layer 200 corresponding to the third region A3 is greater than the thickness corresponding to the second region A2, so that the thickness of the gate insulating layer 321 between the second region A2 of the gate 351 and the active layer 310 is greater than the thickness between the third region A3 of the gate 351 and the active layer 310, that is, the distance between the second region A2 of the active layer 310 and the channel region is greater than the distance between the third region A3 and the channel region, so that under the same level signal of the gate 351, the electric field strength of the third region A3 acting on the channel region is greater than the electric field strength of the second region A2 acting on the channel region, which is equivalent to a resistor connected in series in the channel region, generating an uneven electric field in the channel region, and suppressing the concentration of the electric field at the source end. In addition, the gate insulating layer 321 is set thicker at the positions corresponding to the first region A1 and the second region A2, which facilitates the formation of the gate insulating layer 321 and reduces the process difficulty.

[0059] Before the active layer 310 is made, the buffer layer 200 is patterned first, and a grey tone mask can be used to make structures with different heights at both ends and in the middle of the channel (the height difference is within a few to tens of microns, within the focal depth DOF of optical equipment such as ELA and photo). Subsequently, the active layer 310 and the gate insulating layer 321 are made in sequence. Due to the different coverage of different film forming technologies, the active layer 310 has a better conformality due to its thin film layer and the a-Si CVD deposition of the front film layer, and basically replicates the pattern of the buffer layer 200. The gate insulating layer 321 is generally thicker than the active layer 310, and a variety of deposition technologies such as CVD / PVD can be used to flatten the pattern of the buffer layer 200 to a certain extent, so that the non-uniformity of the gate insulating layer 321 is formed in the channel (actually, only the thickness of the gate insulating layer 321 near the source 330 and the drain 340 needs to be different, and the gate insulating layer 321 inside the channel can be uniform).

[0060] The manufacturing process of this structure is to add buffer (buffer layer 200) patterning before the conventional self-aligned LTPS PMOS process. The other processes are the same. Among them, the manufacturing of the gate insulating layer 321 is the most critical to the electrical properties. CVD can be used to deposit silicon oxide (the interface between silicon oxide and LTPS is good), and then high-K materials (such as zirconium oxide, hafnium oxide, etc.) can be deposited by sputtering to make the thickness of the gate insulating layer 321 in the channel uneven.

[0061] In one embodiment of the present disclosure, Figure 3As shown, the gate 351 is formed with a first hollow portion 3511 on the first area A1. The first hollow portion 3511 generates an uneven electric field in the channel by patterning the gate 351, thereby forming a voltage divider. As a result, when the gate 351 is under the same level signal, the electric field strength of the third area A3 acting on the channel area is greater than the electric field strength of the first area A1 acting on the channel area, thereby reducing the electric field concentration near the drain end, thereby reducing the leakage of the thin film transistor.

[0062] Specifically, Figure 3 and Figure 4 As shown, the first hollow portion 3511 may be a strip-shaped hollow structure, and the length extension direction of the strip-shaped hollow structure intersects with the length direction of the channel region, for example, the length extension direction of the strip-shaped hollow structure is perpendicular to the length direction of the channel region. Of course, the first hollow portion 3511 may also be curved, shaped, or formed by a plurality of discontinuous through holes, and the present disclosure does not limit this. Any hollow region can achieve the effect of weakening the electric field effect on the channel.

[0063] Furthermore, if Figure 3 and Figure 4 As shown, the gate 351 is formed with a second hollow portion 3512 on the second area A2. An uneven electric field is generated in the channel to form a voltage divider, so that the electric field strength of the third area A3 acting on the channel area of ​​the gate 351 under the same level signal is greater than the electric field strength of the second area A2 acting on the channel area, thereby reducing the electric field concentration near the source end.

[0064] Specifically, Figure 4 As shown, the second hollow portion 3512 may be a strip-shaped hollow structure, and the length extension direction of the strip-shaped hollow structure intersects with the length direction of the channel region, for example, the length extension direction of the strip-shaped hollow structure is perpendicular to the length direction of the channel region. Of course, the second hollow portion 3512 may also be curved, shaped, or formed by a plurality of discontinuous through holes, and the present disclosure does not limit this. Any hollow region can achieve the effect of weakening the electric field effect on the channel. Among them, the shape and size of the first hollow portion 3511 and the second hollow portion 3512 may be the same or different.

[0065] Furthermore, if Figure 5 As shown, the gate 351 has a third hollow portion 3513 formed on the third area A3, that is, a plurality of hollow structures are formed along the length direction of the channel. The hollow portion weakens the effect of the electric field of the channel, which is equivalent to connecting a number of resistors in series in the channel, thereby reducing the electric field concentration near the drain end, thereby reducing the leakage of the thin film transistor.

[0066] Specifically, Figure 5As shown, the third hollow portion 3513 may be a strip-shaped hollow structure, and the length extension direction of the strip-shaped hollow structure intersects with the length direction of the channel region, for example, the length extension direction of the strip-shaped hollow structure is perpendicular to the length direction of the channel region. Of course, the third hollow portion 3513 may also be curved, shaped, or formed by a plurality of discontinuous through holes, and the present disclosure does not limit this. Any hollow region can achieve the effect of weakening the electric field effect on the channel. Among them, the shape and size of the third hollow portion 3513 and the first hollow portion 3511 and the second hollow portion 3512 may be the same or different.

[0067] Specifically, Figure 5 As shown, the first hollow portion 3511, the second hollow portion 3512 and the third hollow portion 3513 are strip-shaped hollow structures, and the length extension direction of the strip-shaped hollow structure intersects with the length direction of the channel region. The multiple hollow portions weaken the influence of the electric field in the channel region, which is equivalent to connecting a number of resistors in series in the channel region, which can reduce the concentration of the electric field at the drain end, thereby reducing the leakage of the thin film transistor.

[0068] Specifically, Figure 6 As shown, the first hollow portion 3511 is connected to the second hollow portion 3512 and the third hollow portion 3513, and the gate 351 forms an interdigitated structure. The multiple hollow portions weaken the influence of the electric field in the channel region, which is equivalent to connecting a number of resistors in series in the channel region, thereby reducing the concentration of the electric field at the drain end, thereby reducing the leakage of the thin film transistor.

[0069] Of course, the first hollow portion 3511 may be partially connected to the second hollow portion 3512 and the third hollow portion 3513 so that the gate 351 forms an interdigitated structure, and part of the structure is an unconnected spaced strip hollow structure. The present disclosure does not limit this, and any technical solution that achieves the effect of weakening the electric field effect on the channel by changing the size and shape of the hollow portion belongs to the protection scope of the present disclosure.

[0070] Among them, since the hollowing of the gate 351 requires the addition of a SD doping mask, the other processes are the same as those of conventional PMOS. For the newly added SD doping mask, in order to reduce the impact of manufacturing deviations (such as photo cover and precision overlay, etc.) on TFT uniformity, Figure 7 As shown, the photoresist 800 can be used to cover only the hollowed-out area of ​​the gate 351, and the gate 351 is still used as a hard mask in other parts to block SD doping ions, which is partially self-aligned.

[0071] In one embodiment of the present disclosure, Figure 1-Figure 3As shown, the thin film transistor further includes: a second gate insulating layer 322 (the gate insulating layer 321 is used as a first gate insulating layer), an interlayer insulating layer 360, a source electrode 330 and a drain electrode 340. The second gate insulating layer 321 is disposed on the side of the first gate insulating layer 321 away from the gate electrode 351; the interlayer insulating layer 360 is located on the side of the gate electrode 351 away from the active layer 310, and is formed with through holes exposing the source region and the drain region respectively; the source electrode 330 and the drain electrode 340 are located on the side of the interlayer insulating layer 360 away from the active layer 310, and the source electrode 330 and the drain electrode 340 are in contact with the source region and the drain region respectively.

[0072] The embodiment of the present disclosure also provides an array substrate, which includes the above-mentioned thin film transistor. The thin film transistor array substrate is a main component of the current LCD device and AMOLED device, which is directly related to the development direction of high-performance flat panel display devices. It is used to provide a driving circuit for the display. It is usually provided with several gate scanning lines and several data lines. The several gate scanning lines and several data lines define a plurality of pixel units. Each pixel unit is provided with a thin film transistor and a pixel electrode. The gate of the thin film transistor is connected to the corresponding gate scanning line. When the voltage on the gate scanning line reaches the turn-on voltage, the source and drain of the thin film transistor are turned on, so that the data voltage on the data line is input to the pixel electrode, thereby controlling the display of the corresponding pixel area. Usually, the structure of the thin film transistor on the array substrate includes a gate, a gate insulating layer, an active layer, a source and a drain, and an insulating protective layer stacked on the substrate. Please refer to the above discussion on the thin film transistor for its beneficial effects, which will not be repeated here.

[0073] like Figure 1 As shown, the array substrate also includes: a substrate 100, on which the above-mentioned thin film transistor is arranged; a planar layer (PLN) 400, which is arranged on the interlayer insulating layer 360 and covers the source 330 and the drain 340; a pixel electrode 500, which is arranged on the side of the planar layer 400 away from the second gate insulating layer 322 and contacts the source 330 or the drain 340 through a via; a metal layer (GI2) 352, which is arranged between the second gate insulating layer 321 and the interlayer insulating layer 360; a pixel defining layer (PDL) 600, which is arranged on the side of the planar layer 400 away from the interlayer insulating layer 360; and a spacer (PS) 700, which is arranged on the side of the pixel defining layer 600 away from the planar layer 400.

[0074] The embodiment of the present disclosure further provides a display panel, which includes the above array substrate. The display panel can be used for any product or component with display function, such as a vehicle display device, a liquid crystal panel, an advertising screen, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame or a navigator. The beneficial effects thereof can be referred to the above discussion on thin film transistors, which will not be repeated here.

[0075] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0076] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A thin film transistor, characterized in that: include: An active layer, comprising a channel region and a source region and a drain region located on both sides of the channel region; A gate insulating layer, located on one side of the active layer; a gate, located at a side of the gate insulating layer away from the active layer, the gate comprising a first region close to the drain region, a second region close to the source region, and a third region between the first region and the second region; wherein, under the same level signal of the gate, the electric field strength of the third region acting on the channel region is greater than the electric field strength of the first region acting on the channel region; In which, the thin film transistor also includes a buffer layer, which is located on the side of the active layer away from the gate insulating layer, and the thickness of the buffer layer corresponding to the third region is greater than the thickness corresponding to the first region, so that the thickness of the gate insulating layer between the first region of the gate and the active layer is greater than the thickness between the third region of the gate and the active layer; or, the gate has a first hollow portion formed on the first region.

2. The thin film transistor according to claim 1, characterized in that: When the gate is subjected to the same level signal, the electric field strength of the third region acting on the channel region is greater than the electric field strength of the second region acting on the channel region.

3. The thin film transistor according to claim 1, characterized in that: The thickness of the gate insulating layer between the first region of the gate and the active layer is greater than the thickness of the gate insulating layer between the third region of the gate and the active layer.

4. The thin film transistor according to claim 3, characterized in that: The thickness of the gate insulating layer between the second region of the gate and the active layer is greater than the thickness of the gate insulating layer between the third region of the gate and the active layer.

5. The thin film transistor according to claim 1, characterized in that: The thickness of the buffer layer corresponding to the third region is greater than the thickness corresponding to the second region, so that the thickness of the gate insulation layer located between the second region of the gate and the active layer is greater than the thickness between the third region of the gate and the active layer.

6. The thin film transistor according to claim 1, characterized in that: The gate has a second hollow portion formed on the second region.

7. The thin film transistor according to claim 6, characterized in that: The gate has a third hollow portion formed on the third region.

8. The thin film transistor according to claim 7, characterized in that: The first hollow portion, the second hollow portion and the third hollow portion are strip-shaped hollow structures, and a length extension direction of the strip-shaped hollow structure intersects with a length direction of the channel region.

9. The thin film transistor according to claim 7, characterized in that: The first hollow portion is connected to the second hollow portion and the third hollow portion, and the gate forms an interdigitated structure.

10. The thin film transistor according to claim 1, characterized in that: In a direction from the gate toward the drain region, a width of the first region is 0.001 μm to 50 μm.

11. The thin film transistor according to claim 1 or 3, characterized in that: The thickness of the gate insulating layer between the first region of the gate and the active layer is greater than the thickness of the gate insulating layer between the third region of the gate and the active layer by 1 μm to 50 μm.

12. The thin film transistor according to claim 3, characterized in that: The gate insulating layer comprises: A first sub-insulating layer, located between the active layer and the gate; The second sub-insulating layer is located between the first sub-insulating layer and the gate, and a selective etching ratio of the second sub-insulating layer to the first sub-insulating layer is greater than 10:

1.

13. The thin film transistor according to claim 1, characterized in that: The material of the gate insulating layer includes at least one of silicon oxide and high-K material.

14. An array substrate, characterized in that: A thin film transistor comprising any one of claims 1 to 13.

15. A display panel, characterized in that: Comprising the array substrate as claimed in claim 14.

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