Display device and method for manufacturing display device

Abstract

A display device and a method for manufacturing the display device are provided. An embodiment of the display device includes: a first substrate; a second substrate disposed on the first substrate; a first partition wall and a second partition wall disposed on the second substrate, the second partition wall being disposed outside the first partition wall; a first trench disposed inside the first partition wall and having a first width; a second trench disposed between the first and second partition walls and having a second width greater than the first width; an alignment key configured to overlap with the second trench; a first spacer disposed on the alignment key; and a sealing member disposed along the edge between the first and second substrates, not overlapping with the alignment key, wherein the first spacer partially overlaps with the first partition wall, the second partition wall, and the sealing member.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0075704, filed on June 22, 2020, with the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Specifically, this disclosure relates to a display device and a method for manufacturing a display device. More specifically, this disclosure relates to a display device capable of promoting substrate bonding through alignment bonds and a method for manufacturing a display device. Background Technology

[0004] In recent years, with the development of multimedia technology, the importance of display devices has steadily increased. Accordingly, various types of display devices, such as liquid crystal displays (LCDs) and organic light-emitting displays (OLEDs), have been widely used.

[0005] In display devices, self-emissive display devices include self-emissive elements such as organic light-emitting diodes (OLEDs). Typically, a self-emissive element may include two opposing electrodes and an emissive layer between them. When using an organic light-emitting diode as a self-emissive element, electrons and holes from the two opposing electrodes recombine in the emissive layer to generate excitons, which then transition from an excited state to a ground state, thereby emitting light.

[0006] Such self-emissive display devices have attracted attention as next-generation display devices because they can meet high display quality requirements such as wide viewing angles, high brightness and contrast, and fast response speeds, and because they can be manufactured with low power consumption, light weight and thinness since they do not require a separate power supply. Summary of the Invention

[0007] This disclosure provides a display device and a method of manufacturing the display device, which facilitates substrate bonding through alignment bonds that are readily visible from the front surface of the substrate.

[0008] However, the aspects of this disclosure are not limited to any one aspect set forth herein. These and other aspects of the disclosure will become more apparent to those skilled in the art upon reference to the following detailed description of the disclosure.

[0009] An embodiment of the display device includes: a first substrate; a second substrate disposed on the first substrate; a first partition wall and a second partition wall disposed on the second substrate, the second partition wall being disposed outside the first partition wall; a first trench disposed inside the first partition wall and having a first width; a second trench disposed between the first partition wall and the second partition wall and having a second width greater than the first width; an alignment key configured to overlap with the second trench; a first spacer disposed on the alignment key; and a sealing member disposed along the edge between the first substrate and the second substrate, not overlapping with the alignment key, wherein the first spacer partially overlaps with the first partition wall, the second partition wall, and the sealing member.

[0010] Another embodiment of the display device includes: a first substrate; a second substrate disposed on the first substrate; a sealing member disposed between the first substrate and the second substrate along an edge of the first substrate; a first partition wall and a second partition wall disposed on the second substrate, the second partition wall being configured to surround the first partition wall; an alignment key disposed between the first partition wall and the second partition wall and not overlapping with the sealing member; and a first spacer disposed on the alignment key and partially overlapping with the first partition wall and the second partition wall, wherein the sealing member is disposed on the first spacer and the second partition wall.

[0011] An embodiment of a method for manufacturing a display device includes: preparing a first substrate and a second substrate, defining a display area, a dummy area surrounding the display area, and a sealing area surrounding the dummy area in the first substrate and the second substrate; forming a first partition wall in the dummy area of ​​the second substrate and a second partition wall in the sealing area of ​​the second substrate; forming a first spacer in a trench defined by an outer surface of the first partition wall, an upper surface of the second substrate, and an inner surface of the second partition wall; disposing a sealing member on the second partition wall and the first spacer, the sealing member being disposed along an edge of the second substrate; and bonding the first substrate and the second substrate, wherein the first spacer partially overlaps with the first partition wall and the second partition wall.

[0012] According to the display device and method of manufacturing the display device according to the embodiments, the display device may include a trench disposed in a non-display area and having alignment keys disposed therein. Spacers may be disposed inside the trench to overlap with the alignment keys. The spacers may include a transparent material so that the alignment keys are easily visible from the front surface of the substrate, thereby promoting substrate bonding.

[0013] The effects of this disclosure are not limited to those described above, and various other effects are included in this specification. Attached Figure Description

[0014] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0015] Figure 1 This is a perspective view of the display device according to the embodiment;

[0016] Figure 2 It is along Figure 1 A cross-sectional view taken from line II-II';

[0017] Figure 3 It is shown Figure 1 A plan view of a portion of the display device;

[0018] Figure 4 yes Figure 3 A partial cross-sectional view of the display area;

[0019] Figure 5 It is along Figure 3 A cross-sectional view taken by line V-V';

[0020] Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 This is a schematic diagram illustrating a method for manufacturing a display device according to an embodiment;

[0021] Figure 12 This is a plan view of a display device according to another embodiment;

[0022] Figure 13 It is along Figure 12 A cross-sectional view taken from line XIV-XIV';

[0023] Figure 14 This is a plan view of a display device according to yet another embodiment;

[0024] Figure 15 It is along Figure 14 A cross-sectional view taken from line XV-XV'; and

[0025] Figure 16 This is a cross-sectional view of a display device according to yet another embodiment. Detailed Implementation

[0026] This disclosure will now be described more fully below with reference to the accompanying drawings, in which preferred embodiments of the disclosure are illustrated. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0027] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on that other layer or substrate, or there may be an intermediate layer. Conversely, when an element is referred to as being "directly" on another element, there is no intermediate element.

[0028] For ease of description, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” are used herein to describe the relationship between one element or feature and another element(s)(s) shown in the figures. It will be understood that, in addition to the orientation depicted in the figures, spatial relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as “beneath” or “below” other elements or features will then be oriented “above” other elements or features. Thus, the example term “beneath” can cover both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or oriented in other orientations), and the spatial relative descriptive terms used herein will be interpreted accordingly.

[0029] Throughout the specification, the same reference numerals indicate the same components.

[0030] In the following description, embodiments will be described in detail with reference to the accompanying drawings.

[0031] Figure 1 This is a perspective view of a display device according to an embodiment.

[0032] Reference Figure 1 Display device 1 can refer to any electronic device that provides a display screen. Examples of display device 1 may include televisions, laptops, monitors, billboards, mobile phones, smartphones, tablet PCs, electronic watches, smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, game consoles, digital cameras, Internet of Things devices, etc.

[0033] The display device 1 shown in the attached figure is a television (TV). The display device 1 may have high resolution or ultra-high resolution, such as HD, UHD, 4K and 8K, but is not limited thereto.

[0034] The display device 1 may have a rectangular shape in the plan view. The planar shape of the display device 1 is not limited to the illustrated shape, but may have a circular shape or other shapes.

[0035] The display device 1 may include a display area DA for displaying images and a non-display area NDA for not displaying images. The display area DA may include multiple pixels PX (see...). Figure 3The non-display area NDA can be located around and surround the display area DA. See below for further details. Figure 3 , Figure 4 and Figure 5 Describe the details of the display area DA and the non-display area NDA.

[0036] Figure 2 It is along Figure 1 A schematic cross-sectional view taken from line II-II'.

[0037] Reference Figure 2 The display device 1 may include a first substrate 10 and a second substrate 20 facing the first substrate 10. The display device 1 may also include a sealing member 50 for bonding the first substrate 10 to the second substrate 20 and a filler layer 70 for filling between the first substrate 10 and the second substrate 20.

[0038] The first substrate 10 may include elements and circuitry for displaying an image (e.g., pixel circuitry such as switching elements), and a pixel defining layer PDL defining the emitting and non-emitting areas (see...). Figure 4 And self-emissive elements. In example embodiments, the self-emissive element may include at least one of organic light-emitting diodes, quantum dot light-emitting diodes, inorganic micro light-emitting diodes (e.g., micro LEDs), and inorganic nano light-emitting diodes (e.g., nano LEDs). Hereinafter, the case where the self-emissive element is an organic light-emitting diode will be described by way of example.

[0039] The second substrate 20 may be disposed on the first substrate 10 and may face the first substrate 10. The second substrate 20 may include a color control structure that converts the color of the incident light. The color control structure can control the wavelength of the incident light, thereby converting the color of the incident light.

[0040] The sealing member 50 may be located between the first substrate 10 and the second substrate 20 in the non-display area NDA. The sealing member 50 may be disposed along the edges of the first substrate 10 and the second substrate 20 in the non-display area NDA, and may surround the display area DA in a plan view.

[0041] A filler layer 70 may be disposed in the space between the first substrate 10 and the second substrate 20, which is surrounded by the sealing member 50. The filler layer 70 may fill the space between the first substrate 10 and the second substrate 20.

[0042] Figure 3 It is shown Figure 1 A plan view of a portion of the display device. Figure 4 yes Figure 3 A partial cross-sectional view of the display area. Figure 5 It is along Figure 3 A cross-sectional view taken from line V-V'. Figure 5It is a cross-sectional view of a portion of the virtual and sealed areas of the display device.

[0043] Reference Figure 3 , Figure 4 and Figure 5 The display area DA and the non-display area NDA may be defined in the display device 1 as described above. The display area DA may include a plurality of pixels PX and contribute substantially to the image display. As used herein, the term "pixel" may mean a single area defined by dividing the display area DA for image display or color display in a planar diagram, and a pixel may display a predetermined primary color. That is, a pixel may be the smallest unit area capable of displaying color independently of other pixels. Examples of primary colors may include red, green, and blue, but this disclosure is not limited thereto.

[0044] Each of the plurality of pixels PX can display a different color. In an example embodiment, the plurality of pixels PX may include a first pixel displaying a first color, a second pixel displaying a second color having a peak wavelength shorter than the first color, and a third pixel displaying a third color having a peak wavelength shorter than the second color. The first pixel, the second pixel, and the third pixel may form a repeating unit, and the repeating unit may be arranged repeatedly in a first direction DR1. Each of the first to third pixels may also be repeated in a second direction DR2, such that the plurality of pixels PX can be arranged in a matrix in a planar view.

[0045] A non-display area NDA may be disposed around the display area DA. The non-display area NDA may completely or partially surround the display area DA. Unlike the display area DA, the non-display area NDA may not contribute to the image display. The non-display area NDA may form the bezel of the display device 1. Components required to drive the display device 1 (e.g., connection pads, drive circuitry, etc.) may be disposed within the non-display area NDA.

[0046] The non-display area NDA may include a sealed area SA with a sealing member 50 and a dummy area DMA located inside the sealed area SA (i.e., on the display area DA side). The display area DA may be surrounded by the dummy area DMA. Furthermore, the dummy area DMA may be surrounded by the sealed area SA.

[0047] A dummy region DMA may include multiple dummy pixels DX. The dummy pixels DX set in the dummy region DMA do not contribute to the image display, but may include dummy pixel electrodes PXEd.

[0048] In the display area DA, the first substrate 10 may include a first base substrate 11, a pixel electrode PXE disposed for each pixel PX of the first base substrate 11, a pixel defining layer PDL disposed along the boundary of the pixel PX of the first base substrate 11, a light emitting layer EML disposed on the pixel electrode PXE in an opening exposed by the pixel defining layer PDL, a common electrode CME disposed across multiple pixels PX on the light emitting layer EML and the pixel defining layer PDL, and a packaging structure ECL disposed on the common electrode CME.

[0049] The pixel defining layer (PDL) may overlap with the edge portion of the pixel electrode (PXE). The light-emitting layer (EML) may include an organic light-emitting material. The organic light-emitting material of the EML may emit the same color, regardless of the color of the pixel (PX). For example, the EML may emit blue light from all red, green, and blue pixels (PX). However, embodiments of this disclosure are not limited thereto. The pixel defining layer (PDL) may include openings exposing the pixel electrode (PXE). The pixel defining layer (PDL) may be disposed on the first base substrate 11 across the display area (DA) and the dummy area (DMA), which will be described later, but is not limited thereto.

[0050] The encapsulation structure ECL may include at least one thin-film encapsulation layer. The encapsulation structure ECL may be disposed entirely over the first base substrate 11, above the display area DA and the dummy area DMA and sealing area SA, which will be described later. The encapsulation structure ECL serves to protect the components disposed on the first base substrate 11 from external environmental influences. For example, the thin-film encapsulation layer may include a first inorganic layer 17, an organic layer 18, and a second inorganic layer 19. The first inorganic layer 17 and the second inorganic layer 19 may include insulating inorganic materials, and the organic layer 18 may include insulating organic materials.

[0051] In the display area DA, the second substrate 20 may include a second base substrate 21, a light-shielding member BML disposed on one surface of the second base substrate 21 facing the first base substrate 11, a color filter layer CFL disposed on one surface of the second base substrate 21 in an opening defined by the light-shielding member BML, a first cover layer 22 disposed on the color filter layer CFL, a first partition wall PTL1 disposed on the first cover layer 22 to overlap with the light-shielding member BML, a first trench TR1 defining a space surrounded by the first partition wall PTL1, a wavelength conversion layer WCL and a light-transmitting layer TPL disposed in the first trench TR1, and a first spacer CS1 disposed on at least a portion of the first partition wall PTL1. Additionally, in the display area DA, the second substrate 20 may also include a second cover layer 23 covering the first partition wall PTL1, the wavelength conversion layer WCL, the light-transmitting layer TPL, and the first spacer CS1.

[0052] A light-shielding member BML may be disposed in the light-shielding region BA to overlap with the pixel defining layer PDL, and includes an opening that exposes one surface of the second base substrate 21 while overlapping with the light-transmitting region TA. The light-shielding member BML may be disposed on the second base substrate 21 across the dummy region DMA, the sealing region SA, and the display region DA, which will be described later.

[0053] The color filter layer CFL may include a first color filter layer CFL1 disposed in a first color pixel PX, a second color filter layer CFL2 disposed in a second color pixel PX, and a third color filter layer CFL3 disposed in a third color pixel PX. For example, the first color filter layer CFL1 may be a red color filter layer, the second color filter layer CFL2 may be a green color filter layer, and the third color filter layer CFL3 may be a blue color filter layer.

[0054] The first cover layer 22 may cover the light-shielding member BML and the color filter layer CFL. The first cover layer 22 may span the dummy region DMA and the sealing region SA, which will be described later, and the display region DA, and is disposed above the second base substrate 21.

[0055] The first partition wall PTL1 may include a plurality of first grooves TR1 penetrating the first partition wall PTL1 in the thickness direction. The first grooves TR1 may be spaced apart from each other. The first partition wall PTL1 may be integrally formed with the second partition wall PTL2, which will be described later, but is not limited thereto.

[0056] The wavelength conversion layer WCL may include a first wavelength conversion pattern WCL1 disposed in a first color pixel PX and a second wavelength conversion pattern WCL2 disposed in a second color pixel PX. The light-transmitting layer TPL may be disposed in a third color pixel PX.

[0057] The first wavelength conversion pattern WCL1 may include a first base resin BRS1 and a first wavelength conversion material WCP1 and a scatterer SCP disposed within the first base resin BRS1. The second wavelength conversion pattern WCL2 may include a second base resin BRS2 and a second wavelength conversion material WCP2 and a scatterer SCP disposed within the second base resin BRS2. The light-transmitting layer TPL may include a third base resin BRS3 and a scatterer SCP disposed within the third base resin BRS3.

[0058] The first base resin BRS1, the second base resin BRS2, ​​and the third base resin BRS3 may include light-transmitting organic materials. For example, the first base resin BRS1, the second base resin BRS2, ​​and the third base resin BRS3 may include epoxy resin, acrylic resin, cardo resin, imide resin, etc. The first base resin BRS1, the second base resin BRS2, ​​and the third base resin BRS3 may be formed from the same material, but this disclosure is not limited thereto.

[0059] The scattering material (SCP) can be a metal oxide particle or an organic particle. Examples of metal oxides include titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO), tin oxide (SnO2), etc. Examples of organic particle materials include acrylic resins and polyurethane resins.

[0060] The first wavelength conversion material WCP1 converts a third color to a first color, and the second wavelength conversion material WCP2 converts a third color to a second color. The first wavelength conversion material WCP1 and the second wavelength conversion material WCP2 can be quantum dots, quantum rods, phosphors, etc. Examples of quantum dots may include group IV nanocrystals, group II-VI compound nanocrystals, group III-V compound nanocrystals, group IV-VI nanocrystals, and combinations thereof. The first wavelength conversion pattern WCL1 and the second wavelength conversion pattern WCL2 may also include a scatterer SCP for increasing wavelength conversion efficiency.

[0061] A light-transmitting layer (TPL) located in the third-color pixel (PX) transmits third-color light emitted from the emissive layer (EML) while maintaining the light's wavelength. The scattering component (SCP) of the TPL can be used to control the emission path of light passing through the TPL. The TPL may not include wavelength conversion material.

[0062] The first spacer CS1 may be disposed on a portion of the first partition wall PTL1, and may also be disposed in the light-shielding area BA. The first spacer CS1 may be used in the display area DA to maintain the distance between the first substrate 10 and the second substrate 20. The first spacer CS1 may be formed by an exposure and development process. For example, the first spacer CS1 may comprise an organic material, and this organic material may be a photosensitive organic material. In this case, the first spacer CS1 may be formed by applying an organic material layer for the spacer and then exposing and developing it. The organic material layer for the spacer may be a negative photosensitive material cured at the portion exposed to light, but is not limited thereto. The first spacer CS1 may be made of a transparent material.

[0063] A filler layer 70 may be disposed between the first substrate 10 and the second substrate 20. The filler layer 70 may fill the space between the first substrate 10 and the second substrate 20 and may be used to bond them together. The filler layer 70 may be disposed between the encapsulation structure ECL of the first substrate 10 and the second cover layer 23 of the second substrate 20.

[0064] In the dummy region DMA, the first substrate 10 may include a first base substrate 11, a dummy pixel electrode PXEd disposed for each dummy pixel DX of the first base substrate 11, a pixel defining layer PDL disposed along the boundary of the dummy pixel DX of the first base substrate 11, a dummy light-emitting layer EMLd disposed on the dummy pixel electrode PXEd in an opening exposed by the pixel defining layer PDL, a common electrode CME disposed across multiple dummy pixels DX on the dummy light-emitting layer EMLd and the pixel defining layer PDL, and a packaging structure ECL disposed on the common electrode CME. In the non-display region NDA, the dummy region DMA and the sealed region SA can be distinguished by an imaginary line perpendicular to the edge of the common electrode CME. For example, the dummy region DMA and the sealed region SA can be disposed on one side and the other side respectively, relative to the imaginary line perpendicular to the edge of the common electrode CME.

[0065] The descriptions of the dummy pixel electrode PXEd, pixel confinement layer PDL, dummy light-emitting layer EMLd, and common electrode CME disposed in the dummy region DMA are the same as those of the pixel electrode PXE, pixel confinement layer PDL, light-emitting layer EML, and common electrode CME disposed in the display region DA. In the dummy region DMA, the first substrate 10 may include all, but is not limited to, the dummy pixel electrode PXEd, pixel confinement layer PDL, dummy light-emitting layer EMLd, and common electrode CME, and some of them may be omitted.

[0066] In the dummy region DMA, the second substrate 20 may include a second base substrate 21, a light-shielding member BML disposed on one surface of the second base substrate 21 facing the first base substrate 11, a dummy color filter layer CFLd disposed on one surface of the second base substrate 21 in an opening defined by the light-shielding member BML, a first cover layer 22 disposed on the dummy color filter layer CFLd, a second partition wall PTL2 disposed on the first cover layer 22 overlapping the light-shielding member BML, a second trench TR2 defining a space surrounded by the second partition wall PTL2, dummy wavelength conversion layers WCL1d and WCL2d and a dummy light-transmitting layer TPLd disposed in the second trench TR2, and a second spacer CS2 disposed on at least a portion of the second partition wall PTL2. The second substrate 20 may also include a second cover layer 23 disposed on the dummy wavelength conversion layers WCL1d and WCL2d, the dummy light-transmitting layer TPLd, the second partition wall PTL2 and the second spacer CS2.

[0067] The light-shielding member BML may be disposed in the light-shielding area BAD to overlap with the pixel defining layer PDL, and may include an opening that exposes a surface of the second base substrate 21 while overlapping with the light-transmitting area TAd.

[0068] The dummy color filter layer CFLd may include a first dummy color filter layer CFL1d, a second dummy color filter layer CFL2d, and a third dummy color filter layer CFL3d. The descriptions of the first dummy color filter layer CFL1d, the second dummy color filter layer CFL2d, and the third dummy color filter layer CFL3d are the same as those of the first color filter layer CFL1, the second color filter layer CFL2, and the third color filter layer CFL3 described above, and therefore will be omitted.

[0069] The second partition wall PTL2 may include a plurality of second grooves TR2 penetrating the second partition wall PTL2 in the thickness direction. The second grooves TR2 may be spaced apart from each other. Each of the second grooves TR2 may have a first width. As described above, the second partition wall PTL2 may be integrally formed with the first partition wall PTL1, but is not limited thereto. The upper surface of the second partition wall PTL2 may be located in the same plane as the upper surface of the first partition wall PTL1.

[0070] The dummy wavelength conversion layers WCL1d and WCL2d may include a first dummy wavelength conversion pattern WCL1d disposed in a first color dummy pixel DX and a second dummy wavelength conversion pattern WCL2d disposed in a second color dummy pixel DX. The dummy light-transmitting layer TPLd may be disposed in a third color dummy pixel DX.

[0071] The descriptions of the dummy wavelength conversion layers WCL1d and WCL2d and the dummy light-transmitting layer TPLd in the dummy region DMA are the same as those for the wavelength conversion layer WCL and the light-transmitting layer TPL in the display region DA described above, and therefore will be omitted. In the dummy region DMA, the second substrate 20 may include, but is not limited to, all of the light-shielding member BML, the dummy color filter layer CFLd, the second partition wall PTL2, the dummy wavelength conversion layers WCL1d and WCL2d, the dummy light-transmitting layer TPLd, and the second spacer CS2, and some of them may be omitted.

[0072] The second spacer CS2 may be disposed on the second partition wall PTL2, or it may be disposed in the light-shielding region BAd. The second spacer CS2 can be used to maintain the distance between the first substrate 10 and the second substrate 20 in the dummy region DMA. Other details of the second spacer CS2 are the same as those of the first spacer CS1 described above, and therefore will be omitted.

[0073] The sealing region SA can be located outside the dummy region DMA. In the sealing region SA, the first substrate 10 may include a first base substrate 11 and a package structure ECL disposed on the first base substrate 11. Similar to the package structure ECL disposed in the display region DA and the dummy region DMA, the package structure ECL disposed in the sealing region SA may include a first inorganic layer 17, an organic layer 18, and a second inorganic layer 19.

[0074] In the sealing region SA, the second substrate 20 may include a second base substrate 21; a light-shielding member BML disposed on one surface of the second base substrate 21 facing the first base substrate 11; a first cover layer 22 disposed on the light-shielding member BML; a third partition wall PTL3 disposed on the first cover layer 22 overlapping the light-shielding member BML; a third trench TR3 defined by the outer surface of the outermost second partition wall PTL2, the inner surface of the third partition wall PTL3, and the upper surface of the first cover layer 22; and a third spacer CS3 disposed in the third trench TR3. Furthermore, in the sealing region SA, the second substrate 20 may also include a second cover layer 23 covering the third partition wall PTL3 and the third spacer CS3.

[0075] The display device 1 according to an embodiment may include a third trench TR3, which is a space defined by the outer surface of the outermost second partition wall PTL2, the inner surface of the third partition wall PTL3, and the upper surface of the first cover layer 22. The third trench TR3 may be disposed in the non-display area NDA. In one embodiment, the third trench TR3 may be disposed across the dummy area DMA and the sealed area SA, but is not limited thereto. The third trench TR3 may have a second width greater than the first width of the second trench TR2.

[0076] The third trench TR3 may partially expose the first cover layer 22. A third spacer CS3 may be disposed in the third trench TR3. The third spacer CS3 may be used to maintain the distance between the first substrate 10 and the second substrate 20 in the sealing region SA. The third spacer CS3 may be made of the same material as the first spacer CS1 and the second spacer CS2, and may be formed together, but is not limited thereto.

[0077] The third spacer CS3 may partially overlap with the outermost second partition wall PTL2 and the third partition wall PTL3. The third spacer CS3 may be configured to partially cover the upper surfaces of the outermost second partition wall PTL2 and the third partition wall PTL3. A flat area may be provided between the area of ​​the third spacer CS3 that overlaps with the outermost second partition wall PTL2 and the area of ​​the third spacer CS3 that overlaps with the third partition wall PTL3. Compared to the flat area, the area of ​​the third spacer CS3 that overlaps with the outermost second partition wall PTL2 and the third partition wall PTL3 may have a protruding shape, but is not limited to this.

[0078] The display device 1 according to an embodiment may further include an alignment key AK disposed within the third trench TR3. The alignment key AK may be configured to align the first substrate 10 and the second substrate 20 when they are bonded together. The alignment key AK may be arranged to overlap with the third trench TR3. The alignment key AK may include, for example, organic or inorganic materials, but is not limited thereto. The alignment key AK may be patterned in a cross shape, but is not limited thereto.

[0079] In the sealing region SA, a sealing member 50 may be disposed between the first substrate 10 and the second substrate 20. The first substrate 10 and the second substrate 20 may be bonded to each other via the sealing member 50. The sealing member 50 may include an organic material. The sealing member 50 may be made of epoxy resin, but is not limited thereto. The sealing member 50 may be disposed on the third spacer CS3 and the third partition wall PTL3. The sealing member 50 may partially overlap with the third spacer CS3 and the third partition wall PTL3. The sealing member 50 may be disposed outside the alignment key AK without overlapping with the alignment key AK. A filler layer 70 may be disposed inside the sealing member 50.

[0080] In the display device 1 according to the embodiment, the dummy region DMA including the dummy pixel DX can be provided outside the display region DA in order to prevent the display quality of the display device 1 from being degraded due to the residual phenomenon occurring in the space between the first partition walls PTL1 in the display region DA.

[0081] Furthermore, the second substrate 20 may include an alignment key AK to align the first substrate 10 and the second substrate 20 when they are joined together. When the alignment key AK is located in the dummy region DMA, it may be difficult to visually identify the alignment key AK from the front surface of the second substrate 20 due to the dummy pixel DX.

[0082] The second substrate 20 included in the display device 1 according to the embodiment may have a third trench TR3 disposed in the non-display area NDA, and the alignment key AK may be disposed in the third trench TR3. Furthermore, a third spacer CS3 may be disposed in the third trench TR3 to overlap with the alignment key AK. The third spacer CS3 may include a transparent material so that the alignment key AK can be easily seen from the front surface of the second substrate 20.

[0083] The method of manufacturing the display device 1 will be described below.

[0084] Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 This is a schematic diagram illustrating a method for manufacturing a display device according to an embodiment. Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 The non-display region NDA is shown in the manufacturing process of the second substrate 20. For ease of description, Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 Shown in an inverted state Figure 5 The second substrate 20.

[0085] Reference Figure 6 A light-shielding member BML is formed on a surface of the second base substrate 21 of the second substrate 20. The light-shielding member BML can be formed by applying a light-shielding material containing a material for light shielding and then exposing and developing it. Multiple light-shielding member BMLs can be formed together in one process. The patterned light-shielding member BML can partially expose the second base substrate 21.

[0086] Reference Figure 7A dummy color filter layer CFLd can be formed between the light-shielding members BML that expose the second base substrate 21. Specifically, the dummy color filter layer CFLd may include a first dummy color filter layer CFL1d, a second dummy color filter layer CFL2d, and a third dummy color filter layer CFL3d. The first dummy color filter layer CFL1d, the second dummy color filter layer CFL2d, and the third dummy color filter layer CFL3d can be formed by applying a photosensitive organic material containing a specific color material and then exposing and developing it. The first dummy color filter layer CFL1d, the second dummy color filter layer CFL2d, and the third dummy color filter layer CFL3d can be formed in the order of the third dummy color filter layer CFL3d, the first dummy color filter layer CFL1d, and the second dummy color filter layer CFL2d, but this disclosure is not limited thereto.

[0087] Subsequently, a first capping layer 22 may be formed on the patterned dummy color filter layer CFLd to cover it. The first capping layer 22 may be disposed on the entire surface of the second base substrate 21.

[0088] Subsequently, referring to Figure 8 The second partition wall PTL2 and the third partition wall PTL3 can be formed on the first cover layer 22. Specifically, patterned second partition walls PTL2 and the third partition wall PTL3 can be formed on the first cover layer 22. The second partition walls PTL2 and the third partition walls PTL3 can be formed together in one process. The second partition walls PTL2 and the third partition walls PTL3 can be arranged above the light-shielding member BML. The patterned second partition walls PTL2 and the third partition walls PTL3 can be formed by an exposure and development process. For example, the second partition walls PTL2 and the third partition walls PTL3 may include an organic material, which may be a photosensitive organic material. In this case, the patterned second partition walls PTL2 and the third partition walls PTL3 can be formed by applying an organic material layer for the partition walls and then exposing and developing it. The organic material layer for the partition walls may be a negative photosensitive material that is cured at the portion exposed to light, but is not limited to this.

[0089] Reference Figure 9The second spacer CS2 may be formed on the upper surface of a portion of the patterned second partition wall PTL2, and the third spacer CS3 may be formed in a third trench TR3 defined by the outer surface of the outermost second partition wall PTL2, the inner surface of the third partition wall PTL3, and the upper surface of the first cover layer 22. The second spacer CS2 and the third spacer CS3 may be formed together in a single process. The second spacer CS2 and the third spacer CS3 may be formed by applying an organic material layer for the spacer and then exposing and developing it. The organic material layer for the spacer may be a negative photosensitive material that is cured at the portion exposed to light, but is not limited thereto. The organic material layer for the spacer may be made of a transparent material, but is not limited thereto. The organic material layer for the spacer may be made of a translucent material.

[0090] Reference Figure 10 The dummy wavelength control layers WCL1d, WCL2d, and TPLd can be formed in the second trench TR2. The dummy wavelength control layers WCL1d, WCL2d, and TPLd can be formed using an inkjet printer (IZD) via an inkjet printing process. Specifically, the first dummy wavelength conversion pattern WCL1d (see also...) Figure 11 ) can be directed toward the first light-transmitting area TA1d (see Figure 5 The ink IK is formed by jetting ink containing the material included in the first dummy wavelength conversion pattern WCL1d. The ink IK can be injected from a region overlapping the first light-transmitting region TA1d into a second trench TR2 defined by a second partition wall PTL2. That is, the second partition wall PTL2 can be used to stably guide the ink IK to a desired location to form the first dummy wavelength conversion pattern WCL1d.

[0091] Similarly, the second dummy wavelength conversion pattern WCL2d can be oriented towards the second light-transmitting region TA2d (see...). Figure 5 The ink IK is formed by jetting ink containing the material included in the second dummy wavelength conversion pattern WCL2d. The ink IK can be injected from a region overlapping the second light-transmitting region TA2d into a second trench TR2 defined by a second partition wall PTL2. That is, the second partition wall PTL2 can be used to stably guide the ink IK to a desired location to form the second dummy wavelength conversion pattern WCL2d.

[0092] Similarly, the dummy light-transmitting layer TPLd can be positioned towards the third light-transmitting region TA3d (see...). Figure 5The dummy light-transmitting layer TPLd is formed by jetting ink IK, which contains the material included in the dummy light-transmitting layer TPLd. The ink IK can be injected from a region overlapping with the third light-transmitting region TA3d into a second trench TR2 defined by a second partition wall PTL2. That is, the second partition wall PTL2 can be used to stably guide the ink IK to a desired location to form the dummy light-transmitting layer TPLd.

[0093] The amount of ink IK ejected can be determined by taking into account surface tension and volume shrinkage after the ink IK dries.

[0094] Reference Figure 11 The second cover layer 23 may be formed on the second partition wall PTL2, the third partition wall PTL3, the second spacer CS2, the third spacer CS3, and the dummy wavelength control layers WCL1d, WCL2d, and TPLd. The second cover layer 23 may completely cover the second partition wall PTL2, the third partition wall PTL3, the second spacer CS2, the third spacer CS3, and the dummy wavelength control layers WCL1d, WCL2d, and TPLd. Figure 11 The second overlay 23 is shown to be formed only in the dummy region DMA and the sealed region SA, but this disclosure is not limited thereto. The second overlay 23 may also be formed in the display region DA.

[0095] Subsequently, fill layer 70 (see...) Figure 5 The first substrate 10 and the second substrate 20 can be coated onto the second cover layer 23 and spacers CS2 and CS3, and the first substrate 10 and the second substrate 20 can be bonded to each other. The sealing member 50 (see...) Figure 5 It is disposed on the third partition wall PTL3 and the third spacer CS3. The sealing member 50 is disposed along the edge of the second substrate 20. Since the above are well known facts, their detailed description will be omitted.

[0096] According to the method of manufacturing display device 1 according to the embodiment, a virtual region DMA including a virtual pixel DX can be provided outside the display region DA in order to prevent the display quality of display device 1 from being degraded due to the presence of residue in the space between the first partition walls PTL1 in the display region DA.

[0097] Furthermore, the second substrate 20 included in the display device 1 according to the embodiment may have a third trench TR3 disposed in the non-display area NDA, and the alignment key AK may be disposed in the third trench TR3. A third spacer CS3 may also be disposed in the third trench TR3 to overlap with the alignment key AK. The third spacer CS3 may include a transparent material so that the alignment key AK is easily visible from the front surface of the second substrate 20.

[0098] Other embodiments will be described below. In the embodiments described below, the description of components that are the same as those in the embodiments described above will be omitted or simplified, and the differences will be mainly described.

[0099] Figure 12 This is a plan view of a display device according to another embodiment. Figure 13 It is along Figure 12 A cross-sectional view taken from line XIV-XIV'.

[0100] Reference Figure 12 and Figure 13 According to this embodiment, the third partition wall PTL3_1 included in the display device 1_1 may have a main portion PTL31_1 formed along the outer line of the display device 1_1 and a branch portion PTL32_1 protruding inward from the main portion PTL31_1.

[0101] Since the difference between the display device 1_1 according to this embodiment and the display device 1 according to the embodiment lies in the structure of the third partition wall PTL3_1, the structure of the third groove TR3_1 defined by the inner surface of the third partition wall PTL3_1, the upper surface of the first cover layer 22 and the outer surface of the outermost second partition wall PTL2_1 can also be formed accordingly.

[0102] In the third trench TR3_1, a third spacer CS3_1 may be provided. The third spacer CS3_1 may cover a portion of the outermost second partition wall PTL2_1 and a portion of the main trunk PTL31_1 and the entire branch PTL32_1 of the third partition wall PTL3_1, but is not limited thereto.

[0103] The third partition wall PTL3_1 included in the display device 1_1 according to this embodiment has a main portion PTL31_1 and a branch portion PTL32_1 protruding inward from the main portion PTL31_1, thereby effectively maintaining the height of the third spacer CS3_1.

[0104] The display device 1_1 according to this embodiment may include a third groove TR3_1 disposed in a non-display area NDA and having an alignment key AK disposed therein. A third spacer CS3_1 may be disposed in the third groove TR3_1 to overlap with the alignment key AK. The third spacer CS3_1 may include a transparent material so that the alignment key AK is easily visible from the front surface of the display device 1_1.

[0105] Figure 14 This is a plan view of a display device according to yet another embodiment. Figure 15 It is along Figure 14 A cross-sectional view taken from line XV-XV'.

[0106] Reference Figure 14 and Figure 15 The display device 1_2 according to this embodiment may include a third partition wall PTL3_2 with a planar shape having a grid structure. The third groove TR3_2 included in the display device 1_2 according to this embodiment may not only have a third a groove TR31_2 defined by the outer surface of the outermost second partition wall PTL2_2, the upper surface of the first cover layer 22 and the inner surface of the third partition wall PTL3_2, but also have a third b groove TR32_2 disposed in the third partition wall PTL3_2.

[0107] The third b-groove TR32_2 can be arranged in a grid pattern within the third partition wall PTL3_2, but is not limited to this. The third b-groove TR32_2 can be arranged irregularly. In a plan view, the third b-groove TR32_2 can have a rectangular or square shape, but is not limited to this. The third b-groove TR32_2 can have a circular shape or another polygonal shape.

[0108] The third partition wall PTL3_2 included in the display device 1_2 according to this embodiment has a planar shape with a grid structure, thereby effectively maintaining the height of the third spacer CS3_2.

[0109] The display device 1_2 according to this embodiment may include: a third a-groove TR31_2 disposed in a non-display area NDA and having an alignment key AK disposed therein; and a third b-groove TR32_2 disposed in a third partition wall PTL3_2. In the third groove TR3_2, a third spacer CS3_2 may be configured to overlap with the alignment key AK. The third spacer CS3_2 may include a transparent material so that the alignment key AK is easily visible from the front surface of the display device 1_2.

[0110] Figure 16 This is a cross-sectional view of a display device according to yet another embodiment.

[0111] The display device 1_3 according to this embodiment differs from the display device 1 according to this embodiment in that the light-shielding member BML is omitted. During the manufacturing process of the display device 1_3, when the partition walls PTL1, PTL2_3, and PTL3_3 are formed, residues of the material forming the partition walls can be generated in the space between the partition walls PTL1, PTL2_3, and PTL3_3. To prevent the display quality of the display device 1_3 from deteriorating due to the generation of partition wall material residues in the display area DA, a virtual area DMA including dummy pixels DX can be provided outside the display area DA. Accordingly, light emission can be substantially not performed in the virtual area DMA, and a light-shielding member and a color filter can be omitted therein.

[0112] The display device 1_3 according to this embodiment may include a third groove TR3_3 disposed in a non-display area NDA and having an alignment key AK disposed therein. In the third groove TR3_3, a third spacer CS3_3 may be configured to overlap with the alignment key AK. The third spacer CS3_3 may include a transparent material so that the alignment key AK is easily visible from the front surface of the display device 1_3.

[0113] In concluding this detailed description, those skilled in the art will appreciate that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of this disclosure. Therefore, the preferred embodiments of this disclosure are used in a general and descriptive sense only and are not intended for limiting purposes.

Claims

1. A display device, comprising: First substrate; A second substrate is disposed on the first substrate; A first partition wall and a second partition wall are disposed on the second substrate, with the second partition wall disposed outside the first partition wall; A first groove is disposed between the two first partition walls and has a first width; The second groove is disposed between the first partition wall and the second partition wall, and has a second width greater than the first width; An alignment key is disposed on the second substrate and overlaps with the second trench; A first spacer is disposed on the alignment key; as well as A sealing member is disposed along the edge between the first substrate and the second substrate, and does not overlap with the alignment key. The first spacer partially overlaps with the first partition wall, the second partition wall, and the sealing member.

2. The display device according to claim 1, wherein, The display device includes a dummy area and a sealed area, and The alignment key is located in the sealing area and inside the sealing member.

3. The display device according to claim 1, wherein, The sealing component does not overlap with the first partition wall.

4. The display device according to claim 1, wherein, The wavelength control pattern is set in the first trench.

5. The display device according to claim 4, further comprising a second spacer disposed on a portion of the first partition wall and not overlapping the alignment key.

6. The display device according to claim 5, wherein, The first spacer and the second spacer are formed by the same process.

7. The display device according to claim 6, wherein, The first spacer comprises a transparent material.

8. The display device according to claim 4, wherein, The wavelength control pattern includes at least one of a wavelength conversion material and a scattering material.

9. The display device according to claim 1, further comprising a filler disposed between the first substrate and the second substrate inside the sealing member.

10. A display device, comprising: First substrate; A second substrate is disposed on the first substrate; A sealing member is disposed between the first substrate and the second substrate along the edge of the first substrate; A first partition wall and a second partition wall are disposed on the second substrate, wherein the second partition wall is configured to surround the first partition wall; The alignment key is positioned between the first partition wall and the second partition wall and does not overlap with the sealing member; as well as A first spacer is disposed on the alignment key and partially overlaps with the first and second spacer walls. The sealing member is disposed on the first spacer and the second partition wall.

11. The display device of claim 10, further comprising a second spacer disposed on a portion of the first partition wall and not overlapping the alignment key.

12. The display device according to claim 11, wherein, The first spacer and the second spacer are formed by the same process.

13. The display device according to claim 12, wherein, The first spacer comprises a transparent material.

14. The display device according to claim 10, wherein, The sealing component does not overlap with the first partition wall.

15. The display device of claim 10, further comprising a filler disposed between the first substrate and the second substrate inside the sealing member.

16. The display device according to claim 10, wherein, The alignment key is disposed on the second substrate and inside the sealing member.

17. A method for manufacturing a display device, comprising the following steps: A first substrate and a second substrate are prepared, wherein a display area, a dummy area configured to surround the display area, and a sealing area configured to surround the dummy area are defined in the first substrate and the second substrate; A first partition wall is formed in the dummy region of the second substrate, and a second partition wall is formed in the sealing region of the second substrate; A first spacer is formed in a trench defined by the outer surface of the first partition wall, the upper surface of the second substrate, and the inner surface of the second partition wall; A sealing member is provided on the second partition wall and the first spacer, the sealing member being disposed along the edge of the second substrate; as well as The first substrate is combined with the second substrate. The first spacer partially overlaps with both the first and second partition walls. The method further includes arranging alignment keys in the trench before forming the first spacer in the trench.

18. The method according to claim 17, wherein, The formation of the first spacer in the trench is accompanied by the formation of a second spacer on the upper surface of at least one of the first spacer walls.

19. The method according to claim 18, wherein, The first spacer and the second spacer are formed by the same process.

20. A method for manufacturing a display device, comprising the following steps: A first substrate and a second substrate are prepared, wherein a display area, a dummy area configured to surround the display area, and a sealing area configured to surround the dummy area are defined in the first substrate and the second substrate; A first partition wall is formed in the dummy region of the second substrate, the dummy region including dummy pixels, and a second partition wall is formed in the sealing region of the second substrate; A first spacer is formed in a trench defined by the outer surface of the first partition wall, the upper surface of the second substrate, and the inner surface of the second partition wall; A sealing member is provided on the second partition wall and the first spacer, the sealing member being disposed along the edge of the second substrate; as well as The first substrate is combined with the second substrate. The first spacer partially overlaps with both the first and second partition walls. The dummy pixel includes at least one of a dummy pixel electrode and a dummy light-emitting layer, and the dummy pixel electrode and the dummy light-emitting layer are disposed on the first substrate.

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