Implement mask synthesis consistency across random regions of integrated circuit chips

Abstract

The system generates masks for circuit designs while implementing symmetry and consistency across random regions of the mask. The system constructs a mask solution database that maps circuit patterns to mask patterns. The system uses this database to replace the circuit patterns of the circuit design with mask patterns. The system identifies properties in the circuit patterns of the circuit design and implements the same properties in the corresponding mask patterns. Examples of implemented properties include symmetry within the circuit patterns and similarity across circuit patterns. The system combines mask patterns from different regions of the circuit and resolves conflicts that arise when multiple masks exist within a single region.

Description

[0001] Cross-reference of related applications

[0002] This application claims the benefit of U.S. Patent Application Serial No. 62 / 875,579, filed July 18, 2019, the contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to the field of electronic design automation, and more specifically, to mask synthesis for chip placement of all integrated circuits based on geometric design analysis. Background Technology

[0004] Mask synthesis utilizes photolithography tools to perform full-chip optical proximity correction (OPC), inverse lithography (ILT), and process inspection and analysis of integrated circuit layout patterns. As chip dimensions shrink, the number of noise factors in circuit design increases while fault tolerance decreases. Different circuit patterns on an integrated circuit chip may have subtle differences caused by noise factors. However, using separate masks for these circuit patterns increases the cost of mask synthesis solutions such as OPC, ILT, and model-based auxiliary feature (MBAF). Asymmetries and inconsistencies in mask synthesis solutions are undesirable in chip manufacturing and contribute to overall errors and manufacturing costs. Summary of the Invention

[0005] A configuration (e.g., a system, method, or non-transitory computer-readable storage medium storing processor-executable instructions) for generating masks for circuit designs is disclosed. A system (e.g., a mask design system) receives a circuit design for mask generation. The system constructs a mask solution database that maps circuit patterns to mask patterns. The system identifies a set of unique circuit patterns within the circuit by placing search windows at different locations within the circuit design. A search window represents a bounding box placed at a location. A circuit pattern represents the geometry of the circuit design appearing within the bounding box of the search window. If a circuit pattern is not already included in the set, the system adds that circuit pattern to the set of unique circuit patterns. The system generates mask patterns for the set of unique circuit patterns and stores them in the mask solution database. Each mask pattern is indexed to the circuit pattern used to generate the mask pattern. For example, the system may generate a signature based on the geometry within the circuit pattern and use that signature to index the mask pattern. The system generates a mask for the circuit design to match the circuit patterns using the mask patterns stored in the mask solution database.

[0006] In one embodiment, the system receives a circuit design and a mask for the circuit design, and implements certain properties, such as consistency and symmetry, in the mask. The system identifies circuit patterns within the circuit design and identifies mask patterns corresponding to the circuit patterns. The system determines the properties of the circuit patterns based on the geometry in which each circuit pattern appears. For example, a property could be a type of symmetry in the circuit pattern. Examples of different types of symmetry include rotational symmetry, mirror symmetry, translational symmetry, partial spacing symmetry, or combinations thereof. Alternatively, the property could indicate that the circuit patterns are similar to each other. The system modifies the mask patterns such that one or more modified mask patterns have the same properties as the corresponding circuit patterns. For example, if the circuit patterns have a particular type of symmetry, the system modifies the mask patterns to have the same symmetry. If the circuit patterns are similar to each other, the system replaces the mask patterns with similar mask patterns. In one embodiment, the system determines an aggregated mask pattern from multiple mask patterns and uses the aggregated mask pattern instead of individual mask patterns. The system replaces portions of the mask design with the modified mask pattern.

[0007] In one embodiment, the system receives a circuit design and determines mask patterns for different overlapping regions of the circuit design. If multiple mask patterns are determined for a region, the system resolves conflicts between the mask patterns. The system identifies regions within the circuit pattern. The system identifies multiple mask patterns for that region. At least some of the mask patterns overlap. The mask patterns use a vector representation of their geometry. The system rasterizes each mask pattern for that region to generate an image mask representation of the mask pattern. The image mask representation includes pixel values. The system determines a weighted aggregation of the image mask representations to generate an aggregated image mask representation. Weighting is performed such that pixel values ​​closer to the center of the region are weighted higher than pixel values ​​farther from the center of the region. The system generates a mask pattern from the aggregated image mask representation and modifies the mask design to use the generated mask pattern.

[0008] The features and advantages described in the present invention and the following detailed description are not exhaustive. Many additional features and advantages will be apparent to those skilled in the art from the accompanying drawings, specification, and claims. Attached Figure Description

[0009] This disclosure will be more fully understood from the detailed descriptions given below and the accompanying drawings of embodiments according to this disclosure. The drawings are provided to give knowledge and understanding of embodiments of this disclosure and are not intended to limit the scope of this disclosure to these specific embodiments. Furthermore, the drawings are not necessarily drawn to scale.

[0010] Figure 1 The illustration shows the entire process of mask synthesis for a circuit design according to one embodiment.

[0011] Figure 2 A block diagram of the system architecture of a mask synthesis system according to one embodiment is shown.

[0012] Figure 3 A flowchart depicts a process for mask synthesis for performing circuit design according to one embodiment.

[0013] Figure 4 An example search window for identifying circuit patterns in a circuit design is shown according to one embodiment.

[0014] Figure 5 An example search window for identification in another example circuit is shown according to one embodiment.

[0015] Figure 6 A circuit diagram showing the placement of a search window according to one embodiment is illustrated.

[0016] Figure 7 The study describes various types of symmetry detected and implemented on mask patterns within each circuit pattern by a mask design system.

[0017] Figure 8A An example of a pattern centered on a point having a clipping window shown by an outer frame, according to one embodiment, is shown.

[0018] Figure 8B The rasterization step of an algorithm for generating an average solution according to one embodiment is shown, namely, the transformation from a mask representation as a polygon to a grid-based representation.

[0019] Figure 9 A flowchart illustrating a process for generating a mask from multiple overlapping mask patterns according to one embodiment is shown.

[0020] Figure 10A An example symmetrical mask pattern obtained from a set of similar mask patterns according to one embodiment is shown.

[0021] Figure 10B The illustration shows a set of mask patterns with minor inconsistencies being combined according to one embodiment to obtain an average solution.

[0022] Figure 10C The illustration shows an aggregated mask pattern and a symmetrical version of the mask pattern according to one embodiment.

[0023] Figure 11 A flowchart according to one embodiment is shown, illustrating the process of replacing a mask pattern for an overlapping circuit pattern to obtain a combined mask pattern.

[0024] Figure 12 An example circuit pattern with an overlapping mask pattern is illustrated according to one embodiment.

[0025] Figure 13 An example circuit pattern according to one embodiment is illustrated, which is obtained by replacing the mask pattern in the correct position using the correct rotation / translation / mirroring based on the original mask pattern.

[0026] Figure 14 The final, consistent, and symmetrical mask pattern is shown, which has the characteristics of being compatible with... Figure 8A The measurement results are compared with the mask.

[0027] Figure 15 An example of pixel-based blending of a mask pattern according to one embodiment is shown.

[0028] Figure 16 A flowchart according to one embodiment is shown, illustrating the process of combining mask patterns for a full circuit design using a hybrid approach.

[0029] Figure 17 An example of a circuit pattern representing a region of a circuit design according to one embodiment is shown.

[0030] Figure 18 An example mask pattern according to one embodiment is shown, illustrating the features and auxiliary features of the mask in the region.

[0031] Figure 19 A blending region according to one embodiment is depicted, which is highly weighted at the center of the region and decays towards the edge.

[0032] Figure 20 The illustration shows an overlapping region created by a search window centered on three adjacent geometries of a circuit design, according to one embodiment.

[0033] Figure 21A A polygon with some sub-sides and their offsets is shown according to one embodiment.

[0034] Figure 21B Alternative results of offsets generated as different sub-edges according to one embodiment are shown.

[0035] Figure 21C An example is shown. Figure 21A and Figure 21B The superposition of the two offset results shown.

[0036] Figure 22 The illustration outlines an implementation of an auxiliary feature center as an OPC offset according to one embodiment.

[0037] Figure 23 The three adjacent design polygons and the Vinno boundary are depicted according to one embodiment.

[0038] Figure 24 It describes how, if the mask design system does not constrain some auxiliary features to the Vino boundary, these auxiliary features extend into another region and overlap with other auxiliary features.

[0039] Figure 25 Flowcharts depict various processes used during the design and manufacture of integrated circuits according to some embodiments.

[0040] Figure 26 An abstract diagram of an example computer system in which embodiments may operate is depicted. Detailed Implementation

[0041] The Electronic Design Automation (EDA) process includes a tape-out stage, which creates data used to generate a photomask. During mask synthesis, the tape-out data is used to generate the photomask, which is then used to produce the finished integrated circuit. As chip dimensions shrink, simulation and mask synthesis techniques become increasingly complex, and the number of noise factors increases while the error budget decreases. Various noise factors in lithography simulation lead to inconsistent and asymmetric mask synthesis solutions. These inconsistencies complicate and increase the cost of mask synthesis and chip manufacturing processes. Asymmetries in mask synthesis solutions are undesirable and impact the overall error budget during chip manufacturing.

[0042] Photolithography tools can apply symmetry to repeating cells in the hierarchical structure of a hierarchical circuit design. For example, the tool can analyze the hierarchical structure of a circuit design to find periodically repeating cell structures and apply symmetry within these cell structures. However, these tools cannot identify symmetry across random regions that do not represent repeating cells in the hierarchical design. For example, these tools cannot identify symmetry across circuit patterns consisting of circuit portions smaller than the smallest cell in the hierarchical circuit design, or across circuit patterns that span multiple cells without overlapping the entire cell structure of the hierarchy.

[0043] The implementation maintains consistency and symmetry across random regions of the circuit design during mask synthesis. The system extracts unique circuit patterns from the circuit design and constructs a mask solution database that maps these circuit patterns to mask patterns. The system identifies sets of unique circuit patterns by placing search windows at different locations within the circuit design. The system generates mask patterns for these sets of unique circuit patterns and stores them in the mask solution database. The system uses the mask patterns stored in the mask solution database to generate a mask for the circuit design.

[0044] In one embodiment, the system implements certain properties in the mask based on corresponding properties in the circuit pattern. For example, the property could be a type of symmetry in the circuit pattern. Examples of different types of symmetry include rotational symmetry, mirror symmetry, translational symmetry, fractional pitch symmetry, or combinations thereof. The system modifies the mask pattern to have the same properties as the corresponding circuit pattern. The system then replaces portions of the mask design with the modified mask pattern.

[0045] In one embodiment, the system identifies multiple mask patterns for a region of a circuit and resolves conflicts between the mask patterns to generate a mask for the circuit design. The system rasterizes each mask pattern for that region to generate an image mask representation of the mask pattern. The system determines a weighted aggregation of the image mask representations to generate an aggregated image mask representation. The system generates a mask pattern from the aggregated image mask representation and modifies the mask design to use the generated mask pattern.

[0046] These embodiments generate consistent and symmetrical masks for circuit designs. The generated masks are sent for circuit fabrication based on the circuit designs. When the same circuit pattern is found for a specific circuit design or multiple circuit designs across a shared mask solution database, the system according to various embodiments guarantees the same mask. This improves the cost of the manufacturing process. The embodiments also improve the computational efficiency of mask synthesis for circuit designs by reusing mask solutions for previously encountered circuit patterns. The computational effort required to look up a circuit pattern in the mask solution database is significantly less than the computational effort required to generate a mask solution because signature lookup in the mask solution database is efficient. As a result, fewer computational resources (e.g., processor usage) can be used to generate the mask.

[0047] Overall system environment

[0048] Figure 1 The illustration shows the entire process of mask synthesis for a circuit design according to one embodiment. The mask design system 100 receives the circuit design 110 as input. Various embodiments may have... Figure 1 The components shown are different from those described herein.

[0049] The mask synthesis system 100 extracts circuit patterns from a circuit by identifying identical, repeating circuit design regions. The mask design system 100 generates mask patterns for these circuit patterns to generate a library, such as a mask solution database 120. The mask design system 100 uses this library as a lookup table for performing full-chip mask synthesis to generate a mask 130 for the circuit design 110.

[0050] The mask design system 100 creates a library of mask solutions for random circuit patterns across a specific circuit design or across multiple circuit designs. The mask design system 100 addresses consistency and symmetry issues by ensuring that any identical arrangement of the design geometry produces the same mask and by implementing any locally detected design symmetry on the mask. This improves the chip manufacturing process by reducing sources of error in the process.

[0051] The embodiments implement symmetry across circuit patterns consisting of circuit portions smaller than the smallest unit in a hierarchical circuit design, or across circuit patterns that span multiple units without overlapping with the entire unit of the hierarchical structure. For example, a unique circuit pattern identified and processed by the embodiments for generating a mask pattern may not have any identity as a unit in a hierarchical circuit design. Therefore, the embodiments implement symmetry and consistency across circuit patterns that are sub-units and non-hierarchical.

[0052] Layout classification system architecture

[0053] Figure 2 A block diagram of the system architecture of a mask synthesis system according to one embodiment is shown. The mask design system 100 includes a circuit pattern extraction component 220, a mask synthesis component 230, a circuit dictionary 240, and a mask solution database 120. Other embodiments may include more or fewer components than those indicated herein. Functions indicated herein as being performed by a particular module may be performed by other modules different from those indicated herein.

[0054] Circuit pattern extraction module 220 extracts a set of circuit patterns from representations of circuit designs (e.g., a layout representation of the physical design of a circuit). Circuit pattern dictionary 240 maps each circuit pattern to a unique identifier, such as a hash key, which can be used to look up the circuit pattern. Circuit pattern extraction module 220 stores the circuit patterns in mask solution database 120. In one embodiment, the representation of the circuit design processed by mask design system 100 is based on a Graphical Design System (GDS) format, such as GDSII or Open Schematic System Exchange Standard (OASIS) format. Other embodiments may use any format to represent the circuit design.

[0055] The mask synthesis component 230 generates a mask solution database 120 by generating mask solutions from circuit patterns stored in the circuit pattern dictionary 240. The mask synthesis component 230 also uses the mask solution database 120 to process input circuit designs to generate masks for the circuits.

[0056] Mask solution database 120 stores mask solutions for circuit patterns. Mask solution database 120 can index mask solutions to signature values ​​corresponding to circuit patterns, such as geometric hash keys obtained from the geometry of the circuit pattern. In some embodiments, mask solution database 120 stores mask solutions for circuit patterns obtained from the circuit for which the mask was generated. In other embodiments, mask solution database 120 stores mask solutions for circuit patterns obtained from multiple circuits and acts as a library that can be used across circuit designs.

[0057] In some embodiments, the mask design system 100 is implemented as a distributed system with multiple computer processors that process different parts of the circuit design in parallel. For example, the mask design system 100 can extract circuit patterns from different parts of the circuit in parallel, and the mask synthesis component 230 can generate masks for different parts of the circuit in parallel.

[0058] The following describes in detail the various processes performed by the components of the mask design system 100.

[0059] The overall process of mask synthesis in circuit design

[0060] Figure 3 A flowchart depicts a process for mask synthesis for performing circuit design according to one embodiment. Figure 3 The steps shown in the flowchart can be executed in a different order than that indicated in the flowchart. For example, some steps can be executed in parallel with other steps. Furthermore, the individual steps shown in the flowchart can be executed using parallel or distributed systems.

[0061] The mask design system 100 receives a representation of a circuit design 310. The circuit design can represent a complete chip design or a representative set of test patterns. The mask design system 100 searches for unique circuit patterns in the circuit design by repeatedly performing steps 320, 330, 340, and 350.

[0062] The mask design system 100 places search windows 320 at different locations within the circuit design. A search window represents a bounding box placed at a specific location within the circuit design. Within the bounding box of the search location, one or more geometries or portions of geometries of the circuit design may exist. The placement of the search window can be selectively chosen using the circuit design hierarchy or through heuristic sparse sampling of the circuit design to improve efficiency by reducing the number of locations processed without compromising the quality of the results.

[0063] For each location, the mask design system 100 identifies a circuit pattern 330 by cutting the circuit design 330 into a search box. The circuit pattern comprises a set of geometries, such as a set of polygons. The mask design system 100 calculates a signature for the circuit pattern 340, such as a hash key, like a geometric hash key. The mask design system 100 can determine the geometric hash key by generating a mathematical representation of the circuit pattern and calculating a function based on that representation. For example, the mathematical representation of the geometry of the circuit pattern can include a set of values, such as a set of vectors representing features in the geometry of the circuit pattern. The mask design system 100 applies a function to the set of values ​​representing the geometry of the circuit pattern to generate a hash value that is used as the signature of the circuit pattern.

[0064] In one embodiment, if a variation of the circuit pattern can be obtained by rotation, translation, or mirroring along an axis, the mask design system 100 uses a signature that maps the variation to the same signature value. The signature acts as an identifier for the circuit pattern and is invariant to certain types of transformations. In one embodiment, the mask design system 100 acquires the circuit pattern and performs various transformations on it, including rotation, translation, or mirroring, and determines a signature value for each transformed circuit pattern. The mask design system 100 uses certain rules to consistently select signature values ​​from the set of acquired signature values. For example, the mask design system 100 may generate hash keys for each value in the set of values ​​to generate a set of hash key values, and select the hash key with the smallest value from the generated set of hash keys.

[0065] The mask design system 100 uses signature values ​​to index circuit patterns 350 into a dictionary storing the circuit patterns. In one embodiment, the dictionary is a mask solution database 120.

[0066] The mask design system 100 performs 360-degree mask synthesis on circuit patterns from a set of unique circuit patterns to generate a mask pattern corresponding to each unique circuit pattern. The mask design system 100 stores the mask patterns for the set of unique circuit patterns in a mask solution database 120.

[0067] The mask design system 100 performs 370 generation of a mask for a circuit design by using stored mask solutions for the circuit pattern. When performing mask synthesis on an input circuit design or a new circuit design, the mask design system 100 uses the same search / hash technique to find a circuit pattern with a mask solution stored in the mask solution database 120. The mask design system 100 appropriately places the mask pattern in those locations in the circuit design. The mask design system 100 performs blending of the mask solutions to produce a lithographically optimized mask. Details of the blending process are further described herein.

[0068] According to various embodiments, Figure 3 The different steps of the process shown can be executed using multiple processors, for example, using a distributed architecture. Steps 320, 330, 340, and 350 can be executed in parallel for different parts of the circuit. For example, one processor can identify a unique pattern in one part of the circuit design, and another processor can identify a unique pattern in another part of the circuit design. Similarly, step 360 can be executed using multiple processors, each processor performing 360 mask synthesis on one or more circuit partitions. Similarly, step 370 can be executed using multiple processors, each processor performing mask synthesis on a portion of the circuit design. Therefore, large circuit designs can be broken down across a large number of processors to accelerate the execution of the process.

[0069] Unique pattern logo

[0070] Figures 4 to 6 The illustration shows the selection of a location for placing a search box within a circuit design. Some embodiments use heuristics based on user expertise to identify relevant locations, such as the center of a repeating pattern, and are therefore suitable for identifying unique circuit patterns.

[0071] Figure 4 An example search window for identifying circuit patterns in a circuit design is shown according to one embodiment. More specifically, Figure 4 This demonstrates how to use a search window to identify circuit patterns in the contact layer for a circuit design. The mask design system 100 places the search window 410 at a location centered on the center of the contact portion in the contact layer.

[0072] like Figure 4 As shown, the circuit has an array of contact portions 410. For Figure 4 In the circuit 400 shown on the left, the mask design system 100 searches at the outermost contact portion. The search window 415 is centered on point 410, which represents the center of the contact portion.

[0073] The circuit 420 shown on the right partially illustrates the overlapping search box 425. This overlap illustrates that when the mask design system 100 inserts mask solutions into the database for these locations, the mask design system 100 also processes the areas where the search boxes overlap, as further described herein.

[0074] Figure 5 The illustration shows a circuit pattern, according to one embodiment, where a search window is placed to identify layers of the circuit using another example circuit. For longer shapes, the mask design system 100 divides the shape into smaller segments and uses these segments as the center of the search box, such as... Figure 5 As shown, X 510 indicates the center of the search box within the longer polygon 520.

[0075] The mask design system 100 identifies the center of a search window and places the search window at the location represented by the search window center. The search window represents a bounding box centered at the location represented by the search window center. The mask design system 100 cuts the geometry of the circuit design to each of these bounding boxes represented by the search window to determine a circuit pattern representing the portion of the circuit design that appears within the search window. The mask design system 100 computes a unique identifier, such as a geometric hash key, based on the geometry appearing within the circuit pattern. The mask design system 100 uses the geometric hash key as a compact identifier for each cut geometry, allowing each cut geometry to be compared with other cut geometries to see if they are identical. In one embodiment, the hash key is a mathematical function of the vertex positions of the geometry.

[0076] Figure 6 A circuit pattern based on the placement of search window 610 according to one embodiment is shown. In one embodiment, mask design system 100 selects the window size based on some physical model parameters, such as the wavelength of the scanner laser and the numerical aperture of the scanner system. For example, mask design system 100 may select the window size as a linear function, where a scaling factor is applied to the wavelength of the scanner laser or the numerical aperture of the scanner system. The cut geometry representation including polygon 620 can be stored in mask solution database 120 of the circuit pattern.

[0077] For each circuit pattern, the mask design system 100 stores a hash key for that circuit pattern in the mask solution database 120. The mask solution database 120 allows the system to identify which circuit patterns exist in different locations on the chip, thereby identifying a unique set of circuit patterns in the circuit design.

[0078] The mask design system 100 examines all possible geometric transformations to store a single master version of each circuit pattern. Possible geometric transformations include rotation, translation, and mirroring of the pattern. In one embodiment, the mask design system 100 stores a single master version by storing a circuit pattern on which the lowest hash key of all possible geometric transformations is stored. This ensures that any transformed version of the circuit pattern will map to the same mask pattern.

[0079] Creation of mask solutions

[0080] For this step, the mask design system 100 creates mask solutions for circuit patterns. Below are two embodiments of a method for generating mask solutions for circuit designs. In a first embodiment (M1), the mask design system 100 generates mask solutions for a circuit design across the entire chip, and then modifies the generated mask solutions to make them symmetrical and consistent across the chip. For example, the mask design system 100 may aggregate mask solutions for similar circuit patterns. In a second embodiment (M2), the mask design system 100 first identifies all unique circuit patterns, and then generates a mask solution for each unique circuit pattern. The mask design system 100 uses these mask patterns to generate a mask solution for a circuit design across the entire chip.

[0081] The mask design system 100 can determine which embodiment (i.e., M1 or M2) to use based on various factors, such as the number of circuit patterns relative to the size of a chip region. The mask design system 100 can determine that if there are more than a threshold number of unique circuit patterns in the chip, then the mask design system 100 selects the first embodiment (M1) above. This occurs in circuits with many circuit patterns that are close to each other and whose search boxes overlap. In this case, the first embodiment M1 above is expected to run faster than the second embodiment M2. However, if the number of unique circuit patterns is below the threshold, the mask design system 100 selects the second embodiment M2 because this embodiment is expected to run faster.

[0082] After creating all solutions, the mask design system 100 can implement the symmetry within each circuit pattern based on the symmetry of the design within the circuit pattern. The different types of symmetry considered by the mask design system 100 include mirroring, translation, rotation, and hierarchical combinations of these types of symmetry. The mask design system 100 detects these symmetries within each circuit pattern and implements the same symmetry on the mask pattern within each circuit pattern. Therefore, if a certain type of symmetry exists in the circuit pattern, the mask design system 100 ensures that the corresponding mask also has the same symmetry. For example, if the mask design system 100 determines that the circuit pattern is symmetrical along the X-axis, then the mask design system 100 ensures that the corresponding mask is symmetrical along the X-axis. If the mask design system 100 determines that the circuit pattern is symmetrical along the Y-axis, then the mask design system 100 ensures that the corresponding mask pattern is symmetrical along the Y-axis. If the mask design system 100 determines that a portion of a circuit pattern can be obtained by rotating another portion of the circuit pattern, then the mask design system 100 ensures that the corresponding mask patterns have the same symmetry properties, and that the corresponding portion of the mask pattern can be obtained by rotating the same portion of another corresponding portion of the mask pattern.

[0083] Figure 7The mask design system 100 describes various types of symmetries detected and implemented on mask patterns within each circuit pattern. These symmetries include mirroring, translation, rotation, and hierarchical combinations of these types of symmetries. Figure 7 Examples of rotations shown include 90-degree rotations and 180-degree rotations. Figure 7 Examples of translations shown include: (1) diagonal translation, in which a portion of the circuit pattern repeats at a position obtained by diagonal translation; (2) X-translation, in which a portion of the circuit pattern repeats at a position obtained by translation along the X-axis; (3) Y-translation, in which a portion of the circuit pattern repeats at a position obtained by translation along the Y-axis; and (4) partial spacing translation, in which two portions of the circuit pattern can be matched by appropriately translating their sub-parts.

[0084] Figure 8A An example of a circuit pattern according to one embodiment is shown. The circuit pattern is centered at point 810, and a search window 820 is shown by an outer frame. The circuit pattern is represented by four squares 830a, 830b, 830c, and 830d at the center of the image, and the mask pattern is a circular shape 840 surrounding the circuit pattern. The mask may be asymmetrical across some axes. The mask design system 100 determines that the circuit pattern has mirror symmetry along the diagonal, and therefore implements a corresponding diagonal symmetry on the mask pattern.

[0085] In one embodiment, the mask design system 100 uses the method M1 described above to generate a mask for the entire chip and identifies multiple instances of circuit patterns in the circuit design, including mask patterns with slight differences. The mask design system 100 combines these mask patterns to generate a single mask pattern for all these similar circuit patterns. The mask design system 100 can use various techniques to combine the mask patterns, such as by calculating an average mask pattern, as further described herein. Alternatively, the mask design system 100 selects an optimal mask pattern based on some lithographic performance of the mask pattern, such as a mask pattern with optimal process window, edge placement error, etc. The mask design system 100 can select an optimal mask by determining a weighted aggregation of various factors and selecting the mask pattern that receives the highest weight, or by selecting the mask pattern that provides the best lithographic performance.

[0086] Implement consistency and symmetry in the mask.

[0087] In one embodiment, mask design system 100 implements consistency and symmetry across mask designs generated from circuit designs, for example, using the method M1 described herein. Mask design system 100 receives a circuit design as input and generates a mask design for the circuit design. Mask design system 100 identifies one or more circuit patterns within the circuit design. Mask design system 100 determines a mask pattern corresponding to each identified circuit pattern in the identified circuit patterns. Mask design system 100 determines the properties of a circuit pattern based on the geometry within the circuit pattern. For example, circuit patterns may be determined to be similar to each other or circuit patterns may be some type of symmetry. Mask design system 100 modifies the mask pattern such that the modified mask pattern has the same properties as the circuit pattern. For example, if the circuit pattern is determined to have some type of symmetry, mask design system 100 modifies the mask pattern to have the same symmetry. If a set of circuit patterns is similar, mask design system 100 ensures that the corresponding mask patterns are also similar or identical. Mask design system 100 replaces portions of the mask for the circuit design with the modified mask pattern. This makes the various parts of the mask consistent and symmetrical compared to the original mask.

[0088] Figure 9 A flowchart illustrating a process for generating a mask from multiple overlapping mask patterns according to one embodiment is shown. A mask design system 100 identifies 910 one or more mask patterns for corresponding matching circuit patterns. These circuit patterns are determined to be similar to each other. For example, the mask design system 100 may determine a similarity score based on the matching of the geometry of the circuit patterns. If their similarity scores are greater than a threshold, the mask design system 100 determines that two circuit patterns are similar to each other.

[0089] The mask design system 100 overlaps the identified mask patterns 920. The mask design system 100 rasterizes each mask pattern 930, that is, converts the mask pattern from a vector representation to a rasterized mask representation for the mask pattern. For example, the rasterized mask representation can be a pixelated mask representation, such as a bitmap representation, for example, as... Figure 8B As shown in the image. Figure 8B The mask polygon rectangle 830 and the rasterized one-dimensional cutting line 840 are shown, which are cross sections of the model, where the depth of the layer depends on the pixel value at that location.

[0090] The mask design system 100 aggregates 940 rasterized mask representations. The mask design system 100 can aggregate rasterized mask representations by averaging corresponding pixel values ​​in the rasterized mask representations. Alternatively, the mask design system 100 can aggregate rasterized mask representations by selecting one rasterized mask representation from the rasterized mask representations using certain rules. For example, the mask design system 100 can select the rasterized mask representation that provides the best lithography results. The aggregation 940 of mask representations... Figure 10A and Figure 10B The diagram is shown in the middle, and combined with... Figure 10A and Figure 10B Described.

[0091] The mask design system 100 extracts a 950 mask pattern from the aggregated rasterized mask representation by converting the aggregated rasterized mask representation into a vector representation. The mask design system 100 performs symmetry transformation on the mask pattern. Therefore, the mask design system 100 determines whether symmetry exists in the circuit pattern. If symmetry exists in the mask pattern, the mask design system 100 generates a mask pattern with the corresponding symmetry. Figure 10A An example symmetrical mask pattern 1020 obtained from a set of similar mask patterns 1010 according to one embodiment is shown.

[0092] Figure 10B The illustration shows a set of non-overlapping mask patterns with minor inconsistencies being combined to obtain an average solution according to one embodiment. The mask design system 100 processes different mask patterns 1030a, 1030b, 1030c, etc., obtained from corresponding sets of matching circuit patterns to generate a composite mask solution 1040. Figure 10B The diagram illustrates the averaging process as described above. For example, mask 1030 exhibits differences as shown in portions 1035a, 1035b, and 1035c. Portion 1045 is obtained by averaging the corresponding portions 1035a, 1035b, and 1035c.

[0093] like Figure 10B As shown, there are small inconsistencies 1035a, 1035b, and 1035c among the different mask patterns from the ILT (Inverse Lithography) solution. The mask design system 100 performs aggregation to remove these inconsistencies, such that the resulting mask pattern 1040 is identical for all these instances 1030a, 1030b, and 1030c.

[0094] In situations where significant variations in the mask need to be addressed and averaging may result in a poor lithography solution, the mask design system 100 examines the lithography performance of the average solution relative to individual mask solutions to determine if the degradation from averaging is too significant, for example, above a threshold. If the mask design system 100 determines the degradation is too significant, it can use a lithography-based selection method to select a mask pattern with optimal lithography performance. The mask design system 100 can generate a combined mask using a combination of spatial averaging and lithography performance selection / weighting.

[0095] For method M1, mask patterns are aggregated by averaging, using optimal lithographic results, etc., to produce a consistent and symmetrical single mask pattern. For method M2, the mask synthesis system 100 runs a mask synthesis method such as ILT to produce a single solution. After creating these solutions, the mask synthesis system 100 post-processes the mask to implement any symmetry present in the local design geometry of the mask itself. For example, in Figure 10B The circuit pattern in the design exhibits both X-mirror and Y-mirror symmetry. The mask design system 100 implements the same symmetry on the final mask. Similarly, Figure 10A An example of a mask pattern is shown, in which the mask design system 100 implements mirror symmetry along a diagonal axis from the lower left corner to the upper right corner.

[0096] Figure 10C The illustration depicts an aggregated mask pattern according to one embodiment, as well as a symmetrical version of the mask pattern. Inconsistencies exist between the upper / lower halves and the left / right halves of mask pattern 1070. Mask design system 100 modifies mask pattern 1070 to obtain a symmetrical mask pattern 1080. For example, mask design system 100 identifies shapes 1050 and 1055, which represent inconsistencies in symmetry along the Y-axis. Mask design system 100 modifies mask pattern 1070 to generate a symmetrical mask pattern 1080 with symmetry along the Y-axis, as shown by modified shapes 1060 and 1065 corresponding to shapes 1050 and 1055, respectively.

[0097] The mask design system 100 stores mask patterns in the mask solution database 120 for use, for example, in... Figure 3 In step 370 of the illustrated process, the mask pattern for the entire circuit design is replaced. In some embodiments, the mask solution database 120 operates offline, i.e., outside of any specific step of the process described herein. This embodiment allows for cross-chip consistency compared to intra-chip consistency only.

[0098] Placement of mask patterns in circuit design layout

[0099] After the mask pattern has been created, the mask design system 100 replaces the mask pattern in the circuit layout at the location where the corresponding circuit pattern is found. If multiple windows overlap, such as... Figure 4 As shown, the mask design system 100 determines how to resolve conflicts caused by differences in mask patterns at the same location in the circuit design. Based on the context within each mask pattern, overlapping portions of two mask patterns can have differences within the mask patterns. When mask patterns are combined, the mask design system 100 determines the resulting mask for the shared portion.

[0100] Two embodiments for combining mask patterns for a full circuit design are presented here. The first technique uses a centerline-based mask placement, which uses a Voronoi diagram to divide the circuit design into non-overlapping regions to avoid collisions in the mask patterns. The second technique uses a hybrid-based mask placement, which uses a rasterized representation of the mask patterns to smoothly combine overlapping mask patterns.

[0101] Mask placement based on the central axis

[0102] In this embodiment, the mask design system 100 uses a centerline-based mask placement method to combine mask patterns for the entire circuit design, which divides the circuit design to create non-overlapping regions. Figure 11 A flowchart according to one embodiment is shown, illustrating a process for replacing a mask pattern for an overlapping circuit pattern to obtain a combined mask pattern. The process uses... Figure 12 The example shown is used to illustrate this.

[0103] The mask design system 100 identifies more than 1110 overlapping circuit patterns. Each circuit pattern is defined by placing a search window at a location within the circuit design. The circuit patterns include geometries such as polygons. A circuit pattern can be defined using a search window placed at a location representing a point within the geometry, such as the center of a polygon. If two polygons are within a threshold distance of each other, the corresponding circuit patterns overlap.

[0104] Figure 12 An example circuit pattern with an overlapping mask pattern is illustrated according to one embodiment. Figure 12 The example shown has four polygons: 1220a, 1220b, 1220c, and 1220d. For this example, the center of each polygon determines the location where a search window is placed to determine the circuit pattern. Because the distance between the polygons is less than the size of the search window, these circuit patterns have significant overlap. For example, the circuit pattern determined based on polygon 1220 could include... Figure 12 All of the remaining polygons 1220 shown, or at least a portion of the remaining polygons.

[0105] The mask design system 100 determines 1120 a mask pattern corresponding to each circuit pattern. For example, a mask may have been pre-calculated for the circuit design, and the mask design system 100 extracts the mask pattern as a part of the mask corresponding to each circuit pattern.

[0106] The mask design system 100 uses a central axis between the geometries of the circuit to divide the circuit design being processed into non-overlapping regions 1130. The central axis represents a point between geometries that have at least two nearest points on the boundary of the geometry. Therefore, each point on the central axis is equidistant from at least two points on the boundary of the geometry closest to that point.

[0107] In one embodiment, mask design system 100 generates a Venn diagram that divides the circuit design into regions at each center of a set of polygon centers. Mask design system 100 can generate the Venn diagram using an incremental technique that starts with an edge and expands the Venn diagram by adding edges. Mask design system 100 can use a divide-and-conquer technique that divides the region into multiple parts and determines the Venn diagram for each part, then combines the individual Venn diagrams. Mask design system 100 can use other techniques to determine the Venn diagram.

[0108] like Figure 12 As shown, the mask design system 100 uses a central axis, represented by lines 1205a and 1205b, to divide the circuit design. Line 1205 divides the design into regions near the center of each polygon, with each polygon center defining a search window corresponding to the circuit pattern. Each non-overlapping region of the Venn diagram is associated with the polygon used to define that region. Thus, region 1210a is associated with polygon 1220a, region 1210b with polygon 1220b, region 1210c with polygon 1220c, and region 1210c with polygon 1220c.

[0109] The mask design system 100 identifies a mask pattern for each circuit pattern corresponding to a search window and determines 1140 portions of the mask pattern within each region 1210. The mask design system 100 uses correct geometric transformations (e.g., rotation / translation / mirroring) from the master copy of the mask pattern to replace the polygons of the mask pattern in the correct positions in the circuit design.

[0110] Figure 13 The illustration shows an example circuit pattern according to one embodiment, which is obtained by replacing a mask pattern in the correct position using the correct geometric transformations (e.g., rotation / translation / mirror) based on a base mask pattern. Shape 1310 represents a circuit pattern for... Figure 12 The mask fragments for each of the respective regions 1210 shown are illustrated. For example, the mask pattern portion for region 1210a is shown as 1310a, the mask pattern portion for region 1210b is shown as 1310b, the mask pattern portion for region 1210c is shown as 1310c, and the mask pattern portion for region 1210d is shown as 1310d.

[0111] The mask design system 100 identifies portions of the mask in which a mask pattern from one region connects to a mask pattern from another region at the region boundary, and modifies the mask pattern 1150 as necessary to ensure that the mask patterns are aligned at the region boundaries. For example, if the corners of the mask pattern are not aligned at the region boundaries, the mask design system 100 can stretch the polygons to ensure that the corners are aligned.

[0112] Alternatively, the mask design system 100 can add edges between polygons to create continuous geometry across regions. Figure 14 This demonstrates the final, consistent, and symmetrical masking solution, which has the ability to be used with... Figure 8A The measurement results are compared with the mask.

[0113] When mismatches exist at boundaries, some embodiments use pixel-based techniques to combine mask patterns across regions. These embodiments perform blending at region boundaries through pixel-based averaging and smoothing.

[0114] Figure 15 An example of pixel-based blending of a mask solution according to one embodiment is shown. Figure 15 A portion of circuit design 1500a is shown, comprising a set of design polygons 1510a, 1510b, and 1510c with shaded areas on the left. Mask design 1505 on the right shows transition weight fields used to blend the average rasterized mask near the edges of the ownership regions. Mask design system 100 uses transition regions to merge mismatches that occur at the boundaries of these regions.

[0115] The mask design system 100 treats a region of the circuit design as an image. The mask design system 100 initializes the background field corresponding to the region of the circuit design to a fixed value, for example, zero at all pixels. The mask design system 100 performs the following steps for each mask pattern inserted into the circuit design.

[0116] (1) The mask design system 100 receives a mask that can represent, for example, a combination of... Figures 10A-10CThe described method determines the aggregate mask. (2) The mask design system 100 rasterizes the mask, that is, converts the mask into a pixel representation, where the pixel value at a certain point depends on whether a mask exists at that point. (3) The mask design system 100 multiplies the rasterized representation of the mask by a transition field for that specific region, such as Figure 15 As shown in the diagram. (4) The mask design system 100 adds the product of the rasterized representation and transition field determined in step (3) to the background mask. The end result is a combined mask solution that is consistent for each instance of the design geometry placement.

[0117] Hybrid Mask Placement

[0118] In one embodiment, the mask design system 100 uses a hybrid mask placement method to combine mask patterns for a full circuit design, which uses a hybrid approach to smoothly combine mask patterns from overlapping circuit patterns.

[0119] Figure 16 A flowchart according to one embodiment is shown, illustrating the process of combining mask patterns for a full circuit design using a hybrid approach.

[0120] The mask design system 100 includes receiver circuit design and mask design for the circuit design. The mask can be generated using any known technique, such as... Figure 3 The process is illustrated. The mask design system 100 identifies a region within the circuit design 1610. This region may correspond to multiple overlapping circuit patterns. Therefore, multiple mask patterns exist for this region, with at least some of the mask patterns overlapping other mask patterns.

[0121] Figure 17 An example of a circuit pattern representing a region of a circuit design according to one embodiment is shown. The region includes one or more geometries 1720. Figure 11 A search window 1710 centered on a point within geometry 1720a is shown. The mask design system 100 can generate mask patterns based on the search window. Other search windows may exist centered on points within other geometries in the region. Therefore, multiple overlapping mask patterns can be generated within this region. This region includes a core sub-region 1730 and a portion outside this sub-region, referred to as the surrounding sub-region 1740.

[0122] The mask design system 100 rasterizes each mask pattern 1630 to generate an image mask representation of the mask pattern. The mask pattern can be a vector representation of geometry. The mask design system 100 rasterizes the mask pattern 1630 to generate a pixelated representation of the mask pattern. Therefore, the image mask representation for that region can be represented as an array of pixel values, for example, a two-dimensional array of pixel values. Each pixel can indicate whether the mask pattern has or does not have geometry at that pixel location. For example, if the mask pattern has geometry at that location, the pixel value can be 1, and if the mask pattern does not have geometry at that location, the pixel value can be 0.

[0123] The geometry of a mask pattern can represent the features of the mask or auxiliary features of the mask. Auxiliary features may not be located at the geometry of the circuit pattern, but they help in the fabrication of the geometry corresponding to the circuit pattern. Figure 18 An example mask pattern according to one embodiment is shown, illustrating feature 1810 and auxiliary feature 1820 of the mask in the region. Figure 18 The mask pattern shown in the figure comes from Figure 17 The circuit pattern shown is generated. Some features and auxiliary features are within sub-region 1730, and some features and auxiliary features are within surrounding sub-region 1740. For example, feature 1810a and auxiliary feature 1820a are within the core sub-region 1730, and feature 1810b and auxiliary feature 1820b are within the surrounding sub-region 1740.

[0124] The mask design system 100 uses a blending procedure to deweight the portion of the mask pattern outside sub-region 1730, i.e., the portion within the surrounding sub-region 1740. The mask design system 100 determines a weighted aggregation of the 1640 image mask representations to generate an aggregated image mask representation. The mask design system 100 weights pixels such that pixels closer to the center of the region are weighted more than pixels at the periphery of the region. In one embodiment, the mask design system 100 uses a blending / weighting field that is equal to 1 in the central region and decays to 0 at the edges of that region.

[0125] Figure 19 A blending region is depicted according to one embodiment, which is highly weighted at the center of the region and decreases towards the edges. For example, the weight in portion 1910 within the core sub-region 1730 is 1, and the weight in portion 1920 within the surrounding sub-region 1740 gradually decreases with distance from the edge of the core sub-region, for example, the weight decreases to 0 at the outer edge of the surrounding sub-region.

[0126] In one embodiment, the mask design system 100 initializes the background mask field to zero at all pixels corresponding to the region. The mask design system 100 then multiplies the pixel values ​​represented by the image mask by... Figure 19 The blending / weighting field shown in the diagram is used to determine the weighted pixel values ​​for each mask. The mask design system 100 adds weighted pixel values ​​to the mask representation corresponding to that region.

[0127] The mask design system 100 generates a 1650 mask pattern from the aggregated image mask representation by converting the pixel representation into a vector representation.

[0128] The final step is to extract the mask polygons from the background mask field. For this step, we can normalize the mask at each pixel (essentially, do an average) by measuring how much each unique mask contributes to each pixel, and then we can extract the contour at an intermediate level height of 0.5, which should represent the edges of the rasterized mask.

[0129] The mask design system 100 performs this weighting so that features of the mask pattern near the edges of the area are less effective for designs at the center, because they may be created using empty designs outside the area, which is not an accurate representation of the circuit design outside the frame. Therefore, the mask design system 100 only keeps the complete mask pattern at the center of the window, where it is likely most accurate. Blending allows the mask design system 100 to smoothly combine mask patterns from adjacent overlapping windows.

[0130] Figure 20 The diagram illustrates the overlapping region created by search windows centered on three adjacent geometries of the circuit design. (See diagram for example.) Figure 20 As shown, the mask design system 100 performs mask aggregation near the center of the regions for the three masks 2010a, 2010b, and 2010c. Conversely, at the edges of the regions, the mask design system 100 performs averaging only on the individual mask patterns corresponding to the polygons of the circuit design closest to that region. The mask design system 100 normalizes the pixel values ​​by dividing the sum of the pixel values ​​at each location by the number of mask patterns that contribute to the pixel values.

[0131] The mask design system 100 modifies the mask design at 1660 to use the generated mask pattern in region 1710 of the circuit design. Therefore, based on... Figure 16 The process illustrated in the diagram involves the mask design system 100 generating a mask for the entire circuit design by combining mask patterns generated from different regions.

[0132] Offset representation of mask features

[0133] In some embodiments, the mask design system 100 stores the features of the mask as offsets of the edges of the geometry of the circuit design. This representation can be used for best proximity correction (OPC). The mask design system 100 can store multiple local offsets of the mask for OPC, in which case the offset can be defined multiple times for a given location. In this case, the method described in section 3.3.1 will not be applicable because the mask is not a polygon.

[0134] Figure 21A A polygon 2110 with several sub-edges 2115 and their offsets 2120 is shown. There are three sub-edges 2115a, 2115b, and 2115c, and corresponding offsets 2120a, 2120b, and 2120c. The offset values ​​represent the distance the mask edge should deviate from the edge of the circuit design along the normal direction. The mask design system 100 performs an OPC process to determine the offsets 2120 relative to the edges of the polygons in the circuit design. The three offsets 2120a, 2120b, and 2120c are determined using sub-edge 2115b.

[0135] The mask design system 100 can generate multiple offset sets based on the geometry of the circuit design. Figure 21B Alternative results for offset 2130 generated from the edges of the circuit design are shown. The mask design system 100 solves for these offsets to generate a single consistent mask. Figure 21C It shows Figure 21A and Figure 21B The superposition of the two offset results shown.

[0136] The offset results for the two sub-edges may differ. The mask design system 100 selects a unique answer for the offset. The mask design system 100 selects an aggregate value based on the offset, such as the average, minimum, maximum, median, or any other aggregate function of the candidate offsets at a given location.

[0137] Auxiliary feature offset representation

[0138] The mechanism shown for combining offsets can be used to combine auxiliary features. The mask design system 100 allows offsets to be multi-valued, where each value represents the placement of an additional auxiliary feature outside or inside the main feature.

[0139] Figure 22 The illustration outlines an implementation of an auxiliary feature center as an OPC offset according to one embodiment. Figure 22 Polygon 2210 with auxiliary features 2120a, 2120b, and 2120c at distances d1, d2, and d3 is shown, where distances d1, d2, and d3 represent multi-value offset distances from the design of the three auxiliary features. The mask design system 100 is used in conjunction with... Figures 21A-21CThe OPC offset described is similar to the way edge segments with multiple auxiliary feature solutions are aggregated.

[0140] Because auxiliary features may overlap in space when they are placed offset from different neighboring designs, the mask design system 100 uses a Venn diagram to create regions and therefore only calculates the average of the offset auxiliary features that are in the same region as the design point, and places the auxiliary features after they have been aggregated in the region.

[0141] Figure 23 Three adjacent design polygons and a Vino boundary 2310 are depicted according to one embodiment. Auxiliary feature 2320a corresponds to polygon A, auxiliary feature 2320b corresponds to polygon B, and auxiliary feature 2320c corresponds to polygon C.

[0142] Figure 24 This illustrates how, if the mask design system did not constrain some auxiliary features to the Vino map, these auxiliary features would extend into another region and overlap with other auxiliary features. This would create a more complex conflict resolution scenario, which the mask design system 100 avoids by using a Vino map to constrain the auxiliary features to their own regions.

[0143] Electronic Design Automation Process

[0144] Figure 25 The illustration shows an example set 2500 of processes used during the design, verification, and manufacturing of articles such as integrated circuits, for converting and verifying design data and instructions representing integrated circuits. Each of these processes can be structured and implemented as multiple modules or operations. The term 'EDA' stands for 'Electronic Design Automation'. These processes begin with creating a product concept 2510 using information provided by a designer, which is then converted to produce an article using a set of EDA processes 2512. Upon completion of the design, it is tape-out 2534, which is when the original pattern (e.g., geometric pattern) of the integrated circuit is sent to a manufacturing plant to create a mask set, which is then used to manufacture the integrated circuit. After tape-out, semiconductor dies are manufactured 2536, and packaging and assembly processes 2538 are performed to produce the finished integrated circuit 2540.

[0145] Specifications for circuits or electronic structures can range from low-level transistor material placement to high-level description languages. High-level abstractions are used to design circuits and systems by employing hardware description languages ​​('HDL') such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. HDL descriptions can be translated into logic-level register-transfer level ('RTL') descriptions, gate-level descriptions, placement-level descriptions, or mask-level descriptions. Each lower level of abstraction (i.e., a less abstract description) adds more useful details to the design description, such as more details about the modules included in that description. Lower levels of abstraction (i.e., less abstract descriptions) can be computer-generated, exported from design libraries, or created by another design automation process. An example of a specification language used to specify lower levels of abstraction for more detailed descriptions is SPICE, used for detailed descriptions of circuits with many analog components. The description at each level of abstraction is implemented for use by the corresponding tools at that layer (e.g., formal verification tools). The design process can use... Figure 25 The sequence described herein. The described process is implemented by an EDA product (or tool).

[0146] During system design phase 2514, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction. At this stage, the design can be divided into different types of modules or components.

[0147] During logic design and functional verification 2516, modules or components in a circuit are specified in one or more description languages, and the functional accuracy of that specification is checked. For example, components of a circuit can be verified to generate outputs that conform to the requirements of the specifications of the circuit or system being designed. Functional verification can be performed using simulators and other programs, such as test bench generators, static HDL checkers, and formal verifiers. In some embodiments, a special system of components referred to as a “simulator” or “prototype system” is used to accelerate functional verification.

[0148] During synthesis and design 2518 for testing, HDL code is converted into a netlist. In some embodiments, the netlist may be a graph structure, where edges represent components of the circuit, and nodes represent how components are interconnected. Both HDL code and netlist are hierarchical artifacts that can be used by EDA products to verify whether the integrated circuit functions according to a specified design during manufacturing. The netlist can be optimized for a target semiconductor manufacturing technology. Additionally, the completed integrated circuit can be tested to verify that it meets specifications.

[0149] During netlist verification 2520, the consistency between the netlist and timing constraints, as well as the correspondence between the netlist and HDL code, are checked. During design planning 2522, the overall layout of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0150] During the layout or physical implementation of 2524, physical placement (positioning of circuit components such as transistors or capacitors) and wiring (connecting circuit components through multiple conductors) are performed, and cells can be selected from a library to implement a specific logic function. As used herein, the term "cell" can specify a set of transistors, other components, and interconnections that provide Boolean logic functions (e.g., AND, OR, NOT, XOR) or storage functions (such as flip-flops or latches). As used herein, a circuit "block" can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components and are implemented as physical structures and in simulations. Parameters, such as size, are specified for the selected cells (based on "standard cells"), and these parameters are made accessible in a database for use in EDA products.

[0151] During Analysis and Extraction 2526, circuit functionality is verified at the layout level, allowing for finer-grained layout design. During Physical Verification 2528, the layout design is examined to ensure manufacturing constraints are correct, such as DRC constraints, electrical constraints, and lithographic constraints, and to ensure circuit functionality conforms to the HDL design specifications. During Resolution Enhancement 2530, the geometry of the layout is transformed to improve the fabrication of the circuit design.

[0152] During the tape-out process, data is created for the production of a photomask (after which photolithographic enhancement is applied, if appropriate). During mask data preparation 2532, the "tape-out" data is used to generate a photomask, which is used to produce the finished integrated circuit.

[0153] Computer systems (such as) Figure 26 The storage subsystem of the computer system 2600 can be used to store programs and data structures used by some or all of the EDA products described herein, as well as units for developing libraries and products for using the physical and logical designs of the libraries.

[0154] The embodiments can be used to process circuit design during various stages of the electronic design automation process of memory circuit layout, such as during layout or physical implementation 2524, analysis and extraction 2526, mask data preparation 2532, etc.

[0155] Computer Architecture

[0156] Figure 26An example machine of computer system 2600 is shown, within which a set of instructions can be executed to cause the machine to perform any or one of the methods discussed herein. In alternative implementations, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0157] A machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network device, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) to perform the actions to be taken by the specified machine. Furthermore, although a single machine is shown, the term "machine" should also be understood to include any collection of machines that individually or jointly execute a set (or more) of instructions to perform any or more of the methods discussed herein.

[0158] Example computer system 2600 includes processing device 2602, main memory 2604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), static memory 2606 (e.g., flash memory, static random access memory (SRAM), etc.) and data storage device 2618, which communicate with each other via bus 2630.

[0159] Processing device 2602 represents one or more processors, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 2602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 2602 may be configured to execute instructions 2626 for performing the operations and steps described herein.

[0160] The computer system 2600 may also include a network interface device 2608 for communication via a network 2620. The computer system 2600 may also include a video display unit 2610 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 2612 (e.g., a keyboard), a cursor control device 2614 (e.g., a mouse), a graphics processing unit 2622, a signal generation device 2616 (e.g., a speaker), a video processing unit 2628, and an audio processing unit 2632.

[0161] Data storage device 2618 may include machine-readable storage medium 2624 (also known as non-transitory computer-readable medium) on which one or more sets of instructions 2626 or software embodying any one or more of the methods or functions described herein are stored. The instructions 2626 may also reside wholly or at least partially in main memory 2604 and / or processing device 2602 during execution by computer system 2600, which also constitute machine-readable storage media.

[0162] In some implementations, instruction 2626 includes instructions for implementing functions corresponding to this disclosure. Although machine-readable storage medium 2624 is shown as a single medium in the example implementations, the term "machine-readable storage medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) storing one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine and processing device 2602 to perform any one or more methods of the methods of this disclosure. The term "machine-readable storage medium" should therefore be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0163] Some parts of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the most efficient way for those skilled in the art of data processing to communicate the essence of their work to others skilled in the art. An algorithm can be a sequence of operations that leads to a desired result. These operations are operations that require physical manipulation of physical quantities. Such quantities can take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Such signals can be referred to as bits, values, elements, symbols, characters, items, numbers, etc.

[0164] However, it should be remembered that all these and similar terms are associated with appropriate physical quantities and are merely convenient notations applied to those quantities. Unless otherwise stated, it is apparent from this disclosure that, throughout the specification, certain terms refer to the actions and processes of a computer system or similar electronic computing device that manipulate and convert data, represented as physical (electronic) quantities within the registers and memories of the computer system, into other data, similarly represented as physical quantities within the computer system's memory or registers or other such information storage devices.

[0165] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the intended purpose, or it may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0166] The algorithm and display presented herein are not inherently related to any particular computer or other device. Various other systems may be used with the program taught herein, or it may be demonstrated that constructing more specialized devices to perform the method is convenient. Furthermore, this disclosure is not described with reference to any particular programming language. It will be understood that various programming languages ​​may be used to implement the teachings of this disclosure as described herein.

[0167] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium storing instructions that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media include any mechanism for storing information in a machine-readable (e.g., computer-readable) form. For example, machine-readable (e.g., computer-readable) media include machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0168] In the foregoing disclosure, implementations of this disclosure have been described with reference to specific example implementations. It will be apparent that various modifications can be made to these implementations without departing from the scope and broad spirit of the embodiments of this disclosure as set forth in the appended claims. Where elements are referred to in the singular in this disclosure, more than one element may be depicted in the drawings, and the same elements are labeled with the same numerals. Therefore, this disclosure and the drawings should be considered illustrative rather than restrictive.

Claims

1. A method for performing mask synthesis on a circuit design, the method comprising: The circuit design representing the physical layout of the receiving circuit; For each of the multiple locations in the circuit design, a circuit pattern is identified from the circuit design based on a search window placed at the corresponding location in the circuit design, the circuit pattern including one or more geometries within the search window; Generate a signature for the circuit pattern of each identifier; A mask solution database is generated and stored that indexes mask patterns to circuit patterns. The mask solution database stores each mask pattern, each mask pattern being indexed to a circuit pattern used to generate the corresponding mask pattern, wherein each mask pattern is indexed to the circuit pattern using the signature of the corresponding circuit pattern. By searching the signature of the identified circuit pattern in the mask solution database, it is determined that the identified circuit pattern does not correspond to a previously identified circuit pattern from the circuit design; In response to determining that the identified circuit pattern does not correspond to a previously identified circuit pattern, a processing device generates a mask pattern for the identified circuit pattern from the circuit design, and the mask pattern is stored in the mask solution database. Using the mask pattern stored in the mask solution database, a mask for the circuit design is generated.

2. The method of claim 1, wherein the circuit design specifies hierarchical units, and the circuit pattern represents a portion of the circuit design smaller than the smallest hierarchical unit of the circuit design.

3. The method of claim 1, wherein the signature remains unchanged across multiple transformations of the circuit pattern, the transformations including rotation, translation, and mirroring.

4. The method of claim 1, wherein the signature is selected from a set of obtained signatures, each obtained signature representing a geometric hash key obtained by applying a transformation to the circuit pattern, wherein the selected signature represents the obtained hash key having a minimum number of hash keys.

5. The method according to claim 1, further comprising: In response to identifying multiple mask patterns that overlap with each other in a region of the circuit design, the mask patterns are aggregated to determine an aggregated mask pattern, which is used as the mask for the region of the circuit design.

6. The method according to claim 1, further comprising: In response to identifying a geometry within the circuit design that exceeds a threshold size, one or more locations within the geometry are identified; as well as Place the search window in the center of each identified location.

7. A method for performing mask synthesis on a circuit design, the method comprising: The circuit design, which represents the physical layout of the circuit, includes geometry; Receive the mask design for the circuit design; Identify one or more circuit patterns within the circuit design; Identify one or more mask patterns, each mask pattern corresponding to a circuit pattern derived from the one or more circuit patterns; Determine the properties of the one or more circuit patterns, the properties being based on the geometry within the one or more circuit patterns; The processing device determines a mask pattern based on the one or more mask patterns, such that the determined mask pattern has properties corresponding to the one or more circuit patterns; as well as At least a portion of the mask design is replaced with a modified mask pattern.

8. The method according to claim 7, further comprising: The property of the one or more circuit patterns represents a similarity exceeding a threshold between the one or more circuit patterns; as well as Modifying one or more mask patterns includes: The aggregated mask pattern is determined by aggregating one or more mask patterns; as well as Use the aggregated mask pattern, instead of using each of the one or more mask patterns.

9. The method of claim 8, wherein determining the polymer mask pattern comprises: Each of the one or more mask patterns is rasterized to generate an image representation of the mask pattern; The image representation of the aggregated mask pattern; as well as A mask pattern is generated by converting the aggregated image representation into a vector representation.

10. The method of claim 9, wherein the aggregation comprises: Average the one or more mask patterns.

11. The method of claim 9, wherein the aggregation comprises: Select a mask pattern with optimal lithographic performance from the one or more mask patterns.

12. The method of claim 7, wherein the property of the one or more circuit patterns represents symmetry in the circuit patterns, the method further comprising: Modify the mask pattern corresponding to the circuit pattern having the symmetry to implement the symmetry in the mask pattern.

13. The method of claim 12, wherein the symmetry is one of the following: Rotational symmetry; Mirror symmetry; Translational symmetry; Some parts are symmetrically spaced; or Their combination.

14. A method for performing mask synthesis on a circuit design, the method comprising: The circuit design, which represents the physical layout of the circuit, includes geometry; Identify the areas within the circuit design; Identify multiple mask patterns for the region, wherein at least some of the multiple mask patterns overlap, and each mask pattern uses a vector representation of its geometry; For each of the plurality of mask patterns, the mask pattern is rasterized to generate an image mask representation including multiple pixel values; A weighted aggregation of the plurality of image mask representations is determined to generate an aggregated image mask representation, wherein pixel values ​​closer to the center of the region are weighted more than pixel values ​​farther from the center of the region; A mask pattern is generated from the aggregated image mask representation by a processing device; as well as Modify the mask design for the circuit design to use the generated mask pattern for the area of ​​the circuit design.

15. The method of claim 14, further comprising: The central axis is used to define multiple regions within the circuit design such that the regions within these multiple regions do not overlap.

16. The method of claim 14, wherein the region includes a core region, the core region includes the center of the region, and all pixel values ​​in the core region have the same weight.

17. The method of claim 16, wherein the region further comprises a surrounding region around the core region, wherein the weight of pixel values ​​in the surrounding region decreases from the edge of the core region toward the edge of the region.

18. The method of claim 14, wherein determining a weighted aggregation of the plurality of image mask representations to generate an aggregated image mask representation comprises: The weighted pixel values ​​of the rasterized mask pattern are averaged.

19. The method of claim 14, wherein determining the weighted aggregation of the plurality of image mask representations to generate an aggregated image mask representation comprises: Generate a vector representation of the mask pattern.

20. A non-transitory storage medium storing instructions that, when executed by a computer processor, cause the computer processor to perform the steps of the method according to claims 1-19.

21. A computer system, comprising: Computer processor; as well as A non-transitory storage medium storing instructions that, when executed by the computer processor, cause the computer processor to perform the steps of the method according to claims 1-19.

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