Substrate processing apparatus and processing condition adjustment method

Abstract

A substrate processing apparatus for processing a substrate includes a heat processing section for heat processing a substrate; a photographing section for photographing a substrate; and a control section configured to execute a conditioning process for adjusting a condition of processing a substrate, the conditioning process including: a pre-exposure photographing step of controlling the photographing section to photograph an unexposed conditioning substrate on which a resist film is formed; a heat processing step of controlling the heat processing section to perform the heat processing on the conditioning substrate on which a uniform exposure process of exposing each region of a substrate surface with a certain exposure amount has been performed, after the pre-exposure photographing step; a post-heating photographing step of controlling the photographing section to photograph the conditioning substrate, after the heat processing step; a temperature distribution estimation step of estimating an in-plane temperature distribution of the conditioning substrate at the time of the heat processing, based on a photographing result of the pre-exposure photographing step and a photographing result of the post-heating photographing step; and a heat processing condition decision step of deciding a processing condition of the heat processing, based on an estimation result of the in-plane temperature distribution of the conditioning substrate.

Description

Technical Field

[0001] This invention relates to a substrate processing apparatus and a method for adjusting processing conditions. Background Technology

[0002] Patent Document 1 discloses a substrate processing method for uniformly forming a resist pattern of desired linewidth on a wafer. In this method, the film thickness distribution of the resist film formed on the wafer is obtained before exposure in an exposure apparatus. Then, the wafer with the resist film is patterned and exposed. Next, the patterned resist film is heat-treated. Then, the film thickness distribution of the heat-treated resist film is obtained, and film thickness difference data is calculated based on the film thickness distribution before exposure and the film thickness distribution after heat treatment. Next, referring to a linewidth related data table, the linewidth (estimated linewidth) corresponding to the film thickness difference data is calculated within the surface of the wafer. If the calculated estimated linewidth deviates within the surface of the wafer, the resist film is heat-treated again. The conditions for this heat treatment are set such that the heating temperature of areas with larger estimated linewidths is higher than the heating temperature of other areas. Then, the resist film that has undergone the second heat treatment is developed.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2017-28086 Summary of the Invention

[0006] The problem that the invention aims to solve

[0007] The technique of the present invention, in the heat treatment of the substrate, at least after exposure, for the processing of the substrate in order to form a resist pattern, is performed in a manner that the result of the processing is uniform in the plane of the substrate, so as to form a resist pattern with uniform line width in the plane on the substrate.

[0008] Methods for solving problems

[0009] One aspect of the present invention is a substrate processing apparatus for processing a substrate, comprising: a heat treatment unit for heat treatment of the substrate; an imaging unit for imaging the substrate; and a control unit configured to perform an adjustment process for adjusting the conditions for processing the substrate, the adjustment process comprising: a pre-exposure imaging step, wherein the imaging unit is controlled to image an unexposed adjustment substrate having a resist film formed thereon; a heat treatment step, wherein after the pre-exposure imaging step, the heat treatment unit is controlled to perform the heat treatment on the adjustment substrate having undergone uniform exposure treatment in which each area of ​​the substrate surface has been exposed with a certain exposure amount; a post-heating imaging step, wherein after the heat treatment step, the imaging unit is controlled to image the adjustment substrate; a temperature distribution estimation step, wherein based on the imaging results of the pre-exposure imaging step and the imaging results of the post-heating imaging step, the in-plane temperature distribution of the adjustment substrate during the heat treatment is estimated; and a heat treatment condition determination step, wherein based on the estimated in-plane temperature distribution of the adjustment substrate, the processing conditions for the heat treatment are determined.

[0010] Invention Effects

[0011] According to the present invention, the heat treatment, at least after exposure, in the processing of the substrate for forming a resist pattern can be carried out in such a way that the result of the processing becomes uniform in the plane of the substrate, and a resist pattern with uniform line width in the plane can be formed on the substrate. Attached Figure Description

[0012] Figure 1 This is a top view showing the schematic structure of the substrate processing system according to the first embodiment.

[0013] Figure 2 This is a front view showing the schematic structure of the substrate processing system according to the first embodiment.

[0014] Figure 3 This is a rear view showing the schematic structure of the substrate processing system according to the first embodiment.

[0015] Figure 4 It is a longitudinal cross-sectional view showing the general structure of the developing unit.

[0016] Figure 5 It is a cross-sectional view showing the general structure of the developing unit.

[0017] Figure 6 It is a longitudinal cross-sectional view showing the general structure of the heat treatment unit.

[0018] Figure 7 It is a cross-sectional view showing the general structure of the heat treatment unit.

[0019] Figure 8 This is a top view showing the general structure of the hot plate of the heat treatment unit.

[0020] Figure 9 It is a longitudinal cross-sectional view showing the general structure of the defect inspection unit.

[0021] Figure 10 It is a cross-sectional view showing the general structure of the defect inspection unit.

[0022] Figure 11 This is a flowchart illustrating the adjustment process of the processing conditions for PEB processing.

[0023] Figure 12 This is a conceptual diagram of a method for predicting temperature distribution.

[0024] Figure 13 This is a flowchart illustrating the method for obtaining calibration curves of wafer temperature during PEB processing.

[0025] Figure 14 This is a flowchart illustrating the adjustment process of the processing conditions in the second embodiment.

[0026] Figure 15 This is a flowchart illustrating the method for obtaining a calibration curve and a correction curve for determining the film thickness of the resist film after development treatment and the development treatment conditions.

[0027] Figure 16 This is a front view showing an outline of the internal structure of the substrate processing apparatus according to the third embodiment.

[0028] Figure 17 This is a longitudinal cross-sectional view showing the schematic structure of the heat treatment unit of the substrate processing apparatus of the fourth embodiment.

[0029] Figure 18 This is a front view showing an outline of the internal structure of the substrate processing apparatus according to the fifth embodiment. Detailed Implementation

[0030] In the photolithography step of semiconductor device manufacturing processes, a series of processes are performed to form a predetermined resist pattern on a semiconductor wafer (hereinafter referred to as "wafer"). These processes include, for example, resist coating, which involves supplying a resist solution to the wafer to form a resist film, and exposure, which exposes the resist film to the predetermined pattern. Furthermore, these processes also include post-exposure heat treatment (PEB) to promote chemical reactions within the resist film after exposure, and development treatment to develop the exposed resist film.

[0031] The temperature of the wafer during PEB processing significantly affects the linewidth of the resist pattern ultimately formed on the wafer. Furthermore, it is required that the linewidth of the resist pattern be uniformly formed within a plane. Therefore, the heat treatment apparatus for PEB processing is equipped with multiple heating zones, each with a different temperature setting.

[0032] In setting the temperature of each heating zone, the prior art actually performs a series of resist pattern formation processes on the test wafer, measures the linewidth of the resist pattern in each zone, and sets the temperature of each heating zone based on the measurement results. However, although this method improves the uniformity of the resist pattern linewidth within the wafer surface, it cannot ensure that the temperature of the wafer, i.e., the result of the wafer heating process, is uniform within the wafer surface. This is because the pattern exposure conditions, development conditions, etc., also affect the linewidth of the resist pattern. The same applies when the temperature setting of each heating zone in the heat treatment apparatus does not use the linewidth of the actually formed and measured resist pattern, but instead uses the estimated linewidth of the resist pattern as in Patent Document 1.

[0033] To further improve the uniformity of the linewidth of the resist pattern in the plane, it is important to perform the heat treatment of the wafer for forming the resist pattern in a manner that ensures the result of the treatment is uniform in the plane of the substrate.

[0034] Therefore, in the technology of the present invention, the heat treatment after exposure in the processing of the substrate for forming a resist pattern is performed in a way that the result of the processing is uniform in the surface of the substrate, and a resist pattern with uniform line width in the surface can be formed.

[0035] Hereinafter, the substrate processing apparatus and processing condition adjustment method of this embodiment will be described with reference to the accompanying drawings. In this specification and the accompanying drawings, components having substantially the same function and structure are indicated by the same reference numerals, and repeated descriptions of these components are omitted.

[0036] (First Implementation)

[0037] Figure 1 This is an explanatory diagram showing a general outline of the internal structure of the substrate processing apparatus 1 according to the first embodiment. Figure 2 and Figure 3 These are a front view and a rear view, respectively, showing an outline of the internal structure of the substrate processing device 1.

[0038] like Figure 1As shown, the substrate processing apparatus 1 includes, for example, a cassette loading / unloading station 2 for loading and unloading cassettes C between itself and the outside; and a processing station 3 having multiple processing units that perform specified processes such as resist coating and PEB application. The substrate processing apparatus 1 has a structure that integrally connects the cassette loading / unloading station 2, the processing station 3, and an interface station 5 for transferring wafers W between itself and an exposure apparatus 4 adjacent to the processing station 3. Furthermore, the substrate processing apparatus 1 includes a control unit 6 for controlling the substrate processing apparatus 1.

[0039] The cassette loading / unloading station 2 is, for example, divided into a cassette loading / unloading section 10 and a wafer transport section 11. For example, the cassette loading / unloading section 10 is located in the negative direction of the Y-direction of the substrate processing apparatus 1. Figure 1 The end on the left side (towards the left). A box loading / unloading section 10 is provided with a box mounting platform 12. Multiple mounting plates 13, for example, four, are provided on the box mounting platform 12. The mounting plates 13 are positioned in the horizontal X direction ( Figure 1 They are arranged in a row in the vertical direction. The cartridge C can be placed on these mounting plates 13 when the cartridge C is fed in and out relative to the outside of the substrate processing device 1.

[0040] like Figure 1 As shown, a wafer transport unit 21 is provided in the wafer transport section 11, which is movable on a transport path 20 extending in the X direction. The wafer transport unit 21 is movable in the vertical direction and can also move about the vertical axis (θ direction), and can transport wafers W between the junction of the cassette C on each mounting plate 13 and the third block G3 of the processing station 3 described later.

[0041] Processing station 3 is equipped with multiple blocks G1, G2, G3, and G4, each containing various units, for example, the first to the fourth blocks. For example, on the front side of processing station 3 ( Figure 1 The first block G1 is set on the negative X-direction side of the processing station 3. Figure 1 A second block G2 is located on the positive X-direction side of processing station 3. Additionally, on the box loading / unloading station 2 side of processing station 3... Figure 1 A third block G3 is set on the negative Y-direction side, on the interface station 5 side of processing station 3. Figure 1 The fourth block G4 is set on the positive Y-direction side.

[0042] In the first block G1, such as Figure 2 As shown, multiple liquid processing units are arranged sequentially from below, such as a development processing unit 30, which is a development processing section for developing wafer W, and a resist coating unit 31, which coats the wafer W with resist liquid to form a resist film.

[0043] For example, three developing units 30 and three resist coating units 31 are arranged horizontally. The number and arrangement of these developing units 30 and resist coating units 31 can be arbitrarily selected.

[0044] In these developing units 30 and resist coating units 31, spin coating, for example, is performed to coat a specified processing solution onto the wafer W. In spin coating, for example, the processing solution is discharged from a coating nozzle onto the wafer W, and the wafer W is rotated, causing the processing solution to spread across the surface of the wafer W. The structure of the developing unit 30 will be described later.

[0045] For example, in the second block G2, such as Figure 3 As shown, heat treatment units 40, which perform heat treatment processes such as heating and cooling of the wafer W, and peripheral exposure units 41, which expose the outer periphery of the wafer W, are arranged in both the vertical and horizontal directions. The number and arrangement of these heat treatment units 40 and peripheral exposure units 41 can be arbitrarily selected. The structure of the heat treatment unit 40 will be described later.

[0046] Multiple handover units 50 are provided in the third block G3. Additionally, multiple handover units 60 are provided in the fourth block G4, and defect inspection units 61 are installed on them. The structure of the defect inspection unit 61 will be described later.

[0047] like Figure 1 As shown, a wafer transport region D is formed in the area surrounded by the first block G1 to the fourth block G4. A wafer transport unit 70, for example, is disposed in the wafer transport region D.

[0048] The wafer transport unit 70 has a transport arm 70a that is movable, for example, in the Y direction, front-back direction, θ direction, and vertical direction. The wafer transport unit 70 moves within the wafer transport area D and is capable of transporting the wafer W to designated cells within the surrounding first block G1, second block G2, third block G3, and fourth block G4. The wafer transport unit 70 is, for example, as shown in... Figure 3 The diagram shows multiple units arranged vertically, for example, units capable of transporting the chip W to the same height in each block G1 to G4.

[0049] In addition, a shuttle transport unit 71 is provided in the wafer transport area D to transport the wafer W in a straight line between the third block G3 and the fourth block G4.

[0050] Shuttle transport unit 71, for example, in Figure 3 It can move linearly in the Y direction. The shuttle transport unit 71 moves in the Y direction while supporting the wafer W, and can transport the wafer W between the transfer unit 50 of the third block G3 and the transfer unit 60 of the fourth block G4 at the same height.

[0051] like Figure 1 As shown, a wafer transport unit 72 is provided on the positive X-direction side of the third block G3. The wafer transport unit 72 has, for example, a transport arm 72a that is movable in the front-back direction, the θ direction, and the vertical direction. The wafer transport unit 72 moves vertically while supporting the wafer W, and can transport the wafer W to each transfer unit 50 within the third block G3.

[0052] Interface station 5 is provided with a wafer transport unit 73 and a transfer unit 74. The wafer transport unit 73 has, for example, a transport arm 73a that is movable in the Y direction, the θ direction, and the vertical direction. The wafer transport unit 73 is capable of supporting the wafer W in the transport arm 73a and transporting the wafer W between the transfer units 60, the transfer unit 74, and the exposure apparatus 4 within the fourth block G4.

[0053] The aforementioned control unit 6 is, for example, a computer, and has a program storage unit (not shown). The program storage unit stores a program that controls the operation of the drive systems such as the various processing units and transport units, and controls the processing of the wafer W, including the processing condition adjustment processing in the substrate processing apparatus 1. Furthermore, the program is recorded in a computer-readable storage medium H, and can also be installed into the control unit 6 from the storage medium H.

[0054] Next, the structure of the developing unit 30 will be described. Figure 4 and Figure 5 These are a longitudinal section view and a cross section view showing the general structure of the developing processing unit 30, respectively.

[0055] like Figure 4 and Figure 5 As shown, the developing processing unit 30 has a processing container 100 capable of sealing its interior. A wafer W feed outlet (not shown) is formed on the side of the processing container 100 on the wafer transport unit 70 side, and an opening and closing gate (not shown) is provided at the feed outlet.

[0056] A rotary chuck 110 is provided in the center of the processing container 100 to hold and rotate the wafer W. The rotary chuck 110 has a horizontal upper surface, on which a suction port (not shown) for attracting, for example, the wafer W is provided. By being attracted from the suction port, the wafer W can be adsorbed and held on the rotary chuck 110.

[0057] Below the rotary chuck 110 is a chuck drive unit 111, which includes, for example, a motor. The rotary chuck 110 can rotate at a predetermined speed using the chuck drive unit 111. In addition, the chuck drive unit 111 is provided with a lifting drive source, such as a cylinder, so that the rotary chuck 110 can be raised and lowered.

[0058] A cup-shaped portion 112 is provided around the rotary chuck 110 to catch and recover liquid that spills or falls from the wafer W. A discharge pipe 113 for discharging the recovered liquid and an exhaust pipe 114 for evacuating the atmosphere inside the cup-shaped portion 112 are connected to the lower surface of the cup-shaped portion 112.

[0059] like Figure 5 As shown, in the negative X direction of the cup-shaped portion 112 ( Figure 5 The lower side of the middle is formed along the Y direction ( Figure 5 The track 120 extends in the left-right direction (within the cup-shaped portion 112). For example, the track 120 extends from the negative Y-direction of the cup-shaped portion 112 (within the cup-shaped portion 112). Figure 5 The outer side of the left side of the middle forms the positive direction of the Y direction. Figure 5 (To the right of the center) on the outer side. An arm 121 is installed on track 120.

[0060] like Figure 4 and Figure 5 As shown, an application nozzle 122 for supplying developer to the wafer W is supported on arm 121. Arm 121 utilizes... Figure 5 The nozzle drive unit 123 shown is movable on the track 120. As a result, the coating nozzle 122 can be moved from the standby unit 124, which is located on the outer side of the cup-shaped portion 112 in the positive Y direction, to above the center of the wafer W within the cup-shaped portion 112, and then can move radially along the wafer W. Furthermore, the arm 121 is height-adjustable via the nozzle drive unit 123, allowing adjustment of the height of the coating nozzle 122.

[0061] like Figure 4 As shown, a supply pipe 125 for supplying developer to the coating nozzle 122 is connected to the coating nozzle 122. The supply pipe 125 is connected to a developer supply source 126 that stores developer internally. In addition, a supply device assembly 127 including a valve for controlling the flow of developer, a flow regulating unit, etc., is provided in the supply pipe 125.

[0062] Furthermore, the structure of the resist coating unit 31 is the same as that of the developing unit 30 described above. However, the processing liquid supplied from the coating nozzle is different in the developing unit 30 and the resist coating unit 31.

[0063] Next, the structure of the heat treatment unit 40 will be described. Figure 6 and Figure 7 These are, respectively, a longitudinal section view and a cross-sectional view showing the general structure of the heat treatment unit 40.

[0064] For example, such as Figure 6 and Figure 7As shown, the heat treatment unit 40 has a heating section 131 for heating the wafer W and a cooling section 132 for cooling the wafer W within the housing 130. Figure 7 As shown, feed in and feed out ports 133 for feeding in and feeding out wafers W are formed on both sides near the cooling section 132 of the housing 130.

[0065] like Figure 6 As shown, the heating unit 131 has an upper cover 140 that can move up and down, and a lower heat plate storage unit 141 that is integrally formed with the cover 140 to form the processing chamber S.

[0066] The cover 140 has a generally cylindrical shape with an opening at the bottom, covering the surface of the wafer W to be processed, i.e., the upper surface, which is placed on the hot plate 142 described later. An exhaust section 140a is provided at the center of the upper surface of the cover 140. The atmosphere inside the processing chamber S is exhausted through the exhaust section 140a.

[0067] In addition, a temperature sensor 143 is provided on the cover 140 as a temperature measuring unit for measuring the temperature of the cover 140. In the example shown in the figure, the temperature sensor 143 is provided at the end of the cover 140, but it may also be provided at the center of the cover 140, etc.

[0068] A wafer W is placed in the center of the hot plate receiving section 141, and a hot plate 142 is provided to heat the wafer W. The hot plate 142 is formed into a generally disc-shaped structure with a thickness, and a heater 150 is provided inside it to heat the upper surface of the hot plate 142, i.e., the mounting surface of the wafer W. An electric heater is used, for example, as the heater 150. The structure of the hot plate 142 will be described later.

[0069] A lifting pin 151 that penetrates the hot plate 142 in the thickness direction is provided in the hot plate storage section 141. The lifting pin 151 can be raised and lowered by a lifting drive unit 152 such as a cylinder, and can protrude to the upper surface of the hot plate 142 to transfer the wafer W between it and the cooling plate 170 described later.

[0070] For example, such as Figure 6 As shown, the hot plate receiving portion 141 has an annular retaining member 160 that receives and holds the outer periphery of the hot plate 142, and a generally cylindrical support ring 161 that surrounds the outer periphery of the retaining member 160.

[0071] A cooling plate 170, for example, for mounting and cooling a wafer W, is provided in a cooling section 132 adjacent to the heating section 131. The cooling plate 170 is, for example, as shown in the example... Figure 7The plate shown has a roughly square shape, with the end face of the heating section 131 curved into an arc shape. A cooling component (not shown), such as a Peltier element, is built into the interior of the cooling plate 170, enabling the cooling plate 170 to be adjusted to a predetermined set temperature.

[0072] Cooling plate 170, for example Figure 6 The cooling plate 170 is supported by a support arm 171, which is mounted on a track 172 extending in the X direction toward the heating section 131. The cooling plate 170 can move on the track 172 by means of a drive mechanism 173 mounted on the support arm 171. As a result, the cooling plate 170 can move above the hot plate 142 on the heating section 131 side.

[0073] For example, a line is formed along the cooling plate 170. Figure 7 Two slits 174 in the X direction. Slits 174 are formed from the end face of the cooling plate 170 on the heating section 131 side to near the center of the cooling plate 170. These slits 174 prevent interference between the cooling plate 170 moving towards the heating section 131 side and the lifting pin 151 on the hot plate 142. Figure 6 As shown, a lifting pin 175 is provided below the cooling plate 170 located within the cooling section 132. The lifting pin 175 can be raised and lowered using a lifting drive unit 176. The lifting pin 175 rises from below the cooling plate 170 and protrudes upward through the gap 174, for example enabling the transfer of wafer W between the wafer transport unit 70, which enters the interior of the housing 130 from the feed outlet 133, and the wafer W.

[0074] Next, the structure of the hot plate 142 will be described in detail. Figure 8 This is a top view showing the general structure of the hot plate 142. (Example) Figure 8 As shown, the hot plate 142 is divided into multiple, for example, five hot plate regions (hereinafter sometimes referred to as "channels") R1 to R5. The hot plate 142 is, for example, divided into a circular channel R1 located at the center when viewed from the plane and channels R2 to R5 that divide the perimeter of the channel R1 into four equal arcs.

[0075] Each channel R1 to R5 of the hot plate 142 is equipped with a heater 180, which can heat each channel R1 to R5 individually. The heat output of each heater 180 in each channel R1 to R5 is adjusted, for example, by a temperature control unit 181. The temperature control unit 181 can adjust the heat output of each heater 180 to control the temperature of each channel R1 to R5 at a predetermined set temperature. The temperature setting in the temperature control unit 181 is performed by the control unit 6.

[0076] Next, the structure of the defect inspection unit 61 will be described. Figure 9 and Figure 10These are, respectively, a longitudinal section view and a cross-sectional view showing the approximate structure of the defect inspection unit 61. For example... Figure 9 and Figure 10 As shown, the defect inspection unit 61 has a housing 190. A mounting stage 200 for placing the wafer W is disposed within the housing 190. This mounting stage 200 can be rotated and stopped by a rotation drive 201, such as a motor. A flange extending from one end of the housing 190 is provided on the bottom surface of the housing 190. Figure 10 The X-direction (negative direction side) extends to the other end ( Figure 10 The guide rail 202 (on the positive X-direction side) is provided. The stage 200 and the rotation drive unit 201 are provided on the guide rail 202, and can be moved along the guide rail 202 by means of the drive unit 203.

[0077] On the other end side inside the outer casing 190 ( Figure 10 A camera unit 210 is provided on the side of the device (the positive side in the X direction). The camera unit 210 is, for example, a wide-angle CCD camera.

[0078] A translucent reflector 211 is disposed near the center of the upper part of the housing 190. The translucent reflector 211 is positioned opposite the imaging unit 210, tilted upwards at a 45-degree angle from its vertically downward orientation towards the imaging unit 210. An illumination unit 212 is disposed above the translucent reflector 211. The translucent reflector 211 and the illumination unit 212 are fixed to the upper surface inside the housing 190. Illumination from the illumination unit 212 is directed downwards through the translucent reflector 211. Consequently, light reflected from an object located below the illumination unit 212 is further reflected by the translucent reflector 211 and captured by the imaging unit 210. That is, the imaging unit 210 is able to capture images of objects located within the illumination area of ​​the illumination unit 212.

[0079] Next, the wafer processing using the substrate processing apparatus 1 will be described.

[0080] In the wafer processing using the substrate processing apparatus 1, firstly, the wafer W is taken out from the cassette C on the cassette stage 12 by the wafer transport unit 21 and transported to the handover unit 50 of the processing station 3.

[0081] Next, the wafer W is transported by the wafer transport unit 70 to the heat treatment unit 40 of the second block G2 for temperature conditioning. Afterwards, the wafer W is transported to the resist coating unit 31 of the first block G1, where a resist film is formed on the wafer W. Then, the wafer W is transported to the heat treatment unit 40 for pre-applied bake (PAB). The same heat treatment is performed in the pre-baking process, the subsequent PEB process, and the post-baking process. However, the heat treatment units 40 used for each heat treatment are different.

[0082] Then, the wafer W is transported to the peripheral exposure unit 41 for peripheral exposure processing.

[0083] Next, the wafer W is transported to the exposure apparatus 4 for exposure processing with a specified pattern.

[0084] Next, wafer W is transported to heat treatment unit 40 for PEB processing. Then, wafer W is transported, for example, to development unit 30 for development processing. After development processing, wafer W is transported to heat treatment unit 40 for post-bake processing. Then, wafer W is transported to defect inspection unit 61 for defect inspection. In defect inspection, checks are performed for damage, foreign matter adhesion, etc. Afterward, wafer W is transported to cell C on cell stage 12, and a series of photolithography steps are completed.

[0085] Next, use Figure 11 and Figure 12 The process of adjusting the processing conditions for PEB processing to make the processing results uniform within the wafer plane is explained. Figure 11 This is a flowchart illustrating the adjustment process of the processing conditions for PEB processing. Figure 12 This is a conceptual diagram of a temperature distribution estimation method. In the following example, during the adjustment of processing conditions for PEB processing, the set temperatures of each channel R1 to R5 of the hot plate 142 during PEB processing are adjusted. Furthermore, the above adjustment process is performed, for example, during the introduction of the substrate processing apparatus 1 or during maintenance of the substrate processing apparatus 1.

[0086] (Input Steps)

[0087] In the adjustment of processing conditions for PEB treatment, such as Figure 11 As shown, firstly, a wafer W for adjustment (hereinafter referred to as "adjustment wafer W") is fed in (step S1). Specifically, during this adjustment process, the operator places the cassette C containing the adjustment wafer W onto the cassette stage 12, and then removes the adjustment wafer W from the cassette C and transports it to the resist coating unit for the next step. Furthermore, the adjustment wafer W is a bare wafer.

[0088] (Resist film formation steps)

[0089] Next, a resist film is formed on the conditioning wafer W (step S2). Specifically, in the resist coating unit 31, a resist film is formed on the conditioning wafer W under predetermined coating conditions.

[0090] (PAB processing steps)

[0091] Next, the conditioning wafer W is subjected to PAB processing (step S3). Specifically, the conditioning wafer W with a resist film formed is transported to the heat treatment unit 40 for PAB processing and PAB processing is performed under predetermined PAB processing conditions.

[0092] (Pre-exposure shooting steps)

[0093] Next, a resist film is formed, and the adjustment wafer W is photographed before the uniform exposure process described later (step S4). Specifically, the adjustment wafer W, which has undergone PAB treatment, is transported to the defect inspection unit 61, and its surface is photographed by the imaging unit 210. Then, as... Figure 12 As shown, the chip W in the captured image F1 is divided into, for example, 437 regions. In each region, the average brightness values ​​of R (red), G (green), and B (blue) are calculated. Then, for each region (pixel), a table is created that maps the coordinates of that region to the average brightness values ​​of R, G, and B. Then, based on the generated table, the captured image (hereinafter referred to as the "pre-exposure captured image") I1 is obtained for R, G, and B respectively.

[0094] (Uniform Exposure Step)

[0095] After acquiring the captured image, the adjustment wafer W undergoes uniform exposure processing (step S5). Specifically, the adjustment wafer W captured in the pre-exposure imaging step of step S4 is transported to the exposure apparatus 4 for uniform exposure processing, where each area of ​​the wafer surface is exposed with a certain exposure amount. In the exposure apparatus 4, during uniform exposure processing, for example, in each exposure area, no photomask is used, and exposure is performed with the same exposure intensity and the same exposure time. Furthermore, the exposure amount of each area of ​​the wafer surface during uniform exposure processing is less than the exposure amount during actual processing, i.e., during the mass production of the resist pattern; specifically, it is set to half of the exposure amount during actual processing.

[0096] (PEB processing steps)

[0097] After the uniform exposure step, the adjustment wafer W is subjected to PEB processing (step S6). Specifically, the adjustment wafer W that has undergone uniform exposure processing is transported to the heat treatment unit 40 for PEB processing, which is the adjustment object as the processing condition, and PEB processing is performed under the currently set PEB processing conditions.

[0098] (Post-PEB shooting steps)

[0099] Next, the adjustment wafer W is photographed again (step S7). Specifically, the adjustment wafer W, which has undergone PEB processing and is not developed, is transported to the defect inspection unit 61, and its surface is photographed by the imaging unit 210. At this time, since it is not developed, the latent image formed by the resist film on the wafer W is not the resist pattern but is photographed by the imaging unit 210. Then, based on the imaging result F2, the photographed images (hereinafter referred to as "PEB post-images") I2 are acquired for R, G, and B respectively.

[0100] (Steps for predicting temperature distribution)

[0101] Next, the control unit 6 infers the in-plane temperature distribution of the adjustment wafer W during PEB processing based on the imaging results from the pre-exposure imaging step and the imaging results from the post-PEB imaging step (step S8). Specifically, the control unit 6 infers the in-plane temperature distribution of the adjustment wafer W during PEB processing based on the color information of the pre-exposure image I1 and the color information of the post-PEB image I2 obtained in the pre-exposure imaging step. The color information is the brightness information of a specific wavelength (color).

[0102] More specifically, the control unit 6 first performs shading compensation Sh on the pre-exposure image I1 (R, G, and B) acquired in the pre-exposure shooting step and the post-PEB image I2 (R, G, and B) acquired in the post-PEB shooting step. By performing shading compensation Sh, uneven brightness caused by shooting conditions (sensitivity of the shooting element, optical system, moving speed of the stage 200, etc.) can be removed.

[0103] Next, the control unit 6 calculates the difference Δ in brightness values ​​for each R, G, and B, and for each pixel in the captured image, using the pre-exposure captured image I1' and the post-PEB captured image I2' with shading compensation.

[0104] Then, the control unit 6 obtains the in-plane temperature distribution Pr of the adjustment wafer W during PEB processing based on the calibration curve Lr, which shows the relationship between the above-mentioned difference Δr with respect to R and temperature, and the above-mentioned difference Δr with respect to R calculated for each pixel.

[0105] In addition, the control unit 6 obtains the in-plane temperature distribution Pg of the adjustment wafer W during PEB processing based on the calibration curve Lg, which shows the relationship between the difference Δg of G and temperature, and the difference Δg of G calculated for each pixel.

[0106] Furthermore, the control unit 6 obtains the in-plane temperature distribution Pb of the adjustment wafer W during PEB processing based on the calibration curve Lb, which represents the relationship between the difference Δb with respect to B and temperature, and the difference Δb with respect to B calculated for each pixel.

[0107] In addition, the aforementioned calibration curves Lr, Lg, and Lb were obtained in advance. The method for obtaining them will be described later.

[0108] Furthermore, the control unit 6 selects one of the three in-plane temperature distributions Pr, Pg, and Pb obtained during PEB processing of the adjustment wafer W. For example, it selects the in-plane temperature distribution of the adjustment wafer W during PEB processing obtained based on an image taken with a wavelength corresponding to the thickness of the resist film. More specifically, when the resist film is thicker, the in-plane temperature distribution Pr obtained based on an image taken with a longer wavelength R is selected, and when the resist film is thinner, the in-plane temperature distribution Pb obtained based on an image taken with a shorter wavelength B is selected. That is, the control unit 6 estimates (predicts) the in-plane temperature distribution of the adjustment wafer W during PEB processing based on an image taken with a wavelength corresponding to the thickness of the resist film. In addition, when selecting the in-plane temperature distribution obtained based on an image taken with a wavelength corresponding to the thickness of the resist film as described above, it is also possible to omit obtaining the in-plane temperature distribution based on images taken with other wavelengths.

[0109] (Heat treatment conditions determine the steps)

[0110] After the temperature distribution prediction step, the control unit 6 determines the processing conditions for PEB processing based on the prediction results of the in-plane temperature distribution of the adjustment wafer W during PEB processing (step S9).

[0111] Specifically, the control unit 6 determines the processing conditions for PEB processing based on the in-plane temperature distribution of the adjustment wafer W selected during the temperature distribution prediction step. For example, the control unit 6 determines the set temperature of each of the channels R1 to R5 of the hot plate 142 based on the following formula (1). More specifically, it determines the offset from the reference temperature determined according to each type of resist film for each channel of the hot plate 142.

[0112] [Formula 1]

[0113] O=A·T…(1)

[0114]

[0115]

[0116]

[0117] In Equation (1), O is a matrix representing the offset of each channel of the hot plate 142, T is a matrix representing the in-plane temperature distribution of the adjustment wafer W during PEB processing, and A is a transformation matrix.

[0118] By using the above formula (1), the processing conditions for PEB processing are determined in such a way that the offset of the channel corresponding to the region where the temperature during PEB processing is lower than the reference temperature is increased, and the offset of the channel corresponding to the region where the temperature during PEB processing is higher than the reference temperature is decreased.

[0119] The determined processing conditions for PEB processing are stored in the storage unit (not shown) and used in subsequent actual processing, etc., of PEB processing.

[0120] (Excluding steps)

[0121] In addition, a process is performed to remove the resist film formed on the adjustment wafer W (step S10). Specifically, the adjustment wafer W photographed in the PEB post-photographing step is transported to the resist coating unit 31, which serves as a removal unit. Diluent is supplied to the adjustment wafer W from a discharge nozzle (not shown), and the resist film on the adjustment wafer W is peeled off. Alternatively, the unit for removal processing may be provided separately from the resist coating unit 31, etc.

[0122] (After removing the shooting steps)

[0123] Next, the adjustment wafer W is photographed again (step S11). Specifically, the adjustment wafer W, with the resist film removed, is transported to the defect inspection unit 61, and its surface is photographed by the imaging unit 210 to obtain a substrate image showing the state of the wafer surface.

[0124] (Reusing the judgment step)

[0125] Next, the control unit 6 determines whether the adjustment wafer W can be reused based on the substrate image obtained in the removal and imaging step (step S12). Specifically, the control unit 6 compares the substrate image of the adjustment wafer W obtained in the removal and imaging step with the substrate image of the bare wafer in an unprocessed state obtained in advance, and determines whether the adjustment wafer W can be reused based on the comparison result.

[0126] (Notification Steps)

[0127] If the chip cannot be reused (step S12, "No"), the control unit 6 reports a message indicating that it cannot be reused (step S13). Specifically, the control unit 6, for example, causes the display unit (not shown) to display a warning indicating that the adjustment chip W cannot be reused.

[0128] (Send-out steps)

[0129] If the wafer can be reused (step S12: "Yes"), or after the reporting step in step S11, the control unit 6 sends out the adjustment wafer W (step S14). Specifically, the adjustment wafer W is returned to its original cassette C on the cassette stage 12 by the wafer transport unit 21. Alternatively, if the wafer cannot be reused, it can be transported separately to the waste cassette C placed on the cassette stage 12.

[0130] Thus, the adjustment of the processing conditions for PEB processing is completed.

[0131] In the actual processing after the adjustment of the processing conditions for the above-mentioned PEB processing is completed, PEB processing is performed under the processing conditions determined by the adjustment process.

[0132] Next, use Figure 13 The methods for obtaining the calibration curves Lr, Lg, and Lb described above are explained. Figure 13 This is a flowchart illustrating the method for obtaining calibration curves Lr, Lg, and Lb.

[0133] When obtaining calibration curves Lr, Lg, and Lb, for example, firstly, the unit in the multiple heat treatment units 40 for PEB processing used to obtain calibration curves is determined based on user input, etc. (step S21).

[0134] (Input Steps)

[0135] Next, a wafer W (hereinafter referred to as "calibration curve acquisition wafer W") for obtaining a calibration curve is fed in, similar to step S1. The calibration curve acquisition wafer W is a bare wafer.

[0136] (Resist film formation steps)

[0137] Next, similar to step S2, a resist film is formed on the wafer W used to obtain the calibration curve.

[0138] (PAB processing steps)

[0139] Then, similar to step S3, the wafer W used to obtain the calibration curve is subjected to PAB processing.

[0140] (Pre-exposure shooting steps)

[0141] Next, the calibration curve is obtained by taking an image of the chip W in the same manner as in step S4.

[0142] (Uniform Exposure Step)

[0143] Next, similar to step S5, the wafer W used to obtain the calibration curve is subjected to uniform exposure processing.

[0144] (PEB processing steps)

[0145] Following the uniform exposure step, similar to step S6, the wafer W used to obtain the calibration curve undergoes PEB processing. Furthermore, the PEB processing is performed in the heat treatment unit 40 determined in step S21.

[0146] (Post-PEB shooting steps)

[0147] Next, the calibration curve is obtained by photographing the chip W in the same manner as in step S7.

[0148] (Send-out steps)

[0149] Then, similar to step S14, the calibration curve acquisition chip W is sent out.

[0150] For each of the N calibration curve acquisition wafers W, the steps from the input step in step S1 to the output step in step S14 described above are performed. However, the temperature of the hot plate 142 in the PEB processing step is different for each calibration curve acquisition wafer W. In addition, the temperature of each of the channels R1 to R5 of the hot plate 142 is common.

[0151] (Calibration curve calculation steps)

[0152] Then, based on the images of wafer W obtained in the pre-exposure imaging step and the post-PEB imaging step, calibration curves Lr, Lg, and Lb are calculated. Specifically, in the case of calibration curve Lr, firstly, the average R brightness within the wafer surface in the pre-exposure imaging step image is set as the grayscale value Ir1, and the average R brightness within the wafer surface in the post-PEB imaging step image is set as the grayscale value Ir2. For each temperature of the hot plate 142 in the PEB processing step, the grayscale value change ΔIr (=Ir2-Ir1) is calculated. Then, the explanatory variable is set as the grayscale value change, and the target variable is set as the temperature of the hot plate 142 in the PEB processing step. An approximate curve of the temperature of the hot plate 142 relative to the grayscale value change is obtained, and this is used as calibration curve Lr.

[0153] The calibration curves Lg and Lb are obtained in the same way as the calibration curve Lr.

[0154] As described above, the adjustment process for PEB processing conditions in this embodiment includes: a pre-exposure imaging step, which images the adjustment wafer W before uniform exposure processing to which a resist film is formed; a PEB processing step, which performs PEB processing on the adjustment wafer W after uniform exposure processing following the pre-exposure imaging step; a post-PEB imaging step, which images the adjustment wafer W after PEB processing; a temperature distribution estimation step, which estimates the in-plane temperature distribution of the adjustment wafer during PEB processing based on the imaging results in the pre-exposure imaging step and the imaging results in the post-PEB imaging step; and a PEB processing condition determination step, which determines the processing conditions for PEB processing based on the estimated in-plane temperature distribution of the adjustment wafer. Therefore, in this embodiment, instead of basing the in-plane temperature distribution on the linewidth of the resist pattern, PEB processing is actually performed under currently set processing conditions, and the processing conditions for PEB processing are determined based on the in-plane temperature distribution of the adjustment wafer W estimated from the imaging results after processing. Therefore, according to this embodiment, PEB processing can be performed in such a way that the processing result of PEB processing (i.e., the temperature of the wafer W) becomes uniform within the wafer plane. Therefore, it is possible to form resist patterns with higher in-plane uniformity and linewidth.

[0155] Furthermore, according to this embodiment, for each heat treatment unit 40 for PEB processing, the temperature of the wafer W can be made uniform within the wafer surface at a reference temperature set according to each type of resist film. Therefore, temperature deviations of the wafer W between the heat treatment units 40 for PEB processing can be suppressed.

[0156] Furthermore, in this embodiment, as described above, the control unit 6 selects the in-plane temperature distribution of the adjustment wafer W during PEB processing, obtained based on an image captured at a wavelength corresponding to the thickness of the resist film, according to the three in-plane temperature distributions Pr, Pg, and Pb acquired during PEB processing. That is, the control unit 6 estimates the in-plane temperature distribution of the adjustment wafer W during PEB processing based on an image captured at one wavelength corresponding to the thickness of the resist film. This allows for a more accurate prediction of the in-plane temperature distribution during PEB processing, resulting in a more uniform PEB processing result within the wafer plane.

[0157] Furthermore, when the control unit 6 selects one of the in-plane temperature distributions Pr, Pg, and Pb of the adjustment wafer W during the processing of the three PEBs, it can also make the selection as follows. For example, a temperature sensor can be pre-installed on the hot plate 142, and the in-plane temperature distribution that is closest to the measurement result of the temperature sensor and the estimated temperature of the pixel corresponding to the placement position of the temperature sensor can be selected.

[0158] In addition, the control unit 6 can also use the following formula (2) to infer the in-plane temperature distribution of the adjustment wafer W during one PEB processing based on all the captured images of R, G, and B.

[0159] [Equation 2]

[0160] t = S i ·L+C…(2)

[0161]

[0162] S i =[S iR S iG S iB ]

[0163] t = Estimated temperature

[0164] J = Brightness value of the image taken before exposure

[0165] The brightness value of the image after K=PEB.

[0166] L = Change in brightness value

[0167] S i =Temperature sensitivity matrix

[0168] L = K - JC = constant

[0169] When the temperature sensitivity matrix is ​​film thickness dependent, the control unit 6 can also use the following equation (3) to predict the in-plane temperature distribution of the adjustment wafer W during PEB processing.

[0170] [Formula 3]

[0171] t=(S i ·(S if ·f))·L+C…(3)

[0172]

[0173] f = S f ·J+C

[0174] S f =[S fR S fG S fB ]

[0175] f = film thickness

[0176] S f =Film thickness sensitivity matrix

[0177] S if =Temperature sensitivity film thickness sensitivity matrix

[0178] Furthermore, in this embodiment, the exposure amount of each region on the wafer surface during uniform exposure processing is less than the actual exposure amount during processing, for example, by half. Therefore, during the adjustment of the processing conditions for PEB processing, the change in the thickness of the resist film before and after PEB processing increases due to the different PEB processing results. Consequently, the change in brightness in the captured images before and after PEB processing increases due to the different PEB processing results. That is, even if the difference in PEB processing results is small, the difference in brightness between the image captured before exposure and the image captured after PEB processing increases. Therefore, the in-plane temperature distribution of the wafer W used for adjustment during PEB processing can be predicted with high accuracy based on the images captured before and after PEB processing. Additionally, half the actual exposure amount during processing corresponds to the exposure amount irradiating the edge portion of the resist pattern.

[0179] Furthermore, in this embodiment, based on the substrate image obtained in the post-removal imaging step, it is determined whether the adjustment wafer W, after the resist film has been removed, can be reused. Therefore, the consumption of the adjustment wafer W can be suppressed without compromising the adjustment accuracy of the processing conditions.

[0180] Furthermore, in this embodiment, a bare wafer is used as the adjustment wafer W. Therefore, the processing conditions for PEB processing can be appropriately determined.

[0181] (Second Implementation)

[0182] Figure 14 This is a flowchart illustrating the adjustment process of the processing conditions in the second embodiment.

[0183] In the first embodiment, the processing conditions for PEB processing are adjusted; however, in this embodiment, the processing conditions for development processing are adjusted. The adjustment of the development processing conditions is performed, for example, immediately after the adjustment of the PEB processing conditions. Furthermore, as described above, the adjustment of the PEB processing conditions is performed when the substrate is introduced into the substrate processing apparatus 1, etc., so the adjustment of the development processing conditions is also performed at the same time. However, it is also possible to adjust the development processing conditions without adjusting the PEB processing conditions.

[0184] (Input Steps)

[0185] In the adjustment process of the development process, firstly, the adjustment wafer W is fed in in the same way as in the aforementioned step S1.

[0186] (Resist film formation steps)

[0187] Next, a resist film is formed on the adjustment wafer W in the same manner as in step S2 described above.

[0188] (PAB processing steps)

[0189] Then, the adjustment chip W is subjected to PAB processing in the same way as in step S3 (step S3).

[0190] (Uniform Exposure Step)

[0191] Next, the wafer W for adjustment is subjected to uniform exposure processing in the same manner as in step S5 above. In the adjustment processing of the development processing conditions, the exposure amount of each area on the wafer surface in the uniform exposure processing is also less than the exposure amount in the actual processing, for example, set to 1 / 2.

[0192] (PEB processing steps)

[0193] After the uniform exposure step, the adjustment wafer W is subjected to PEB processing in the same manner as in step S6 described above. However, if the processing conditions for PEB processing are adjusted, then PEB processing is performed under the adjusted PEB processing conditions.

[0194] (Developing process)

[0195] Then, the adjustment wafer W is developed (step S31). Specifically, the adjustment wafer W, which has undergone PEB processing, is transported to the development processing unit 30 of the adjustment object under the processing conditions, and developed under the currently set development processing conditions.

[0196] (Post-development shooting steps)

[0197] Next, the adjustment wafer W is photographed again (step S32). Specifically, the adjustment wafer W, which has undergone development processing, is transported to the defect inspection unit 61, and its surface is photographed by the imaging unit 210 to obtain an image (hereinafter referred to as "post-development image") I3.

[0198] (Steps for predicting the remaining film thickness distribution)

[0199] Next, based on the imaging results in the post-development imaging step, the control unit 6 estimates the in-plane distribution of the thickness of the resist film after development treatment (hereinafter referred to as "remaining film thickness of the resist film") in the adjustment wafer W (step S33).

[0200] Specifically, the control unit 6 calculates, and thus infers, the in-plane distribution of the remaining film thickness of the resist film on the adjustment wafer W based on the color information of the image I3 captured after development of B (blue).

[0201] More specifically, the control unit 6 calculates the remaining film thickness of the resist film for each pixel in the developed image I3 about B, based on the brightness and the pre-obtained calibration curve Ldev, and obtains the in-plane distribution of the remaining film thickness.

[0202] Additionally, the calibration curve Ldev represents the relationship between the brightness in the developed image I3 and the remaining thickness of the resist film. The method for obtaining the calibration curve Ldev will be described later.

[0203] Here, the in-plane distribution of the remaining film thickness is calculated based on the image taken about B, but it can also be calculated based on images taken about G and R. Alternatively, similar to the estimation of the in-plane temperature distribution of the adjustment wafer W during PEB processing, it can be estimated based on images taken at wavelengths corresponding to the thickness of the resist film.

[0204] (Developing conditions determine the steps)

[0205] After the residual film thickness distribution estimation step, the control unit 6 determines the processing conditions for the development process based on the estimation results of the in-plane distribution of the residual film thickness of the resist film (step S34).

[0206] Specifically, the control unit 6 determines and corrects the supply time of the developer solution, which is a processing condition for the development process, based on, for example, the in-plane distribution of the remaining film thickness of the resist film on the adjustment wafer W.

[0207] More specifically, the control unit 6 determines the processing conditions for the developing process, such that in the conditioning wafer W, when the remaining thickness of the resist film is close to the target amount in the center of the wafer and greater than the target amount in the outer periphery of the wafer, the supply of developer to the outer periphery of the wafer is increased. The length Δt of the increased supply time of developer to the outer periphery of the wafer is calculated, for example, from the correction curve Lamd, which represents the relationship between the supply time of developer and the remaining film thickness.

[0208] In addition, the aforementioned correction curve Lamd is obtained in advance. The method for obtaining it will be described later.

[0209] In this way, by setting the length Δt of the extended supply time of the developer to the outer periphery of the wafer, the remaining film thickness of the resist film on the outer periphery of the wafer can also be a suitable value close to the target amount.

[0210] In addition, the calculated length Δt of the increased supply time of the developer to the outer periphery of the wafer, i.e. the determined development processing conditions, is stored in the storage unit (not shown) and used in subsequent actual processing and other development processes.

[0211] In addition, the same steps as those described above (S10 to S14) are performed, thereby completing the adjustment of the processing conditions for the developing process.

[0212] Next, use Figure 15 The methods for obtaining the aforementioned calibration curve Ldev and correction curve Lamd are explained. Figure 15 This is a flowchart illustrating the method for obtaining the calibration curve Ldev and the correction curve Lamd.

[0213] When acquiring the calibration curve Ldev, firstly, the unit in the multiple development processing units 30 for acquiring the calibration curve and the correction curve is determined based on user input, etc. (step S41).

[0214] (Input Steps)

[0215] Next, the wafer W used to obtain the calibration curve and correction curve (hereinafter referred to as "calibration curve acquisition wafer W") is fed in in the same manner as in step S1. In addition, the calibration curve acquisition wafer W is also a bare wafer.

[0216] (Resist film formation steps)

[0217] Next, a resist film is formed on the wafer W for obtaining the calibration curve, in the same manner as in step S2.

[0218] (PAB processing steps)

[0219] Then, the wafer W used to obtain the calibration curve is subjected to PAB processing in the same way as in step S3.

[0220] (Uniform Exposure Step)

[0221] Next, the wafer W used to obtain the calibration curve is subjected to uniform exposure processing in the same manner as in step S5.

[0222] (PEB processing steps)

[0223] After the uniform exposure step, the wafer W used to obtain the calibration curve is subjected to PEB processing in the same manner as in step S6.

[0224] (Developing process)

[0225] Subsequently, the wafer W used to obtain the calibration curve is subjected to development processing in the same manner as in step S31. In addition, the development processing is carried out in the development processing unit 30 determined in step S41, and during the spin coating of the developer, the developer is supplied only from the coating nozzle 122 to the center of the wafer.

[0226] (Post-development shooting steps)

[0227] Next, the calibration curve is obtained by taking an image of the chip W in the same manner as in step S32. Thus, at least an image of B is obtained.

[0228] (Send-out steps)

[0229] Then, in the same manner as in step S14, the wafer W for obtaining the calibration curve is sent out.

[0230] (Steps for measuring remaining film thickness)

[0231] Then, the remaining film thickness of the resist film on the wafer W is obtained by acquiring the calibration curve (step S42). Specifically, for example, the wafer W for acquiring the calibration curve after PEB processing is transported to an external film thickness measuring device (not shown) to measure the remaining film thickness of the resist film at the center of the wafer. Alternatively, the film thickness measuring device can be pre-installed in the substrate processing apparatus 1, and the remaining film thickness can be measured using this film thickness measuring device.

[0232] (Calculation steps for calibration curve and correction curve)

[0233] Then, based on the image captured by the wafer W used for obtaining multiple calibration curves during the post-development imaging step, the calibration curve Lpeb and the correction curve Lamd are calculated (step S43). Specifically, in the case of calibration curve Lpeb, the explanatory variable is set to the B brightness in the image captured during the post-development imaging step (signature plate image), and the target variable is set to the remaining film thickness of the resist film obtained during the remaining film thickness measurement step. An approximate curve of the change in the remaining film thickness relative to the B brightness value is obtained and used as calibration curve Lpeb. In the case of correction curve Lamd, the explanatory variable is set to the developer supply time during the development step, and the target variable is set to the remaining film thickness of the resist film obtained during the remaining film thickness measurement step. An approximate curve of the remaining film thickness of the resist film relative to the developer supply time is obtained and used as correction curve Lamd.

[0234] As described above, in this embodiment, the development process is actually performed under the currently set processing conditions, and the processing conditions for the development process are determined based on the in-plane distribution of the resist film thickness after development, which is inferred from the processing results. Therefore, according to this embodiment, the development process can be performed in a manner that makes the processing results uniform within the wafer plane. Thus, a resist pattern with higher in-plane uniformity in linewidth can be formed.

[0235] Furthermore, in this embodiment, the exposure amount of each region on the wafer surface during uniform exposure processing is less than the actual exposure amount during processing, for example, by half. Therefore, during the adjustment of the development processing conditions, the thickness of the resist film after development varies significantly due to differences in the development processing results. As a result, the brightness in the image after development varies considerably depending on the development processing results. That is, even if the difference in the development processing results is small, the brightness in the image after development will vary greatly. Therefore, based on the image after development, the in-plane distribution of the resist film thickness after development processing can be predicted with high accuracy.

[0236] (Third Implementation)

[0237] Figure 16 This is a front view showing an outline of the internal structure of the substrate processing apparatus 1a according to the third embodiment.

[0238] In the first embodiment, the uniform exposure process is performed by an external exposure device 4 adjacent to the substrate processing device 1, which is used for actual exposure during processing. In contrast, in this embodiment, as... Figure 16 As shown, the substrate processing apparatus 1a has an exposure unit 62 that is independent of the exposure apparatus 4. The exposure unit 62 performs uniform exposure processing on the adjustment wafer W.

[0239] According to this structure, the adjustment of processing conditions can be completed within the substrate processing apparatus 1 without the use of an external exposure device.

[0240] In addition, the exposure unit 62 is provided, for example, on the defect inspection unit 61 in the fourth block G4.

[0241] (Fourth Implementation)

[0242] Figure 17 This is a longitudinal cross-sectional view showing the schematic structure of the heat treatment unit 40a of the substrate processing apparatus of the fourth embodiment.

[0243] In this embodiment, the heat treatment unit 40a has a heater 140b provided on the cover 140 as a temperature regulating mechanism for regulating the temperature of the cover 140.

[0244] In the aforementioned first embodiment, the conditions of the hot plate 142 during actual PEB processing, such as adjusting the offset of each channel of the hot plate 142, were adjusted. However, if only the conditions of the hot plate 142 are adjusted, the overall wafer temperature during the PEB processing may sometimes be lower than the required temperature. In these cases, as in this embodiment, by providing a heater 140b that adjusts the temperature of the cover 140, the temperature of the wafer W during actual PEB processing can be made to the required temperature. This is because the wafer W is affected by the radiant heat of the cover 140.

[0245] Furthermore, unlike this embodiment, if the heater 140b is not provided, the temperature of the cover 140 during PEB processing will differ, for example, during the adjustment process of the hot plate conditions in PEB processing and during actual processing. By providing the heater 140b, the temperature of the cover 140 during PEB processing can be made the same during the adjustment process and during actual processing. As described above, the wafer W is affected by the radiant heat of the cover 140. Therefore, compared to the case where the temperature of the cover 140 during PEB processing differs between the adjustment process and the actual processing, the in-plane uniformity of the PEB processing result during the adjusted actual processing can be improved.

[0246] (A variation of the first embodiment)

[0247] In the first embodiment, in the actual processing after the adjustment of the processing conditions for PEB processing is completed, PEB processing is performed based on the processing conditions determined by the adjustment process, that is, based on the offset of each channel of the hot plate 142 determined by the above-mentioned adjustment process.

[0248] On the other hand, in this modified example, during PEB processing, the offset determined by the above-described adjustment process is corrected based on the temperature measurement result of the cover 140 of the heat treatment unit 40 obtained by the temperature sensor 143. This is because the wafer W is affected by the radiant heat of the cover 140 as described above.

[0249] (A variation of the first embodiment)

[0250] In the first embodiment, the adjustment of the processing conditions for PEB processing is performed when the substrate processing apparatus 1 is introduced or during maintenance of the substrate processing apparatus 1. The timing of the adjustment of the processing conditions for PEB processing is not limited to these. For example, the control unit 6 may also measure the thickness of the resist film formed during actual processing and start the adjustment of the processing conditions for PEB processing based on the measurement result. Specifically, the adjustment of the processing conditions for PEB processing may also begin when the measured deviation of the resist film thickness within the wafer surface, or when the average value of the film thickness within the wafer surface exceeds a threshold.

[0251] It should be noted that the thickness of the resist film can be measured as follows. That is, the wafer W with the resist film formed after PEB treatment during actual processing can be photographed using the imaging unit 210 of the defect inspection unit 61, and the thickness of the resist film can be measured / estimated based on the image obtained from the photograph.

[0252] (Modifications of the first to fourth embodiments)

[0253] The timing for adjusting the processing conditions of PEB processing and development processing can also be determined as follows. For example, the control unit 6 can estimate the linewidth of the resist pattern formed during actual processing, and start adjusting the processing conditions of PEB processing and development processing based on the estimated result. Specifically, the adjustment of processing conditions can also be started when the deviation of the estimated linewidth in the wafer plane or the average linewidth in the wafer plane exceeds a threshold.

[0254] Furthermore, the linewidth of the resist pattern can be estimated as follows. That is, the wafer W with the resist pattern formed after the development process during actual processing can be photographed using the imaging unit 210 of the defect inspection unit 61, and the linewidth of the resist pattern can be estimated based on the photographed image obtained from the photographing result.

[0255] In addition, when adjusting the processing conditions, the operator can place the adjustment chip W on the cassette stage 12 while it is stored in the cassette C, but it can also be stored in the container in the substrate processing apparatus 1.

[0256] (Fifth Implementation)

[0257] Figure 18 This is a front view showing an outline of the internal structure of the substrate processing apparatus 1b according to the fifth embodiment.

[0258] As shown in the figure, the substrate processing apparatus 1b has an inspection unit 63. Unlike the defect inspection unit 61, which is a unit that takes pictures of the entire surface of the wafer W for inspection, the inspection unit 63 only takes pictures of the periphery of the wafer W for inspection.

[0259] In this embodiment, the control unit 6 performs the adjustment processing of the peripheral exposure processing conditions by the peripheral exposure unit 41. Furthermore, the timing of the execution of the peripheral exposure processing condition adjustment processing is determined as follows: After the actual peripheral exposure processing, the peripheral portion of the wafer W is photographed using the imaging unit (not shown) of the inspection unit 63. Based on the photographing result, the adjustment processing of the peripheral exposure processing conditions begins. For example, based on the photographing result, the peripheral exposure width obtained from the peripheral exposure processing is estimated. If the estimated peripheral exposure width is abnormal, the adjustment processing of the peripheral exposure processing conditions begins.

[0260] The adjustment of processing conditions based on the imaging results of the peripheral portion of wafer W is not limited to the adjustment of processing conditions for peripheral exposure processing, but can also be the adjustment of processing conditions for other processing of the peripheral portion of the wafer. Other processing of the peripheral portion of the wafer includes, for example, EBR processing (processing to remove the film from the outer periphery of wafer W) and edge coating processing (processing to cover only the peripheral portion of wafer W). In adjusting the processing conditions for peripheral exposure processing, EBR processing, and edge coating processing, for example, the origin position of each process may be adjusted.

[0261] It should be understood that the embodiments of the present invention are illustrative in all respects and not restrictive. The above embodiments may be omitted, substituted, or modified in various ways without departing from the spirit of the present invention.

[0262] Furthermore, the following structures also fall within the technical scope of this invention.

[0263] (1) A substrate processing apparatus for processing a substrate, comprising:

[0264] A heat treatment section for heat treatment of the substrate;

[0265] The filming department for shooting base films; and

[0266] Control Department

[0267] The control unit is configured to perform adjustment processing for adjusting the conditions for processing the substrate.

[0268] The adjustment process includes:

[0269] The pre-exposure shooting step involves controlling the shooting unit to photograph an unexposed adjustment substrate with a resist film formed on it.

[0270] The heat treatment step involves controlling the heat treatment unit after the pre-exposure imaging step to perform the heat treatment on the adjustment substrate that has undergone uniform exposure treatment by exposing each area of ​​the substrate surface to a certain exposure amount.

[0271] After the heat treatment step, the imaging unit is controlled to capture images of the adjustment substrate.

[0272] The temperature distribution estimation step, based on the imaging results of the pre-exposure imaging step and the imaging results of the post-heating imaging step, estimates the in-plane temperature distribution of the adjustment substrate during the heat treatment; and

[0273] The heat treatment condition determination step determines the heat treatment conditions based on the predicted in-plane temperature distribution of the substrate for adjustment.

[0274] According to (1) above, the actual heat treatment is performed, and the heat treatment conditions are determined based on the in-plane temperature distribution of the substrate, which is inferred from the imaging results after the treatment. Therefore, according to this embodiment, heat treatment can be performed in such a way that the temperature of the substrate becomes uniform in the substrate plane as a result of the heat treatment. Therefore, it is possible to form a resist pattern with higher in-plane uniformity in linewidth.

[0275] (2) The substrate processing apparatus described in (1) above has an exposure unit that is different from the external exposure device that performs the exposure processing during actual processing, and is used to perform the uniform exposure processing.

[0276] According to (2) above, the adjustment of processing conditions can be completed within the substrate processing apparatus without the use of an external exposure device.

[0277] (3) The substrate processing apparatus as described in (1) above, wherein the uniform exposure processing is performed by an external exposure apparatus that performs the exposure processing during actual processing.

[0278] (4) The substrate processing apparatus described in any of (1) to (3) above, wherein the certain exposure amount is less than the exposure amount during actual processing.

[0279] (5) The substrate processing apparatus as described in any one of (1) to (4) above, wherein the pre-exposure imaging step and the post-heating imaging step respectively acquire images at each wavelength of the plurality of wavelengths.

[0280] The temperature distribution estimation step is based on the captured image with respect to the wavelength corresponding to the thickness of the resist film, to estimate the in-plane temperature distribution of the conditioning substrate during the heat treatment.

[0281] Based on the above (5), the in-plane temperature distribution during heat treatment can be predicted more accurately, and the heat treatment result can be made more uniform in the substrate plane.

[0282] (6) The substrate processing apparatus described in any one of (1) to (5) above, which includes a developing unit for developing a substrate.

[0283] The adjustment process includes:

[0284] The developing process step involves controlling the developing unit to perform the developing process on the adjustment substrate after the heating and imaging step.

[0285] The post-development imaging step involves controlling the imaging unit to capture images of the adjustment substrate after the development process.

[0286] The film thickness distribution estimation step involves estimating the in-plane distribution of the resist film thickness after development treatment in the adjustment substrate based on the imaging results of the heat treatment step; and

[0287] The developing process condition determination step determines the developing process conditions based on the in-plane distribution of the film thickness.

[0288] According to (6), the development process can be performed in such a way that the result of the development process becomes uniform within the substrate surface. As a result, a resist pattern with higher in-plane uniformity in linewidth can be formed.

[0289] (7) The substrate processing apparatus as described in any one of (1) to (6) above, comprising a removal section for removing the resist film from the substrate.

[0290] The adjustment process includes:

[0291] In the removal step, the removal unit is controlled to remove the resist film formed on the conditioning substrate;

[0292] After the removal step, the imaging unit is controlled to capture images of the adjustment substrate; and

[0293] The judgment step, based on the shooting results of the post-removal shooting step, determines whether the adjustment substrate should be reused.

[0294] According to (7) above, the consumption of the adjustment substrate can be suppressed without compromising the adjustment accuracy of the processing conditions.

[0295] (8) A substrate processing apparatus as described in any one of (1) to (7), wherein the control unit is configured to start the adjustment process based on a prediction of the linewidth of the resist pattern formed on the substrate during actual processing.

[0296] (9) The substrate processing apparatus as described in any one of (1) to (8), wherein the control unit is configured to start adjusting the processing conditions for processing the peripheral portion of the substrate based on the imaging results of the peripheral portion of the substrate during actual processing.

[0297] (10) The substrate processing apparatus as described in any one of (1) to (9) above, wherein the heat treatment unit comprises:

[0298] A hot plate for mounting a substrate;

[0299] A cover covering the substrate on the hot plate; and

[0300] A temperature regulating mechanism for adjusting the temperature of the cover.

[0301] (11) A method for adjusting processing conditions for substrate processing, comprising:

[0302] Pre-exposure photographing procedure for photographing an unexposed conditioning substrate with a resist film formed;

[0303] The uniform exposure step involves subjecting the adjustment substrate to uniform exposure processing after the pre-exposure shooting step, exposing each area of ​​the substrate surface to a certain exposure amount.

[0304] A heat treatment step following the uniform exposure step, in which the adjustment substrate is subjected to heat treatment;

[0305] A post-heating photographing step is performed on the substrate for adjustment after the heat treatment step.

[0306] The temperature distribution estimation step, based on the imaging results of the pre-exposure imaging step and the imaging results of the post-heating imaging step, estimates the in-plane temperature distribution of the adjustment substrate during the heat treatment; and

[0307] The heat treatment condition determination step determines the treatment conditions during heat treatment based on the predicted in-plane temperature distribution of the substrate for adjustment.

[0308] Explanation of reference numerals in the attached figures

[0309] 1, 1a, 1b Substrate processing apparatus

[0310] 6. Control Department

[0311] 40, 40a heat treatment unit

[0312] 210 Photography Department

[0313] F1 shooting results

[0314] F2 shooting results

[0315] W chip.

Claims

1. A substrate processing apparatus for processing substrates, characterized in that, include: A heat treatment section for heat treatment of the substrate; The filming department for shooting base films; and Control Department The control unit is configured to perform adjustment processing for adjusting the conditions for processing the substrate. The adjustment process includes: The pre-exposure shooting step involves controlling the shooting unit to photograph an unexposed adjustment substrate with a resist film formed on it. The heat treatment step involves controlling the heat treatment unit after the pre-exposure imaging step to perform the heat treatment on the adjustment substrate that has undergone uniform exposure treatment by exposing each area of ​​the substrate surface to a certain exposure amount. After the heat treatment step, the imaging unit is controlled to capture images of the adjustment substrate. The temperature distribution estimation step, based on the imaging results of the pre-exposure imaging step and the imaging results of the post-heating imaging step, calculates the brightness information difference of the imaging results, and uses a calibration curve showing the relationship between the brightness information difference and temperature to estimate the in-plane temperature distribution of the adjustment substrate during the heat treatment; and The heat treatment condition determination step determines the heat treatment conditions based on the predicted in-plane temperature distribution of the substrate for adjustment.

2. The substrate processing apparatus as described in claim 1, characterized in that: It has an exposure unit that is different from the external exposure device that performs the exposure process during actual processing, and is used to perform the uniform exposure process.

3. The substrate processing apparatus as described in claim 1, characterized in that: The uniform exposure process is performed by an external exposure device that performs the exposure process during actual processing.

4. The substrate processing apparatus as described in claim 1, characterized in that: The specified exposure amount is less than the actual exposure amount during processing.

5. The substrate processing apparatus as described in claim 1, characterized in that: The pre-exposure imaging step and the post-heating imaging step respectively acquire images at each wavelength of the multiple wavelengths. The temperature distribution estimation step is based on the captured image with respect to the wavelength corresponding to the thickness of the resist film, to estimate the in-plane temperature distribution of the conditioning substrate during the heat treatment.

6. The substrate processing apparatus as described in claim 1, characterized in that: It has a developing unit for developing substrates. The adjustment process includes: The developing process step involves controlling the developing unit to perform the developing process on the adjustment substrate after the heating and imaging step. The post-development imaging step involves controlling the imaging unit to capture images of the adjustment substrate after the development process. The film thickness distribution estimation step involves estimating the in-plane distribution of the resist film thickness after development treatment in the adjustment substrate based on the imaging results of the post-development imaging step; and The developing process condition determination step determines the developing process conditions based on the in-plane distribution of the film thickness.

7. The substrate processing apparatus as described in claim 1, characterized in that: It has a removal section for removing the resist film from the substrate. The adjustment process includes: In the removal step, the removal unit is controlled to remove the resist film formed on the conditioning substrate; After the removal step, the imaging unit is controlled to capture images of the adjustment substrate; and The judgment step, based on the shooting results of the removal and subsequent shooting steps, determines whether the adjustment substrate should be reused.

8. The substrate processing apparatus as described in claim 1, characterized in that: The control unit is configured to start the adjustment process based on the estimated linewidth of the resist pattern formed on the substrate during actual processing.

9. The substrate processing apparatus as described in claim 1, characterized in that: The control unit is configured to adjust the processing conditions for the peripheral portion of the substrate based on the imaging results of the peripheral portion of the substrate during actual processing.

10. The substrate processing apparatus as claimed in claim 1, characterized in that: The heat treatment section includes: A hot plate for mounting a substrate; A cover covering the substrate on the hot plate; and A temperature regulating mechanism for adjusting the temperature of the cover.

11. A method for adjusting processing conditions on a substrate, comprising: Pre-exposure photographing procedure for photographing an unexposed conditioning substrate with a resist film formed; The uniform exposure step involves subjecting the adjustment substrate to uniform exposure processing after the pre-exposure shooting step, exposing each area of ​​the substrate surface to a certain exposure amount. A heat treatment step following the uniform exposure step, in which the adjustment substrate is subjected to heat treatment; A post-heating photographing step is performed on the substrate for adjustment after the heat treatment step. The temperature distribution estimation step involves calculating the brightness information difference between the shooting results in the pre-exposure shooting step and the post-heating shooting step, and using a calibration curve showing the relationship between the brightness information difference and temperature, to estimate the in-plane temperature distribution of the adjustment substrate during the heat treatment. and The heat treatment condition determination step determines the treatment conditions during heat treatment based on the predicted in-plane temperature distribution of the substrate for adjustment.

12. The processing condition adjustment method as described in claim 11, characterized in that: The specified exposure amount is less than the actual exposure amount during processing.

13. The processing condition adjustment method as described in claim 11, characterized in that: The pre-exposure imaging step and the post-heating imaging step respectively acquire images at each wavelength of the multiple wavelengths. The temperature distribution estimation step is based on the captured image with respect to the wavelength corresponding to the thickness of the resist film, to estimate the in-plane temperature distribution of the conditioning substrate during the heat treatment.

14. The processing condition adjustment method as described in claim 11, characterized in that, include: A developing process step is performed on the substrate for conditioning after the heat treatment step. After the development process step, a post-development photographing step is performed on the adjustment substrate; The film thickness distribution estimation step involves estimating the in-plane distribution of the resist film thickness after development treatment in the adjustment substrate based on the imaging results of the post-development imaging step. and The developing process condition determination step is to determine the processing conditions for the developing process based on the in-plane distribution of the film thickness.

15. The processing condition adjustment method as described in claim 11, characterized in that, include: The removal step of removing the resist film formed on the conditioning substrate; After the removal step, a post-removal photographing step of the adjustment substrate is taken. and Based on the shooting results of the removal and shooting steps, a determination step is taken to determine whether to reuse the adjustment substrate.

Images