Circuit and method for calibrating circuits in integrated circuit devices

Abstract

A circuit apparatus for calibrating a circuit in an integrated circuit device is described. The circuit apparatus can include a main circuit (1102) configured to receive input data at a first input (1106) and generate output data at a first output (1108), wherein the output data is based on the input data and a function of the main circuit; a replica circuit (1104) configured to receive calibration data at a second input (1114) and generate calibration output data at a second output (1118) based on the calibration data, wherein the replica circuit provides a replicated function of the function of the main circuit; and a calibration circuit (1120) configured to receive the output data from the main circuit during a foreground calibration mode and receive the calibration output data from the replica circuit during a background calibration mode; wherein the calibration circuit provides a control signal to the main circuit during the background calibration mode. A method of calibrating a circuit in an integrated circuit device is also described.

Description

Technical Field

[0001] The various embodiments generally relate to integrated circuits, and more specifically to circuits and methods for calibrating circuits in integrated circuit devices. Background Technology

[0002] Modern networks are responsible for interconnecting computing devices that can operate to exchange data. For example, in a computer or server, data can be exchanged from board to board along a common backplane. In some implementations, data can be exchanged over long distances, such as from a travel agency's computer to an airline server on a cloud network. Modern networks may use various media, including physical lines, radio frequency (RF) channels, or fiber optics. Data exchanged between computing devices can include data packets containing multiple bits. In some network implementations, bits can be sent and received simultaneously. This communication can be called parallel and can include multiple parallel connections referred to as buses. In some implementations, data can be transmitted one bit at a time or serially.

[0003] Given a common signal frequency, serial data communication is slower than parallel communication because each bit is transmitted individually in serial communication, whereas in parallel communication, a group of bits is communicated simultaneously in sequential time slices. However, as the communication signal frequency increases (and the time slice decreases), bit transmission time can become a significant factor contributing to challenges regarding the simultaneous data arrival time in parallel data implementations. Since serial transmission implementations transmit one bit of data at a time, there is essentially no synchronization data. This aspect of serial transmission allows data to be transmitted at higher signaling frequencies. Therefore, network designers can weigh the various advantages and disadvantages of parallel versus serial data transmission for specific applications. Summary of the Invention

[0004] A circuit arrangement for calibrating circuitry in an integrated circuit device is described. The circuit arrangement may include: a main circuit configured to receive input data at a first input and generate output data at a first output, wherein the output data is based on the input data and the function of the main circuit; a replication circuit configured to receive calibration data at a second input and generate calibration output data at a second output based on the calibration data, wherein the replication circuit provides a replication function of the main circuit; and a calibration circuit configured to receive output data from the main circuit during a foreground calibration mode and receive calibration output data from the replication circuit during a background calibration mode, wherein the calibration circuit provides a control signal mode to the main circuit during background calibration.

[0005] In some embodiments, the circuit may further include a selection circuit configured to receive output data from the main circuit and calibration output data from the replication circuit, wherein the selection circuit controls the selection of the output data and calibration output data during foreground calibration mode.

[0006] In some implementations, the main circuit may include a first serializer circuit configured to receive parallel input data and generate serial output data, wherein the first serializer circuit generates serial output data during an operating mode.

[0007] In some implementations, the replication circuit may include a second serializer circuit configured to receive parallel test mode and generate calibration output data during operation mode.

[0008] In some implementations, the calibration circuit can be configured to receive multiple clock phases of the input clock signal, and the calibration clock signal generated by the calibration circuit can be coupled to a first control terminal of the main circuit and a second control terminal of the replication circuit.

[0009] In some implementations, the calibration circuit can be configured to receive calibration output data from the replication circuit during the foreground calibration mode to determine the initial replication correction code.

[0010] In some implementations, the calibration circuit can be configured to receive calibration output data from the replication circuit during background calibration mode to determine an updated replication correction code.

[0011] In some implementations, the calibration circuitry can determine the difference between the initial copy correction code and the updated copy correction code.

[0012] In some implementations, the calibration circuit can generate calibration control signals sent to the main circuit and the replication circuit based on the initial calibration correction code for the main circuit and the difference between the initial copy correction code and the updated copy correction code.

[0013] In some implementations, the correction control signal may include a correction clock signal.

[0014] A method for calibrating circuitry in an integrated circuit device is also described. The method may include: configuring a main circuit to receive input data at a first input and generate output data at a first output, wherein the output data is based on the input data and the functionality of the main circuit; configuring a replication circuit to receive calibration data at a second input and generate calibration output data at a second output based on the calibration data, wherein the replication circuit provides a replication function of the main circuit; and configuring a calibration circuit to receive output data from the main circuit during a foreground calibration mode and to receive calibration output data from the replication circuit during a background calibration mode, wherein the calibration circuit provides control signals to the main circuit and the replication circuit during the background calibration mode.

[0015] In some embodiments, the method may further include configuring a selection circuit to receive output data from the main circuit and calibration output data from the replication circuit, wherein the selection circuit controls the selection of the output data and calibration output data during the foreground calibration mode.

[0016] In some implementations, the main circuit may include a first serializer circuit configured to receive parallel input data and generate serial output data, wherein the first serializer circuit generates serial output data during an operating mode.

[0017] In some implementations, the replication circuit may include a second serializer circuit configured to receive parallel test mode and generate calibration output data during operation mode.

[0018] In some embodiments, the method may further include configuring a calibration circuit to receive multiple clock phases of an input clock signal and coupling a calibration clock signal generated by the calibration circuit to a first control terminal of the main circuit and a second control terminal of the replication circuit.

[0019] In some implementations, the calibration circuit can be configured to receive calibration output data from the replication circuit during the foreground calibration mode to determine the initial replication correction code.

[0020] In some implementations, the calibration circuit can be configured to receive calibration output data from the replication circuit during background calibration mode to determine an updated replication correction code.

[0021] In some implementations, the method may further include determining the difference between the initial replication correction code and the updated replication correction code.

[0022] In some embodiments, the method may further include generating a correction control signal sent to the main circuit and the copy circuit based on the initial correction code of the main circuit and the difference between the initial copy correction code and the updated copy correction code.

[0023] In some implementations, the calibration control signal may include a calibration clock signal.

[0024] Details of various embodiments are set forth in the accompanying drawings and the following description. Other features and advantages will be apparent from the description and drawings, as well as from the claims. Attached Figure Description

[0025] Figure 1 An exemplary multiplexer clock phase calibration module implemented within a serializer integrated circuit (IC) or module is described, which improves the reliability and noise immunity of high-speed serializer / deserializer (SERDES) applications.

[0026] Figure 2 An exemplary 4-to-1 multiplexer implementation is described.

[0027] Figure 3 A multiplexer combined with an exemplary clock phase alignment module is described.

[0028] Figure 4A , 4B The 4C describes the output data stream from an exemplary multiplexer circuit with a variable duty cycle in response to a variable clock phase.

[0029] Figure 5 An exemplary duty cycle calibration module is described.

[0030] Figure 6A and 6B An exemplary clock phase alignment module is described.

[0031] Figure 7 An exemplary eye diagram illustrating clock jitter without a multiplexer clock phase calibration module is depicted.

[0032] Figure 8 An exemplary eye diagram illustrating clock jitter in the case of a multiplexer clock phase calibration module is depicted.

[0033] Figure 9A and 9B An exemplary programmable integrated circuit (IC) on which the disclosed circuitry and processes can be implemented is depicted.

[0034] Figure 10 A flowchart illustrating an exemplary clock phase alignment method is provided.

[0035] Figure 11 A block diagram of a circuit arrangement for calibrating the master circuit using a replication circuit is depicted.

[0036] Figure 12A flowchart illustrating a method for calibrating circuitry used to receive input data and generate output data is provided.

[0037] Figure 13 Another flowchart illustrating a method for calibrating circuitry used to receive input data and generate output data is shown.

[0038] Figure 14 Another block diagram depicts the circuitry used to calibrate a serializer that receives parallel data and generates serial data.

[0039] Figure 15 Another block diagram depicts the circuitry used to calibrate a serializer that receives parallel data and generates serial data.

[0040] Figure 16 An exemplary block diagram of a circuit that can provide IQ detection is depicted.

[0041] Figure 17 An exemplary block diagram of a circuit that can provide IQ correction is depicted.

[0042] Figure 18 A graph showing the mismatch as a function of size (N) with respect to the simulation and 1 / sqrt(N) is plotted.

[0043] Figure 19 A flowchart illustrating a method for performing circuit calibration is provided.

[0044] The same reference symbols in each figure represent the same element. Detailed Implementation

[0045] To aid understanding, this document is organized as follows. First, refer to... Figure 1 An exemplary use case is briefly introduced. Next, refer to... Figure 2 This presents an exemplary multiplexer circuit of the type used in this paper. See below for reference. Figure 3 The multiplexer is replicated and used in the exemplary phase adjustment module, which (based on in-phase and quadrature input clocks) generates a set of clocks for duty cycle and phase adjustment. Referring now to Figure 4, an example diagram is given to aid understanding. Figure 2 The Replication Multiplexer (RMUX) described in [the document]. See next for reference. Figure 5 The functionality of an exemplary sensing module is described. Figure 6A and 6B The sequential and recursive clock adjustment functions in the exemplary duty cycle and phase adjustment module are presented. Next, refer to... Figure 7 and 8 Further illustrative discussion and experimental data are presented to explain the improvements in clock jitter. Next, refer to... Figure 9A and 9BThis describes exemplary programmable integrated circuits (ICs) on which the disclosed circuits and processes can be implemented. Finally, refer to Figure 10 This presents an exemplary clock phase alignment method.

[0046] Throughout this application, CK is stipulated. x It can be used to define clock signals, where the subscript x indicates the relative phase delay in degrees. Additionally, CK... 0,180 It can be used as shorthand to define a pair of clock signals CK0 and CK0. 180 CK 90,270 It can be used as a pair of clock signals CK 90 and CK 270 Shorthand. The term in-phase clock can be used to define a pair of differential clocks CK. 0,180 The term quadrature clock can be used to define a pair of differential clocks CK. 90,180 The term system clock can be used to define combinations of in-phase and quadrature clocks (CK). 0,180,90,270 In various examples, the system clock can be generated in addition to the embodiments described. Furthermore, the series switches depicted throughout the figures can be controlled by logic signals coupled to the switch symbols. Unless otherwise stated, the switch is defined as closed when the control logic is high. Therefore, the switch is defined as open when the control logic is low.

[0047] Throughout this application, the term "replica" and its conjugate can be defined as copying using the same circuit layout pattern on a common substrate. In this application, a master multiplexer (MMUX) with a predefined circuit layout pattern can be replicated to form a replicated multiplexer (RMUX) to replicate the specific functions and timing of the MMUX (e.g., clock delay, signal delay, rise time, fall time). Furthermore, the RMUX can replicate or substantially simulate the timing of the MMUX in terms of process, voltage, and temperature.

[0048] Figure 1 An exemplary multiplexer clock calibration module implemented within a serializer module is depicted, which improves the reliability and noise immunity of high-speed serializer / deserializer (SERDES) applications. Computer communication application 100 includes a computing device 105 (e.g., a personal computer) communicating with a router 110 via Gigabit Ethernet 115. The computing device 105 provides high-speed serial data 140 from the serializer module 120.

[0049] In the depicted example, the serializer module 120 includes a multiplexer clock calibration module 125. The multiplexer clock calibration module 125 receives a set of system clocks 130 (e.g., multiplexer clocks) and input data 135. In response to the input data 135, which is timed by the set of system clocks 130, the multiplexer clock calibration module 125 outputs serial data 140.

[0050] The multiplexer clock calibration module 125 includes a clock calibration controller 145. The clock calibration controller 145 receives the set of system clocks 130, detects their deviations from the expected duty cycle, and provides error correction signals to the delay line module 150. The clock calibration controller 145 also receives D from the duplicate multiplexer 155. out-r The signal indicates the group of system clocks 130 (e.g., the in-phase clock group CK). 0,180 Quadrature clock group CK 90,270 The phase error between the clocks. The clock calibration controller 145 responds to the in-phase clock group CK. 0,180 and quadrature clock group CK 90,270 The deviation between the expected phase shifts provides an error correction signal to the delay line module 150.

[0051] A set of calibration clocks 160 (CK) from delay line module 150 0’,180’ CK 90’,270’ The input data 135 is sent to a replica multiplexer 155 for subsequent offset determination. A multiplexer clock calibration module 125 provides iterative offset detection and clock adjustment. The replica multiplexer 155 can be manufactured as a substantial replica of the master multiplexer 165. The master multiplexer 165 receives the same set of calibration clocks 160 as the replica multiplexer 155. The replica multiplexer 155 replicates the timing parameters of the master multiplexer 165. Therefore, the master multiplexer 165 serializes the input data 135 with the set of calibration clocks 160, thereby providing a low bit error rate. The multiplexer clock calibration module 125 can be implemented, for example, within a multi-gigabit transceiver (MGT) on a field-programmable gate array (FPGA).

[0052] Figure 2 An exemplary 4-to-1 multiplexer implementation is described. The 4-to-1 data multiplexer 200 includes input buffers 2050, 2051, 2052, and 2053 (collectively referred to as "input buffer 205"). Input buffer 205 receives parallel input data D. in0 D in2 D in1 and D in3Input buffer 205 is coupled to series switches 2100, 2101, 2102, and 2103 (hereinafter collectively referred to as "series switch 210"). Series switches 2100 and 2101 are respectively powered by quadrature clock CK. 90 and CK 270 Control, and thus control data D1. Series switches 2102 and 2103 are controlled by quadrature clock CK. 270 and CK 90 Control, and thus control data D2.

[0053] Data D1 and data D2 are coupled to intermediate buffers 2150 and 2151 (hereinafter collectively referred to as "intermediate buffer 215"), respectively. Intermediate buffer 215 is coupled to series switches 2200 and 2201 (hereinafter collectively referred to as "series switch 220"). Series switches 2200 and 2201 are powered by in-phase clock CK. 180 CK0 controls and controls the data sent to the final buffer 225. The final buffer 225 drives the output data D. out .

[0054] When CK 90 and CK 180 Valid (e.g., logic high) and CK 270 When CK0 is invalid (e.g., logic low), the 4-to-1 data multiplexer 200 can convert the input data D... in0 Passed to output data D out When CK 270 And CK0 is valid (e.g., logic high) and CK 90 and CK 180 When invalid (e.g., logic low), the 4-to-1 data multiplexer 200 can convert the input data D in1 Passed to output data D out When CK 270 and CK 180 Valid (e.g., logic high) and CK 90 When CK0 is invalid (e.g., logic low), the 4-to-1 data multiplexer 200 can convert the input data D... in2 Passed to output data D out When CK 90 And CK0 is valid (e.g., logic high) and CK 270 and CK 180 When invalid (e.g., logic low), the 4-to-1 data multiplexer 200 can convert the input data D in3 Passed to output data D out .

[0055] The 4-to-1 data multiplexer 200 can be a compact MUX structure. The 4-to-1 data multiplexer 200 uses a quarter-rate clock (e.g., CK). 0,90,180,270 Therefore, it inherently has lower power consumption. When CK0 or CK 180 When high, the final stage switch (series switch 220) passes through two consecutive bits. Therefore, both clock power and MUX output jitter are very low. Simulations can be performed to demonstrate that the output jitter is approximately 359 fs and the power consumption is approximately 2.4 mW, including the power consumption of the clock buffer (not shown).

[0056] Because when CK0 or CK 180 When the signal is high, the final-stage switch (series switch 220) of this 4-to-1 data multiplexer 200 passes two bits to the output Dout, so the internal data D1 and D2 are directly affected by CK0 or CK0. 180 The effect of clock phase alignment. If CK0 or CK 180 If the centers of the data bits on D1 and D2 are not aligned, then the output node D... out Bit width variations may occur, resulting in greater output data jitter.

[0057] In the illustrative example, the data signal array may include data signal D. in0 D in1 D in2 and D in3 D in0 It can be configured to respond to CK 90 Connect to form the first internal node. D in2 It can be configured to respond to CK 270 Connect to the first internal node. D in1 It can be configured to respond to CK 270 Connect to form a second internal node. D in3 It can be configured to respond to CK 90 Connect to the second internal node. The first internal node can be configured to respond to CK. 180 Connect to form D out Furthermore, the second internal node can be configured to form a D connection in response to the CK0 connection. out .

[0058] Figure 3 A multiplexer combined with an exemplary clock phase alignment module is depicted. The clock phase alignment module 300 receives a set of in-phase clocks (CK). 0,180 )305 and a set of quadrature clocks (CK) 90,270 310. Adjustable Delay Line (ADL1) 3151 Receives In-Phase Clock (CK) 0,180305 and correction signal 320. Adjustable delay line (ADL2) 3152 receives quadrature clock (CK). 90,270 )310 and correction signal 325. (Adjustable delay lines 3151 and 3152 can be collectively referred to as "adjustable delay line 315.") Each of the adjustable delay lines 315 may include one or more delay lines, each of which is operable to generate a delayed input signal. DCC 330 responds to a deviation from a set of corrected in-phase clocks (CK). 0’,180’ The DCC330 generates a correction signal 320 based on a 50% duty cycle deviation. The DCC330 responds to deviations from a set of corrected quadrature clocks (CK). 90’,270’ The 50% duty cycle deviation of clock 340 generates a correction signal 325. The adjustable delay line (ADL1) 3151 responds to the correction signal 320 to the in-phase clock (CK). 0,180 The leading and / or trailing edges of the 305 are delayed to generate the corrected in-phase clock (CK). 0’,180’ 335. Adjustable delay line (ADL2) 3152 responds to correction signal 325 to quadrature clock (CK) 90,270 The leading and / or trailing edges of the 310 are delayed to generate a set of corrected quadrature clocks (CK). 90’,270’ )340. Therefore, the corrected in-phase clock (CK) 0’,180’ )335 and the corrected quadrature clock (CK) 90’,270’ The 340 can have a duty cycle of approximately 50%.

[0059] Adjustable delay line 315 provides a calibrated in-phase clock (CK) to master multiplexer (MMUX) 345. 0’,180’ )335 and the corrected quadrature clock (CK) 90’,270’ )340. In some examples, the MMUX 345 receives clocks 335 and 340 via multiphase control inputs. The MMUX 345 inputs a parallel data bus (D in0 D in1 D in2 D in3 350 serialized into a data stream (D out )355.

[0060] The RMUX 360 copy multiplexer also receives a calibrated in-phase clock (CK). 0’,180’ )335 and the corrected quadrature clock (CK) 90’,270’)340. In some examples, the RMUX 360 receives clocks 335 and 340 via multiphase control inputs. The RMUX 360 can be manufactured as a substantial replica of the MMUX 345, can be fabricated together with the master multiplexer 345 on a common substrate, and can replicate the configuration, function, and timing characteristics of the master multiplexer 345. Therefore, with the data stream (D out The timing associated with the data bits within 355 can be related to the data stream of the RMUX 360 (D). out-r A time-series copy of the data bits within 370.

[0061] RMUX 360 receives input data bus (D) in0-r D in1-r D in2-r D in3-r 365. Input data bus (D) in0-r D in1-r D in2-r D in3-r )365 is configured to generate a data stream with alternating data bit logic (D out-r 370. Data Stream (D) out-r The RMUX 360 is timed via the RMUX 370, and the RMUX 360 can be manufactured as a substantial replica of the MMUX 345. Since the RMUX 360 is manufactured on the same substrate as the MMUX 345, its configuration, functionality, and timing characteristics can be a replica of the MMUX 345. Furthermore, the clock-to-data phasing on the RMUX 360 can be a replica of the clock-to-data phasing on the MMUX 345. In the illustrative example, if the corrected in-phase clock (CK...) 0’,180’ The edge of the 335 is connected to the main serial data stream (D). out Centered on the data bits in the 355, the corrected in-phase clock (CK) 0’,180’ The edge of the 335 is used to replicate the serial data stream (D). out-r The data bits in 370 are centered.

[0062] Because the data bits on the RMUX 360 input are configured with alternating logic, the data stream (D) out-r The RMUX 370 can generate alternating bit logic. Furthermore, the data stream (D) from the RMUX 360... out-r The duty cycle of 370 can indicate the calibrated in-phase clock (CK). 0’,180’ )335 and the corrected quadrature clock (CK) 90’,270’ The center of RMUX 340. Data stream from RMUX 360 (D out-r )370 is sent to DCC 330. DCC 330 responds to the off-data stream (Dout-r The 50% duty cycle deviation of DCC 370 generates correction signals 320 and / or 325. Since the deviation may involve a correction delay for the in-phase clock or a correction delay for the quadrature clock, DCC can generate correction signals 320 and / or 325. In response to correction signal 320, adjustable delay line 3151 can adjust the corrected in-phase clock (CK). 0’,180’ The phase of 335. In response to the correction signal 325, the adjustable delay line 3152 can further adjust the corrected quadrature clock (CK). 90’,270’ The phase is 340. Corrected phase positioning will essentially center the clock edge on the data stream (D). out Within each data bit of 355.

[0063] In various implementations, correction signals 320 and 325 can each be a set of data buses. For example, correction signals 320 and 325 can each include buses containing rising edge delay values ​​and falling edge delay values. Therefore, adjustable delay line 315 can adjust the phase of clocks 335 and 340 by changing the rising edge and falling edge delays by the same amount. Furthermore, adjustable delay line 315 can adjust the in-phase clock (CK) of the correction by changing the rising edge and falling edge delays. 0’,180’ )335 and the corrected quadrature clock (CK) 90’,270’ )340 duty cycle.

[0064] In various examples, the clock phase alignment module 300 can generate continuous duty cycle-equalized and phase-aligned in-phase and quadrature clocks. Duty cycle-equalized and phase-aligned clocks can advantageously reduce jitter in various serializer-deserializer (SERDES) applications. For example, Figure 3 The implementation described herein can be a clock phase-calibrated multiplexer.

[0065] Figure 4A , 4B The diagram above (4C) depicts an output data stream from an exemplary multiplexer circuit that has a variable output duty cycle in response to a variable clock phase. The diagram includes an in-phase clock (CK0) and an out-of-phase clock (CK). 180 )pass Figure 2 The multiplexer 200 shown multiplexes data signals D1 and D2. Multiplexer 200 can represent the logical configuration of MMUX 345 and RMUX 360. Figure 3 On the multiplexer 200, when data is input to D in0 and D in2 Keep it high, while D in1 and D in3 When held low, a data stream may be generated on D1 and D2, with the data occurring in the quadrature clock CK. 90and CK 270 Each time it transitions, it is converted to the opposite logic level.

[0066] Figure 4A , 4B Exemplary waveforms for 4C can be generated from multiplexer 200, where data input D... in0 and D in2 Keep it high, while D in1 and D in3 Keep it low. During runtime, refer to... Figure 4A , 4B With 4C, when the in-phase clock CK0 is low, the data signal D1 is transmitted to D in real time. out Furthermore, when the inverse phase clock CK... 180 When the signal is high, the data signal D2 is transmitted to D in real time. out Because data signals D1 and D2 are connected in series via switch 220, the actual data signal, including the data conversion signal, is selectively transmitted from D1 to D2. out Or pass from D2 to D out .

[0067] Therefore, in response to the in-phase clocks CK0 and CK 180 The edge is close to the transformation center on D1 and D2, D out Signal generation duty cycle. In-phase clocks CK0 and CK... 180 The closer the clock edge is to the midpoint between the transitions of data signals D1 and D2, the better. out The duty cycle becomes closer to 50%. out The duty cycle indicates the center of the clock and the data boundaries in data signals D1 and D2.

[0068] like Figure 4A As shown, the in-phase clock CK0 is centered around the transitions on D1 and D2. The transitions on D1 and D2 can represent quadrature clocks ( Figure 2 CK in 90 and CK 270 The conversion of in-phase clocks (CK0 and CK2) is described. Various embodiments of clock phase alignment modules can be used to convert in-phase clocks (CK0 and CK2) into phase-aligned clocks. 180 The phase adjustment is basically centered on the quadrature clock (CK). 90 and CK 270 The transformation between D and D makes D out Generates a duty cycle of approximately 50%.

[0069] like Figure 4B As shown, the in-phase clock CK0 arrives earlier than the midpoint of the transitions on data signals D1 and D2. In this example, in response to the earlier arrival of the in-phase clock, D... out Generate a duty cycle greater than 50%.

[0070] like Figure 4C As shown, the in-phase clock CK0 is delayed relative to the midpoint of the transitions on data signals D1 and D2. In this example, in response to the delayed in-phase clock, D... out Generate a duty cycle of less than 50%.

[0071] In some examples, data input can be configured to be similar to... Figures 4A-4C Conversely as described in the text, thus, D in0 and D in2 For logic low, and D in1 and D in3 This is logic high. In such an example, data signals D1 and D2 can be... Figures 4A-4C The opposite of those described in the text. In the case of an in-phase clock arriving earlier, such as... Figure 4B As shown, D out The duty cycle may be less than 50%. In the case of in-phase clock delay, such as... Figure 4C As shown, D out The duty cycle may be greater than 50%. The corresponding downstream circuit can be implemented using inverse logic to achieve the same overall result.

[0072] Figure 4A , 4B The diagram above (4C) details the operation of the Replica Multiplexer (RMUX) 360. In the illustrative example, this is achieved by connecting the inputs of the RMUX 360 to alternating logic (e.g., D...). in0-r and Din 2-r Connected to logic high, D in1-r and Din 3-r Connecting to logic low allows for the generation of, for example, a 14-GHz clock waveform at the RMUX 360's data signals (internal nodes) D1 and D2. If CK... 0,180 Basically, the conversion of data signals D1 and D2 is the core, so the data stream output by the RMUX 360 (D...) out-r The 370 can be a 28GHz signal with a duty cycle of approximately 50%. In contrast, the RMUX 360 output can respond to CK. 0,180 Early or delayed clock edges on the data stream (D) out-r Generate a duty cycle greater than 50% or less than 50% on 370.

[0073] Figure 5 An exemplary duty cycle calibration module (DCC) is depicted. The duty cycle calibration module (DCC) 500 includes a sensing module 505 and a calibration processing module 510. In some examples, the DCC 500 may be a DCC 330 (…). Figure 3Sensing module 505 receives one or more differential pairs. In the depicted example, sensing module 505 receives D... out-r Difference pairs, CK 0,180 Difference pairs and CK 90,270 Difference pairs.

[0074] D out-r Difference pairs are generated by RMUX ( Figure 3 Project 360). D out-r The differential pair is filtered by a low-pass filter (LPF) 515. The LPF 515 generates a pair of average voltage V. AVE (D out-r ) and V AVE (D out-r The average voltage is sent to error amplifier 520, where an error signal 520A is generated to indicate the in-phase clock (CK). 0,180 Relative to quadrature clocks (CK) 90,270 Aligned phase shift.

[0075] In the illustrative example, the sensing module 505 can be configured to respond to the in-phase clock (CK). 0,180 ) and quadrature clocks (CK) 90,270 A zero-error signal 520A is generated when the phase shift is 90 degrees. A 90° phase shift indicates optimal alignment. The sensing module 505 can be configured to generate a zero-error signal 520A when the phase shift is 90 degrees. 0,180 ) and quadrature clocks (CK) 90,270 A positive error signal 520A is generated when the phase shift of the clock is less than 90°, and when the phase shift of the clock (CK) is less than 90°, a positive error signal 520A is generated. 0,180 ) and quadrature clocks (CK) 90,270 When the phase shift of CK0 exceeds 90°, a negative error signal 520A is generated. For example, in response to a positive error, the rising and falling edges of CK0 (and CK...) generate a negative error signal 520A. 180 The associated rising and falling edges (of the clock) can be delayed simultaneously to increase the phase shift of the in-phase clock. Therefore, for example, in response to a negative error, CK 90 Rising and falling edges (and CK) 270 The associated rising and falling edges may be delayed simultaneously to increase the phase shift of the quadrature clock. The error signal 520A may include an indication of the magnitude of the deviation from 90°.

[0076] CK 0,180 The differential pair is filtered by an LPF 525. The LPF 525 generates a pair of average voltage V. AVE (CK0) and V AVE (CK 180 The average voltage is sent to error amplifier 530, where an indicator CK is generated. 0,180 The error signal of the duty cycle of the differential pair is 530A.

[0077] In the illustrative example, the sensing module 505 can be configured to when CK 0,180 The differential pair generates a zero-error signal 530A when the duty cycle is 50%. The sensing module 505 can be configured to... 0,180 A positive error signal 530A is generated when the duty cycle of the differential pair is greater than 50%, and when CK... 0,180 A negative error signal 530A is generated when the duty cycle of the differential pair is less than 50%. For example, in response to a positive error, the rising edge of CK0 (and CK...) generates a negative error signal 530A. 180 The associated falling edge of CK0 (and CK0) may be delayed to reduce the duty cycle of the in-phase clock. Therefore, for example, in response to a negative error, the falling edge of CK0 (and CK0) may be delayed. 180 The associated rising edge may be delayed to increase the duty cycle of the in-phase clock. The error signal 530A may include an indication of the magnitude of the deviation from the 50% duty cycle.

[0078] CK 90,270 The differential pair is filtered by an LPF 535. The LPF 535 generates a pair of average voltage V. AVE (CK 90 ) and V AVE (CK 270 The average voltage is sent to error amplifier 540, where an indicator CK is generated. 90,270 The error signal of the duty cycle of the differential pair is 540A.

[0079] In the illustrative example, the sensing module 505 can be configured to when CK 90,270 The differential pair generates a zero-error signal 540A when the duty cycle is 50%. The sensing module 505 can be configured to... 90,270 A positive error signal 540A is generated when the duty cycle of the differential pair is greater than 50%, and when CK... 90,270 A negative error signal of 540A is generated when the duty cycle of the differential pair is less than 50%. For example, in response to a positive error, CK... 90 The rising edge (and CK) 270 The associated falling edge (of the clock) may be delayed to reduce the quadrature clock duty cycle. Therefore, for example, in response to a negative error, CK 90 The falling edge (and CK) 270 The associated rising edge can be delayed to increase the quadrature clock duty cycle. In some examples, the error signal 540A may include an indication of the magnitude of the deviation from the 50% duty cycle.

[0080] The calibration processing module 510 receives error signals 520A, 530A, and 540A. The calibration processing module 510 generates an in-phase clock correction signal 545 and a quadrature clock correction signal 550.

[0081] In the illustrative example, the in-phase clock correction signal 545 may include one or more digital control and data buses.

[0082] The digital control and data bus can include the time delay magnitude of both the rising and falling edges, which can be sent to a delay line module, such as the adjustable delay line (ADL1) 3151. Figure 3 This allows for adjustment of the duty cycle and the phase of the in-phase clock.

[0083] In the illustrative example, the quadrature clock correction signal 550 may include one or more digital control and data buses. The digital control and data buses may include the time delay magnitudes of both the rising and falling edges, which can be sent to a delay line module, such as the adjustable delay line (ADL2) 3152. Figure 3 This allows for adjustment of the duty cycle and the phase of the in-phase clock.

[0084] Figure 6A and 6B A block diagram and associated timing diagram of an exemplary clock phase alignment module are depicted. (Reference) Figure 6A The clock phase alignment module 600 includes a digital delay module 605. The clock phase alignment module 600 can be used to adjust one or more input clocks 610. The input clocks 610 can include in-phase differential pairs (e.g., CK0, CK2). 180 ) and orthogonal differential pairs (CK 90 CK 270 The adjustment of the input clock 610 can be controlled by a delay control signal 615. In the depicted example, the delay control signal 615 includes one or more delay modules controlling the data bus. The digital delay module 605 can generate a set of adjustment clocks 620 (which can be defined as an in-phase adjustment clock CK) by adjusting the rise and / or fall delays of the set of input clocks 610 in response to the delay control signal 615. 0’ CK 180’ and quadrature adjustment clock CK 90’ CK 270’ Therefore, the adjusted clock 620 can reflect the input clock 610 with duty cycle and phase adjustment.

[0085] The sensing module 625 receives the adjustment clock 620 and the data output signal 635 generated by the copy multiplexer 640. The data output signal 635 can indicate the phase alignment between the in-phase clock and the quadrature clock. The sensing module 625 can generate a duty cycle sensing signal 630, which indicates the duty cycle of the following items: (1) the in-phase adjustment clock CK. 0’ CK 180’ (2) Quadrature adjustment of clock CK 90’ CK270’ (3) Data output signal 635.

[0086] The calibration processing module 645 receives the duty cycle sensing signal 630 generated by the sensing module 625. The calibration processing module 645 generates a delay control signal 615 based on the duty cycle sensing signal 630.

[0087] In the depicted example, the calibration processing module 645 includes a preprocessing module 650 and a postprocessing module 655. The preprocessing module 650 generates a set of amplitude and direction signals 660 in response to each of the received duty cycle sensing signals 630. The postprocessing module 655 generates a delay control signal 615 in response to the set of amplitude and direction signals 660. The delay control signal 615 may include one or more delay modules controlling a data bus. The calibration processing module 645 may generate the delay control signal 615 based on the duty cycle sensing signals.

[0088] The calibration processing module 645 includes a clock divider 665. The clock divider 665 generates one or more enable signals 670 in response to the processing clock 675. The enable signals 670 can repeatedly and continuously activate three functions (in-phase clock duty cycle, quadrature clock duty cycle, and phase duty cycle) within the sensing module 625.

[0089] In various examples, each of the three enable signals 670 can be activated in a repetitive mode during one or more processing clocks 675. Furthermore, the enable signal 670 can select one of the sensing signals from the sensing module 625 as an output to the duty cycle sensing signal 630.

[0090] For example, during the first enable signal (cal_i_duty_enable), the duty cycle sensing signal 630 can be used as an in-phase clock (CK). 0,180 The result is the LPF sensing signal. The preprocessing module 650 within the calibration processing module 645 can determine the amplitude and direction signals 660 of the in-phase clock based on the received duty cycle sensing signal 630. The postprocessing module 655 within the calibration processing module 645 can receive the amplitude and direction signals 660 and generate delay amplitudes for the in-phase clock edges (e.g., cki_falling[7:0], cki_rising[7:0]). During the first enable signal (cal_i_duty_enable), the calibration processing module 645 can perform this determination process eight times, for example, each determination process lasting 16 processing clock cycles.

[0091] Next, during the second enable signal (cal_q_duty_enable), the duty cycle sensing signal 630 can be the LPF sensing signal as a result of the quadrature clock. The preprocessing module 650 within the calibration processing module 645 can determine the amplitude and direction signals 660 of the quadrature clock based on the received duty cycle sensing signal 630. The postprocessing module 655 within the calibration processing module 645 can receive the amplitude and direction signals 660 and generate the delay amplitude for the quadrature clock edges (e.g., ckq_falling[7:0], ckq_rising[7:0]). During the second enable signal (cal_q_duty_enable), the calibration processing module 645 can perform this determination process eight times, for example, each determination process lasting 16 processing clock cycles.

[0092] Finally, during the third enable signal (cal_iq_phase_enable), the duty cycle sensing signal 630 can be the LPF sensing signal generated by the replication multiplexer 640 as a result of the data output signal 635. The preprocessing module 650 within the calibration processing module 645 can determine the amplitude and direction signals 660 of the data output signal 635 generated by the replication multiplexer 640 based on the received duty cycle sensing signal 630. The postprocessing module 655 within the calibration processing module 645 can receive the amplitude and direction signals 660 and generate a common delay amplitude for in-phase and quadrature clock edges (e.g., cki_falling[7:0], cki_rising[7:0], ckq_falling[7:0], ckq_rising[7:0]). During this third enable signal (cal_iq_phase_enable), the calibration processing module 645 can perform this determination process eight times, for example, each determination process lasting 16 processing clock cycles.

[0093] The duplicate multiplexer 640 is a replica of the master multiplexer 680. In various examples, the clock phase alignment module 600 can generate the set of adjusted clocks 620, which can be a corrected replica of the input clock 610, with adjusted duty cycle and phase. The master multiplexer 680 can generate a serial output data stream 685 with reduced jitter in response to the set of adjusted clocks 620.

[0094] refer to Figure 6B The timing diagram of an exemplary clock phase alignment module 600 includes sequential enable signals 670. For example... Figure 6A As shown, the enable signal activates one of the three functions in the duty cycle sensing module 625.

[0095] As in Figure 6BAs depicted in the example, when cki_Duty_enable is active (e.g., high), the duty cycle of the in-phase clock (represented by "i" in the signal name cki_Duty_enable) can be sensed and evaluated in sensing module 625. Sensing module 625 can generate a duty cycle sensing signal 630 with an in-phase clock duty cycle LPF value and send that value to calibration processing module 645. In various examples, calibration processing module 645 can allow multiple cycles (represented as "n" cycles in Figure 6) to allow the in-phase clock duty cycle LPF value to stabilize. Calibration processing module 645 can generate delay control signal 615 by converting the duty cycle sensing signal 630 into correction values ​​cki_Duty_cntl[7:0] and cki_Duty_dir.

[0096] When ckq_Duty_enable is active (e.g., high), the duty cycle of an orthogonal clock (represented by "q" in the signal name ckq_Duty_enable) can be sensed and evaluated in sensing module 625. Sensing module 625 can generate a duty cycle sensing signal 630 with an orthogonal clock duty cycle LPF value and send this value to calibration processing module 645. In various examples, calibration processing module 645 can allow multiple cycles to pass (in... Figure 6B (represented as "n" cycles) to allow the quadrature clock duty cycle LPF value to be stable. The calibration processing module 645 can generate the delay control signal 615 by converting the duty cycle sensing signal 630 into the correction values ​​ckq_Duty_cntl[7:0] and ckq_Duty_dir.

[0097] When ckiq_Phase_enable is active (e.g., high), the duty cycle indicating in-phase to quadrature phase shifting can be sensed and evaluated in sensing module 625, such as data output signal 635. Sensing module 625 can generate a duty cycle sensing signal 630 with an in-phase to quadrature phase shifting duty cycle (LPF) value and send that value to calibration processing module 645. In various examples, calibration processing module 645 can allow multiple cycles to be experienced (in... Figure 6B(represented as "n" periods) to allow the in-phase to quadrature duty cycle LPF value to stabilize. The calibration processing module 645 can generate a delay control signal 615 by converting the duty cycle sensing signal 630 into correction values ​​ckiq_Phase_cntl[7:0] and ckiq_Phase_dir. In some examples, the calibration processing module 645 can generate the delay control signal 615 by converting the duty cycle sensing signal 630 into correction values ​​ckiq_Phase_cntl[7:0] and ckiq_Phase_dir. Therefore, the relative phase of the clock can be adjusted by simultaneously delaying the rising and falling edges of the in-phase and / or quadrature clocks.

[0098] In various examples, the number of clock cycles for the settling time (as represented by the first "n" samples after activation of enable signal 670) can be different for each function. For example, the settling time for in-phase clock duty cycle sensing can be 5 clock cycles, the settling time for quadrature clock duty cycle sensing can be 10 clock cycles, and the settling time for phase sensing duty cycle can be 12 clock cycles.

[0099] The calibration processing module 645 can control the sensing module 625 via the enable signal 670 to indicate which parameter (e.g., in-phase clock, quadrature clock, or phase positioning between in-phase and quadrature clocks) will be sampled and corrected. The calibration processing module 645 can, as shown in... Figure 6B The sequential repetition mode shown enables parameters. Repeated correction of parameters (e.g., in-phase clock, quadrature clock, and phase positioning between in-phase and quadrature clocks) can provide real-time compensation for power supply and temperature variations.

[0100] In some examples, enablement can be activated asymmetrically. For example, calibration processing module 645 can enable in-phase clock duty cycle sensing (ID), quadrature clock duty cycle sensing (QD), then return to ID, and then return to QD before activating in-phase to quadrature phase (IQP). This principle can be further extended, for example, calibration processing module 645 can generate an enable sequence of ID, QD, ID, QD, ID, QD before activating IQP. In various implementations, enablement can be activated in different orders, and calibration processing module 645 generates an enable sequence such as QD, ID, IQP. In some examples, calibration processing module 645 can determine the enable sequence based, for example, on other factors such as the comparison amplitude of the duty cycle error signal or die temperature, rather than a fixed pattern.

[0101] In the illustrative example, the cki_Duty_dir and ckq_Duty_dir signals can be represented as 0 to increase the duty cycle and as 1 to decrease the duty cycle. Furthermore, ckiq_Phase_dir can be represented as 0 to delay the in-phase clock path and as 1 to delay the quadrature clock path.

[0102] Figure 7 An exemplary eye diagram illustrating clock jitter without a multiplexer clock phase calibration module is depicted. In the depicted example, the jitter measurement is 1.563 picoseconds.

[0103] Figure 8 An exemplary eye diagram illustrating clock jitter with a multiplexer clock phase calibration module is depicted. In the depicted example, the jitter measurement is 0.514 picoseconds. Reference Figure 7 , Figure 8 The measured value indicates a jitter reduction of approximately 67%.

[0104] Figure 9A and 9B An exemplary programmable integrated circuit (IC) on which the disclosed circuitry and processes can be implemented is depicted. Figure 9A and 9B The description will be combined. Figure 9A and 9B The connections between them are depicted as dots A, B, C, and D. The programmable IC 900 includes field-programmable gate array (FPGA) logic. The programmable IC 900 can be implemented using various programmable resources and can be referred to as a system-on-a-chip (SoC). The FPGA logic can include several different types of programmable logic blocks in the array.

[0105] For example, Figure 9A and Figure 9B The illustration depicts a programmable IC 900 comprising numerous different programmable slices, including a multi-gigabit transceiver (MGT) 901, a configurable logic block (CLB) 902, a block of random access memory (BRAM) 903, an input / output block (IOB) 904, configuration and clock logic (CONFIG / CLOCKS) 905, a digital signal processing block (DSP) 906, dedicated input / output blocks (I / O) 907 (e.g., clock ports), and other programmable logic 908 (e.g., digital clock manager, analog-to-digital converter, system monitoring logic). The programmable IC 900 includes a dedicated processor block (PROC) 910. The programmable IC 900 may include internal and external reconfiguration ports (not shown).

[0106] In various examples, the serializer / deserializer can be implemented using the MGT 901. The MGT 901 can include various data serializers and deserializers. The data serializer can include various multiplexer implementations. The data deserializer can include various demultiplexer implementations.

[0107] In some examples of FPGA logic, each programmable slice includes a programmable interconnect element (INT) 911 with standardized interconnects 924 leading to and from corresponding interconnect elements in each adjacent slice. Thus, the programmable interconnect elements employed together implement the programmable interconnect structure of the FPGA logic shown. The programmable interconnect element INT 911 includes internal connections 920 leading to and from programmable logic elements within the same slice, such as... Figure 9B The example included in Figure 9 shows that the programmable interconnect element INT 911 includes an inter-INT connection 922 to and from the programmable interconnect element INT 911 within the same segment.

[0108] For example, CLB 902 may include a configurable logic element (CLE) 912 that can be programmed to implement user logic, and a single programmable interconnect element INT 911. BRAM 903 may include a BRAM logic element (BRL) 913 and one or more programmable interconnect elements. In some examples, the number of interconnect elements included in a slice may depend on the height of the slice. In the illustrated embodiment, a BRAM slice has the same height as five CLBs, but other numbers (e.g., four) may also be used. DSP slice 906 may include a DSP logic element (DSPL) 914 and one or more programmable interconnect elements. IOB 904 may include, for example, two instances of input / output logic element (IOL) 915 and one instance of programmable interconnect element INT 911. For example, the actual I / O bonding pads connected to the I / O logic element 915 may be fabricated using metal layered above the various illustrated logic blocks and may not be limited to the area of ​​the input / output logic element 915.

[0109] In the illustrated implementation scheme, the columnar region near the center of the die ( Figure 9A (The shaded area in the graph) is used for configuration, clocking, and other control logic. The horizontal area 909, extending from the column, distributes clock and configuration signals across the width of the programmable IC. Note that the references to "bar" and "horizontal" areas are relative to viewing the graph in a portrait orientation.

[0110] Some use Figure 9A and Figure 9BThe programmable IC architecture shown includes additional logic blocks that break up the regular columnar structure that makes up most of the programmable IC. These additional logic blocks can be programmable blocks and / or dedicated logic. For example, Figure 9A The processor block PROC 910 shown spans multiple columns of CLB 902 and BRAM 903.

[0111] It should be pointed out that, Figure 9A and Figure 9B This is intended to illustrate only an example of a programmable IC architecture. The number of logic blocks in a column, the relative width of the columns, the number and order of the columns, the types of logic blocks contained in the columns, the relative sizes of the logic blocks, and the interconnect / logic implementation are provided purely as examples. For instance, in a real programmable IC, more than one adjacent column of CLB 902 can be included, regardless of where the CLB 902 appears, to facilitate efficient implementation of user logic.

[0112] Figure 10 A flowchart illustrating an exemplary clock phase alignment method is provided. The exemplary clock phase alignment method 1000 includes block 1005. At block 1005, in response to an in-phase clock signal (CKI) and a quadrature clock signal (CKQ), the clock phase alignment method 1000 generates a replicated serial data output signal (RDOUT) using a replicated multiplexer (RMUX). Execution then continues from block 1005 to block 1010. In block 1010, the clock phase alignment method 1000 receives clock signals CKI and CKQ via a DCC. The DCC may also receive the replicated serial data output signal (RDOUT). Next, method 1000 executes one of three decision blocks 1015, 1030, or 1045. Method 1000 can be executed iteratively, and can execute each of the three decision blocks in the execution queue. In various examples, method 1000 can execute each of the three decision blocks sequentially and periodically.

[0113] Method 1000 may execute decision block 1015. In decision block 1015, the method compares CKI with an inverted CKI. If the result is a signal with a duty cycle greater than or equal to 50%, the falling edge of CKI is delayed by an adjustable delay line at block 1020. If the result is a signal with a duty cycle less than 50%, the rising edge of CKI is delayed by an adjustable delay line at block 1025. Execution then continues to block 1060.

[0114] Method 1000 can execute decision block 1030. In decision block 1030, the method compares CKQ with an inverted CKQ. If the result is a signal with a duty cycle greater than or equal to 50%, the falling edge of CKQ is delayed by an adjustable delay line at block 1035. If the result is a signal with a duty cycle less than 50%, the rising edge of CKQ is delayed by an adjustable delay line at block 1040. Execution then continues to block 1060.

[0115] Method 1000 can execute decision block 1045. In decision block 1030, the method compares RDOUT with the inverted RDOUT. If the result is a signal with a duty cycle greater than or equal to 50%, the rising and falling edges of CKI are delayed by an adjustable delay line at block 1050. If the result is a signal with a duty cycle less than 50%, the rising and falling edges of CKQ are delayed by an adjustable delay line at block 1055. Execution then continues to block 1060.

[0116] At block 1060, method 1000, in response to CKI and CKQ, replicates the multiplexer operation of the replicated multiplexer using the master multiplexer (MMUX). Then, execution of method 1000 can be completed.

[0117] refer to Figure 5 The exemplary clock phase alignment method 1000 can be executed by the calibration processing module 510. The calibration processing module 510 can be implemented in hardware or software or a combination thereof.

[0118] While various embodiments have been described with reference to the accompanying drawings, other embodiments are also possible. For example, various embodiments may not be limited to four inputs to one output. Thus, the multiplexer may take 8, 16, 32, 64, or 128 bits or more as inputs and generate one output. Various embodiments may employ one or more 4-to-1 multiplexers connected in various configurations to achieve a wider input bus.

[0119] Various embodiments can generate delay control signals using a digital signal processor (DSP). For example, various differential signal pairs can be individually low-pass filtered, and the analog results are read by the DSP. The DSP can compare the analog results by executing pre-programmed instructions fetched from a storage device. The DSP can provide analog output signals to a compatible (analog input) delay line to further adjust the duty cycle and / or phase of a set of clocks. In some embodiments, the DSP can provide one or more digital output buses to the compatible (digital input) delay line. In various embodiments, the DSP can provide low-pass filtering. Furthermore, in some examples, the DSP can provide delay line functionality.

[0120] In various examples, clock timing skew may be reflected as output jitter in the MMUX and RMUX. Recommended clock calibration techniques can adjust / calibrate the CK. 0,180 Phase is optimized to minimize output jitter. The tuning resolution can be determined by the minimum adjustable range of the delay line. Therefore, the tuning loop can produce calibrated clock timing within the resolution of the delay line.

[0121] Various examples of modules can be implemented using circuitry, including a wide range of electronic hardware. By way of example, and not limitation, hardware may include transistors, resistors, capacitors, switches, integrated circuits, and / or other modules. In various examples, a module may include analog and / or digital logic, discrete components, traces, and / or memory circuitry fabricated on a silicon substrate including various integrated circuits (e.g., FPGAs, ASICs). In some embodiments, a module may relate to the execution of pre-programmed instructions and / or software executed by a processor. For example, various modules may involve both hardware and software.

[0122] In an exemplary aspect, a multiplexer clock calibration module can be adapted to track and compensate multiplexer clock inputs under dynamic operating conditions. The multiplexer clock calibration module may include a master multiplexer module (MMUX) configured to receive a first data signal array and operable to generate a master serial data output signal (MDout) by selecting one of the data signals in the first array in response to a multiphase MMUX control input. The multiplexer clock calibration module may include a replica multiplexer module (RMUX) fabricated together with the MMUX on a common substrate and configured to replicate the operation of the MMUX. The RMUX may be configured to receive a second data input array and can be used to generate a replica serial data output signal (RDout). The RMUX may be configured to generate RDout by selecting one of the data inputs in the second array in response to a multiphase RMUX control input. In various examples, the RMUX may be configured to simulate the operating characteristics of the MMUX over process, voltage, and temperature (PVT). RDout and MDout may each be formed as differential signals.

[0123] The multiplexer clock calibration module may include a duty cycle calibration module (DCC) comprising three signal processing circuits. Each signal processing circuit may include at least one low-pass filter (LPF) coupled to a differential error amplifier. The DCC may be configured to generate a first delay control signal and a second delay control signal in response to RDout to adjust the phase relationship between the in-phase clock signal (CKI) and the quadrature clock signal (CKQ).

[0124] The multiplexer clock calibration module may include an adjustable delay line module (ADLM) configured to generate CKI and CKQ signals. The ADLM may include a first adjustable delay line module adapted to delay the system in-phase clock signal (CKQ) in response to a first delay control signal. 0,180 The ADLM may include a second adjustable delay line module adapted to delay the system quadrature clock signal (CK) in response to a second delay control signal. 90,270 The multiphase MMUX control input and multiphase RMUX control input are operably connected to the ADLM to receive the CKI and CKQ clock signals.

[0125] The DCC can be configured to dynamically modulate only the first delay control signal during a first portion of the time interval. The DCC can be configured to dynamically modulate only the second delay control signal during a second portion of the time interval. The DCC can be configured to dynamically modulate both the first and second delay control signals during a third portion of the time interval. The first, second, and third portions may not overlap.

[0126] In some embodiments, each of the first and second adjustable delay line modules may include a voltage-controlled delay line. In various examples, the DCC may be configured to inject an offset voltage into at least one of a first delay control signal and a second delay control signal to adjust at least one of the voltage-controlled delay lines in response to a change in the duty cycle of RDout relative to a 50% duty cycle.

[0127] DCC can be configured to repeat dynamic modulation over multiple time intervals. A first adjustable delay line module may include a delay line adapted to modulate the duty cycle of CKI in response to a first delay control signal, and a second adjustable delay line module may include a delay line adapted to modulate the duty cycle of CKQ in response to a second delay control signal.

[0128] In some implementations, the first and second adjustable delay line modules can be configured to modulate the phase relationship between CKI and CKQ by modulating the timing between the rising or falling edge of CKI relative to the rising or falling edge of CKQ. When modulating the timing between the rising or falling edges of CKI relative to the rising or falling edge of CKQ, the duty cycles of CKI and CKQ can remain substantially the same. The data input in the second array can be configured to form RDout as a square wave clock signal with a frequency twice that of either CKI or CKQ, and a substantially 50% duty cycle.

[0129] The following description Figure 11-18A method for calibrating a master circuit using a replication circuit is provided, wherein the master circuit is used to perform a predetermined function (e.g., converting parallel data into serial data) and the replication circuit is configured to replicate specific functions and timing (e.g., clock delay, signal delay, rise time, fall time) of the master circuit, thereby performing the replication function of the master circuit. As shown below... Figure 11-18 The circuits and methods described herein can be embedded in any circuit device with master and replica circuitry, including master and replica serializer circuitry that can be implemented in a MUX. Calibration schemes are commonly used in integrated circuits to measure electrical characteristics such as offset voltage, timing mismatch, and impedance. Once these characteristics are measured, appropriate correction / adaptation schemes can be used to tune the performance of these circuits to the desired state. While it may be best to perform calibration on the actual circuit being calibrated, replica circuitry can also be used. As described in more detail below, replica circuitry is a copy of the actual circuitry to provide the same functionality and timing, and it may or may not be scaled to mimic the behavior of the actual circuitry. For example, replica circuitry may be required due to limitations in input mode, loading, or layout. That is, any attempt to use the master circuitry to obtain information that can be used for master circuitry calibration may interrupt or otherwise adversely affect the operation of the master circuitry. While a serializer circuitry implemented in a MUX is provided as an example, it should be understood that this circuitry and method can be applied to any function implemented in a circuit.

[0130] The circuits and methods described below illustrate an energy-efficient approach to calibrating circuits, including, for example, in-phase (I) and quadrature (Q) clock signals, collectively referred to as IQ clock signals or IQ. According to an implementation, IQ mismatch of a transmitter (TX) employing a low-power 4-to-1 multiplexer (MUX) is described. As mentioned above, a 4-to-1 multiplexer is used instead of a 2-to-1 multiplexer as the final serialization stage of the TX because it eliminates the need for a 2T clock (where T is the bit period), which is less power efficient in a given technology compared to the 4T clock required by a 4-to-1 multiplexer. Figure 2 As shown in the timing diagram, the low-power 4-to-1 multiplexer uses four phases of a 4T clock, namely phases 0, 90, 180, and 270, to serialize 4T parallel data into a 1T bit stream without generating a 1T pulse.

[0131] like Figure 2As seen in the low-power 4-to-1 MUX schematic, in addition to the clock skew between phases, there is also a delay mismatch between the MUX's I-path (tied using clock signal phases 0 and 180) and Q-path (tied using clock signal phases 90 and 270). If this IQ mismatch is not calibrated, it will manifest as deterministic jitter (DJ) at the TX output. Deterministic jitter can degrade link performance, especially for high-speed transceivers operating at, for example, 112 Gb / s. However, IQ mismatch information can be obtained by sending a fixed pattern (e.g., a 1010 pattern) to the four inputs of the 4-to-1 MUX. The IQ mismatch can be determined by observing the pulse width of the serialized 1010 pattern at the output. Since restricting the input patterns of the link is unhelpful, and stopping the real-time flow of the main circuit for calibration is impractical, a duplicate 4-to-1 MUX is used for IQ calibration when such a 4-to-1 MUX is used as the main circuit. Because the duplicated path mimics the electrical characteristics of the actual path, it limits the minimum size of the MUX. In other words, since smaller sizes translate to higher IQ mismatches, larger replication MUXs can be used to minimize the mismatch.

[0132] However, if the size of the MUX results in a mismatch between the actual circuitry and the replica circuitry within the allocated TX DJ budget, high clock power may be required, thus defeating the original low-power design intent. To overcome any limitations in replica circuitry size relative to the master circuitry, Figure 11-18 The circuitry and method described below implement a two-stage calibration scheme. First, a foreground calibration is performed on the main circuit to measure the actual IQ mismatch. Since the calibration is performed in the foreground (i.e., during operation before the main circuit is used for its intended function, such as providing serialized data via a serializer), there are no restrictions on the input mode of the 4 to 1 MUX. A smaller, replicated 4 to 1 MUX with a fixed input mode can also be used for background calibration to track variations in operating conditions, such as voltage and temperature (VT) drift during actual circuit operation (which may be referred to as task-mode operation). Since voltage and temperature affect the electrical characteristics of transistors in the circuit, such as mobility and threshold voltage, in a deterministic manner, even a small replicated MUX should provide first-order VT drift tracking. That is, even if a small replicated MUX exhibits a large random mismatch, any size limitations of a replicated 4 to 1 MUX can be eliminated by combining the two stages of calibration to minimize the IQ mismatch, thereby enabling a reduction in clock power resulting from the use of a 4 to 1 MUX. The circuitry and method described below divide the continuous calibration using the replicated circuitry into a foreground calibration using the actual circuitry and a background calibration using the replicated circuitry. By doing so, low-power operation can be achieved, where the replica circuit does not need to be larger than the main circuit and can be smaller than the main circuit (e.g., a smaller transistor).

[0133] Figure 11 A block diagram of a circuit arrangement for calibrating a master circuit using a replication circuit is depicted. More specifically, the circuit arrangement 1100 includes a master circuit 1102 and a replication circuit 1104, wherein the master circuit 1102 is configured to provide functionality, and the replication circuit is also configured to provide the same functionality and to perform calibration on the master circuit 1102. The master circuit 1102 is configured to receive input data at input 1106 and generate output data at output 1108, wherein the output data is also provided to a selection circuit 1110, shown here as a multiplexer by way of example, at input 1112. As will be described in more detail below, the selection circuit 1110 enables selection of the outputs of the master circuit and the replication circuit during the foreground and background phases of calibration in response to a selection control signal. The replication circuit 1104 is configured to receive calibration data at input 1114 and generate calibration output data at output 1116, wherein the calibration output data is provided to the selection circuit 1110 at input 1118. As will be described in more detail below, for example, calibration data provided to the replication circuit input may include a fixed data pattern. Calibration circuit 1120 is configured to provide a control signal to input 1122 to generate a signal at output 1124 that is provided to inputs 1112 and 1118. Calibration circuit 1120 may generate a correction code as described in more detail below. The control signal (e.g., based on the correction code) is then provided to main circuit 1102, which may also be based on the correction code. The control signal may control any aspect of the main circuit to change its operation or performance, including electrical characteristics such as offset voltage, timing mismatch, impedance, signal phase, signal frequency, and signal duty cycle.

[0134] According to one embodiment, the calibration circuit 1120 can operate in two stages. The calibration circuit 1120 can control the selection circuit 1110 at different stages to detect the outputs of the main circuit and the replication circuit, and generate control signals during main circuit operation to provide to the main circuit and the replication circuit without interrupting the input data stream of the main circuit. More specifically, a foreground calibration (i.e., calibration performed before the main circuit operates to implement its normal function, wherein the main circuit implements its normal function after the initial calibration operation to obtain the initial calibration code of the main circuit) is performed at block 1202. During the foreground calibration of the main circuit, control signals are provided to the selection circuit to enable the foreground calibration of the main circuit. It should be noted that the calibration function may depend on the functionality of the main circuit and can be used to initially calibrate the main circuit to make it operate correctly by changing any adjustable parameters to alter the operation or performance of the main circuit (e.g., adjusting the voltage, frequency, phase, duty cycle, or offset of the clock signal). For the parameter, an initial value is determined for the parameter being calculated, wherein the initial value can be adjusted during normal operation of the main circuit (i.e., during the background calibration phase, and for example based on a correction code).

[0135] Then, at block 1204, a foreground calibration of the replication path is performed on the replication circuit to determine the initial values ​​of the replication circuit parameters. Specifically, control signals generated by the calibration circuit enable the selection of the replication circuit output to be received by the calibration circuit during the foreground calibration. Initial values ​​for parameters associated with the replication circuit can be determined, such as an initial correction code. Changes in the replication circuit parameter values ​​relative to the initial values ​​can then be monitored, where these changes are used to determine changes in the operating environment, such as voltage or temperature variations. More specifically, a background calibration is performed on the replication circuit during block 1206 to determine changes in the operating environment.

[0136] The main circuit can then be calibrated based on detected changes in parameters associated with the replication circuit. That is, changes in parameters associated with the replication circuit detected during background calibration are used to adjust the parameters of the main circuit in step 1208. For example, the parameters of the main circuit are adjusted based on changes detected in the same parameters of the replication circuit. According to one embodiment, parameters associated with a clock signal, such as the phase of a clock signal for a transmitter circuit (e.g., a serializer circuit for receiving parallel data and generating serial data), can be adjusted during background calibration of the transmitter circuit based on changes detected during background calibration of the replication circuit. For example, a calibration clock signal as described above can be generated by a calibration circuit and provided to the main circuit. Reference is made below. Figure 19 Additional examples describing foreground and background calibration.

[0137] Figure 13 Another flowchart illustrating a method for calibrating circuitry for receiving input data and generating output data is shown. At block 1302, the main circuitry is configured to receive input data at a first input and generate output data at a first output, wherein the output data is based on the input data and the functionality of the main circuitry. At block 1304, a replication circuitry is configured to receive calibration data at a second input and generate calibration output data at a second output based on the calibration data, wherein the replication circuitry provides a replication function of the main circuitry. At block 1306, the calibration circuitry is configured to receive output data from the main circuitry during a foreground calibration mode and calibration output data from the replication circuitry during a background calibration mode. At block 1308, the calibration circuitry provides control signals to the main circuitry and the replication circuitry during the background calibration mode to enable calibration of the main circuitry.

[0138] The method may further include configuring a selection circuit to receive output data from a main circuit and calibration output data from a replication circuit, wherein the selection circuit controls the selection of output data and calibration output data during a foreground calibration mode. The main circuit may include a first serializer circuit configured to receive parallel input data and generate serial output data, wherein the first serializer circuit generates serial output data during an operation mode. The replication circuit may include a second serializer circuit configured to receive parallel test data and generate calibration output data during an operation mode. Background calibration may run continuously or periodically during an operation mode. The method may further include configuring a calibration circuit to receive multiple clock phases of an input clock signal and coupling a calibration clock signal generated by the calibration circuit to a first control terminal of the main circuit and a second control terminal of the replication circuit.

[0139] The calibration circuit can also be configured to receive the output of the replication circuit during a foreground calibration mode to determine an initial replication calibration code, and to receive the output of the replication circuit during a background calibration mode to determine an updated replication calibration code. The method may further include determining the difference between the initial replication calibration code and the updated replication calibration code. Based on the initial calibration code of the main circuit and the difference between the initial and updated replication calibration codes, a correction control signal can then be provided to the main circuit and the replication circuit, wherein the correction control signal includes a correction clock signal.

[0140] Figure 11-13 The circuits and methods described herein can be extended to any calibration scheme that requires a replicated path due to input pattern constraints (e.g., the inability to pause data input to the main circuit for calibration). Furthermore, any mismatch issues can be avoided by using foreground calibration and subsequently using the replicated path to track any system variations caused by changes in the operating environment. The circuits and methods described can be used with any type of circuit where environmental changes (e.g., voltage and temperature) cause deterministic and unidirectional variations in the paths of the actual circuit and the replicated circuit.

[0141] Figure 14 Another block diagram depicts a circuit arrangement 1400 for calibrating a serializer circuit that receives parallel data and generates serial data. A master serializer circuit 1402 and a replica serializer circuit 1404 (shown here as an example of a 4:1 serializer circuit) are configured to receive parallel data and generate serial data. More specifically, the master serializer circuit 1402 is configured to receive parallel input data at input 1406 and generate serial data at output 1410. The master serializer circuit 1402 is used to receive parallel input data during normal operation of the serializer circuit (i.e., operation of the serializer circuit after performing foreground calibration). The replica serializer circuit 1404 is configured to receive calibration data at input 1412 and generate serialized data at output 1414.

[0142] Selection circuit 1416 (shown as a multiplexer by way of example) is configured to receive the output of master serializer circuit 1402 at input 1418 and the output of replica serializer at input 1420. A selection control signal provided to control input 1422 generates at output 1424 either a signal coupled to input 1418 or a signal coupled to input 1420, selected as one of the two signals. Calibration circuit 1426 is coupled to receive the selection signal generated at the output of selection circuit 1416, wherein calibration circuit 1426 generates the selection control signal provided to the control input of selection circuit 1416. Calibration circuit also receives an input clock signal, shown here by example as four in-phase and quadrature (I and Q) phases 1428 of the clock signal, designated CLK0, CLK90, CLK180, and CLK270. The calibration circuit 1426 generates an output clock signal (e.g., a correction clock signal) at output 1430 that may have different electrical characteristics (e.g., offset voltage, timing mismatch, frequency, phase, or impedance) and provides it to selection inputs 1432 and 1434. The calibration circuit 1426 can generate a correction code as described in more detail below. For example, the output clock signal can be a delayed clock signal. The output clock signal generated by the calibration circuit can be as described above (reference provided). Figure 3-10 It is generated as described.

[0143] Therefore, with 4 to 1 MUX Figure 14 The circuitry can be used for the final serialization stage of a transmitter timed by four phases (0, 90, 180, 270) of a 4T clock, where T is the bit period. Using only a 4T clock for 4-to-1 serialization provides significant energy savings in clock generation and propagation because it eliminates the need for higher frequency clocks. However, as mentioned above, this topology has an inherent IQ mismatch that needs to be calibrated. Since a fixed input mode may be advantageous for calibrating a 4-to-1 MUX, a replication path can be used, allowing calibration to continue continuously to track, for example, voltage and temperature drift.

[0144] Figure 15 Another block diagram depicts a circuit arrangement 1500 for calibrating a serializer circuit that receives parallel data and generates serial data. Figure 15 The implementation method is similar to Figure 14 The implementation, but including a first-stage serializer circuit 1502, shown as an N:4 serializer by way of example, is configured to receive parallel input data at multiple inputs 1504 and generate an output at output 1506. The output 1506 of the first-stage serializer 1502 is provided to the input of a serializer circuit 1508, shown here as a 4:1 serializer circuit by way of example, wherein serialized output data is generated at output 1510 in response to a clock signal provided to the control input 1512 of the serializer circuit 1508.

[0145] The replica serializer circuit 1514 is configured to receive an input signal at input 1516, shown as a fixed input pattern "1010" for example, and its output is generated at output 1518 in response to a clock signal provided to control terminal 1520. The output 1510 of serializer circuit 1508 and the output 1518 of replica serializer 1514 are coupled to selection circuit 1522 at inputs 1524 and 1526, shown here as a multiplexer for example. A selection control signal provided to control terminal 1528 enables selection of one of the signals provided to inputs 1524 and 1526, which is generated at output 1530 and coupled to calibration circuit 1532.

[0146] The calibration circuit 1532 includes an IQ detection circuit 1534 and an IQ correction circuit 1536. Figure 16 An example of the IQ detection circuit 1534 is shown in the figure. Figure 17 An example of IQ correction 1536 is shown. Although Figure 16 and 17 The circuit is shown as an example, but it should be understood that other IQ detection and IQ correction circuits can be implemented. The calibration circuit 1532 is adapted to receive the input clock 1538 (CK0, CK...). 90 CK 180 CK 270 The calibration clock signal is generated at output 1540 and coupled to control terminals 1512 and 1520 to select the inputs of the master serializer circuit 1508 and the replica serializer circuit 1514, which are coupled to selection circuit 1522. That is, as part of the calibration process, the calibration clock signal is provided to the master circuit at least once, and the calibration circuit 1532 enables the operation of the master circuit based on the detected IQ mismatch and the corrected IQ mismatch. IQ detection circuit 1534 and IQ correction circuit 1536 can... Figure 5 The DDC circuit 500 is implemented to generate in-phase to quadrature alignment.

[0147] Figure 16 An exemplary block diagram is depicted of a circuit that can provide IQ mismatch detection to detect clock signals (I(CK0), Q(CK0)). 90 ), Ib(CK) 180 ), Qb(CK) 270The IQ detection circuit 1600 includes a first detection block 1602 and a second detection block 1604. The first detection block 1602 includes an output node 1605 coupled to a first terminal of a resistor 1606 (having a second terminal coupled to a power reference node) and a first terminal of a capacitor 1607 (having a second terminal coupled to a ground node). The first detection block also includes multiple signal paths between nodes 1605 and 1608 coupled to a current source 1610 providing a current path to ground. The multiple signal paths include a first signal path having a first transistor 1611 with a gate coupled to receive an I clock signal, and a second transistor 1612 coupled in series to receive a Qb clock signal. The second signal path includes a first transistor 1614, which has a gate coupled to receive a Qb clock signal. The first transistor 1614 is connected in series with a second transistor 1616, which has a gate coupled to receive an I clock signal. The third signal path includes a first transistor 1618, which has a gate coupled to receive a Q clock signal. The first transistor 1618 is connected in series with a second transistor 1620, which has a gate coupled to receive an Ib clock signal. The fourth signal path includes a first transistor 1622, which has a gate coupled to receive an Ib clock signal. The first transistor 1622 is connected in series with a second transistor 1624, which has a gate coupled to receive a Qb clock signal.

[0148] The second detection block 1604 includes an output node 1625 coupled to a first terminal of a resistor 1626 (having a second terminal coupled to a power supply reference node) and coupled to a first terminal of a capacitor 1627 (having a second terminal coupled to a ground node). Multiple signal paths of the second detection block 1604 include a first signal path having a first transistor 1630 with a gate coupled to receive an I clock signal, and a second transistor 1632 coupled in series with a gate coupled to receive a Q clock signal. A second signal path includes a first transistor 1634 with a gate coupled to receive a Q clock signal, and a second transistor 1636 coupled in series with a gate coupled to receive an I clock signal. The third signal path includes a first transistor 1638, which has a gate coupled to receive the QB clock signal. The first transistor 1638 is connected in series with a second transistor 1640, which has a gate coupled to receive the Ib clock signal. The fourth signal path includes a first transistor 1642, which has a gate coupled to receive the Ib clock signal. The first transistor 1642 is connected in series with a second transistor 1644, which has a gate coupled to receive the Qb clock signal. A detection circuit 1646 is coupled to nodes 1605 and 1625 to detect the voltage difference in the nodes. If I and Q are perfectly balanced, the voltages are the same. If not, the I and Q clock signals are corrected. According to one embodiment, for example, a... Figure 17 An IQ mismatch correction circuit is used to correct the I and Q signals.

[0149] Figure 17An exemplary block diagram of a circuit 1700 that can provide IQ correction is depicted. Circuit 1700 includes a first circuit 1701 adapted to correct clock CK_I and a second circuit 1702 adapted to correct clock CK_Q. The first circuit 1701 includes a first series of transistors 1703 adapted to generate a delayed clock signal based on an input clock signal. More specifically, a p-channel transistor 1704 is coupled between a reference voltage and a second p-channel transistor 1706. As shown, an n-channel transistor 1708 is also coupled in series with transistor 1706 and includes a gate coupled to the gate of transistor 1706. An n-channel transistor 1710 is coupled to transistor 1708. Transistor 1704 includes a gate configured to receive the output of a digital-to-analog converter (DAC) 1712, and transistor 1710 is configured to receive the output of DAC 1714. Circuit 1701 also includes a series of inverters 1716-1720 for generating corrected output signals with various delays, where t1 is generated at the output of inverter 1716, t2 at the output of inverter 1717, t3 at the output of inverter 1718, and t4 at the output of inverter 1720. The gates of transistors 1706 and 1708 are coupled together at the output of inverter 1716, while the drains of transistors 1706 and 1708 are coupled together at the output of inverter 1717.

[0150] The first circuit 1701 includes a second series of transistors 1722 adapted to generate a delayed clock signal based on an input clock signal. More specifically, a p-channel transistor 1724 is coupled between a reference voltage and a second p-channel transistor 1726. As shown, an n-channel transistor 1728 is also coupled in series with transistor 1726 and includes a gate coupled to the gate of transistor 1726. An n-channel transistor 1730 is coupled to transistor 1728. Transistor 1724 includes a gate configured to receive the output of a digital-to-analog converter (DAC) 1732, and transistor 1730 is configured to receive the output of DAC 1734. The gates of transistors 1726 and 1728 are coupled together at the output of an inverter 1717, while the drains of transistors 1726 and 1728 are coupled together at the output of an inverter 1717. The second circuit 1702 is configured in the same manner as the first circuit 1701, but is adapted to receive a clock signal CK_Q.

[0151] Inverters 1716-1720 introduce a delay associated with the clock edges of the inputs to the first circuit 1701 and the second circuit 1702 to eliminate IQ mismatch. DACs 1712, 1714, 1732, and 1734 represent digital codes used to change the rising and falling edges of the clock. These can be used... Figure 16The IQ detection circuit iteratively adjusts the digital code to reduce or eliminate IQ mismatch.

[0152] Figure 18 A graph showing the mismatch as a function of size (N) is plotted with respect to simulation and 1 / sqrt(N), where N is related to the size of the replica circuit. Figure 18 As shown, timing mismatch is inversely proportional to 1 / sqrt(area), and reducing mismatch by increasing size is an energy-intensive task. For example, to reduce timing mismatch to half, the area must be increased by four times. The circuit and method using a two-stage calibration process eliminate the need for large replication circuits implemented to reduce timing mismatch. Furthermore, the simulation results shown in Table 1 demonstrate the benefits of using a two-stage calibration process, such as reducing IQ mismatch based on VT tracking. The simulation measured 4 to 1 MUX IQ errors with random mismatch. When compared to VT drift without replication path tracking, the average IQ error is reduced from ~300 fs to ~100 fs, and the sigma value is halved from ~130 fs to ~60 fs.

[0153]

[0154] Table 1

[0155] Figure 19 A flowchart illustrating a method for performing circuit calibration is provided. Figure 19 The method performs a two-step calibration process, including a first calibration mode comprising a foreground calibration mode and a second calibration mode comprising a background calibration mode. The foreground calibration mode is performed before the circuit being calibrated operates in its operating mode. For example, the operating mode of a serializer circuit would be when the serializer circuit receives parallel data converted to serial data. The background calibration mode is performed during the operating mode of the circuit being calibrated. Figure 19 The method can be used as described above. Figure 11 , 14 And 15 circuits, or some other suitable circuits to achieve this.

[0156] At block 1902, foreground calibration is enabled. For example, this is enabled in response to the startup or reset of a device with the circuit being calibrated, or during the startup or reset of the circuit being calibrated. At block 1904, the "copy" signal is set to 0, indicating that IQ testing should be performed on the data associated with the circuit being calibrated (i.e., the master circuit receives the data and performs calibration on the data during foreground calibration). For example, see the reference above. Figure 11 , 14As described in 15, the replication signal can be provided to the selection control terminal of the selection circuit, which is configured to receive the output of either the main circuit or the replication circuit. Then, IQ detection is performed on the main circuit at block 1906. For example, as referenced above... Figure 16 As described, during IQ detection, changes in the clock edges of different phases of the clock signal can be detected, and then IQ correction is performed during the iteration process (e.g., as mentioned above). Figure 17 As described, IQ correction is performed at block 1910. Therefore, it is then determined at block 1908 whether IQ correction has been completed for the main circuit. If variations in the clock edges of different phases of the clock signal may require correction, indicating that IQ correction for the path may also be necessary, then IQ correction will be performed at block 1910. After IQ correction for the main circuit correction is complete, the initial correction code for the main circuit (which may be an IQ correction code) is set to equal N at block 1912. As will be described in more detail below, the initial correction code N represents the current correction code, which can be adjusted or updated during the main circuit's operating mode based on changes in the replicated circuitry during background calibration.

[0157] Then, at block 1914, the replication signal is set to "1" to perform IQ correction for the replication circuit by resetting the replication correction code at block 1916. The replication correction code can be, for example, a replication IQ correction code, and IQ detection associated with the replication circuit is performed at block 1918. Then, at block 1920, it is determined whether the IQ correction for the replication circuit is complete. If not, IQ correction is performed at block 1922, and subsequently, IQ detection is performed iteratively at block 1918 until the IQ mismatch has been corrected. After determining that the IQ correction for the replication circuit is complete at block 1920, the replication correction code (which can be a replication IQ correction code) is set to R0 at block 1924, where R0 represents the initial replication correction code for the replication circuit. As will be described in more detail below, the initial replication correction code for the replication circuit can be used to determine changes in the replication circuit, for example, due to voltage or temperature, where the detected changes in the replication circuit are used to update or correct the correction code for the main circuit.

[0158] More specifically, after determining the replication correction code at block 1924, background calibration is enabled at block 1926. Then, IQ detection is performed on the replication circuit at block 1928 to determine whether the IQ correction code of the main circuit should be updated at block 1930. That is, if there is no change in the replication correction code based on IQ detection step 1928, the correction code of the main circuit remains at N at block 1932, and the process performs IQ detection at block 1928. However, if it is determined at block 1930 that an IQ code update is necessary, the updated replication correction code (which could be the updated IQ replication correction code) is set to equal Rn at block 1934. Then, the updated correction code of the main circuit (which could be the updated IQ correction code) is set to Nnew = N + (Rn - R0) at block 1936, and IQ correction is performed at block 1938. Therefore, Figure 19 The method approximates changes in the master circuit's calibration code based on variations in the replication circuit's operation during the master circuit's operating mode, which may be caused by changes in voltage or temperature, for example. Therefore, to circumvent size constraints imposed by timing mismatches, a two-stage calibration scheme can be implemented. The calibration code can be used to control and generate control signals provided to the master and replication circuits, such as controlling the clock signals provided to the master and replication circuits, where rising and falling edges can be, for example, as shown in the example... Figure 17 Adjustment is performed using the DAC value as described in [the text]. Although in [the text] Figure 19 The IQ correction code and IQ correction are described with examples, but it should be understood that... Figure 19 The method can involve any type of correction code provided to the main circuit and the replication circuit in response to the need for correction of any type of circuit operation.

[0159] Many embodiments have been described. However, it should be understood that various modifications can be made. For example, advantageous results may be obtained if the steps of the disclosed technology are performed in a different order, or if the components of the disclosed system are combined in a different manner, or if the components are supplemented with other components. Therefore, other embodiments are also covered within the scope of the following claims.

Claims

1. A circuit apparatus for calibrating circuits in an integrated circuit device, characterized in that, The circuit device includes: A main circuit configured to receive input data at a first input and generate output data at a first output, wherein the output data is based on the input data and the function of the main circuit; A replication circuit configured to receive calibration data at a second input and generate calibration output data at a second output based on the calibration data, wherein the replication circuit provides a replication function of the main circuit; and A calibration circuit configured to receive the output data from the main circuit during a foreground calibration mode and the calibration output data from the replication circuit during a background calibration mode. The calibration circuit is coupled to the main circuit and the replication circuit, wherein the calibration circuit is configured to provide control signals to the main circuit and the replication circuit during the background calibration mode.

2. The circuit device according to claim 1, characterized in that, The circuitry also includes a selection circuit configured to receive the output data from the main circuit and the calibration output data from the replication circuit, wherein the selection circuit controls the selection of the output data and the calibration output data during the foreground calibration mode.

3. The circuit device according to claim 1, characterized in that, The main circuit includes a first serializer circuit configured to receive parallel input data and generate serial output data, wherein the first serializer circuit generates the serial output data during an operation mode.

4. The circuit device according to claim 3, characterized in that, The replication circuit includes a second serializer circuit configured to receive a parallel test mode and generate the calibration output data during the operation mode.

5. The circuit device according to claim 4, characterized in that, The calibration circuit is configured as follows: Multiple error signals are generated based on the duty cycle of one or more differential pairs of input signals being equal to or greater than 50%. as well as Based on the multiple error signals, multiple correction signals are generated to adjust the duty cycle and phase of the in-phase clock, wherein the in-phase clock is one of the input signals.

6. The circuit device according to claim 1, characterized in that, The calibration circuit is configured to receive the calibration output data of the replication circuit during the foreground calibration mode to determine an initial replication correction code.

7. The circuit device according to claim 6, characterized in that, The calibration circuit is configured to receive calibration output data from the replication circuit during the background calibration mode to determine the updated replication correction code.

8. The circuit device according to claim 7, characterized in that, The calibration circuit determines the difference between the initial copy correction code and the updated copy correction code.

9. The circuit device according to claim 8, characterized in that, The calibration circuit generates a calibration control signal that is sent to the main circuit and the replication circuit based on the initial calibration correction code for the main circuit and the difference between the initial replication correction code and the updated replication correction code.

10. The circuit device according to claim 9, characterized in that, The correction control signal includes a correction clock signal.

11. A method for calibrating circuits in an integrated circuit device, characterized in that, The method includes: The main circuit is configured to receive input data at a first input and generate output data at a first output, wherein the output data is based on the input data and the functionality of the main circuit. The replication circuit is configured to receive calibration data at a second input and generate calibration output data at a second output based on the calibration data, wherein the replication circuit provides a replication function of the main circuit; and The calibration circuit is configured to receive the output data from the main circuit during foreground calibration mode and the calibration output data from the replication circuit during background calibration mode. The calibration circuit is coupled to the main circuit and the replication circuit, wherein the calibration circuit is configured to provide control signals to the main circuit and the replication circuit during the background calibration mode.

12. The method according to claim 11, characterized in that, The method further includes: configuring a selection circuit to receive the output data from the main circuit and the calibration output data from the replication circuit, wherein the selection circuit controls the selection of the output data and the calibration output data during the foreground calibration mode, wherein the main circuit includes a first serializer circuit configured to receive parallel input data and generate serial output data, wherein the first serializer circuit generates the serial output data during an operation mode, and wherein the replication circuit includes a second serializer circuit configured to receive a parallel test mode and generate the calibration output data during the operation mode.

13. The method according to claim 12, characterized in that, The method further includes: Multiple error signals are generated based on the duty cycle of a difference pair of one or more input signals being equal to or greater than 50%; and Based on the multiple error signals, multiple correction signals are generated to adjust the duty cycle and phase of the in-phase clock, wherein the in-phase clock is one of the input signals.

14. The method according to claim 11, characterized in that, The calibration circuit is configured to receive the calibration output data of the replication circuit during the foreground calibration mode to determine an initial replication correction code, and wherein the calibration circuit is configured to receive the calibration output data of the replication circuit during the background calibration mode to determine an updated replication correction code.

15. The method according to claim 14, characterized in that, The method further includes: determining the difference between the initial replication correction code and the updated replication correction code, and generating a correction control signal sent to the main circuit and the replication circuit based on the initial correction code for the main circuit and the difference between the initial replication correction code and the updated replication correction code.

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