Integrated circuit device having multiple stacked dies

Abstract

An integrated circuit device having a plurality of stacked dies is described. The integrated circuit device includes a first die of the plurality of stacked dies, the first die having an input / output element configured to receive an input signal, the first die including a signal drive circuit configured to provide the input signal to each die of the plurality of stacked dies, and a chip select circuit to generate a plurality of chip select signals for the plurality of stacked dies; a second die of the plurality of stacked dies coupled to the first die, the second die having a functional block configured to receive the input signal; wherein the second die receives the input signal in response to a chip select signal of the plurality of chip select signals corresponding to the second die. A method of implementing an integrated circuit device having a plurality of stacked dies is also described herein.

Description

Technical Field

[0001] This invention relates generally to integrated circuit devices, and more particularly to integrated circuit devices having multiple stacked dies and methods for implementing integrated circuit devices having multiple stacked dies. Background Technology

[0002] As the size, power, and performance of integrated circuit devices decrease, the implementation methods of integrated circuit devices are constantly evolving. Different types of integrated circuit devices can include multiple dies, often referred to as chips. Integrated circuit devices with multiple dies are often referred to as 3D integrated circuit devices. Some 3D integrated circuit devices with multiple dies may include an interposer and are often referred to as devices implementing Stacked Silicon Interconnect Technology (SSIT). For example, multiple dies can be placed individually on the surface of the interposer instead of being stacked on top of each other. Microbumps and through-silicon vias (TSVs) can be used to connect each die to the interposer. However, the size of microbumps can limit the connectivity between dies. More recent 3D IC devices may not include a silicon interposer, where the connectivity between dies is provided by direct interconnects, which can be achieved by using hybrid bumps and TSVs. Hybrid bumps are typically smaller than microbumps, allowing for more connections to be established between chips.

[0003] While stacking dies in a stacked integrated circuit device increases the logic capacity of the integrated circuit device, it also reduces the die edge width and die surface area, which includes the contact pads of the die itself that can be accessed by the contacts of the integrated circuit device itself. Due to this reduction in die surface area, fewer pads on the top of the die, accessible from the contacts on the stacked integrated circuit device, are available for testing and other access to the die of the integrated circuit device. Because of the reduced number of available pads on the top die, the number of power and ground pads on the top die may have to be reduced compared to a conventional monolithic integrated circuit device or an integrated circuit device with multiple dies individually placed on a surface of an interposer. The availability of input / output (IO) contacts (often referred to as IO pads) on the top die may also affect some essential functions of the stacked IC device, such as test functions.

[0004] Therefore, there is a need for a circuit and method for implementing an integrated circuit device with stacked dies to overcome problems associated with stacked dies, such as the problem of reduced number of I / O contacts on the top die of the stack. Summary of the Invention

[0005] An integrated circuit device having multiple stacked dies is described. The integrated circuit device includes a first die among multiple stacked dies, the first die having input / output elements configured to receive input signals, the first die including signal driving circuitry and chip select circuitry, the signal driving circuitry being configured to provide an input signal to each of the multiple stacked dies, and the chip select circuitry being configured to generate multiple chip select signals for the multiple stacked dies; and a second die among the multiple stacked dies coupled to the first die, the second die having a functional block configured to receive input signals; wherein the second die receives the input signal in response to one of the multiple chip select signals corresponding to the second die.

[0006] A method for implementing an integrated circuit device having multiple stacked dies is also described. The method includes configuring a first die among the multiple stacked dies to receive an input signal at an input / output element; configuring signal driving circuitry on the first die to provide the input signal to each of the multiple stacked dies; configuring chip select circuitry to generate multiple chip select signals for the multiple stacked dies; coupling a second die among the multiple stacked dies to the first die, the second die having a functional block configured to receive the input signal; and receiving the input signal on the second die in response to one of the chip select signals corresponding to the second die. Attached Figure Description

[0007] Figure 1 This is a block diagram of an exemplary stacked integrated circuit device;

[0008] Figure 2 This is a cross-sectional view of an exemplary stacked integrated circuit device, for example... Figure 1 Integrated circuit devices;

[0009] Figure 3 It is a block diagram of a portion of an integrated circuit device having stacked integrated circuit dies;

[0010] Figure 4 It is a block diagram of a chip selection circuit that can be implemented in a bare die of a stacked integrated circuit device;

[0011] Figure 5 This is another block diagram of an integrated circuit device with stacked integrated circuit dies;

[0012] Figure 6 It is a block diagram of a signal driving circuit used to transmit signals between dies of integrated circuit devices implemented in stacked integrated circuit devices;

[0013] Figure 7 This is an example data diagram that can be transmitted using a shift register of a signal-driven circuit that can be implemented in the die of a stacked integrated circuit device;

[0014] Figure 8 It is a block diagram of a programmable logic device that enables circuits and methods for transmitting signals in integrated circuit devices;

[0015] Figure 9 yes Figure 8 A block diagram of configurable logic elements for a programmable logic device; and

[0016] Figure 10 This is a flowchart illustrating a method for implementing multiple dies in a stacked integrated circuit device. Detailed Implementation

[0017] Circuits and methods for implementing integrated circuit devices with stacked dies include control circuitry between I / O contacts of the die and functional blocks on one or more other dies in the stack. The control circuitry on one of the stacked dies is capable of accessing the other dies for any purpose, including programming, testing, or operational purposes. For example, a chip select circuit on the first die can be used to enable signals from signal driving circuitry to be routed to circuitry, such as a functional block, on one of the other dies in the stack. That is, by using the chip select circuitry, signals can be transmitted to each of the other chips using a common signal driving circuitry, depending on which of the other chips the chip select circuitry selects. According to some embodiments, the circuitry and methods can be used with programmable logic devices (PLDs) where data can be routed to a configuration memory array associated with a functional block, commonly referred to as configuration random access memory (CRAM). The circuitry and methods can also be used to improve the testability of 3D stacked chip technology. By using control circuitry on the die to access circuitry of other dies in a stacked die arrangement, a small number of I / O pads on top of the die can be assigned to test circuitry, such as CRAM or function blocks, for each stacked die.

[0018] While the specification includes claims that define features of one or more embodiments of the invention considered novel, it is believed that the circuits and methods will be better understood by considering the description in conjunction with the accompanying drawings. Although various circuits and methods are disclosed, it should be understood that these are merely examples of arrangements of the invention, which may be embodied in various forms. Therefore, the specific structural and functional details disclosed in this specification should not be construed as limiting, but only as the basis for the claims and as a representative basis for teaching those skilled in the art to use the apparatus of the invention in various ways in virtually any suitably detailed structure. Furthermore, the terminology and phrases used herein are not intended to be limiting, but rather to provide an understandable description of the circuits and methods.

[0019] First turn Figure 1A block diagram of an exemplary stacked integrated circuit device 100 is shown. More specifically, the substrate 102 of the package substrate shown here as an example is configured to receive a plurality of bare dies electrically connected via interconnect units, as will be shown in [the diagram]. Figure 2 As described in more detail below. The package substrate includes pads 103, which can be used, for example, to attach to a circuit board and to provide or receive signals to or from a die attached to the package substrate. Alternatively, the substrate may include an interposer layer located on the package substrate, or any other unit for receiving a die of an integrated circuit device. Figure 1 As shown, the first die stack includes a first substrate 106 having a corresponding interconnect layer 108, which includes interconnect cells capable of routing signals to and from the package substrate. For example, the interconnect cells may include solder bumps, hybrid interconnect technologies, or any other conductive elements for routing signals to and from the die. A second substrate 110 has a corresponding interconnect layer 112, which includes interconnect cells capable of routing signals. A third substrate 116 has a corresponding interconnect layer 118, which includes interconnect cells capable of routing signals. A fourth substrate 120 has a corresponding interconnect layer 122, which includes interconnect cells also capable of routing signals. A fifth substrate 124 has a corresponding interconnect layer 126, which includes interconnect cells capable of routing signals. A package cover 128 may also be included to cover the substrate 124 or package multiple dies. The substrate and interconnect layer pairs (106 and 108, 110 and 112, 116 and 118, 120 and 122, 124 and 126) shown in the figure form five dies and are configured to route signals between the dies, as referenced below. Figure 2 In more detail, interconnect layer 108 can be connected to corresponding contact pads 132 of the package substrate via solder points 130 (e.g., C4 bumps) to enable communication with pads 103.

[0020] It should be understood that Figure 1The arrangement is intended to illustrate, by way of example, a general arrangement of stacked dies, wherein a specific arrangement of dies can be face-to-face dies (also known as Active-on-Active (AoA) dies) and back-to-back dies with different configurations, where the face represents a metal layer side-back end line (BEOL) and the back represents the substrate. Depending on the die configuration, interconnect units may include TSVs or BEOL metal layers of the die. For face-to-back bonding, interconnects between dies are implemented in the substrate (e.g., using TSVs). According to one example, interconnect layer 112 may include metal layers (i.e., on one face) coupled to vias of substrate 110 (i.e., the back), wherein interconnect layer 112 and substrate 110 together constitute a die layer. Interconnects from one die to another or between a substrate package and a die may include metal layers (e.g., hybrid bumps) or TSVs, depending on the die orientation. While the exemplary stacked integrated circuit device 100 is shown by way of example, it should be understood that other arrangements of dies may be applied, including multiple stacks of dies.

[0021] Turn now Figure 2 A cross-sectional view of a portion of an exemplary stacked integrated circuit device 200 is shown, which may be Figure 1 A cross-sectional view of a portion of an integrated circuit device. The stacked integrated circuit device 200 includes multiple dies, with dies 1-5 as examples here. Each die typically includes the same type of cells, such as active cells, metal traces, and vias formed in silicon, which are indicated by the same reference numerals in each die. For example, each die may include a substrate 202 with an active element 204 and a gate region 210, the active element 204 being shown here by way of example as a transistor, which includes a source 206 and a drain 208 in a well region 209.

[0022] The active cells of the substrate of the die are interconnected with each other via interconnect cells. The active cells may include metal traces and vias in metal layers separated by non-conductive layers, with the vias connecting portions of the metal layers through the non-conductive layers. More specifically, interconnect cells 212 in the respective layers may be coupled together via vias 214 as shown. Vias 216 extending through the substrate, commonly referred to as through-silicon vias (TSVs), extend from contact cells 218 on the back side of the substrate. Contact cells 218 may be coupled to contact cells 220, which extend through insulating layer 224 to connect to contact pads 222 to provide external connectivity. Contact pads 222 may correspond to contact pads of interconnect layer 108 to connect to solder joints 130 on contact pads 132, where interconnect cells of substrate 102 can connect to pads 103 for transmitting signals from or receiving signals on IC devices. Other contact cells may also be implemented to provide electrical connections between dies. For example, the first contact unit 226 of the first die can be electrically coupled to the second contact unit 228 of the second die, wherein contact units 226 and 228 can be part of a hybrid contact unit 230. Provided Figure 2 The following example illustrates a device that can be implemented in more detail below. Figure 3 and 4 The circuit.

[0023] Figure 2 The circuit is shown by way of example and can include any number of dies, which can be implemented in any orientation. Although a face-to-face arrangement of dies is shown between die 1 and die 2, and a face-to-back arrangement is shown in the connection of another die, it should be understood that other orientations of the dies can be implemented. Some or all of the dies can be the same type of device, such as a programmable logic device (PLD), or they can have a specific function, such as memory or logic, in different dies.

[0024] Turn now Figure 3 This diagram illustrates a portion 300 of an integrated circuit device having stacked integrated circuit dies. The integrated circuit device can be as follows... Figure 1 and Figure 2 The implementation shown illustrates, by way of example, the arrangement of components in different dies of an integrated circuit device to enable the use of circuitry such as driver circuitry, which can be accessed via I / O contacts on the integrated circuit device. By using common circuitry, such as driver circuitry on a first die in a stack of dies, to drive signals to each of the other dies in the stack, the same I / O contacts on the first die can be used to access circuitry, such as function blocks, on each of the other dies. That is, the same I / O contacts or multiple contacts required to access circuitry on one die in a stack of dies can be used to access circuitry on each of the other dies in the stack of dies.

[0025] For details, please refer to the following: Figure 3 The components of the bare die, Figure 3 A portion of the integrated circuit device includes, for example, five stacked dies, including a first die 302 (also called the top die and which may, for example, correspond to...) Figure 2 The top die includes a first die 1), a second die 304, a third die 306, a fourth die 308, and a fifth die 310. The I / O circuitry 312 of the top die may include contact units accessible from outside the integrated circuit. The I / O circuitry 312 is coupled to a control circuitry 313, wherein the I / O circuitry 312 is shown herein as an example to provide a signal, which may be a receive input (INPUT) signal at the contact unit of the I / O circuitry 312, to control the circuitry 313. For example, the I / O circuitry 312 may be coupled to, for example... Figure 2 Contact unit 222. It should be understood that the I / O circuit can be implemented as a dedicated input circuit, a dedicated output circuit, or it can function as a receiver of input signals or a generator of output signals, depending on the operation of the control circuit, the function of the function block, or other circuits that receive signals from the signal drive circuit. Examples of function blocks will be referenced below. Figure 8 and 9 To describe in more detail.

[0026] Control circuitry 313 may include signal driving circuitry 314 and chip selection circuitry 316. That is, control circuitry uses a chip selection signal generated by chip selection circuitry 316 to transmit a signal to the circuitry of another die among a plurality of dies, wherein the chip selection signal can operate as an enable signal to enable the circuitry on the selected chip to receive the signal from signal driving circuitry 314. More specifically, signal driving circuitry 314 provides signals to each of dies 304-310 via signal line 318. Although a single signal line 318 is shown, it should be understood that a single line 318 may be multiple signal lines, such as a signal bus for transmitting different signals (e.g., address, data, and control signals), or multiple signal lines may be driven by signal driving circuitry. Signal line 318 is provided to register 320 at signal input 322.

[0027] Chip select circuit 316 generates a chip select signal on chip select signal line 323, wherein the signal from the first signal line of chip select signal line 323 is routed to enable input 324 of register 320. Figure 3In one implementation, the select signal line 323 includes four lines, with each of the four dies 304-310 coupled to a corresponding line in the chip select signal line. According to other implementations, the signal on a single line provided to each die can be decoded to determine whether data is intended for that die. The chip select circuit 316 can receive an enable signal passed to a particular die in response to enable select signals (a and b), as referenced... Figure 4 The chip select signal can be any type of signal that enables register 320, such as a clock signal. The signal driven by signal drive circuit 314 can be data stored in memory, configuration data for the PLD circuit in configuration memory, control signals, or test signals for various circuits used to test the integrated circuit device, as described in more detail below. The output 325 of register 320 is provided to input 326 of function block 328, where the output of function block is generated at output 329.

[0028] The signal generated by the signal driving circuit 314 is also provided to another functional block 306-310 via signal line 318. More specifically, die 306 includes a register 330 adapted to receive a data signal on signal line 318 at signal input 332 and an enable signal on a second signal line of multiple signal lines 323 at enable input 334. Data generated at output 335 of register 330 is provided to input 336 of functional block 338, where the output of functional block is generated at output 339. Similarly, die 308 includes a register 340 adapted to receive a data signal on signal line 318 at signal input 342 and an enable signal on a third signal line of multiple signal lines 323 at enable input 344. Data generated at output 345 of register 340 is provided to input 346 of functional block 348, where the output of functional block is generated at output 349. Furthermore, die 310 includes register 350, adapted to receive a data signal on signal line 318 at signal input 352, and an enable signal for the fourth signal line of a plurality of signal lines 323 at enable input 354. Data generated at output 355 of register 350 is provided to input 356 of function block 358, where the output of function block is generated at output 359. Data generated by function block can be routed via signal line 363 coupled to input 364 of signal receiver to control circuitry 360 having signal receiver 362. Control signals can generate an output (OUTPUT) signal at I / O circuitry 366.

[0029] like Figure 3 As shown, the signal provided on signal line 318 is supplied to multiple dies, for example via the reference above. Figure 2The hybrid bonding or TSV described herein allows signals on signal line 318 to be received by one or more specific dies based on a chip select signal generated by chip select circuitry 316. Therefore, it can be understood that only a single contact unit, such as the bonding pad of IO circuitry 312, is needed to route signals to functional blocks 328, 338, 348, and 358 of dies 304-310. That is, common IO contacts and common signal drive circuitry can be used to selectively route signals to functional blocks in different stacked dies based on a chip select signal generated in the first die.

[0030] Therefore, the control circuitry 313 on one of the stacked dies can be used to enable access to other dies in the stack for any purpose, including programming, testing, or operational purposes. According to some embodiments, the circuitry and methods can be used with a PLD, as will be referenced below. Figure 8 and Figure 9 In more detail, data can be routed to a function-dependent configuration memory array, such as a CRAM block, as will be referenced below. Figure 5 The circuitry and methods described in more detail can also be used to improve testability in 3D stacked die technology. By using control circuitry on the die to access circuitry elements of other dies in a stacked die arrangement, a small number of test pads on top of the die are sufficient to test the CRAM or functional blocks in each stacked die. It should be noted that die 302 with control circuitry may also include functional blocks, where signals can be routed by the control circuitry to the functional blocks to enable testing or functional operation of the functional blocks of die 302. Furthermore, while input and output signals for configuration, testing, and other operations are provided via I / O circuitry (e.g., 312 and 366), it should be understood that signals routed to or received from any of dies 304-310 can be stored or generated in die 302. Although individual functional blocks are shown in each of dies 304-310 and accessed via I / O circuitry for providing data to die 302 or for routing signals from die 302, it should be understood that many functional blocks and I / O circuitry can be implemented in the die as described above and as referenced. Figure 8 and 9 Interconnected as described. The circuit can be implemented as part of a packaged circuit that provides test signals or other signals to a set of functional blocks, which may be referred to as a wrapper.

[0031] Turn now Figure 4 A block diagram of a chip select circuit 400 that can be implemented in a die of a stacked integrated circuit device is shown. Figure 4As shown, an enable signal, such as the enable signal coupled to chip select circuit 316, can be generated using enable select signals a, a_bar, b, and b_bar, wherein the enable signal is provided to one of the dies according to the value of the enable select signal. More specifically, enable select signal a is provided to the input of inverter 402, where a_bar is generated at the output of inverter 402. Similarly, enable select signal b is provided to the input of inverter 404, where enable select signal b_bar is generated at the output of inverter 404. Enable select signals a and b (and therefore a_bar and b_bar) are selected to route the enable signal to one of dies 2-dies 5. That is, enable select signal a is provided to the gate of transistor 406 to route the enable signal to die 2, and to the gate of transistor 408 to route the enable signal to die 3. Enable selection signal a_bar is provided to the gate of transistor 410 to route the enable signal to die 4, and to the gate of transistor 412 to route the enable signal to die 5. Enable selection signal b is provided to the gate of transistor 414 to route the enable signal to die 2, and to the gate of transistor 420 to route the enable signal to die 4. Enable selection signal b_bar is provided to the gate of transistor 418 to route the enable signal to die 3, and to the gate of transistor 420 to route the enable signal to die 5. Figure 4 As shown, the four combinations of a and b can select any one of the four dies to route data signals to those dies. Although the chip select circuit 400 is shown as an example, it should be understood that other similar circuits can be implemented to provide enable signals to one or more dies.

[0032] Turn now Figure 5 Another block diagram shows a portion 500 of an integrated circuit device having stacked integrated circuit dies. According to... Figure 5 The arrangement of different I / O circuits is used for different parts of integrated circuit devices. Figure 5 The integrated circuit layout includes 5 dies, including those that can be referenced above. Figure 1 and 2Dies 502-510 are implemented as described, wherein the connections between dies can be implemented using, for example, hybrid bonding or TSV. I / O circuitry 512 is configured to receive input signals destined for the integrated circuit device at contact units of contact pads such as die 502, wherein the received input signals are provided to control circuitry 513. Control circuitry 513 is adapted to control signal drive circuitry 514 and chip select circuitry 515 to selectively provide signals to individual circuit blocks in different dies. For example, the signals driven by the signal drive circuitry can be data stored in memory, addresses for storing or receiving data, configuration data of PLD circuitry stored in configuration memory, control signals, or test signals for various circuits used to test the integrated circuit device, as will be described in more detail below.

[0033] Signal driving circuit 514 is configured to drive signals to the circuitry of dies 504-510, while chip select circuit 515 is configured to select the die receiving signals from signal driving circuit 514 based on signals from chip select signal line 516. Figure 5 In one implementation, a first output signal generated at signal output 518 is provided on a first signal line 519 and a second output signal generated at signal output 520 is provided on signal line 521, wherein signal lines 519 and 521 are routed to each of dies 504-510. Figure 5 Each die in the implementation includes memory and function blocks, wherein the memory may include configuration data for the function blocks, as will be described in more detail below.

[0034] Each die includes a register 522 adapted to receive data from memory 524 (here illustrated as a CRAM array by way of example), and another register 526 for receiving data from a bit-line buffer 528 coupled to memory 524 and register 529. For example, register 529 may be a shift register, receiving a chip select signal associated with the chip. More specifically, a signal from signal line 521, such as an address signal, is coupled to input 530, while a chip select signal from a first chip select signal line of multiple chip select signal lines 516 is coupled to enable input 532. It should be understood that the chip select signal can be any type of enable signal for enabling register 522 and may include a clock signal for receiving data provided to input 530. Register 522 may include a shift register for providing an address associated with data to be stored in memory 524. Data produced at output 534 of register 522 is provided to input 536 of memory 524. Memory 524 communicates with bit line buffer 528 via interface 538, which enables data to be read from memory 524 to bit line buffer or data to be written from bit line buffer to memory 524. Die 502 also includes a receiving circuit 542 of control circuitry 544. The receiving circuit 542 is configured to receive the output of register 529 of the bit line buffer of the selected die via signal line 545 coupled to input 546 of the receiving circuit 542.

[0035] Signal line 519 is coupled to input 551, and the first chip select signal line of the multiple chip select signal lines 516 is coupled to the enable input 552 of register 526, wherein output 547 is coupled to input 549 of bit line buffer 528. Data provided to bit line buffer 528 can be written to memory 524, or data read from memory 524 and provided to bit line buffer can be generated at output 559 of bit line buffer 528 and provided to register 529. Die 502 also includes I / O circuitry 548, which is capable of generating an output, for example, during testing, based on a signal provided to receiving circuitry 542 via register 529. That is, control circuitry can provide signals received by receiving circuitry 542 to I / O circuitry 548. According to another embodiment, the output of bit line buffer 528 can be held in a tri-state value, which eliminates the need for register 529 at the output of bit line buffer 528.

[0036] Figure 5The circuit layout may also include functional blocks, wherein control circuitry 550 is coupled to I / O circuitry 557, and further includes a driver 553 and a chip select circuitry 554 coupled to multiple chip select lines 555. Each die includes a register 556 and a functional block 558, wherein a signal generated at the output 560 of driver 553 is coupled to input 562 of register 556. Register 556 is configured to receive a signal for the functional block and a chip select signal from a first chip select line of the multiple chip select lines 555 at input 564. Output 566 of register 556 is coupled to input 568 of functional block 558. Output 570 of functional block may be provided by signal line 572 to input 574 of receiving circuitry 575 of control circuitry 550. The output of functional block may be held in a tri-state value so that only the output of the functional block of the selected die is provided on signal line 572. Alternatively, a register may be implemented at output 570, such as register 529 at the output of bit line buffer 528.

[0037] After the functional block design is completed, it is usually necessary to design a circuit that facilitates testing the functional block, such as a scan chain circuit. Figure 3 and Figure 5 The control circuitry is implemented to enhance testability and reduce circuit requirements by implementing a single circuit to facilitate testing of the circuitry on each of multiple stacked dies. The control circuitry acts as an interface between the I / O circuitry and the circuitry (e.g., functional blocks) of the chip under test. For example, test modes and control signals can be loaded from the I / O circuitry to a control circuitry such as a control circuitry 513 or 550. These modes and signals are then used to test functional blocks on another chip. After testing, the test results can be loaded back to another control circuitry, provided to the I / O circuitry, and output by the integrated circuit device. According to some implementations, the control circuitry can store input data and control data used to test the functional blocks. For example, to test a math processor, input_A = 00001, input_B = 00010, control = 00 => input_A + input_B; if control = 01 => input_A x input_B.

[0038] It should be noted that, in order to apply signal routing to a specific die selected by the chip select signal, various blocks of inputs and outputs are shown; various blocks, such as functional blocks, may have other outputs; and the outputs of the various blocks shown can be provided to other parts of the integrated circuit device. Various connections to the circuit elements of the dies are provided to illustrate implementations that allow data to be routed from a first die (e.g., die 502) to another die (e.g., one of dies 504-510), so as to route signals to the circuitry of each die, particularly the die selected by the chip select signal. According to some embodiments, data can be received at the first die from the selected die, for example, during a test operation.

[0039] Although Figure 5 The circuit arrangement illustrates the use of control circuitry to route signals to memory and function blocks, but it should be understood that the circuitry and methods for routing signals to dies of multiple stacked dies can use any type of circuit block, such as those shown below. Figure 8 and 9 Any type of circuit block described herein. Furthermore, similar circuit blocks (i.e., CRAM arrays with associated bit line buffers and function blocks) are shown by way of example in each die. It should be understood that any die need not have the same circuitry; different dies may include similar or different circuitry. For example, one die may primarily consist of memory cells, while two other dies may primarily consist of function blocks associated with the PLD.

[0040] Turn now Figure 6 A block diagram of a signal driving circuit 600 for transmitting signals between dies of integrated circuit devices that can be implemented in stacked integrated circuit devices is shown. The signal driving circuit 600 can be implemented as... Figure 3 Signal drive circuit 314 or Figure 5The signal driving circuits 600 and 601 are provided. Signal driving circuit 600 includes a first shift register 602 configured to receive an address at address input 603. The output of shift register 602 can be provided to address decoder 604. Word line control circuit 606 is configured to receive the decoded address and provide its output to word line driver 608. The address generated by word line driver is generated as the output of signal driving circuit 600. For example, the address can be provided to input 530 of register 522. This address can be used to select a frame address in a specific die. Signal driving circuit 600 may also include a shift register 610 configured to receive data at bit line data input 611. The output of shift register 610 is provided to bit line decoder 612. An output representing the decoded value is provided to bit line control circuit 614 to generate data output by signal driving circuit 600. This data can be applied to the data lines of the CRAM cell at the selected frame address. Control signals are also generated by shift register 616 in response to input control bits provided to input 618. These control bits are used to control the operation of the selected CRAM cell, such as read and write operations.

[0041] like Figure 7 The diagram illustrates exemplary data that can be transferred using a shift register with signal-driven circuitry that can be implemented in the die of a stacked integrated circuit device. According to one embodiment, the address may include multiple fields, including a secondary address, a primary address, and a stacking layer. Figure 7 The example shift register has a top row of "tags" and a bottom row of the shift register, where each small block ("0", "1", ...) stores one bit (bit0, bit1, bit2, ...). Figure 7 The shift register can be dedicated to storing the CRAM addresses of the CRAM array on each chip, which is divided into many sectors. Each sector may contain a certain density of CRAM cells. The "stack layer" (bit0-bit2) can be used to store the "chip address" (e.g., chip 2, chip 3, chip 4, chip 5), the "major address" (bit3-bit7) can be used to store the sector address, and the "minor address" (bit8-bin(n-1)) can be used to store the word line address (WL0, WL1, WL2...). These address bits can be decoded to select a chip, a sector, and a word line associated with the memory array of the selected chip.

[0042] Turn now Figure 8This diagram illustrates a block diagram of a programmable logic device that can implement circuitry and methods for transmitting signals within a stacked integrated circuit device. While devices with programmable resources can be implemented in any type of integrated circuit device, such as application-specific integrated circuits (ASICs) with programmable resources, other devices include application-specific programmable logic devices (PLDs). One type of PLD is a complex programmable logic device (CPLD). A CPLD comprises two or more "functional blocks" connected together via an interconnect switch matrix and linked to input / output (I / O) resources. Each functional block of a CPLD contains a two-level AND / OR gate structure similar to that used in programmable logic arrays (PLAs) or programmable array logic (PAL) devices. Another type of PLD is a field-programmable gate array (FPGA) with multiple functional blocks. In a typical FPGA, a set of configurable logic blocks (CLBs) is coupled to programmable input / output blocks (IOBs). CLBs and IOBs are interconnected via a hierarchy of programmable routing resources. These CLBs, IOBs, and programmable routing resources comprise functional blocks that are customized by loading a configuration bitstream (typically from off-chip memory) into the FPGA's configuration memory cells. For both types of programmable logic devices, the device's functionality is controlled by configuration data bits (or configuration data bits sent during partial reconfiguration) provided to the device's configuration bit stream for this purpose. These configuration data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), non-volatile memory (e.g., flash memory, as in some CPLDs), or any other type of memory cell.

[0043] Figure 8 The device includes an FPGA architecture 800 with a large number of different functional blocks implemented as programmable blocks, including a multi-gigabit transceiver (MGT) 801, a CLB 802, a block of random access memory (BRAM) 803, an input / output block (IOB) 804, configuration and clock logic (CONFIG / CLOCKS) 805, a digital signal processing block (DSP) 806, dedicated input / output blocks (I / O) 807 (e.g., configuration ports and clock ports), and other programmable logic 808, such as a digital clock manager, an analog-to-digital converter, system monitoring logic, etc. For example, some FPGAs also include a dedicated processor block (PROC) 810, which can be used to implement software applications.

[0044] In some FPGAs, each programmable block includes a programmable interconnect unit (INT) 811, which has standardized connections to corresponding interconnect units in each adjacent block. Thus, the programmable interconnect units together implement the programmable interconnect structure of the FPGA shown. The programmable interconnect unit 811 also includes connections to and from programmable logic units within the same block, such as... Figure 8 The example included at the top is shown.

[0045] For example, CLB 802 may include configurable logic elements (CLEs) 812, which can be programmed to implement user logic plus a single programmable interconnect unit 811. In addition to one or more programmable interconnect units, BRAM 803 may include BRAM logic elements (BRLs) 813. BRAM includes dedicated memory separate from the distributed RAM of the configuration logic blocks. Typically, the number of interconnect units contained in a tile depends on the height of the tile. In the illustrated embodiment, a BRAM tile has the same height as five CLBs, but other numbers may also be used. In addition to an appropriate number of programmable interconnect units, DSP block 806 may also include DSP logic elements (DSPLs) 814. In addition to one instance of programmable interconnect unit 811, IOB 804 may, for example, include two instances of input / output logic elements (IOLs) 815. Circuitry and methods can be implemented using IOLs 815. The location of device connections is controlled by configuration data bits provided to the device's configuration bitstream for this purpose. In response to the bits configuring the bit stream, programmable interconnects enable connections including interconnects to be used to couple various signals to circuits implemented by programmable logic or other circuits such as BRAM or processors.

[0046] In the illustrated embodiment, the column region near the center of the die is used for configuration, clock, and other control logic. A configuration / clock distribution region 809 extending from this column is used to distribute clock and configuration signals across the width of the FPGA. Some utilize... Figure 8 The FPGA architecture shown includes additional logic blocks that disrupt the conventional column structure that makes up the majority of the FPGA. These additional logic blocks can be programmable blocks and / or dedicated logic. For example, Figure 8 The processor block PROC 810 shown spans several columns of CLB and BRAM.

[0047] It should be pointed out that, Figure 8 This is intended to demonstrate only an exemplary FPGA architecture. The number of logic blocks in a column, the relative width of the column, the number and order of columns, the types of logic blocks contained in the column, the relative size of the logic blocks, and the contents contained within the columns are all specified. Figure 8 The top interconnect / logic implementation is purely exemplary. For example, in a real FPGA, more than one column of adjacent CLBs is typically included wherever a CLB appears, to facilitate efficient implementation of user logic. While Figure 8 The implementations relate to integrated circuits with programmable resources; however, it should be understood that the circuits and methods described above can be implemented in any type of device with a combination of programmable resources and hardware.

[0048] Turn now Figure 9 , showed Figure 8 A block diagram of the configurable logic elements of a programmable logic device. Specifically, Figure 9 The diagram is presented in a simplified form. Figure 8 The configuration logic block 802 is a configurable logic element as an example of programmable logic. Figure 9 In this implementation, slice M 901 includes four lookup tables (LUTMs) 901A-901D. Each lookup table is driven by six LUT data input terminals A1-A6, B1-B6, C1-C6, and D1-D6. Each lookup table provides two LUT output signals O5 and O6. The O6 output terminal of LUTs 901A-901D drives the on-chip output terminal AD respectively. The LUT data input signals are provided by the FPGA interconnect structure through an input multiplexer, which can be implemented by a programmable interconnect unit 911. The LUT output signals are also provided to the interconnect structure. Slice M also includes: output selection multiplexers 911A-911D driving the AMUX-DMUX outputs; multiplexers 912A-912D driving the data inputs of storage elements 902A-902D; combination multiplexers 916, 918, and 919; bounce multiplexer circuits 922-923; circuitry represented by inverter 905 and multiplexer 906 (which together provide optional inversion on the input clock path); and carry logic with multiplexers 914A-914D, 915A-915D, 920-921, and XOR gates 913A-913D. All these components are as follows: Figure 9 They are coupled together as shown. For Figure 9 The multiplexer shown does not display the selection input; the selection input is controlled by the configuration memory unit. That is, the configuration bits of the configuration bitstream stored in the configuration memory unit are coupled to the selection input of the multiplexer to select the correct input sent to the multiplexer. These well-known configuration memory units are, for clarity, referred to from... Figure 9 And figures from other options in this article are omitted.

[0049] In the illustrated embodiment, each memory cell 902A-902D can be programmed to function as a synchronous or asynchronous flip-flop or latch. The synchronous / asynchronous selection circuit 903 is programmed to select between synchronous and asynchronous functions for all four memory elements in the slice. The REV input provides a set function when the memory element is programmed such that the S / R (set / reset) input signal provides a reset function. Memory cells 902A-902D are timed by a clock signal CK, which can be provided, for example, by a global clock network or interconnect structure. Such programmable memory cells are well-known in the FPGA design field. Each memory cell 902A-902D provides registered output signals AQ-DQ to the interconnect structure. Since each LUT 901A-901D provides two output signals O5 and O6, the LUT can be configured as two 5-input LUTs with five shared input signals (IN1-IN5), or a single 6-input LUT with input signals IN1-IN6.

[0050] exist Figure 9 In this implementation, each LUTM 901A-901D can operate in any of several modes. In lookup table mode, each LUT has six data input signals IN1-IN6, provided by the FPGA interconnect structure via input multiplexers. Based on the values ​​of signals IN1-IN6, one of 64 data values ​​is programmably selected from the configuration memory cell. In RAM mode, each LUT functions as a single 64-bit RAM or two 32-bit RAMs with shared addressing. RAM write data is provided to the 64-bit RAM via input DI1 (via multiplexers 917A-917C for LUTs 901A-901C), or to the two 32-bit RAMs via inputs DI1 and DI2. RAM write operations in the LUT RAM are controlled by the clock signal CK from multiplexer 906 and the write enable signal WEN from multiplexer 907, which can selectively pass either the clock enable signal CE or the write enable signal WE. In shift register mode, each LUT functions as two 16-bit shift registers, or two 16-bit shift registers can be cascaded to create a single 32-bit shift register. The shift-in signal is provided through one or both of inputs DI1 and DI2. The 16-bit and 32-bit shift-out signals can be provided through the LUT outputs, with the 32-bit shift-out signal also provided more directly through LUT output MC31. The 32-bit shift-out signal MC31 of the LUT 901A can also be provided through the output selector multiplexer 911D and the CLE output DMUX to a general interconnect structure used for shift register chains. Therefore, the circuits and methods described above can be applied to, for example... Figure 8 and 9Implemented in devices such as those, or any other suitable devices.

[0051] Figure 10 This is a flowchart illustrating a method for implementing multiple dies in a stacked integrated circuit device. The first die in the stacked dies is, for example... Figure 3 and 5 The stacked dies are configured to receive input signals at the input / output element at block 1002. An integrated circuit having multiple stacked dies and configured to receive input signals can be, for example, as referenced above. Figure 1 and Figure 2 The device may be formed as described, or using other methods for forming an integrated circuit device with stacked dies. A signal driving circuit for the first die, such as signal driver 314 or 514, is configured in block 1004 to provide an input signal to each of the plurality of stacked dies. A chip select circuit is configured in block 1006 to generate a plurality of chip select signals for the plurality of stacked dies. In block 1008, a second die of the plurality of stacked dies is coupled to the first die, wherein the second die has a functional block, such as functional block 328, configured to receive an input signal. In block 1010, an input signal is received at the second die in response to a chip select signal corresponding to the second die among the plurality of chip select signals.

[0052] The method may further include configuring a receiver on the first die to receive an output signal from a function block, and coupling a second input / output element of the first die to receive the output signal. Furthermore, the method may include configuring a register on the second die to receive an input signal from a signal driving circuit at a data input and a chip select signal from a chip select circuit at an enable input. Data associated with the function block may also be stored in the memory of the second die. The method may further include configuring a first register on the second die to receive an input signal from a signal driving circuit at a data input and a chip select signal from a chip select circuit at an enable input, and coupling the output of the first register to an input of the memory. The second register may also be configured to receive an address signal from a signal driving circuit at a data input and a chip select signal from a chip select circuit at an enable input, and the bit line buffer of the second die may also be configured to receive the address signal at the data input and the chip select signal from the chip select circuit at the enable input. According to some implementations, other dies can be stacked, for example by coupling a third die of a plurality of stacked dies to a second stacked die, wherein the third die includes a register configured to receive an input signal from a signal driving circuit at a data input and a chip select signal from a chip select circuit at an enable input.

[0053] Figure 10The method can be achieved by using Figure 1-9 The circuit described herein, or some other suitable circuit, may be used to implement it. Although a specific unit of the method has been described, it should be understood that other units of the method or other details related to that unit may be implemented according to... Figure 1-9 It will be implemented based on publicly available information.

[0054] Therefore, it can be understood that novel circuits and methods for implementing stacked integrated circuit devices have been described. Those skilled in the art will understand that various alternatives and equivalents exist in conjunction with the disclosed invention. Therefore, the invention is not limited to the foregoing embodiments, but only to the following claims.

Claims

1. An integrated circuit device having a plurality of stacked dies, the integrated circuit device comprising: The first die in the plurality of stacked dies has an input / output element configured to receive an input signal. The first die includes a signal driving circuit and a chip selection circuit. The signal driving circuit is configured to provide an input signal to each of the plurality of stacked dies, and the chip selection circuit is configured to generate a plurality of chip selection signals for the plurality of stacked dies. and The second die in the plurality of stacked dies is coupled to the first die, and the second die has a functional block configured to receive the input signal; The second die receives the input signal in response to one of the plurality of chip select signals corresponding to the second die, and the second die includes a register configured to receive the input signal from the signal driving circuit at a data input and the chip select signal from the chip select circuit at an enable input.

2. The integrated circuit device according to claim 1, characterized in that, The first die includes a receiver configured to receive the output signal of the functional block.

3. The integrated circuit device according to claim 1, characterized in that, The functional block includes a storage element.

4. The integrated circuit device according to claim 1, characterized in that, The second die further includes a memory configured to store data associated with the functional block.

5. The integrated circuit device according to claim 1, characterized in that, The integrated circuit device further includes a third die among the plurality of stacked dies, the third die being coupled to the second die, wherein the third die includes another register configured to receive the input signal from the signal driving circuit at a data input and the chip select signal from the chip select circuit at an enable input.

6. A method for implementing an integrated circuit device having multiple stacked dies, characterized in that, The method includes: Configure the first die in a stack of multiple stacked dies to receive input signals at input / output elements; Configure the signal driving circuit of the first die to provide input signals to each of the plurality of stacked dies; A chip selection circuit is configured to generate multiple chip selection signals for the plurality of stacked dies; A second die in the plurality of stacked dies is coupled to the first die, the second die having a functional block configured to receive the input signal; and In response to one of the plurality of chip select signals corresponding to the second die, the input signal is received on the second die, wherein the register of the second die is configured to receive the input signal from the signal driving circuit at a data input and to receive the chip select signal from the chip select circuit at an enable input.

7. The method according to claim 6, characterized in that, The method further includes configuring a receiver for the first die to receive the output signal of the functional block.

8. The method according to claim 7, characterized in that, The method further includes a second input / output element coupled to the first die to receive the output signal.

9. The method according to claim 6, characterized in that, The functional block includes a storage element.

10. The method according to claim 6, characterized in that, The method further includes storing data associated with the functional block in the memory of the second die.

11. The method according to claim 10, characterized in that, The output of the register is coupled to the input of the memory.

12. The method according to claim 6, characterized in that, The method further includes coupling a third die of the plurality of stacked dies to the second die, wherein the third die includes another register configured to receive the input signal from the signal driving circuit at a data input and the chip select signal from the chip select circuit at an enable input.

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