Memory device, method of operating a memory device, and storage system

Abstract

A method of operating a memory device can be provided, the method including receiving a multi-level signal having M levels transmitted by an external controller through a clock receive pin, where M is a natural number greater than 2, and decoding the multi-level signal to recover at least one of data bus inversion (DBI) data, data mask (DM) data, cyclic redundancy check (CRC) data, or error correction code (ECC) data. The multi-level signal is a clock signal transmitted by the external controller and is a signal that is based on an intermediate reference signal swing that is an intermediate value between a minimum level and a maximum level of the M levels.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0112481, filed on September 3, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0003] The present invention relates to storage devices, methods of operating storage devices, and / or storage systems. Background Technology

[0004] The storage device can provide the function of writing and erasing data or reading recorded data in response to control signals received from one or more external controllers. The storage device can receive data from the controller and store the received data in the storage unit, and in order to improve the communication speed between the storage device and the controller, at least one communication channel can use a multi-level signal different from the non-return-to-zero (NRZ) signal. Summary of the Invention

[0005] Some example embodiments provide storage devices, methods for operating storage devices, and / or storage systems in which the number of pins is reduced and power consumption can be reduced by generating clock signals and data strobe signals into multi-level signals and sending the generated signals along with data.

[0006] According to an example embodiment, a method of operating a storage device may include: receiving a multilevel signal having M levels transmitted by an external controller via a clock receive pin, where M is a natural number greater than 2; and decoding the multilevel signal to store at least one of Data Bus Inverted (DBI) data, Data Masked (DM) data, Cyclic Redundancy Check (CRC) data, or Error Correction Code (ECC) data. The multilevel signal may be a clock signal transmitted by the external controller and may be a signal that swings based on an intermediate reference signal having an intermediate level between the minimum and maximum levels of the M levels.

[0007] According to an example embodiment, a method of operating a storage device may include: receiving a data strobe signal sent by an external controller via a DQS pin, the data strobe signal having M levels, where M is a natural number greater than 2; and decoding the data strobe signal to recover the data encoded into the data strobe signal by the external controller. The data strobe signal may be a signal that oscillates based on an intermediate level between the minimum and maximum levels among the M levels.

[0008] According to an example embodiment, the storage device may include: a buffer configured to receive a multilevel signal having M levels via a DQS pin, where M is a natural number greater than 2; a delay circuit configured to generate a delayed clock signal by delaying the multilevel signal; a first sense amplifier configured to generate a first output signal based on a data strobe signal and a first reference signal at the rising and falling edges of a reference clock signal; a second sense amplifier configured to generate a second output signal based on a data strobe signal and a second reference signal greater than the first reference signal at the rising and falling edges of the delayed clock signal; and a decoder configured to recover at least one of DBI data, DM data, CRC data, or ECC data encoded as a multilevel signal using at least one of the first and second output signals.

[0009] According to an example embodiment, the storage system may include a storage device having multiple storage cells and a controller connected to the storage device via an interface. The controller may be configured to send a clock signal and a data strobe signal to the storage device, and at least one of the clock signal or the data strobe signal may be a pulse amplitude modulated signal. The controller may also be configured to send at least one of DBI data, ECC data, CRC data, data mask data, or command / address data to the storage device using the pulse amplitude modulated signal. The pulse amplitude modulated signal may be a multi-level signal having multiple levels and may be oscillating based on an intermediate reference signal having an intermediate level between the minimum and maximum levels among the multiple levels.

[0010] According to an example embodiment, the storage device may include: a plurality of pins connected to an external controller configured to exchange signals with the storage device via the plurality of pins; and a plurality of storage cells configured to store data. The storage device may be configured to receive a clock signal or a data strobe signal as a pulse amplitude modulated signal via at least one of the plurality of pins. The pulse amplitude modulated signal may include at least one of DBI data, ECC data, CRC data, data mask data, or command / address data, and the pulse amplitude modulated signal may be a multi-level signal having multiple levels, and may be oscillating based on an intermediate reference signal having an intermediate level between the minimum and maximum levels of the plurality of levels. Attached Figure Description

[0011] The above and other aspects, features, and advantages of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0012] Figure 1 This is a schematic diagram of a system including a storage device according to an example embodiment;

[0013] Figure 2 and Figure 3 This is a diagram illustrating a multi-level signal received by a storage device according to an example embodiment;

[0014] Figure 4 and Figure 5 This is a schematic diagram illustrating a semiconductor device according to an example embodiment;

[0015] Figure 6 and Figure 7 These are diagrams provided to illustrate the operation of a storage device according to an example embodiment;

[0016] Figure 8A , Figure 8B and Figure 9 This is a schematic diagram illustrating a storage device according to an example embodiment;

[0017] Figure 10A and Figure 10B These are diagrams provided to illustrate the operation of a storage device according to an example embodiment;

[0018] Figure 11 These are diagrams provided to illustrate the operation of a storage device according to an example embodiment;

[0019] Figure 12 This is a schematic diagram of a storage system according to an example embodiment;

[0020] Figure 13 This is a schematic diagram of a storage device included in a storage system according to an example embodiment;

[0021] Figure 14 This is a schematic diagram of a storage device included in a storage system according to an example embodiment;

[0022] Figures 15 to 17 These are diagrams provided to illustrate the operation of a storage device according to an example embodiment;

[0023] Figure 18 These are diagrams provided to illustrate the operation of a storage device according to an example embodiment;

[0024] Figure 19 This is a schematic diagram of a storage system according to an example embodiment; and

[0025] Figure 20 This is a schematic diagram of a mobile system including a storage device according to an example embodiment. Detailed Implementation

[0026] In the following description, some exemplary embodiments will be illustrated with reference to the accompanying drawings.

[0027] Figure 1 This is a schematic diagram of a system including a storage device according to an example embodiment.

[0028] Reference Figure 1 According to an example embodiment, system 1 may include a first semiconductor device 10 and a second semiconductor device 20 that exchange data with each other. Figure 1 In the system 1 of the example embodiment shown, a first semiconductor device 10 can send data to a second semiconductor device 20. The first semiconductor device 10 may be a processor such as a central processing unit, an application processor (AP), or a system-on-a-chip, while the second semiconductor device 20 may be a storage device for storing data.

[0029] For example, the first semiconductor device 10 can transmit data signals and clock signals to the second semiconductor device 20. The first semiconductor device 10 may include a first output circuit 11 and a second output circuit 12 for transmitting data signals, a clock generator 13 for transmitting clock signals, and a core circuit 14 for controlling the overall operation of the first semiconductor device 10, etc. The second semiconductor device 20 may include a first multilevel receiver 21 and a second multilevel receiver 22 for receiving data signals, a clock receiver 23 for receiving clock signals, and a core circuit 24 for controlling the overall operation of the second semiconductor device 20, etc.

[0030] Each of the first output circuit 11 and the second output circuit 12 can transmit the data signal as a multi-level signal. Therefore, each of the data signals transmitted via the first communication channel CH1 and the second communication channel CH2 can be a multi-level signal with M levels, where M can be a natural number greater than 2. For example, M can be a power of 2 and can be determined depending on the amount of data to be transmitted via each of the first communication channel CH1 and the second communication channel CH2. However, according to some example embodiments, the outputs of the corresponding first output circuit 11 and the second output circuit 12 can also be generated as non-return-to-zero (NRZ) signals instead of multi-level signals.

[0031] Clock generator 13 can send an external clock signal to second semiconductor device 20 via third communication channel CH3. In an example embodiment, the external clock signal can also be generated as a multi-level signal similar to a data signal and sent to second semiconductor device 20. According to some example embodiments, the number of levels that the external clock signal can have and the number of levels that the data signal can have can be the same or different from each other.

[0032] The first multilevel receiver 21 and the second multilevel receiver 22 can receive and recover data signals. For example, the first multilevel receiver 21 may include N sense amplifiers, each receiving a multilevel signal having one of M levels and a reference signal. N can be a natural number less than M, which defines the multilevel signal, and the first multilevel receiver 21 may also include a decoder that recovers the outputs of the N sense amplifiers. The configuration and operation of the second multilevel receiver 22 may be the same as or substantially similar to the configuration and operation of the first multilevel receiver 21.

[0033] The clock receiver 23 may also include multiple sense amplifiers. For example, the clock receiver 23 may include a first sense amplifier that compares an external clock signal received via the third communication channel CH3 with a first reference signal, and a second sense amplifier that compares the external clock signal with a second reference signal. The level of the first reference signal may be different from the level of the second reference signal. In other words, the clock receiver 23 may include a first sense amplifier that operates based on the external clock signal received via the third communication channel CH3 and the first reference signal, and a second sense amplifier that operates based on the external clock signal and the second reference signal.

[0034] Furthermore, the clock receiver 23 may include a decoder that uses the outputs of a first sense amplifier and a second sense amplifier to generate desired (or alternatively, predetermined) data. The data generated by the decoder may correspond to the raw data encoded and transmitted by the first semiconductor device 10 using an external clock signal. For example, the decoder may use the outputs of the first and second sense amplifiers to generate raw data. In some example embodiments, the decoder may use the output of the first sense amplifier to generate first raw data and may use the output of the second sense amplifier to generate second raw data.

[0035] The first semiconductor device 10 can encode an external clock signal based on the original data, enabling the second semiconductor device 20 to recover the original data using the external clock signal. Therefore, at least one pin used for individually transmitting the original data can be omitted, increasing the integration density of semiconductor devices 10 and 20 and reducing power consumption.

[0036] Figure 2 and Figure 3 This is a diagram illustrating a multi-level signal received by a storage device according to an example embodiment.

[0037] Reference Figure 2 and Figure 3 According to the example embodiment, the multi-level signal received by the storage device can have four levels LV1-LV4. Figure 2 and Figure 3In the example embodiment shown, the storage device can receive a multilevel signal generated based on Pulse Amplitude Modulation-4 (PAM-4). When receiving data using a multilevel signal generated based on PAM-4, two data bits can be received during one data transmission cycle (PR).

[0038] For example, the four levels LV1 to LV4 can correspond to data 00, 01, 10, and 11, respectively. Therefore, the storage device can receive two bits, for example, one of 00, 10, 01, and 11, during a data transmission cycle PR. The storage device may include a multilevel receiver that receives multilevel signals and recovers data, and the multilevel receiver may include multiple sense amplifiers.

[0039] In an example embodiment, the clock signals sent and received by the storage device can be generated as multi-level signals, such as... Figure 2 and Figure 3 The example embodiment shown. Unlike the multi-level signal generated for transmitting data only, during the transition period (TP) between data transmission cycles (PR), it can be based on the intermediate reference signal V. MID Increase or decrease the level of the clock signal that is generated as a multi-level signal.

[0040] For example, when the clock signal level in the first data transmission cycle (PR) is a first level (LV1) or a second level (LV2), the clock signal level in the second data transmission cycle (PR) can be a third level (LV3) or a fourth level (LV4). Similarly, when the clock signal level in the first data transmission cycle (PR) is a third level (LV3) or a fourth level (LV4), the clock signal level in the second data transmission cycle (PR) can be a first level (LV1) or a second level (LV2).

[0041] On the other hand, a memory device that receives a clock signal as a multi-level signal can synchronize the clock signal with a low reference signal (V). LOW ) or high reference signal (V HIGH At least one of the following is compared to recover the original data encoded as a clock signal and transmitted. In other words, the memory device receiving the clock signal as a multi-level signal can be based on the clock signal and a low reference signal (V). LOW ) or high reference signal (V HIGH At least one of the following is recovered: the original data encoded as a clock signal and transmitted. For example, when the clock signal is below the low reference signal V... LOW When the clock signal is greater than the low reference signal V, the data can be determined to be 0, and when the clock signal is greater than the low reference signal V. LOW When the clock signal is below the high reference signal V, the data can be determined as 1. Similarly, when the clock signal is below the high reference signal V... HIGHWhen the clock signal is greater than the high reference signal V, the data can be determined to be 0, and when the clock signal is greater than the high reference signal V. HIGH At that time, the data can be determined as 1.

[0042] The storage device that receives the clock signal as a multi-level signal may include a means for connecting the clock signal to a low reference signal V. LOW The first sense amplifier for comparison, and the one used to compare the clock signal with the high reference signal V. HIGH A second sense amplifier is used for comparison. The outputs of the first and second sense amplifiers are input to the decoder, and the decoder can use the outputs of the first and second sense amplifiers to generate the original data.

[0043] By comparing the clock signal with the low reference signal V LOW and high reference signal V HIGH By comparing the two sets of original data, the different original data can be recovered. Therefore, a storage device that encodes and transmits clock signals can encode two different types of original data into a single clock signal and send the encoded data to another storage device.

[0044] Figure 4 and Figure 5 This is a schematic diagram illustrating a semiconductor device according to an example embodiment.

[0045] first, Figure 4 This can be a simplified diagram showing the transmitting-side semiconductor device 100, which generates a clock signal as a multi-level signal and encodes desired (or alternatively, predetermined) data into an external clock signal CLK. EXT It then outputs the encoded data to another storage device. For example, semiconductor device 100 may be a device that includes a memory controller (e.g., a central processing unit, an application processor, a solid-state drive (SSD) controller, or a system-on-a-chip). See reference... Figure 4 The semiconductor device 100 may include first to third buffers 101-103, an encoder 110, a driver 120, etc. External clock signal CLK EXT The clock signal can be output to another semiconductor device via the clock transmission pin 105.

[0046] First buffer 101 and second buffer 102 can buffer first data D0 and second data D1, and input the buffered data to encoder 110. First data D0 and second data D1 can be different data, and can be encoded into an external clock signal CLK. EXT The data to be sent is the external clock signal CLK. EXT It is generated as a multi-level signal. The third buffer 103 can buffer the internal clock CLK of the semiconductor device 100.INT And send a buffered clock to encoder 110.

[0047] Encoder 110 and internal clock CLK INT It operates synchronously and can generate an external clock signal CLK capable of transmitting at least one of the first data D0 or the second data D1. EXT External clock signal CLK EXT It can be a clock signal sent to another storage device, or it can be a multilevel signal with four different levels generated by a pulse amplitude modulation method.

[0048] When only the first data D0 is encoded, the external clock signal CLK EXT It can be generated with a level lower than the low reference signal when the first data D0 is 0, and can be generated with a level higher than the low reference signal when the first data D0 is 1. External clock signal CLK EXT It can be sent as a clock signal to another storage device, and can be a multi-level signal that swings relative to an intermediate reference signal for each transition cycle.

[0049] According to some example embodiments, both the first data D0 and the second data D1 can be represented by an external clock signal CLK. EXT Encoding is performed. For example, when both the first data D0 and the second data D1 are 0, the external clock signal CLK... EXT It can be generated with a level lower than the low reference signal, and the external clock signal CLK is 1 when both the first data D0 and the second data D1 are 1. EXT It can be generated with a level greater than the high reference signal. Furthermore, when the first data D0 is 0 and the second data D1 is 1, the external clock signal CLK... EXT It can be generated with levels lower than the high reference signal and higher than the low reference signal. As mentioned above, the external clock signal CLK EXT It can be generated as a multi-level signal that swings based on an intermediate reference signal for each transition cycle.

[0050] Figure 5 A simplified diagram of a receiver-side storage device 200 is shown, which receives an external clock signal CLK that is generated as a multi-level signal. EXT And by controlling the external clock signal CLK EXT Decoding is performed to recover the data. The storage device 200 can receive an external clock signal CLK via the clock receive pin 205. EXT .

[0051] External clock signal CLK EXTThe clock signal CLK can be input to the delay circuit 202 via the clock buffer 201. EXT The inputs can be fed into the first sense amplifier 210 and the second sense amplifier 220, respectively. The first sense amplifier 210 can process the external clock signal CLK. EXT With the first reference signal V REF1 The comparison is performed, and the second sense amplifier 220 can output the external clock signal CLK. EXT With the second reference signal V REF2 Comparison. First reference signal V. REF1 It can be lower than the second reference signal V REF2 .

[0052] Delay circuit 202 can adjust the external clock signal CLK. EXT The phase of the signal is adjusted, and the phase-adjusted signal is input to the first sense amplifier 210 and the second sense amplifier 220. In the example embodiment, the delay circuit 202 can adjust the phase of the external clock signal CLK. EXT The phase is delayed by 90 degrees to generate the delayed clock signal CLK. DLY The first sense amplifier 210 and the second sense amplifier 220 can be synchronized with the delayed clock signal CLK. DLY Synchronous operation.

[0053] For example, due to differences between the first transmission path from clock receive pin 205 to the first sense amplifier 210 and the second transmission path from clock receive pin 205 to the second sense amplifier 220, the external clock signals CLK input to the first sense amplifier 210 and the second sense amplifier 220 are respectively... EXT They can have different phases. The delay circuit 202 can independently adjust the delayed clock signal CLK input to the first sense amplifier 210 and the second sense amplifier 220. DLY The phase of the first sense amplifier 210 and the second sense amplifier 220 are optimized to optimize their operating timing.

[0054] Decoder 230 can generate data (DATA) using a first output signal of the first sense amplifier 210 and a second output signal of the second sense amplifier 220. Each of the first and second output signals can be a non-return-to-zero (NRZ) signal. As an example, the data may include at least one of a first output data generated from the first output and a second output data generated from the second output signal. In the example embodiment, the first output data may correspond to the above reference. Figure 4 The first data D0 is described, and the second output data can correspond to the second data D1.

[0055] In the example embodiment, when the external clock signal CLKEXT Below the first reference signal V REF1 At that time, the first output signal has a first logic value, and when the external clock signal CLK... EXT Greater than the first reference signal V REF1 At this time, the first output signal can have a second logic value. Similarly, when the external clock signal CLK... EXT Below the second reference signal V REF2 At that time, the second output signal has the first logic value, and when the external clock signal CLK... EXT Greater than the second reference signal V REF2 At that time, the second output signal can have a second logic value. The decoder can decode the first data D0 and the second data D1 by converting the first logic value of each of the first and second output signals to 0 and its second logic value to 1.

[0056] Figure 6 and Figure 7 The diagram is provided to illustrate the operation of the storage device according to an example embodiment.

[0057] first, Figure 6 This may be a diagram illustrating a clock signal received by a storage device according to an example embodiment. The clock signal received by the storage device according to the example embodiment may be a multi-level signal generated by a pulse amplitude modulation method, and may have first to fourth levels LV1 to LV4.

[0058] The clock signal can be encoded based on desired (or alternatively, predetermined) data in the transmitting semiconductor device that generates the clock signal. For example, when the data is 0, the clock signal has a value lower than the first reference signal V. REF1 Or the second reference signal V REF2 The clock signal can be generated with a level higher than the first reference signal V when the data is 1. REF1 Or the second reference signal V REF2 The clock signal level. Furthermore, the clock signal can be based on the intermediate reference signal V during the transition period TP. MID The swing allows the receiving-side storage device to generate the internal clock signal required for operation based on the clock signal.

[0059] Figure 7 This diagram illustrates a method for decoding data encoded as a clock signal using a storage device that receives a clock signal. (See reference...) Figure 7 The storage device can generate a delayed clock signal by shifting the clock signal by 90 degrees. Furthermore, the delayed clock signal can be generated based on the clock signal and an intermediate reference signal (e.g., a first reference signal V) at both the rising and falling edges. REF1 Or the second reference signal V REF2Data can be generated by at least one of the following: For example, the clock signal can be compared with a first reference signal V at the rising and falling edges of the delayed clock signal. REF1 Or the second reference signal V REF2 At least one of them is compared to generate data.

[0060] exist Figure 7 In the example embodiment shown, the first data D0 can be obtained by interpolating the clock signal with the first reference signal V at each rising and falling edge of the delayed clock signal. REF1 Data generated through comparison. (Refer to...) Figure 7 During the first data transmission cycle PR, the clock signal is greater than the first reference signal V. REF1 Furthermore, the first data D0 can be restored to 1. During the second transmission cycle PR, because the clock signal is lower than the first reference signal V... REF1 Therefore, the first data D0 can be restored to 0.

[0061] On the other hand, Figure 7 In the example embodiment shown, the second data D1 can be obtained by interpolating the clock signal with the second reference signal V at each rising and falling edge of the delayed clock signal. REF2 Data generated through comparison. (Refer to...) Figure 7 During the first data transmission cycle PR, the clock signal is greater than the second reference signal V. REF2 Furthermore, the second data D1 can be restored to 1. During the second transmission cycle PR, the clock signal is lower than the second reference signal V. REF2 Therefore, the second data D1 can be restored to 0. Since the first data D0 and the second data D1 are generated simultaneously with 1 bit, the storage device can generate 2 bits of data within each data transmission cycle PR of the clock signal received as a multi-level signal.

[0062] For reference Figure 7 As described, a memory device that receives a clock signal generated as a multi-level signal can decode data from the clock signal using a delayed clock signal generated by the delayed clock signal. Therefore, by generating a single clock signal as a multi-level signal, both data and the clock signal required for operation can be received. This reduces the number of transmitters and receivers, as well as the number of pins, required for communication between one memory device and another, improves the integration density of the memory device, and reduces its power consumption.

[0063] Figure 8A , Figure 8B and Figure 9 This is a schematic diagram illustrating a storage device according to an example embodiment.

[0064] first, Figure 8AA simplified diagram may be shown of a transmitting-side semiconductor device 100A, which encodes desired (or alternatively, predetermined) data using a clock signal generated as a multi-level signal and transmits the encoded data. According to... Figure 8A The semiconductor device 100A of the illustrated example embodiment may include a memory controller for controlling memory devices. (Refer to...) Figure 8A The semiconductor device 100A may include a first buffer 101 and a second buffer 102, an encoder 110A, and a driver 120A. External clock signal CLK EXT It can be output to another memory device via clock transmission pin 105.

[0065] exist Figure 8A In the example embodiment shown, semiconductor device 100A can encode the data transmitted in 1 bit per data transmission cycle into an external clock signal CLK. EXT It then outputs the encoded data to another storage device. Semiconductor device 100A may include a mechanism for encoding data into an external clock signal CLK. EXT The circuit. In the following text, reference will be made to... Figure 8B This example embodiment will be described in more detail.

[0066] Figure 8B This may be a simplified diagram showing the transmitter 150 included in the transmitting-side semiconductor device 100A. (Refer to...) Figure 8B The transmitter 150 may include a first driver 151, a second driver 152, and a multiplexer (MUX). Similar to the previous embodiments, the external clock signal CLK generated by the transmitter 150... EXT It can be a multi-level signal with M levels (where M is a natural number greater than 2), and can oscillate based on (or relative to) the intermediate level corresponding to the median value of the minimum and maximum levels among the M levels.

[0067] The first driver 151 can control the external clock signal CLK. EXT Based on the intermediate level swing. For example, for the external clock signal CLK to be generated. EXT In each cycle, the first control signal CTR1 input to the first driver 151 can be changed to a high logic value or a low logic value. For example, when the first control signal CTR1 is a low logic value, the PMOS transistor of the first driver 151 can be turned on, and when the first control signal CTR1 is a high logic value, the NMOS transistor can be turned on. For each cycle, the first control signal CTR1 can be changed to a high logic value or a low logic value, causing the external clock signal CLK to... EXT Based on the mid-level swing.

[0068] In the example embodiment, the first control signal CTR1 can be generated by the external clock signal CLK from the previous cycle. EXT The high-order bit MSB_PRE is determined. For example, the first control signal CTR1 can be latched by the external clock signal CLK from the previous cycle. EXT It is generated using the high-order bits MSB_PRE.

[0069] The second driver 152 can be controlled by an external clock signal CLK. EXT The data transmitted after encoding is manipulated. For example, the second control signal CTR2, which determines the operation of the second driver 152, can be controlled by an external clock signal CLK. EXT The data transmitted during encoding is used to determine this. In an example embodiment, when the data is 0, the second control signal CTR2 may have the external clock signal CLK from the previous cycle. EXT The high-order bit MSB_PRE is supplemented with a value. On the other hand, when the data is 1, the second control signal CTR2 can have the same value as the external clock signal CLK in the previous cycle. EXT The high-order bits MSB_PRE have the same value.

[0070] For example, when the external clock signal CLK EXT During the first cycle, when the level corresponds to

[00] , the NMOS transistors of the first driver 151 and the second driver 152 can be turned on during the first cycle. In the second cycle following the first cycle, the NMOS transistor can be turned off in the first driver 151, and the PMOS transistor can be turned on. On the other hand, when an external clock signal CLK is to be sent... EXT When the transmitted data is 1, the second control signal CTR2 is selected as 0, which is the previous high-order bit MSB_PRE, and the PMOS transistor of the second driver 152 is turned on in the second cycle, and the external clock signal CLK... EXT It can have a level corresponding to

[11] . On the other hand, when the data is 0, the second control signal CTR2 can be selected as 1, which is the complement value of the previous high-order bit MSB_PRE, and the NMOS transistor of the second driver 152 can be turned on in the second cycle. Therefore, in the second cycle, the external clock signal CLK EXT It can have a level corresponding to

[10] .

[0071] Similarly, when the external clock signal CLK EXTWhen the data is 1 and corresponds to the level of

[10] in the first cycle, the second control signal CTR2 in the second cycle can be selected as 1, which is the previous high-order bit MSB_PRE. Therefore, during the second cycle, the NMOS transistor in the second driver 152 is turned on, and the external clock signal CLK is turned on. EXT It can have a level corresponding to

[00] . On the other hand, when the data is 0, in the second cycle, the second control signal CTR2 is determined to be 0, which is the supplementary value of the previous high bit MSB_PRE, and the PMOS transistor in the second driver 152 is turned on, so the external clock signal CLK... EXT It can have a level corresponding to

[01] .

[0072] Next, refer to Figure 9 The receiver-side storage device 200A may include an external clock signal CLK. EXT The sense amplifiers 241-243 are compared with a reference signal, and the decoder 250 is used to recover the data. In the following text, reference will be made to... Figure 10A and Figure 10B The operation of the transmitting-side semiconductor device 100A and the receiving-side storage device 200A is described together.

[0073] Figure 10A and Figure 10B The diagram is provided to illustrate the operation of the storage device according to an example embodiment.

[0074] Figure 10A and Figure 10B This shows the external clock signal CLK received by the storage device 200A. EXT The diagram shows the external clock signal CLK. EXT It can be a multi-level signal with first to fourth levels (LV1 to LV4), and can be based on an intermediate reference signal V. MID swing.

[0075] As mentioned above, the external clock signal CLK can be determined based on the data to be sent. EXT The second driver 152 of the transmitting-side semiconductor device 100A can be operated by a second control signal CTR2 determined according to the data. For example, when the data is 0, the external clock signal CLK... EXT The low bit can be input as is to the second driver 152 as the second control signal CTR2. Therefore, the external clock signal CLK EXT It can have a second level LV2 or a third level LV3. Conversely, when the data is 1, the external clock signal CLK... EXT The low bit is inverted by the multiplexer MUX and can be input to the second driver 152 as the second control signal CTR2. Therefore, the external clock signal CLK...EXT It can have a first level LV1 or a fourth level LV4.

[0076] exist Figure 10A In the example embodiment shown, an external clock signal CLK is used. EXT The data sent can be [11000011100]. On the other hand, in Figure 10B In the example embodiment shown, CLK is used as the external clock signal. EXT The data sent can be [10110100011]. See below for reference. Figure 10A and Figure 10B as well as Figure 9 The operation of the receiver-side storage device 200A will be described below. First, please refer to Table 1 below for a description. Figure 10A The external clock signal CLK shown in the example embodiment EXT The data transmitted and the operation of the receiving-side storage device 200A according to this example embodiment.

[0077] [Table 1]

[0078]

[0079]

[0080] Reference Figure 9 The storage device 200A can be based on an external clock signal CLK. EXT With intermediate reference signal V MID (For example, by comparing the external clock signal CLK) EXT With intermediate reference signal V MID The memory device 200A generates a clock signal CLK. Furthermore, the memory device 200A can also use an external clock signal CLK. EXT With the first reference signal V REF1 The first data D0 is generated by comparison, and can be generated by external clock signal CLK. EXT With the second reference signal V REF2 The comparison is used to generate the second data D1.

[0081] In an example embodiment, the first data D0 and the second data D1 can be used to generate odd data OD and even data ED, respectively. For example, odd data OD can be generated by inputting the second data D1 and the clock signal CLK into a NAND gate and inverting the output of the NAND gate. Even data ED can be generated by inverting the first data D0 to be input into the NAND gate and the clock signal CLK, and inverting the output of the NAND gate. The decoder 250 may include a data output unit 251. The data output unit 251 can alternately output odd data OD and even data ED to generate data using an external clock signal CLK. EXT Encoded data.

[0082] Next, as a basis Figure 10B The external clock signal CLK shown in the example embodiment EXT The transmitted data and the operation of the receiving-side storage device 200A according to this example embodiment are shown in Table 2 below. The operation of the storage device 200A can be understood similarly to that described with reference to Table 1 above.

[0083] [Table 2]

[0084] DATA 1 0 1 1 0 1 0 0 0 1 1 CLK 1 0 1 0 1 0 1 0 1 0 1 D0 1 1 1 0 1 0 1 1 1 0 1 D1 1 0 1 0 0 0 0 0 0 0 1 ED 0 0 0 1 0 1 0 0 0 1 0 OD 1 0 1 0 0 0 0 0 0 0 1

[0085] Figure 11 The diagram is provided to illustrate the operation of the storage device according to an example embodiment.

[0086] Reference Figure 11 The system according to the example embodiment may include a first semiconductor device 300 and a second semiconductor device 400. (Referring to...) Figure 11 In the described example embodiment, the first semiconductor device 300 can generate and transmit a clock signal, while the second semiconductor device 400 can receive the clock signal. In the example embodiment, the first semiconductor device 300 may be a device including a memory controller, while the second semiconductor device 400 may be a memory device that stores data in response to the control of the first semiconductor device 300.

[0087] The first semiconductor device 300 can generate raw data to be transmitted by encoding data into a clock signal (S10). When generating or selecting raw data, the first semiconductor device 300 can generate a clock signal as a multi-level signal based on the data (S11). As described above, the clock signal can be generated as a multi-level signal using a pulse amplitude modulation method. In this case, the multi-level signal can have at least four levels based on at least three reference signals, and the clock signal can oscillate based on an intermediate reference signal with an intermediate level among the reference signals. For example, for each transition cycle, the clock signal can increase or decrease based on the intermediate reference signal.

[0088] The first semiconductor device 300 can send a clock signal to the second semiconductor device 400 (S12). The second semiconductor device 400 can generate a delayed clock signal by delaying the clock signal (S13). For example, the second semiconductor device 400 generates a delayed clock signal by delaying the phase of the clock signal by 90 degrees, and the timing of the second semiconductor device 400 comparing the clock signal with the reference signal can be determined by the delayed clock signal.

[0089] The second semiconductor device 400 includes a multilevel receiver that decodes a clock signal to recover the original data (S14). The multilevel receiver includes a sense amplifier that compares a clock signal with a reference signal, and the timing of the operation of the sense amplifier can be determined by a delayed clock signal.

[0090] Multilevel receivers can recover data based on a multilevel signal (e.g., a clock signal) and a reference signal. For example, for each rising edge and each falling edge of a delayed clock signal, the sense amplifier of the multilevel receiver can compare the clock signal with the reference signal. When the clock signal is greater than the reference signal at the rising or falling edge of the delayed clock signal, the multilevel receiver can recover the data as 1, and when the clock signal is less than the reference signal, it can recover the data as 0.

[0091] Figure 12 This is a schematic diagram of a storage system according to an example embodiment.

[0092] Reference Figure 12 The storage system 500 according to an example embodiment may include a controller 510 and a storage device 520. The controller 510 may include a DQS output circuit 511, a data input / output circuit 512, a clock generator 513, a command / address signal generator 514, a processor 515, etc. The components 511-515 included in the controller 510 can exchange data with each other via a bus 516. On the other hand, the storage device 520 may include a DQS receiver 521, a data transceiver 522, a clock receiver 523, a command / address signal receiver 524, and a storage area 525. The components 521 to 525 included in the storage device 520 can exchange data with each other via a bus 526. The storage area 525 may include a memory bank having memory cells.

[0093] At least one of the data signal DQ, data strobe signal DQS, clock signal CLK, or command / address signal CA transmitted between controller 510 and storage device 520 may be a multi-level signal. In an example embodiment, controller 510 may encode desired (or alternatively, predetermined) data into at least one of clock signal CLK or data strobe signal DQS, and may send the encoded data to storage device 520.

[0094] In an example embodiment, controller 510 can encode desired (or alternatively, predetermined) raw data into a data strobe signal DQS and can transmit the encoded data to storage device 520. DQS receiver 521 of storage device 520 can recover the data strobe signal DQS received as a multi-level signal into an NRZ signal. Furthermore, DQS receiver 521 can compare the data strobe signal DQS received as a multi-level signal with at least one reference signal to recover the raw data encoded as the data strobe signal DQS.

[0095] For example, controller 510 can encode at least one of Data Bus Inverted (DBI) data, Error Correcting Code (ECC) data, Cyclic Redundancy Check (CRC) data, Data Mask (DM) data, or command / address data into a Data strobe signal (DQS) and / or a Clock signal (CLK), and can send the encoded data to storage device 520. As an example, when controller 510 encodes command / address data into a Data strobe signal DQS and / or a Clock signal CLK and sends the encoded data to storage device 520, the command / address signal receiver 524 and the pin for receiving the command / address signal can be omitted from storage device 520. Additionally, when DBI data is encoded into a Data strobe signal DQS and / or a Clock signal CLK and sent to storage device 520, the pin for receiving DBI data may not be included in storage device 520.

[0096] As described above, in the example embodiment, the controller 510 transmits data by including desired (or alternatively, predetermined) data in the data strobe signal DQS and / or the clock signal CLK, and the storage device 520 can decode the data included in the data strobe signal DQS and / or the clock signal CLK. Therefore, the pins for the storage device 520 to receive data as separate signals and the receiver can be omitted, which can improve the integration of the storage device 520 and reduce power consumption.

[0097] Furthermore, the storage device 520 generates a delayed multilevel signal by delaying the data strobe signal DQS and / or the clock signal CLK, which includes the data, and can use the delayed multilevel signal to decode the data included in the data strobe signal DQS and / or the clock signal CLK. Therefore, data encoded as the data strobe signal DQS and / or the clock signal CLK can be received without a separate signal for determining the operation timing.

[0098] Figure 13 This is a schematic diagram of a storage device included in a storage system according to an example embodiment.

[0099] Reference Figure 13 The storage device 600 according to the example embodiment may include a command / address decoder 601, a clock buffer 602, a clock controller 603, a receiver 604, a transmitter 605, a data latch 606, a DQS buffer 607, a DQS transmitter 608, a row decoder 610, a column decoder 620, an input / output circuit 630, a memory bank 640, etc. Components other than the memory bank may be included in the logic circuitry of the storage device 600.

[0100] The row decoder 610 and column decoder 620 can select at least one of the memory cells included in the memory bank 640, and the input / output circuit 630 can write data to the selected memory cell or read data stored in the selected memory cell. The row decoder 610 and column decoder 620 can determine the selected memory cell based on the command / address signal received by the command / address decoder 601.

[0101] Furthermore, the storage device 600 may include multiple circuits connected to pins P1 through P4. For example, a command / address decoder 601 may be connected to command / address pin P1, and a clock buffer 602 and a clock controller 603 may be connected to clock pin P2. A receiver 604 and a transmitter 605 may be connected to data pin P3. A DQS buffer 607 may be connected to DQS pin P4.

[0102] Receiver 604 and transmitter 605 can be connected to input / output circuit 630 via data latch 606. Data latch 606 can store data received by receiver 604 from external semiconductor devices and can transmit the stored data to input / output circuit 630, or transmit data stored in input / output circuit 630 to transmitter 605. Data latch 606 can operate synchronously with a data strobe signal output from DQS transmitter 608.

[0103] For example, at least one of the clock signal received via clock pin P2 or the data strobe signal received via DQS pin P4 can be a multi-level signal. For example, the data strobe signal can be a multi-level signal including at least one of DBI data, ECC data, CRC data, or DM data.

[0104] A multilevel receiver that decodes data from a data strobe signal can be connected to the DQS pin P4. The multilevel receiver can recover the data included in the data strobe signal by comparing the data strobe signal with at least one of a first reference signal or a second reference signal. The first and second reference signals can be reference signals among the multilevel signal's reference signals that have an amplitude different from that of an intermediate reference signal.

[0105] According to some example embodiments, a multilevel receiver can also be connected to clock pin P2. A multilevel receiver connected to clock pin P2 can compare a clock signal with at least one of a first clock reference signal or a second clock reference signal greater than the first clock reference signal to recover data encoded as a clock signal. The first and second clock reference signals can have different levels than the data strobe signal.

[0106] As an example, you can refer to the above reference. Figures 5 to 7 and Figure 9 The described example embodiment is used to understand the operation of a multilevel receiver connected to clock pin P2. The data encoded as a clock signal can be different from the data encoded as a multilevel signal. For example, the data encoded as a multilevel signal can be DBI data, while the data encoded as a clock signal can be ECC data.

[0107] Figure 14 This is a schematic diagram of a storage device included in a storage system according to an example embodiment.

[0108] Reference Figure 14 According to an example embodiment, the storage device 700 can receive a first multi-level signal corresponding to the data strobe signal DQS via a first pin P1, a second multi-level signal corresponding to the inverted data strobe signal DQSB via a second pin P2, and a data signal DQ via a third pin P3. For example, the data signal DQ is connected to a reference voltage V via a sense amplifier 740. REF The data signals are compared and can be stored in the data latch 750. When the data signal DQ is a multi-level signal, the data signal DQ can be input to multiple sense amplifiers. Different reference voltages can be input to multiple sense amplifiers.

[0109] The first multi-level signal and the second multi-level signal can be input to the delay circuit 702 and the DQS transmission circuit 703 through the buffer 701. Furthermore, the first multi-level signal can be jointly input to the first sense amplifier 710 and the second sense amplifier 720 of the multi-level receiver 705. The first sense amplifier 710 can input the first multi-level signal and the first reference signal V... REF1 A comparison is made to generate a first output signal, and the second sense amplifier 720 can generate a first output signal by comparing the second multi-level signal with the second reference signal V. REF2 A comparison is used to generate a second output signal.

[0110] The data strobe signal DQS can be a multi-level signal with M levels (where M is a natural number greater than 2), and the multi-level receiver 705 can include N sense amplifiers (N is a natural number less than M). Figure 11 In the example embodiment shown, the data strobe signal can be a multi-level signal with four levels. When the four levels of the multi-level signal are defined in amplitude order as the first level to the fourth level, the first reference signal V... REF1 It has an intermediate level between the first level and the second level, and the second reference signal V REF2 It can have an intermediate level between the third and fourth levels.

[0111] Delay circuit 702 can generate a delayed multilevel signal DLY by delaying a first multilevel signal and / or a second multilevel signal. First sense amplifier 710 and second sense amplifier 720 can respectively connect the first multilevel signal to a first reference signal V at each rising edge and each falling edge of the delayed multilevel signal DLY. REF1 Second reference signal V REF2 Compare them.

[0112] The first sense amplifier 710 can connect the first multi-level signal with the first reference signal V. REF1 A comparison is made to generate a first output signal, and the second sense amplifier 720 can generate a first output signal by comparing the second multi-level signal with the second reference signal V. REF2 A comparison is made to generate a second output signal. The multilevel receiver 705 may also include a decoder 730, which uses at least one of the first or second output signals to generate data.

[0113] In the following text, we will refer to... Figures 15 to 17 The operation of storage device 700 is described in more detail.

[0114] Figures 15 to 17 The diagram is provided to illustrate the operation of the storage device according to an example embodiment.

[0115] Figure 15 This could be an example of a multi-level signal received by the storage device 700 via the DQS pin P1. (See reference...) Figure 15 Multilevel signals can have first to fourth levels LV1 to LV4, and can be based on an intermediate reference signal V. MID Oscillation. For example, for each transition cycle TP, the multi-level signal can be transmitted through the intermediate reference signal V. MID It can increase or decrease at the same time.

[0116] The DQS transmission circuit 703 can use multi-level signals to recover the data strobe signal DQS and the inverted data strobe signal DQSB back to the NRZ signal. (Refer to...) Figure 16 It can be based on multi-level signals and intermediate reference signals V MID The comparison result is used to generate the data strobe signal DQS. For example, when the multi-level signal is greater than the intermediate reference signal V... MID At that time, the data strobe signal DQS has a high logic value, and when the multi-level signal is lower than the intermediate reference signal V... MID At this time, the data strobe signal DQS can have a low logic value. The inverted data strobe signal DQSB can be the inverted signal of the data strobe signal DQS.

[0117] On the other hand, as described above, the multilevel receiver 705 can decode the data included in the multilevel signal. The first sense amplifier 710 connects the data strobe signal DQS with the first reference signal V. REF1 The comparison is performed, and the second sense amplifier 720 can compare the data strobe signal DQS with the second reference signal V. REF2 The first and second sense amplifiers 710 and 720 compare the data strobe signal with the first reference signal V. REF1 Second reference signal V REF2 The timing of the comparison can be controlled by the delay signal DLY.

[0118] Reference Figure 17 For each rising and falling edge of the delayed signal DLY, the first sense amplifier 710 can synchronize the multi-level signal with the first reference signal V. REF1 The comparison is performed, and the second sense amplifier 720 can compare the multi-level signal with the second reference signal V. REF2 The comparison is performed. The first data D0 can be the data generated by the decoder 730 from the first output signal of the first readout amplifier 710, and the second data D1 can be the data generated by the decoder 730 from the second output signal of the second readout amplifier 720.

[0119] Reference Figure 17 During the first data transmission cycle PR, the multi-level signal can be lower than the first reference signal V. REF1Furthermore, the first data D0 can be generated as 0. Moreover, in the second transmission cycle PR, the multi-level signal can be greater than the first reference signal V. REF1 Furthermore, the first data D0 can be generated as 1. Additionally, during the first data transmission cycle PR, the clock signal can be lower than the second reference signal V. REF2 Furthermore, the second data D1 can be generated as 0. Additionally, during the second transmission cycle PR, the clock signal is greater than the second reference signal V. REF2 Furthermore, the second data D1 can be generated as 1. Since the first data D0 and the second data D1 are generated simultaneously with 1 bit, the storage device 700 can generate 2 bits of data for each data transmission cycle PR of the multi-level signal.

[0120] As described above, the multilevel signal can be a signal received by the memory device 700 via the DQS pin P1. The first data D0 and / or the second data D1 generated from the multilevel signal can include at least one of DBI data, CRC data, ECC data, DB data, or command / address data. Therefore, the memory device 700 may not require a separate pin and receiver for receiving the first data D0 and / or the second data D1, and the density and power consumption of the memory device 700 can be improved.

[0121] According to an example embodiment, the storage device 700 can use first data D0 and second data D1 to recover the original data encoded as a multi-level signal by an external semiconductor device. For example, the first data D0 and second data D1 can be used to generate original data. In some example embodiments, one of the first data D0 or the second data D1 can be processed as dummy data.

[0122] Figure 18 This could be an example of a multi-level signal received by the storage device 700 via the DQS pin P1. (See reference...) Figure 15 Multilevel signals can have first to fourth levels LV1 to LV4, and can be based on an intermediate reference signal V. MID Oscillation. For example, for each transition cycle TP, the multi-level signal can be transmitted through the intermediate reference signal V. MID It can increase or decrease at the same time.

[0123] In the example embodiment, Figure 18 The multi-level signal shown can be derived from a reference. Figure 8BThe transmitter 150 describes the generated signal. For example, when the data to be transmitted via the multilevel signal is 0, the low bit (LSB) of the multilevel signal is input as is as the second control signal CTR2 of the second driver 152, so that the multilevel signal can have a second level LV2 or a third level LV3. When the data to be transmitted as the multilevel signal is 1, the low bit (LSB) of the multilevel signal is inverted and then input to the second driver 152 as the second control signal CTR2, so that the multilevel signal has a first level LV1 or a fourth level LV4. Therefore, in Figure 18 In the example embodiment shown, the data transmitted as a multi-level signal can be [10001110100].

[0124] Included in accordance with Figure 18 The data in the multilevel signal of the example embodiment shown can be obtained from the above reference. Figure 9 The decoder 250 described is used for recovery. As an example, it is used to recover data from... Figure 18 The operation of the readout amplifiers 241 to 243 and the decoder 250 for multi-level signal recovery data in the example embodiment shown can be as described in Table 3 below.

[0125] [Table 3]

[0126] DATA 1 0 0 0 1 1 1 0 1 0 0 CLK 1 0 1 0 1 0 1 0 1 0 1 D0 1 1 1 1 1 0 1 1 1 1 1 D1 1 0 0 0 1 0 1 0 1 0 0 ED 0 0 0 0 0 1 0 0 0 0 0 OD 1 0 0 0 1 0 1 0 1 0 0

[0127] Figure 19 This is a schematic diagram of a storage system according to an example embodiment.

[0128] according to Figure 19 The storage system 1000 of the example embodiment shown may be a solid-state drive (SSD). The storage system 1000 may have a form factor according to the M.2 standard and may communicate with external central processing units, systems-on-a-chip, application processors, etc., according to the Peripheral Component Interconnect Fast (PCIe) protocol.

[0129] The storage system 1000 may include a system board 1001, connector pins 1002 and component elements 1003 formed on the system board 1001, a controller 1010 mounted on the system board 1001, a NAND memory 1020, a DRAM 1030, a PMIC 1040, etc. The connector pins 1002 may contact pins of computer devices and / or server devices on which the storage system 1000 is mounted. The component elements 1003 may include passive components, such as resistors and capacitors required for the operation of the storage system 1000.

[0130] The controller 1010 can control the storage system 1000 according to control commands from computer devices and / or server devices. The controller 1010 can store data received via connector pin 1002 in NAND memory 1020 and / or DRAM 1030, or can read data stored in NAND memory 1020 and / or DRAM 1030 to output the read data to the computer devices and / or server devices. The PMIC 1040 can distribute power received via connector pin 1002 to the controller 1010, NAND memory 1020, DRAM 1030, etc.

[0131] The controller 1010 can be connected to the NAND memory 1020 and DRAM 1030 via wiring formed on the system board 1001. For example, the controller 1010 can generate data signals, etc., using a pulse amplitude modulation method, and send the generated signals to the NAND memory 1020 and / or DRAM 1030. The multi-level receivers of the NAND memory 1020 and / or DRAM 1030 that receive pulse amplitude modulated data signals, etc., can operate synchronously with a clock signal received from the controller 1010.

[0132] As previously referred to Figures 1 to 18 The NAND memory 1020 and / or DRAM 1030 can receive signals other than data signals, such as clock signals and data strobe signals as multi-level signals. The controller 1010 can encode data into clock signals, data strobe signals, etc., and can send the encoded data to the NAND memory 1020 and / or DRAM 1030. The NAND memory 1020 and / or DRAM 1030 can recover the data by decoding the multi-level signals. Therefore, separate pins, transmitters, and receivers for sending and receiving data encoded as multi-level signals can be omitted.

[0133] Figure 20 This is a schematic block diagram illustrating a mobile system including a storage device according to an example embodiment.

[0134] Reference Figure 20 The mobile system 2000 may include a camera 2100, a display 2200, an audio processing unit 2300, a modem 2400, DRAM 2500a and 2500b, flash memory devices 2600a and 2600b, input / output devices 2700a and 2700b, and an application processor (“AP”) 2800.

[0135] The Mobile System 2000 can be implemented as a laptop computer, portable terminal, smartphone, tablet PC, wearable device, healthcare device, or Internet of Things (IoT) device. Alternatively, the Mobile System 2000 can be implemented as a server or personal computer.

[0136] Camera 2100 can capture still images or videos under user control. Mobile system 2000 can use the still images / videos captured by camera 2100 to obtain specific information, or it can convert the still images / videos into another type of data, such as text, and store that data. According to some example embodiments, mobile system 2000 can recognize strings included in the still images / videos captured by camera 2100 and provide text or audio translations corresponding to those strings. Thus, the applications of camera 2100 in mobile system 2000 are becoming increasingly diverse. In example embodiments, camera 2100 can send data such as still images / videos to AP 2800 via a MIPI-based D-Phy or C-Phy interface.

[0137] Display 2200 can be implemented in various forms, such as liquid crystal display (LCD), organic light-emitting diode (OLED) display, active-matrix organic light-emitting diode (AM-OLED), plasma display panel (PDP), field emission display (FED), or electronic paper. In an example embodiment, display 2200 can also be used as an input device for mobile system 2000 by providing touchscreen functionality. Additionally, display 2200 can be integrated with a fingerprint sensor or similar device to provide security features for mobile system 2000. In an example embodiment, AP 2800 can send image data to be displayed on display 2200 via a MIPI-based D-Phy or C-Phy interface.

[0138] The audio processing unit 2300 can process audio data stored in flash memory devices 2600a and 2600b or audio data included in content received from the outside via modem 2400 or input / output devices 2700a and 2700b. For example, the audio processing unit 2300 can perform various processes on the audio data, such as encoding / decoding, amplification, and noise filtering.

[0139] The modem 2400 modulates and transmits signals to send / receive wired / wireless data and demodulates signals received from external sources to recover the original signal. Input / output devices 2700a and 2700b are devices that provide digital input / output and may include ports that can be connected to external recording media, input devices such as touchscreens and mechanical buttons, and output devices that output vibrations in a haptic or other manner. In some examples, input / output devices 2700a and 2700b can be connected to external recording media via ports such as USB, Lightning cable, SD card, micro SD card, DVD, network adapter, etc.

[0140] AP 2800 can control the overall operation of mobile system 2000. Specifically, AP 2800 can control display 2200, causing a portion of the content stored in flash memory devices 2600a and 2600b to be displayed on the screen. Additionally, when user input is received via input / output devices 2700a and 2700b, AP 2800 can perform control operations corresponding to the user input.

[0141] The AP 2800 can be provided as a System-on-Chip (SoC) driving applications, an operating system (OS), etc. Furthermore, the AP 2800 can be included in a semiconductor package and other devices included in the mobile system 2000, such as DRAM 2500a, flash memory 2620, and / or memory controller 2610. For example, the AP 2800 and at least one or more devices can be provided in the form of packages such as, for example, a PoP, a ball grid array (BGA), a chip-scale package (CSP), a system-in-package (SIP), a multi-chip package (MCP), a wafer-level fabrication package (WFP), a wafer-level processing stack package (WSP), etc. The kernel of the operating system running on the AP 2800 can include device drivers and an I / O scheduler for controlling flash memory devices 2600a and 2600b. The device drivers can control the access performance of flash memory devices 2600a and 2600b by referring to the number of synchronization queues managed by the I / O scheduler, or they can control CPU modes, dynamic voltage and frequency scaling (DVFS) levels, etc., within the SoC.

[0142] In an example embodiment, the AP 2800 may include a processor block that performs operations or drives applications and / or an operating system, as well as various other peripheral components connected to the processor block via a system bus. Peripheral components may include a memory controller, internal memory, a power management block, an error detection block, a monitoring block, etc. The processor block may include one or more cores, and in the case of multiple cores in the processor block, each core includes a cache memory, and the processor block may include a common cache shared by the cores.

[0143] In example embodiments, AP 2800 may also include accelerator block 2820, which is dedicated circuitry for AI data computation. According to some example embodiments, a separate accelerator chip may be provided separately from AP 2800, and DRAM 2500b may be additionally connected to accelerator block 2820 or the accelerator chip. Accelerator block 2820 is a functional block that specifically performs the functions of AP 2800 and includes a graphics processing unit (GPU) as a functional block and specifically for processing graphics data, a neural processing unit (NPU) as a block for specifically performing AI computation and inference, a data processing unit (DPU) as a block for specifically handling data transmission, etc.

[0144] According to an example embodiment, the mobile system 2000 may include multiple DRAMs 2500a and 2500b. In an example embodiment, the AP 2800 may include a controller 2810 for controlling the DRAMs 2500a and 2500b, and the DRAM 2500a may be directly connected to the AP 2800.

[0145] AP 2800 controls DRAM by setting Command and Mode Register (MRS) settings compliant with JEDEC standards, or by setting the specifications and functions required by Mobile System 2000 (e.g., low voltage / high speed / reliability) and DRAM interface protocols for CRC / ECC. For example, AP 2800 can communicate with DRAM 2500a through an interface compliant with JEDEC standards such as LPDDR4, LPDDR5, etc. According to some example embodiments, AP 2800 sets a new DRAM interface protocol to control DRAM 2500b, which has a higher bandwidth than DRAM 2500a, via accelerator block 2820 or an accelerator chip provided separately from AP 2800, thereby performing communication.

[0146] although Figure 20Only DRAMs 2500a and 2500b are shown, but the configuration of the mobile system 2000 is not necessarily limited to this type. Depending on the bandwidth, response speed, and voltage conditions of the AP 2800 or accelerator block 2820, other memories besides DRAMs 2500a and 2500b can also be included in the mobile system 2000. In the example, the controller 2810 and / or the accelerator block 2820 can control various types of memory, such as PRAM, SRAM, MRAM, RRAM, FRAM, hybrid RAM, etc. DRAMs 2500a and 2500b have relatively lower latency and relatively higher bandwidth than input / output devices 2700a and 2700b or flash memory devices 2600a and 2600b. DRAM 2500a and 2500b can be initialized at the power-on time of the mobile system 2000, and when the operating system and application data are loaded, DRAM 2500a and 2500b can be used as temporary storage locations for the operating system and application data or as execution space for various software code.

[0147] In DRAMs 2500a and 2500b, arithmetic operations such as addition / subtraction / multiplication / division, vector operations, address operations, or FFT operations can be stored. In another embodiment, DRAMs 2500a and 2500b can be provided as Process-in-Memory (PIM) equipped with computational capabilities. For example, functions for performing inference in DRAMs 2500a and 2500b can be executed. In this case, inference can be performed using an artificial neural network in a deep learning algorithm. The deep learning algorithm can include training operations that train a model with various data and inference operations that use the trained model to identify data. For example, functions for inference can include the hyperbolic tangent function, the sigmoid function, and the rectified linear unit (ReLU) function.

[0148] As an example embodiment, an image captured by a user through camera 2100 can be signal processed and stored in DRAM 2500b, and accelerator block 2820 or accelerator chip can use the data stored in DRAM 2500b and functions for inference to perform AI data operations on the recognition data.

[0149] According to an example embodiment, the mobile system 2000 may include multiple storage devices or multiple flash memory devices 2600a and 2600b with capacities greater than DRAM 2500a and 2500b. Flash memory devices 2600a and 2600b may include a memory controller 2610 and flash memory 2620. The memory controller 2610 receives control commands and data from the AP 2800, writes data to the flash memory 2620 in response to the control commands, or reads data stored in the flash memory 2620 to access the AP 2800, and may send the data to the AP 2800.

[0150] According to an example embodiment, the accelerator block 2820 or accelerator chip can use flash memory devices 2600a and 2600b to perform training operations and AI data computation. In the example embodiment, the operational logic capable of performing the desired (or alternatively, predetermined) operations within the flash memory devices 2600a and 2600b can be implemented in the controller 2610, and the operational logic can appropriately use data stored in the flash memory 2620 to perform at least a portion of the training operations and the operations of inference AI data performed by the AP 2800 and / or the accelerator block 2820.

[0151] In the example embodiment, AP 2800 may include interface 2830, and therefore, flash memory devices 2600a and 2600b can be directly connected to AP 2800. For example, AP 2800 may be implemented as a SoC, flash memory device 2600a may be implemented as a separate chip from AP 2800, and AP 2800 and flash memory device 2600a may be mounted in a single package. However, the example embodiment is not limited thereto, and multiple flash memory devices 2600a and 2600b may be electrically connected to mobile system 2000 via interconnection.

[0152] Flash memory devices 2600a and 2600b can store data such as still images / movies captured by camera 2100, or data received via a communication network and / or ports included in input / output devices 2700a and 2700b, and for example, can store augmented reality / virtual reality, high-definition (HD) or ultra-high-definition (UHD) content.

[0153] Included in reference Figure 20 At least some of the components in the described mobile system 2000, including camera 2100, display 2200, audio processing unit 2300, modem 2400, DRAM 2500a and 2500b, flash memory devices 2600a and 2600b, input / output devices 2700a and 2700b, and AP 2000, can exchange multilevel signals with each other. For example, AP 2800 can exchange multilevel signals with at least one of the other components. Devices for transmitting and receiving multilevel signals can use the above-described references. Figures 1 to 14 At least one of the described example embodiments transmits and receives data via a multilevel signal. For example, the multilevel signal may be a clock signal in addition to the data signal, or it may be a control signal used to notify the timing of data transmission.

[0154] As described above, according to the example embodiment, a clock signal and / or data strobe signal are received from an external controller as a multi-level signal generated by a method such as pulse amplitude modulation, and the received signal is decoded to recover the original data. Therefore, by omitting the separate pins used to transmit the original data between the controller and the storage device, the number of pins can be reduced, thereby improving the integration of the storage device and reducing power consumption.

[0155] Various components disclosed as black boxes in this disclosure (e.g., first / second output circuits, clock generators / receivers, first / second multilevel receivers, core circuits, delay circuits, various decoders, various encoders, drivers, multiplexers, data output units, DQS output circuits, data input / output circuits, command / address signal generators, DQS receivers, data transceivers, clock receivers, various transmitters, and command / address signal receivers) can be implemented as processing circuits, such as hardware or a combination of hardware and software including logic circuits, for example, a processor executing software. For example, the processing circuits may include, but are not limited to, central processing units (CPUs), arithmetic logic units (ALUs), digital signal processors, microcomputers, field-programmable gate arrays (FPGAs), system-on-a-chip (SoCs), programmable logic units, microprocessors, application-specific integrated circuits (ASICs), etc.

[0156] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A method of operating a storage device, comprising: The clock receive pin receives a multi-level signal with M levels sent by an external controller, where M is a natural number greater than 2. Decoding the multi-level signal to recover at least one of the following: inverted DBI data, data masked DM data, cyclic redundancy check (CRC) data, or error correction code (ECC) data; and A first output signal having a first logic value or a second logic value is generated based on the multi-level signal and the first reference signal, and a second output signal having the first logic value or the second logic value is generated based on the multi-level signal and the second reference signal, wherein the first logic value and the second logic value are different. The multi-level signal is a clock signal sent by the external controller, and it is a signal that swings based on an intermediate reference signal. This intermediate reference signal has a midpoint between the minimum and maximum levels among the M levels. Wherein, at least one of the first output signal or the second output signal is used to recover at least one of the DBI data, the DM data, the CRC data, or the ECC data.

2. The method according to claim 1, further comprising: When the multi-level signal is lower than the first reference signal, the first output signal with the first logic value is generated. When the multi-level signal is greater than the first reference signal, a first output signal having the second logic value is generated; when the multi-level signal is lower than the second reference signal which is greater than the first reference signal, a second output signal having the first logic value is generated; and when the multi-level signal is greater than the second reference signal, a second output signal having the second logic value is generated.

3. The method according to claim 1, wherein each of the first output signal and the second output signal is a non-return-to-zero (NRZ) signal.

4. The method according to claim 1, wherein The M levels include a first level, a second level greater than the first level, a third level greater than the second level, and a fourth level greater than the third level. The level of the first reference signal is the intermediate level between the first level and the second level, and the level of the second reference signal is the intermediate level between the third level and the fourth level.

5. The method according to claim 1, further comprising: A delayed multilevel signal is generated by delaying the phase of the multilevel signal. At each rising edge and each falling edge of the delayed multilevel signal, the multilevel signal is compared with the first reference signal and the second reference signal.

6. The method according to claim 1, further comprising: An internal clock signal is generated based on the multi-level signal and the intermediate reference signal.

7. A method of operating a storage device, comprising: The data strobe signal sent by an external controller is received through the DQS pin. The data strobe signal has M levels, where M is a natural number greater than 2. Decode the data strobe signal and recover the data encoded into the data strobe signal by the external controller; and A first output signal having a first logic value or a second logic value is generated based on the data strobe signal and the first reference signal, and a second output signal having the first logic value or the second logic value is generated based on the data strobe signal and the second reference signal, wherein the first logic value and the second logic value are different. The data gating signal is a signal that oscillates between the minimum and maximum levels among the M levels, and... The data is recovered using at least one of the first output signal or the second output signal.

8. The method according to claim 7, further comprising: When the data strobe signal is lower than the first reference signal, the first output signal with the first logic value is generated. When the data strobe signal is greater than the first reference signal, a first output signal having the second logic value is generated; when the data strobe signal is lower than the second reference signal which is greater than the first reference signal, a second output signal having the first logic value is generated; and when the data strobe signal is greater than the second reference signal, a second output signal having the second logic value is generated.

9. The method according to claim 8, wherein The M levels include a first level, a second level greater than the first level, a third level greater than the second level, and a fourth level greater than the third level. The level of the first reference signal is the intermediate level between the first level and the second level, and the level of the second reference signal is the intermediate level between the third level and the fourth level.

10. The method of claim 8, wherein When the data is 0, the data strobe signal has a level greater than the first reference signal and lower than the second reference signal, and When the data is 1, the data strobe signal has a level lower than the first reference signal or higher than the second reference signal.

11. The method according to claim 7, wherein, The data includes at least one of DBI data, DM data, CRC data, or ECC data.

12. A storage device comprising: The buffer is configured to receive a multi-level signal with M levels via the DQS pin, where M is a natural number greater than 2; The delay circuit is configured to generate a delayed clock signal by delaying the multi-level signal; A first sense amplifier is configured to generate a first output signal based on the multi-level signal and a first reference signal at the rising and falling edges of the delayed clock signal. The second sense amplifier is configured to generate a second output signal at the rising and falling edges of the delayed clock signal based on the multi-level signal and a second reference signal greater than the first reference signal; and The decoder is configured to use at least one of the first output signal or the second output signal to recover at least one of DBI data, DM data, CRC data, or ECC data encoded as the multi-level signal. Wherein, the first output signal has a first logic value or a second logic value based on the multi-level signal and the first reference signal, and The second output signal has either the first logic value or the second logic value based on the multi-level signal and the second reference signal, wherein the first logic value is different from the second logic value.

13. The storage device according to claim 12, wherein, The multi-level signal is based on an intermediate reference signal that oscillates, and the intermediate reference signal has a level that is different from the level of the first reference signal and the level of the second reference signal.

14. The storage device according to claim 13, wherein, The intermediate reference signal has a level that is greater than that of the first reference signal and lower than that of the second reference signal.

15. The storage device according to claim 13, further comprising: The DQS transmission circuit is configured to recover the data strobe signal based on the multi-level signal and the intermediate reference signal.

16. The storage device according to claim 13, wherein When the multi-level signal is lower than the first reference signal, the first output signal has the first logic value; and when the multi-level signal is greater than the first reference signal, the first output signal has a second logic value different from the first logic value. When the multi-level signal is lower than the second reference signal, the second output signal has the first logic value, and when the multi-level signal is greater than the second reference signal, the second output signal has the second logic value.

17. The storage device according to claim 12, wherein, The decoder is configured to recover at least one of the DBI data, the DM data, the CRC data, or the ECC data by alternately selecting the first output signal and the second output signal for each cycle of the multi-level signal.

18. The storage device according to claim 12, further comprising: A clock buffer is configured to receive an external clock signal with four levels; as well as A multilevel receiver is configured to recover data encoded with the external clock signal based on at least one of a first clock reference signal or a second clock reference signal greater than the first clock reference signal and the external clock signal.

19. The storage device according to claim 18, wherein, The external clock signal is a signal that oscillates between the minimum and maximum levels of the four levels.

20. The storage device according to claim 18, wherein, The data encoded as the external clock signal is different from the data encoded as the multi-level signal.

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