Method of manufacturing a semiconductor structure

Abstract

The application provides a semiconductor structure preparation method, relates to the technical field of semiconductor chips, and is used for increasing the application range of the preparation method and reducing the cost. The semiconductor structure preparation method comprises the following steps: providing a semiconductor structure to be etched, the semiconductor structure to be etched having an alignment mark; forming a hard mask layer on the semiconductor structure to be etched; and performing processing on at least a part corresponding to the alignment mark in the hard mask layer by using a laser process, so that the light transmittance of the part corresponding to the alignment mark in the hard mask layer after laser processing is greater than or equal to a preset light transmittance. The preset light transmittance is the minimum light transmittance of the part after laser processing in the hard mask layer under the condition that the alignment mark can be recognized from the side of the hard mask layer away from the semiconductor structure to be etched. The semiconductor structure preparation method is used for realizing data reading and writing operations.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip technology, and in particular to a method for fabricating a semiconductor structure. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of the process, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memory with a three-dimensional structure (3D NAND), which increases storage density by arranging storage cells three-dimensionally on a substrate. Summary of the Invention

[0004] The embodiments of the present invention provide a method for fabricating a semiconductor structure and a three-dimensional memory, which can increase the application range of the fabrication method, avoid stress formation in the semiconductor structure, and reduce the fabrication cost.

[0005] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0006] On one hand, a method for fabricating a semiconductor structure is provided. The method includes: providing a semiconductor structure to be etched, the semiconductor structure having alignment marks; forming a hard mask layer on the semiconductor structure to be etched; and processing at least a portion of the hard mask layer corresponding to the alignment marks using a laser process, such that the light transmittance of the portion of the hard mask layer corresponding to the alignment marks after laser processing is greater than or equal to a preset light transmittance. The preset light transmittance is the minimum light transmittance of the laser-processed portion of the hard mask layer when the alignment marks can be identified from the side of the laser-processed hard mask layer away from the semiconductor structure to be etched.

[0007] The semiconductor structure fabrication method provided in some embodiments of the present invention, after forming a hard mask layer on the semiconductor structure to be etched, processes at least the portion of the hard mask layer corresponding to the alignment marks using a laser process. This not only increases the transmittance of the portion of the hard mask layer corresponding to the alignment marks after laser processing, enabling more accurate acquisition of image information of the alignment marks, but also ensures that the stress generated by the laser is located only in the hard mask layer, avoiding stress generation in the semiconductor structure to be etched and preventing interference with subsequent fabrication processes. Furthermore, it ensures that the heat generated by the laser is located only in the hard mask layer, preventing adverse effects on the semiconductor device to be etched, thus expanding the application scope of the semiconductor structure fabrication method provided by the present invention.

[0008] Furthermore, by using laser technology to process at least the portion of the hard mask layer corresponding to the alignment marks, there is no need to laser other structures. Compared with related technologies, this reduces the energy used and lowers costs.

[0009] In some embodiments, processing at least the portion of the hard mask layer corresponding to the alignment mark using a laser process includes: obtaining information about the region where the alignment mark is located in the semiconductor structure to be etched; and processing the portion of the hard mask layer corresponding to the region where the alignment mark is located using a laser process based on the region information.

[0010] In some embodiments, processing at least the portion of the hard mask layer corresponding to the alignment mark using a laser process includes processing the entire hard mask layer using a laser process.

[0011] In some embodiments, the material of the hard mask layer prior to laser lithography includes amorphous silicon.

[0012] In some embodiments, the material of the laser-etched hard mask layer includes silicon in a crystalline state.

[0013] In some embodiments, the laser energy in the laser process is positively correlated with the thickness of the hard mask layer.

[0014] In some embodiments, the laser energy in the laser process is less than or equal to 2 J / cm². 2 .

[0015] In some embodiments, the preset transmittance is greater than the transmittance of at least a portion of the hard mask layer corresponding to the alignment mark before laser etching.

[0016] In some embodiments, the fabrication method further includes: forming a photoresist layer on the laser-etched hard mask layer; acquiring image information of the alignment marks through the laser-etched portion of the hard mask layer; aligning the mask with the semiconductor structure to be etched according to the acquired image information, and patterning the photoresist layer; using the patterned photoresist layer as a mask to pattern the laser-etched hard mask layer; and using the patterned hard mask layer as a mask to pattern the semiconductor structure to be etched.

[0017] In some embodiments, the semiconductor structure to be etched includes: a substrate; a gate stack structure disposed on the substrate; the gate stack structure having a plurality of channel holes; a channel structure located within the channel holes; a connection layer disposed on the gate stack structure; a plurality of contacts and the alignment mark disposed in the connection layer; and a dielectric layer disposed on the connection layer.

[0018] In some embodiments, the patterning process of the semiconductor structure to be etched using a patterned hard mask layer as a mask includes: using the patterned hard mask layer as a mask to pattern the dielectric layer to form a plurality of trenches. The fabrication method further includes: forming bit lines within the trenches; the bit lines being electrically connected to the channel structure through the contacts. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of this invention, the accompanying drawings used in some embodiments of this invention will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this invention, and those skilled in the art can obtain other drawings based on these drawings. Furthermore, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this invention.

[0020] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments of the present invention;

[0021] Figure 2 for Figure 1 A flowchart of the S300 system;

[0022] Figure 3 This is a flowchart illustrating another method for fabricating a semiconductor structure according to some embodiments of the present invention;

[0023] Figures 4a to 4d This is a step diagram of a method for fabricating a semiconductor structure according to some embodiments of the present invention;

[0024] Figures 5a to 5e This is a step diagram of a method for fabricating another semiconductor structure according to some embodiments of the present invention;

[0025] Figures 6a to 6g This is a step diagram illustrating another method for fabricating a semiconductor structure according to some embodiments of the present invention;

[0026] Figure 7 This is a schematic diagram of a semiconductor structure according to some embodiments of the present invention;

[0027] Figure 8 for Figure 7 A cross-sectional view of a memory cell string along section line AA' in the semiconductor structure shown. Detailed Implementation

[0028] The technical solutions in some embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided by the present invention are within the scope of protection of the present invention.

[0029] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0030] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of the invention. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0031] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of the present invention, unless otherwise stated, "a plurality of" means two or more.

[0032] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments invented herein are not necessarily limited to the content of this document.

[0033] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0034] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0035] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0036] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0037] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0038] In the context of this invention, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers therebetween, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers therebetween (i.e., directly on) something.

[0039] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0040] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0041] The term "three-dimensional memory" refers to a semiconductor device formed by strings of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate and extending in a direction perpendicular to the substrate. As used herein, the term "perpendicularly" means nominally perpendicular to the main surface of the substrate (i.e., the lateral surface).

[0042] Semiconductor structures (such as 3D memory) are typically formed by stacking multiple layers of films (such as insulating and / or conductive layers). During the fabrication of semiconductor structures, photolithography is usually employed to etch the films and obtain the desired patterns. A hard mask (HM) layer is used during photolithography to create patterns with clear outlines and fine dimensions.

[0043] In the fabrication techniques of 3D memory, the low transmittance of the hard mask layer can easily affect the outline and size of the subsequently formed pattern. Therefore, after forming the hard mask layer, a rapid thermal annealing (RTA) process is usually used to treat it to increase its transmittance. However, the process of treating the hard mask layer also treats the entire semiconductor structure, which can generate significant stress within the semiconductor structure, hindering subsequent fabrication processes. Furthermore, some structures within the semiconductor structure (such as the channel structure) cannot withstand high temperatures, limiting the types of semiconductor structures that can be used.

[0044] Based on this, some embodiments of the present invention provide a method for fabricating a semiconductor structure, such as... Figure 1 As shown, the preparation method includes: S100~S300.

[0045] S100, such as Figure 4a and Figure 6a As shown, a semiconductor structure 1 to be etched is provided. The semiconductor structure 1 to be etched has alignment marks 11.

[0046] In some examples, the semiconductor structure 1 to be etched may include a substrate 12 and one or more film layers 13 formed on the substrate 12.

[0047] For example, the aforementioned film layer 13 may include an insulating layer and / or a conductive layer. The insulating layer may be composed of one or more combinations of silicon oxide, silicon nitride, or high-dielectric-constant insulating materials. The conductive layer may be composed of one or more combinations of tungsten, cobalt, copper, aluminum, or metal silicides.

[0048] For example, such as Figure 4a and Figure 6a As shown, the alignment mark 11 can be located in the film layer 13.

[0049] S200, such as Figure 4b As shown, a hard mask layer 2 is formed on the semiconductor structure 1 to be etched.

[0050] In some examples, a hard mask layer 2 can be formed by a deposition process.

[0051] For example, the above deposition process can be: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Sputtering, Metal Organic Chemical Vapor Deposition (MOCVD), or Atomic Layer Deposition (ALD).

[0052] S300, such as Figure 4c , Figure 4d and Figure 6b As shown, a laser process is used to process at least the portion of the hard mask layer 2 corresponding to the alignment mark 11, so that the light transmittance of the portion of the hard mask layer 1 corresponding to the alignment mark 11 after laser processing is greater than or equal to the preset light transmittance.

[0053] The preset transmittance is the minimum transmittance of the laser-etched portion of the hard mask layer 2 when the alignment mark 11 can be identified from the side of the hard mask layer 2 away from the semiconductor structure 1 to be etched.

[0054] For example, the preset transmittance is greater than the transmittance of at least the portion of the hard mask layer 2 corresponding to the alignment mark 11 before laser treatment. That is, after laser treatment of at least the portion of the hard mask layer 2 corresponding to the alignment mark 11, the transmittance of that portion can be increased.

[0055] It should be noted that the preset transmittance is related to the lithography equipment itself. When the light source of the lithography equipment has a high requirement for the transmittance of the hard mask, the preset transmittance is larger; when the light source of the lithography equipment has a low requirement for the transmittance of the hard mask, the preset transmittance is smaller.

[0056] In some examples, "corresponding portion" may refer to the portion of the hard mask layer 2 that is opposite to the alignment mark 11 along a direction perpendicular to the substrate 12.

[0057] For example, at least the portion of the hard mask layer 2 corresponding to the alignment mark 11 can be, along a direction perpendicular to the substrate 12, the portion of the hard mask layer 2 opposite to the alignment mark 11 (e.g. Figure 4c (as shown), or the portion of the hard mask layer 2 opposite to the alignment mark 11 and the portions other than the opposite portion (such as... Figure 4d (As shown).

[0058] By laser-processing at least the portion of the hard mask layer 2 corresponding to the alignment mark 11, this portion can absorb laser energy, thereby activating the material in the energy-absorbing portion of the hard mask layer 2 and causing it to crystallize. This increases the light transmittance of the portion of the laser-processed hard mask layer 2 corresponding to the alignment mark 11, making the light transmittance reach or even exceed a preset light transmittance. To more clearly illustrate the structure of the hard mask layer 2, the portion of the hard mask layer 2 that has undergone laser processing and whose light transmittance changes is marked as the light-transmitting portion T in the following text and figures.

[0059] Once the preset transmittance is reached or exceeded, the light emitted by the light source of the photolithography equipment used in the photolithography process can be used to obtain more accurate image information of the alignment mark 11 through the light-transmitting part T. Then, based on the more accurate image information, the photomask used in the photolithography process can be more accurately aligned with the semiconductor structure 1 to be etched, and the pattern in the photomask can be gradually transferred to the semiconductor structure 1 to be etched, so that the transferred pattern has a clearer outline and finer dimensions.

[0060] Furthermore, compared to the RAT process, the laser process allows for controllable processing position when processing at least the portion of the hard mask layer 2 corresponding to the alignment mark 11. For example, the laser depth can be controlled by adjusting the laser energy. This ensures that the heat generated by the laser is confined to the hard mask layer 2, preventing it from penetrating the hard mask layer 2 and entering the semiconductor structure 1 to be etched. Consequently, the stress generated by the laser is confined to the hard mask layer 2, preventing stress from being generated in the semiconductor structure 1 to be etched.

[0061] Therefore, the semiconductor structure fabrication method provided in some embodiments of the present invention, after forming a hard mask layer 2 on the semiconductor structure 1 to be etched, uses a laser process to process at least the portion of the hard mask layer 2 corresponding to the alignment mark 11. This not only increases the transmittance of the portion of the hard mask layer 2 corresponding to the alignment mark 11 (i.e., the light-transmitting portion T) after laser processing, achieving more accurate acquisition of image information of the alignment mark 11, but also ensures that the stress generated by the laser is only located in the hard mask layer 2, avoiding stress in the semiconductor structure 1 to be etched, thus avoiding affecting the subsequent fabrication process. Furthermore, it also ensures that the heat generated by the laser is only located in the hard mask layer 2, avoiding adverse effects on the semiconductor device 1 to be etched, which is beneficial to expanding the application scope of the semiconductor structure fabrication method provided by the present invention.

[0062] Furthermore, when processing at least the portion of the hard mask layer 2 corresponding to the alignment mark 11 using laser technology, there is no need to laser other structures. Compared with related technologies, this reduces the energy required for enabling and lowers costs.

[0063] In some embodiments, the material of the hard mask layer 2 before laser engraving includes amorphous silicon (a-Si).

[0064] For example, the material of the hard mask layer 2 before laser lithography may also include other materials, wherein the material of at least the portion of the hard mask layer 2 before laser lithography corresponding to the alignment mark 11 may be amorphous silicon. These other materials include, but are not limited to, silicon oxide.

[0065] In some embodiments, the material of the hard mask layer 2 after laser etching includes silicon in a crystalline state. This crystalline silicon may, for example, include polycrystalline silicon or monocrystalline silicon (c-Si).

[0066] For example, the material of the portion of the hard mask layer 2 corresponding to the alignment mark 11 (i.e., the light-transmitting portion T) after laser etching includes monocrystalline silicon. That is, after laser etching at least the portion of the hard mask layer 2 corresponding to the alignment mark 11, its material can be crystallized from amorphous silicon to monocrystalline silicon. The transmittance of monocrystalline silicon is greater than that of amorphous silicon.

[0067] It should be noted that the laser energy in the above laser process is positively correlated with the thickness of the hard mask layer 2. That is, the greater the thickness of the hard mask layer 2, the greater the laser depth, and the greater the required laser energy. The smaller the thickness of the hard mask layer 2, the smaller the laser depth, and the less required laser energy.

[0068] In some examples, the laser energy in the laser process is less than or equal to 2 J / cm². 2 .

[0069] For example, the laser energy in the laser process can be 0.1 J / cm². 2 0.5J / cm 2 1J / cm 2 1.7J / cm 2 or 2J / cm 2 wait.

[0070] Here, with the development of science and technology, the thickness of the hard mask layer 2 may change significantly, and consequently the laser energy in the laser process may change. Therefore, the laser energy in the laser process of this invention is not limited to the above-mentioned range.

[0071] In some embodiments, in the above S300, there are various ways to process at least the portion of the hard mask layer 2 corresponding to the alignment mark 11 using laser technology, and the specific method can be selected and set according to actual needs.

[0072] In some examples, such as Figure 2 As shown, laser processing is used to process at least the portion of the hard mask layer 2 corresponding to the alignment mark 11, including: S310a to S320a.

[0073] S310a, obtain information about the region where the alignment mark 11 is located in the semiconductor structure 1 to be etched.

[0074] For example, during the fabrication of the semiconductor structure 100, a coordinate system is established based on the semiconductor structure 100. By marking the coordinates of different structures in the semiconductor structure 100, the relative positional relationships of the different structures in the semiconductor structure 100 are represented. Based on this, a coordinate system can be established based on the semiconductor structure 1 to be etched, and correspondingly, the coordinates of the alignment mark 11 are included in this coordinate system.

[0075] For example, the aforementioned area information refers to the coordinate information of the area occupied by the alignment mark 11 in the semiconductor structure 1 to be etched. Here, "occupied area" can be a continuous area of ​​the alignment mark 11 and its surrounding area, the size of which is based on the area that the laser process equipment can recognize.

[0076] S320a, such as Figure 4c As shown, based on the above area information, a laser process is used to process the portion of the hard mask layer 2 corresponding to the area where the alignment mark 11 is located.

[0077] After obtaining the area information of the alignment mark 11, the position of the laser in the hard mask layer 2 can be determined, that is, the part of the hard mask layer 2 that corresponds to the area where the alignment mark 11 is located.

[0078] In this process, the portion of the hard mask layer 2 corresponding to the area where the alignment mark 11 is located absorbs laser energy and crystallizes, resulting in a light transmittance of this portion that is greater than or equal to a preset light transmittance. The portion of the hard mask layer 2 not corresponding to the area where the alignment mark 11 is located does not crystallize, and its light transmittance remains unchanged.

[0079] In other examples, a laser process is used to process at least the portion of the hard mask layer 2 corresponding to the alignment mark 11, including: S310b.

[0080] S310b, such as Figure 4d As shown, the entire hard mask layer 2 is processed using a laser process.

[0081] For example, the entire hard mask layer 2 can absorb laser energy and crystallize, so that the light transmittance of each part of the hard mask layer 2 is greater than or equal to the preset light transmittance. Accordingly, the entire hard mask layer 2 after laser treatment can be referred to as the light-transmitting part T.

[0082] It should be noted that the method of using laser technology to process at least the portion of the hard mask layer 2 corresponding to the alignment mark 11 is generally related to the equipment used in the laser process.

[0083] For example, if the equipment used in the laser process can obtain information about the region where the alignment mark 11 is located in the semiconductor structure 1 to be etched, the laser process can be performed only on the portion of the hard mask layer 2 corresponding to the region where the alignment mark 11 is located, as shown in S310a to S320a. This helps to reduce the energy used in the laser process and lower the cost of fabricating the semiconductor structure.

[0084] For example, if the equipment used in the laser process cannot obtain information about the area where the alignment mark 11 is located in the semiconductor structure 1 to be etched, the entire hard mask layer 2 can be laser-processed as shown in S310b. This reduces the number of steps required to obtain information about the area of ​​the alignment mark 11, thus simplifying the semiconductor structure fabrication process.

[0085] In some embodiments, after the above-described S300, such as Figure 3 As shown, the method for fabricating the semiconductor structure may also include: S400 to S800.

[0086] S400, such as Figure 5a and Figure 6c As shown, a photoresist layer 3 is formed on the hard mask layer 2 after laser etching.

[0087] For example, the above-mentioned photoresist layer 3 can be formed using a coating process.

[0088] The photoresist material included in the above-mentioned photoresist layer 3 includes a variety of materials, which can be selected and set according to actual needs.

[0089] For example, the photoresist can be a positive photoresist or a negative photoresist.

[0090] This invention uses positive photoresist as an example for illustrative purposes.

[0091] S500, image information of alignment mark 11 is obtained through the laser-etched portion (i.e., the light-transmitting portion T) of the hard mask layer (i.e., the laser-etched hard mask layer 2).

[0092] For example, the light emitted by the light source of the photolithography equipment can pass through the light-transmitting part T and be incident on the alignment mark 11, and the image information of the alignment mark 11 can be acquired.

[0093] Since the light transmittance of the light-transmitting part T is greater than or equal to the preset light transmittance, the image information of the alignment mark 11 obtained by the photolithography equipment is more accurate.

[0094] The aforementioned image information may include, for example, the shape information and / or coordinate information of alignment mark 11.

[0095] S600, such as Figure 5b and Figure 6d As shown, based on the acquired image information, the mask is aligned with the semiconductor structure 1 to be etched, and the photoresist layer 3 is patterned.

[0096] For example, the mask has an alignment pattern that matches the alignment mark 11. Additionally, the mask also has a pattern (e.g., an opening).

[0097] For example, after the photolithography equipment acquires the image information of the alignment mark 11, it can acquire the image information of the alignment pattern of the mask. Based on the image information of the two, the setting position of the mask on the semiconductor structure 1 to be etched is adjusted to achieve the alignment between the mask and the semiconductor structure 1 to be etched.

[0098] For example, after aligning the photomask with the semiconductor structure 1 to be etched, the photoresist layer 3 can be exposed through the photomask. Then, the exposed photoresist layer can be developed to remove the exposed portions of the photoresist layer 3, retaining the unexposed portions, resulting in a patterned photoresist layer 3a. The pattern in the patterned photoresist layer 3a is identical to the pattern in the photomask.

[0099] S700, such as Figure 5c and Figure 6e As shown, the patterned photoresist layer 3a is used as a mask to pattern the laser-etched hard mask layer 2.

[0100] For example, the hard mask layer 2 after laser etching can be patterned using an etching process. This etching process includes, but is not limited to, dry etching, sputtering etching, chemical etching, or high-density plasma etching.

[0101] For example, the pattern in the patterned hard mask layer 2a is the same as the pattern in the patterned photoresist layer 3a.

[0102] S800, such as Figure 5e and Figure 6f As shown, the patterned hard mask layer 2a is used as a mask to pattern the semiconductor structure 1 to be etched.

[0103] For example, such as Figure 5d As shown, the patterned photoresist layer 3a can be removed before the semiconductor structure 1 to be etched is patterned.

[0104] For example, an etching process can be used to pattern the semiconductor structure 1 to be etched. This etching process includes, but is not limited to, dry etching or wet etching.

[0105] For example, the pattern in the patterned semiconductor structure 1 to be etched is the same as the pattern in the patterned hard mask layer 2a, that is, the same as the pattern in the mask. Based on the characteristics of the hard mask layer 2, the pattern in the semiconductor structure 1 to be etched can have a clearer outline and finer dimensions.

[0106] It should be noted that the structure of the semiconductor structure 1 to be etched includes various types, and can be selected and set according to actual needs.

[0107] In some examples, the semiconductor structure 1 to be etched may include an initial stacked layer of a memory array device in a three-dimensional memory. This initial stacked layer may include multiple alternating insulating layers and multiple gate sacrificial layers. The structure to be etched in the semiconductor structure 1 may be this initial stacked layer. After etching the semiconductor structure 1, a channel via can be formed.

[0108] In some examples, the semiconductor structure 1 to be etched may include a gate stack structure. This gate stack structure may include multiple alternating insulating layers and multiple conductive layers, and may have multiple channel vias. In the semiconductor structure 1 to be etched, the structure to be etched is a dielectric layer covering the gate stack structure. After etching the semiconductor structure 1, contact vias can be formed.

[0109] In some examples, the semiconductor structure 1 to be etched may include a gate stack structure and a memory string located in its channel via. Specifically, the structure to be etched in the semiconductor structure 1 is a dielectric layer covering the gate stack structure and the memory string. After etching the semiconductor structure 1, interconnect vias can be formed.

[0110] Of course, the structure of the semiconductor structure 1 to be etched is not limited to the structure exemplified above; it can be etched using a hard mask layer and photolithography.

[0111] This disclosure uses one structure of the semiconductor structure 1 to be etched as an example to illustrate the method for preparing the semiconductor structure.

[0112] In some embodiments, such as Figure 6a As shown, the semiconductor structure 1 to be etched may include: a substrate 12, a gate stack structure 13a, a channel structure 14, a connection layer 15, and a dielectric layer 16.

[0113] The substrate 12 can be referred to in the descriptions of some of the above embodiments, and will not be repeated here.

[0114] In some examples, the gate stack structure 13a may be composed of the aforementioned multiple film layers 13.

[0115] For example, such as Figure 6a , Figure 7 and Figure 8 As shown, the gate stack structure 13a has a stepped morphology. This gate stack structure 13a may include multiple alternating layers of gate conductive layers G and insulating layers. The gate conductive layers G and insulating layers extend along a first direction X. Along a third direction Z, the lowermost gate conductive layer G in the multiple gate conductive layers G is configured as a source select gate SGS, the uppermost gate conductive layer G in the multiple gate conductive layers G is configured as a drain select gate SGD, and the gate conductive layers G in the middle layers of the multiple gate conductive layers G are configured as multiple word lines WL (e.g., ...). Figure 8 (WL1 to WL4 shown).

[0116] For example, the gate stack structure 13a has multiple channel holes.

[0117] In some examples, the number of the aforementioned channel structures 14 is multiple, and they can be arranged in an array. For example, Figure 6a and Figure 7 As shown, the channel structure 14 is located within the channel aperture and extends along the third direction Z through the drain select gate SGD, each layer word line WL, and the source select gate SGS. The channel structure 14 can also connect the word lines WL of each layer in series to form a memory cell string 17.

[0118] For example, one memory cell string 17 is equivalent to the storage capacity of multiple planar memory cells. Therefore, a semiconductor structure (e.g., a three-bit memory) can provide a large storage capacity.

[0119] In some examples, such as Figure 6a As shown, the aforementioned connecting layer 15 is disposed on the gate stack structure 13a.

[0120] For example, such as Figure 6a , Figure 7 and Figure 8 As shown, the connection layer 15 is provided with a plurality of contacts 18 (e.g., bit line contacts BL CNT). Each contact 18 is electrically connected to the top of a memory cell string 17, thereby allowing each memory cell string 17 to be addressed independently by the contact 18.

[0121] For example, the material of the aforementioned interconnect layer 15 includes, but is not limited to, one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, and doped silicon oxide.

[0122] For example, such as Figure 6a As shown, the alignment mark 11 in the semiconductor structure 1 to be etched can be located in the interconnect layer 15.

[0123] For example, during the patterning of the connection layer 15, alignment marks 11 can be formed simultaneously in the connection layer 15.

[0124] In some examples, such as Figure 6a As shown, the dielectric layer 16 is disposed on the connection layer 15. The dielectric layer 16 may, for example, cover the connection layer 15.

[0125] For example, the material of the dielectric layer 16 may include an insulating material having a high dielectric constant.

[0126] Based on this, in some examples, such as Figure 6f As shown, in the above S800, the patterned hard mask layer 2a is used as a mask to perform patterning processing on the semiconductor structure 1 to be etched, including: using the patterned hard mask layer 2a as a mask to perform patterning processing on the dielectric layer 16 to form a plurality of trenches 161.

[0127] For example, an etching process can be used to pattern the semiconductor structure 1 to be etched. This etching process includes, but is not limited to, dry etching or wet etching.

[0128] For example, the groove 161 described above can expose the surface of the contact 18.

[0129] For example, the shape of the groove 161 is the same as the pattern in the patterned hard mask layer 2a, that is, the same as the pattern in the mask. This achieves the transfer of the pattern in the mask.

[0130] In some examples, such as Figure 6g As shown, the method for fabricating the semiconductor structure further includes forming bit lines 19 within the trench 161. The bit lines 19 are electrically connected to the channel structure 14 via contacts 18.

[0131] For example, bit line 19 can be electrically connected to the top of channel structure 14 via contact 18, thereby realizing the electrical connection between bit line 19 and memory cell string 17.

[0132] For example, a deposition process can be used to fill the trench 161 with material to form the bit line 19. This deposition process includes, but is not limited to, CVD, PVD, or ALD processes.

[0133] Since the groove 161 can expose the surface of the contact 18, the bit line 19 can naturally form an electrical connection with the contact 18 after it is formed in the groove 161.

[0134] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The preparation method includes: A semiconductor structure to be etched is provided; the semiconductor structure to be etched has alignment marks; the semiconductor structure to be etched is used to form a three-dimensional memory; A hard mask layer is formed on the semiconductor structure to be etched; The portion of the hard mask layer corresponding to the alignment mark is processed using a laser process, such that the light transmittance of the portion of the hard mask layer corresponding to the alignment mark after laser processing is greater than or equal to a preset light transmittance; wherein, the preset light transmittance is the minimum light transmittance of the portion of the hard mask layer after laser processing when the alignment mark can be identified from the side of the hard mask layer away from the semiconductor structure to be etched. A photoresist layer is formed on the hard mask layer after laser etching; Image information of the alignment mark is obtained through the portion of the hard mask layer after laser etching; Based on the acquired image information, the photomask is aligned with the semiconductor structure to be etched, and the photoresist layer is patterned.

2. The preparation method according to claim 1, characterized in that, The process of using laser technology to process at least the portion of the hard mask layer corresponding to the alignment mark includes: Obtain information about the region where the alignment mark is located in the semiconductor structure to be etched; Based on the region information, a laser process is used to process the portion of the hard mask layer corresponding to the region where the alignment mark is located.

3. The preparation method according to claim 1, characterized in that, The process of using laser technology to process at least the portion of the hard mask layer corresponding to the alignment mark includes: The entire hard mask layer is processed using a laser process.

4. The preparation method according to claim 1, characterized in that, The material of the hard mask layer mentioned before laser engraving includes amorphous silicon.

5. The preparation method according to claim 1, characterized in that, The material of the hard mask layer after laser etching includes silicon in a crystalline state.

6. The preparation method according to claim 1, characterized in that, The laser energy in the laser process is positively correlated with the thickness of the hard mask layer.

7. The preparation method according to claim 6, characterized in that, The laser energy in the laser process is less than or equal to 2J / cm². 2 .

8. The preparation method according to claim 1, characterized in that, The preset transmittance is greater than the transmittance of at least the portion of the hard mask layer corresponding to the alignment mark before laser etching.

9. The preparation method according to claim 1, characterized in that, The preparation method further includes: Using the patterned photoresist layer as a mask, the laser-etched hard mask layer is patterned. The patterned hard mask layer is used as a mask to pattern the semiconductor structure to be etched.

10. The preparation method according to claim 9, characterized in that, The semiconductor structure to be etched includes: Substrate; A gate stack structure disposed on the substrate; the gate stack structure having a plurality of channel holes; The channel structure located within the channel hole; A connection layer is disposed on the gate stack structure; the connection layer shown has multiple contacts and the alignment mark; and... A dielectric layer disposed on the connection layer.

11. The preparation method according to claim 10, characterized in that, The process of patterning the semiconductor structure to be etched using a patterned hard mask layer as a mask includes: Using the patterned hard mask layer as a mask, the dielectric layer is patterned to form multiple trenches; The preparation method further includes: A bit line is formed within the trench; the bit line is electrically connected to the trench structure via the contact.

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