Method of manufacturing a semiconductor device

Abstract

The present disclosure relates to a method of manufacturing a semiconductor device. A gate pattern is formed on a semiconductor layer and a conductive film is formed on the semiconductor layer to cover the gate pattern. A pad layer is formed between the gate patterns via a sidewall spacer by performing a polishing process on the conductive film and patterning the polished conductive film.

Description

[0001] Cross-references to related applications

[0002] The disclosure of Japanese Patent Application No. 2020-148113, filed on September 3, 2020 (including the specification, drawings and abstract), is incorporated herein by reference in its entirety. Background Technology

[0003] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a conductive film formed on an impurity region, the impurity region being intended to serve as a source region or a drain region.

[0004] As a low-power semiconductor device, the technique of forming MISFETs (Metal-Insulator-Semiconductor Field-Effect Transistors) on SOI (Silicon-on-Insulator) substrates is known. The SOI substrate has a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a silicon layer formed on the insulating layer. Forming a MISFET on an SOI substrate can reduce the parasitic capacitance caused by the diffusion region formed in the silicon layer. Therefore, it is possible to improve the operating speed of the MISFET and reduce its power consumption.

[0005] For example, Patent Document 1 discloses a technique for forming an epitaxial layer on a silicon layer on which the source and drain regions of a MISFET are formed.

[0006] The disclosed technologies are listed below.

[0007] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2013-219181 Summary of the Invention

[0008] Because the silicon layer on an SOI substrate is very thin, it is difficult to silicide the silicon layer in which the source and drain regions are formed. Therefore, it is effective to form an epitaxial layer on each of the source and drain regions and perform silicide in that epitaxial layer.

[0009] On the other hand, in a MISFET formed on an SOI substrate, the drive current of the MISFET is controlled by applying a voltage not only to the gate electrode formed on the silicon layer but also to the well region formed in the semiconductor substrate.

[0010] Here, there exists a situation where one or both of the contact holes formed on the source region and the contact holes formed on the drain region can be formed on a device isolation portion on which no epitaxial layer is formed. That is, in some cases, a contact hole is not formed at the desired location, resulting in a defect where the contact hole penetrates the device isolation portion. Furthermore, since the silicon layer is very thin as described above, even if a contact hole is formed at the desired location, if the epitaxial layer growth is insufficient, a defect may still occur where the contact hole penetrates the silicon layer and further penetrates the insulating layer formed beneath the silicon layer. Therefore, if the contact hole penetrates the device isolation portion or the silicon layer, a defect occurs where the source or drain region and the well region are short-circuited through the plug formed in the contact hole.

[0011] Therefore, it is desirable to develop a technology capable of suppressing this defect and improving the reliability of semiconductor devices with MISFETs. Other issues and novel features will become apparent from the description in this specification and the accompanying drawings.

[0012] According to one embodiment, a method of manufacturing a semiconductor device includes the following steps: (a) providing an SOI substrate having a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer; (b) after (a), forming a first conductive film on the semiconductor layer; (c) after (b), forming a first insulating film on the first conductive film; (d) after (c), patterning the first conductive film and the first insulating film to form a gate pattern and a capping film; (e) after (d), implanting impurities into the semiconductor layer located on both sides of the gate pattern to form a... (f) After (e), a first impurity region is formed; (g) After (f), a first sidewall spacer composed of a second insulating film is formed on the side surface of the gate pattern; (h) After (g), a second conductive film is formed on the first impurity region to cover the gate pattern, the capping film and the first sidewall spacer; (i) After (h), a polishing process is performed on the second conductive film until the capping film is exposed; (j) After (i), a portion of the second conductive film is patterned to form a pad layer composed of the remaining second conductive film; and (j) After (i), the portion in which the second conductive film has been removed is filled with a third insulating film.

[0013] Furthermore, according to another embodiment, a method of manufacturing a semiconductor device includes the following steps: (a) forming a first conductive film on a semiconductor substrate; (b) after (a), forming a first insulating film on the first conductive film; (c) after (b), patterning the first conductive film and the first insulating film to form a gate pattern and a capping film; (d) after (c), implanting impurities into the semiconductor substrate located on both sides of the gate pattern to form a first impurity region; (e) after (d), forming a first sidewall spacer composed of a second insulating film on the side surface of the gate pattern; (f) after (e), forming a second conductive film on the first impurity region to cover the gate pattern, the capping film, and the first sidewall spacer; (g) after (f), performing a polishing process on the second conductive film until the capping film is exposed; (h) after (g), patterning a portion of the second conductive film to form a pad layer; and (i) after (h), filling the portion of the second conductive film that has been removed with a third insulating film.

[0014] According to one embodiment, the reliability of semiconductor devices can be improved. Attached Figure Description

[0015] Figure 1 This is a circuit diagram showing a memory cell of a semiconductor device according to a first embodiment;

[0016] Figure 2 This is a plan view showing a memory cell of a semiconductor device according to the first embodiment;

[0017] Figure 3 This is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment;

[0018] Figure 4 It is shown Figure 3 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0019] Figure 5 It is shown Figure 4 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0020] Figure 6 It is shown Figure 5 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0021] Figure 7 It is shown Figure 6 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0022] Figure 8 It is shown Figure 7 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0023] Figure 9It shows that it is in Figure 8 A plan view of the memory cell of a semiconductor device in its current state;

[0024] Figure 10 It is shown Figure 8 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0025] Figure 11 It is shown Figure 10 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0026] Figure 12 It is shown Figure 11 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0027] Figure 13 It is shown Figure 12 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0028] Figure 14 It shows that it is in Figure 13 A plan view of the memory cell of a semiconductor device in its current state;

[0029] Figure 15 It is shown Figure 13 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0030] Figure 16 It shows that it is in Figure 13 A cross-sectional view of another part of a semiconductor device in its current state;

[0031] Figure 17 This is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment;

[0032] Figure 18 It is shown Figure 17 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0033] Figure 19 It is shown Figure 18 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0034] Figure 20 It is shown Figure 19 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0035] Figure 21 It is shown Figure 20 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0036] Figure 22 It is shown Figure 21 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0037] Figure 23 It is shown Figure 22 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0038] Figure 24 It is shown Figure 23 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0039] Figure 25 It is shown Figure 24 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0040] Figure 26 This is a cross-sectional view showing a semiconductor device according to a third embodiment;

[0041] Figure 27 This is a cross-sectional view showing the semiconductor device according to the first modification;

[0042] Figure 28 This shows a cross-sectional view of the semiconductor device according to the second modification; and

[0043] Figure 29 This is a cross-sectional view showing the semiconductor device according to the second modification. Detailed Implementation

[0044] In the following description, embodiments will be illustrated with reference to the accompanying drawings. Note that in all the drawings used to describe the embodiments, components with the same function are indicated by the same reference numerals, and repeated descriptions are omitted. Furthermore, in the following embodiments, unless specifically required, descriptions of the same or similar components will generally not be repeated.

[0045] Furthermore, in order to make the drawings easier to read, the shading lines are sometimes omitted, even in the cross-sectional views, and sometimes even in the plan views.

[0046] Furthermore, the X, Y, and Z directions used in the description of this application intersect and are orthogonal to each other. In this application, the Z direction is sometimes described as the vertical direction, height direction, or thickness direction of a structure. Additionally, the expression "in a plan view" as used in this application refers to viewing the surface formed by the X and Y directions in the Z direction.

[0047] (First Embodiment)

[0048] <Configuration of Memory Unit MC>

[0049] The semiconductor device according to the first embodiment and the method of manufacturing the semiconductor device will now be described. First, reference will be made to... Figure 1 and 2The memory cell MC describes the SRAM circuit included in a semiconductor device.

[0050] like Figure 1 As shown, the memory cell MC is arranged at the intersection of a pair of bit lines BL and / BL with the word line WL. The memory cell MC includes a pair of load transistors Lo1 and Lo2, a pair of access transistors Acc1 and Acc2, and a pair of drive transistors Dr1 and Dr2. Load transistors Lo1 and Lo2 are p-channel transistors, while access transistors Acc1 and Acc2 and drive transistors Dr1 and Dr2 are n-channel transistors.

[0051] Of the six transistors constituting the memory cell MC, load transistor Lo1 and drive transistor Dr1 form a CMOS inverter, and load transistor Lo2 and drive transistor Dr2 form another CMOS inverter. Nodes N1 and N2 are cross-linked to form a flip-flop circuit that serves as an information storage cell storing 1 bit of information. Nodes N1 and N2 are the mutual input / output terminals of this pair of CMOS inverters.

[0052] The connection of the above six transistors will be described below.

[0053] Load transistor Lo1 is connected between the power supply voltage Vdd and node N1, and drive transistor Dr1 is connected between node N1 and reference voltage Vss. The gates of both load transistor Lo1 and drive transistor Dr1 are connected to node N2. Load transistor Lo2 is connected between the power supply voltage Vdd and node N2, and drive transistor Dr2 is connected between node N2 and reference voltage Vss. The gates of both load transistor Lo2 and drive transistor Dr2 are connected to node N1.

[0054] Access transistor Acc1 is connected between bit line BL and node N1, and access transistor Acc2 is connected between bit line / BL and node N2. The gates of access transistors Acc1 and Acc2 are connected to word line WL.

[0055] As described later, the six transistors are formed on an SOI substrate having a semiconductor substrate SUB, an insulating layer BOX, and a semiconductor layer SL. Figure 2 As shown, the SOI substrate is divided into multiple active regions by the element isolation portion STI, which penetrates the semiconductor layer SL and the insulating layer BOX. Among the multiple active regions, active regions AcP1, AcP2, AcN1, and AcN2 are disposed in the memory cell MC.

[0056] Active regions AcP1, AcP2, AcN1, and AcN2 each extend along the Y direction and are separated from each other along the X direction. Furthermore, in the plan view, active region AcN1 is adjacent to active regions AcN2 and AcP1 via the element isolation portion STI, and active region AcN2 is adjacent to active regions AcN1 and AcP2 via the element isolation portion STI.

[0057] Load transistor Lo1 is formed in active region AcN1, load transistor Lo2 is formed in active region AcN2, access transistor Acc1 and drive transistor Dr1 are formed in active region AcP1, and access transistor Acc2 and drive transistor Dr2 are formed in active region AcP2.

[0058] The p-type well region PW is formed in the semiconductor substrate SUB in the active regions AcP1 and AcP2, and the n-type well region NW is formed in the semiconductor substrate SUB in the active regions AcN1 and AcN2.

[0059] A back-gate voltage Vbg1 is applied to the n-type well region NW in the active regions AcN1 and AcN2, and a back-gate voltage Vbg2, which is different from the back-gate voltage Vbg1, is applied to the p-type well region PW in the active regions AcP1 and AcP2.

[0060] The threshold voltage of load transistor Lo1 is controlled by the voltage applied to the gate electrode GE2 and the back gate voltage Vbg1, and the threshold voltage of load transistor Lo2 is controlled by the voltage applied to the gate electrode GE1 and the back gate voltage Vbg1. The threshold voltage of access transistor Acc1 is controlled by the voltage applied to the gate electrode GE3 and the back gate voltage Vbg2, and the threshold voltage of access transistor Acc2 is controlled by the voltage applied to the gate electrode GE4 and the back gate voltage Vbg2. The threshold voltage of drive transistor Dr1 is controlled by the voltage applied to the gate electrode GE2 and the back gate voltage Vbg2, and the threshold voltage of drive transistor Dr2 is controlled by the voltage applied to the gate electrode GE1 and the back gate voltage Vbg2.

[0061] Semiconductor Devices

[0062] The following will refer to Figure 15 A semiconductor device according to a first embodiment will be described. First, regions 1A to 4A in the semiconductor device will be described.

[0063] Region 1A is the active region AcN1 in which a p-channel transistor is formed, and is adjacent to the region along the channel. Figure 14 The cross-sectional view corresponding to line AA (straight line) is shown. Region 2A is the active region AcP1 where an n-channel transistor is formed, and it corresponds to the area along... Figure 14 The cross-sectional view of the BB line (straight line) shown corresponds to this.

[0064] Region 3A is an active region in which a high-voltage transistor is formed, driven by a voltage higher than that of the transistors in regions 1A and 2A. Here, the case where a p-channel high-voltage transistor is formed is used as an example. Region 4A is an active region in which a non-volatile memory cell is formed. Here, a non-volatile memory cell is used as an example, comprising a memory transistor having a silicon nitride film as a charge accumulation layer, and a selection transistor adjacent to the memory transistor.

[0065] Note that regions 3A and 4A are body regions in which the semiconductor layer SL and the insulating layer BOX are removed, and high-voltage transistors and non-volatile memory cells are formed on the semiconductor substrate SUB.

[0066] The detailed configuration of each of regions 1A to 4A will be described together with the method of manufacturing a semiconductor device according to the first embodiment.

[0067] Methods for Manufacturing Semiconductor Devices

[0068] Next, we will refer to Figures 3 to 16 A method for manufacturing a semiconductor device according to a first embodiment is described.

[0069] First, such as Figure 3 As shown, an SOI substrate is provided, which has a semiconductor substrate SUB as a supporting substrate member, an insulating layer BOX formed on the semiconductor substrate SUB, and a semiconductor layer SL formed on the insulating layer BOX.

[0070] The semiconductor substrate SUB is preferably made of single-crystal silicon with a resistivity of about 1 Ωcm to 10 Ωcm, such as p-type single-crystal silicon. The insulating layer BOX is made of, for example, silicon oxide, and the thickness of the insulating layer BOX is, for example, about 10 nm to 20 nm. The semiconductor layer SL is preferably made of single-crystal silicon with a resistivity of about 1 Ωcm to 10 Ωcm, and the thickness of the semiconductor layer SL is, for example, about 10 nm to 20 nm. Note that impurities are not introduced into the semiconductor layer SL by means of ion implantation or the like.

[0071] An example of the process for fabricating such an SOI substrate will be described below. The SOI substrate is formed, for example, by a bonding method. In the bonding method, for example, the surface of a first semiconductor substrate made of silicon is oxidized to form an insulating layer BOX, and then a second semiconductor substrate made of silicon is pressed and bonded to the first semiconductor substrate under high temperature conditions. Subsequently, the second semiconductor substrate is thinned. As a result, the thin film of the second semiconductor substrate remaining on the insulating layer BOX becomes the semiconductor layer SL, and the first semiconductor substrate below the insulating layer BOX becomes the semiconductor substrate SUB.

[0072] Next, trenches are formed that penetrate the semiconductor layer SL and the insulating layer BOX and reach the semiconductor substrate SUB. Then, device isolation portions STIs are formed by filling the trenches with an insulating film such as a silicon oxide film. The device isolation portions STIs are formed in each of regions 1A to 4A, and multiple active regions are defined by the device isolation portions STIs. Note that region 1A corresponds to along... Figure 2 The cross-sectional view of line AA is shown. Furthermore, region 2A corresponds to along... Figure 2 The cross-sectional view of line BB is shown. That is, Figure 2 The AA line and BB line shown correspond to respectively Figure 14 Lines AA and BB are shown.

[0073] Next, a portion of the semiconductor layer SL and the insulating layer BOX in regions 3A and 4A are selectively removed using photolithography and etching processes. Thus, regions 3A and 4A become bulk regions.

[0074] Then, using photolithography and ion implantation, n-type well regions NW are formed in the semiconductor substrate SUB in regions 1A and 3A, and p-type well regions PW are formed in the semiconductor substrate SUB in regions 2A and 4A.

[0075] Note that in order to apply back gate voltages Vbg1 and Vbg2 to the well region NW of region 1A and the well region PW of region 2A, a portion of the semiconductor layer SL and the insulating layer BOX of regions 1A and 2A are removed, and these regions are used as power supply regions, but the power supply regions will not be described in detail here.

[0076] Next, as Figure 4 As shown, a gate insulating film is formed in each of regions 1A to 4A. First, a gate insulating film GI2 made of, for example, silicon oxide is formed in each of regions 1A to 4A by, for example, thermal oxidation. Next, the gate insulating film GI2 formed in regions 1A and 2A and a portion of region 4A is removed by photolithography and etching processes.

[0077] Next, a gate insulating film GI3 is formed in each of regions 1A to 4A. The gate insulating film GI3 is, for example, composed of a stacked film in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially stacked. Furthermore, the aforementioned silicon nitride film serves as a charge accumulation layer for the non-volatile memory cell. Next, the gate insulating film GI3 formed on the gate insulating film GI2 in regions 1A to 3A and in region 4A is removed by photolithography and etching processes.

[0078] Next, a gate insulating film GI1, for example made of silicon oxide, is formed in regions 1A and 2A by, for example, thermal oxidation. The thickness of the gate insulating film GI1 is less than the thickness of the gate insulating films GI2 and GI3.

[0079] Next, a conductive film CF1, for example made of amorphous silicon, is formed on the gate insulating film GI1 in regions 1A and 2A, on the gate insulating film GI2 in regions 3A and 4A, on the gate insulating film GI3 in region 4A, and on the device isolation portion STI, for example by CVD (chemical vapor deposition). Next, an insulating film IF1, for example made of silicon oxide, is formed on the conductive film CF1 by CVD.

[0080] Next, as Figure 5 As shown, the insulating film IF1 and the conductive film CF1 are patterned using photolithography and etching processes. By patterning the conductive film CF1, a gate pattern GP is formed in each of regions 1A to 4A. Furthermore, by patterning the insulating film IF1, a capping film CP is formed on the gate pattern GP.

[0081] Next, using photolithography and ion implantation, impurities are implanted into the semiconductor layer SL or semiconductor substrate SUB located on both sides of the gate pattern GP in each of regions 1A to 4A (one side and the other side of the surface on both sides of the gate pattern GP). Therefore, a p-type extended region (impurity region) EXP is formed in the semiconductor layer SL in region 1A, an n-type extended region (impurity region) EXN is formed in the semiconductor layer SL in region 2A, a p-type extended region (impurity region) EXP is formed in the semiconductor substrate SUB in region 3A, and an n-type extended region (impurity region) EXN is formed in the semiconductor substrate SUB in region 4A.

[0082] Next, in each of regions 1A to 4A, an insulating film made of, for example, silicon nitride is formed by, for example, CVD to cover the gate pattern GP and the capping film CP. Next, by performing an anisotropic etching process on the insulating film, sidewall spacers SW made of the insulating film are formed on the side surface of the gate pattern GP, ​​such as... Figure 5 As shown.

[0083] Here, if the sidewall spacers SW are made of silicon oxide, just like the device isolation portion STI, there is a concern that the device isolation portion STI will also be etched by the anisotropic etching process, and the upper surface of the device isolation portion STI will significantly recede. However, the sidewall spacers SW are made of a different material than the device isolation portion STI, for example, silicon nitride, a material with high etch selectivity relative to the device isolation portion STI in the anisotropic etching process. Therefore, the recess on the upper surface of the device isolation portion STI can be suppressed to the greatest extent.

[0084] Next, as Figure 6As shown, in each of regions 1A to 4A, a conductive film CF2 is formed on the extended regions EXP and EXN by, for example, CVD to cover the gate pattern GP, ​​the capping film CP, and the sidewall spacers SW. The conductive film CF2 is made of silicon, preferably amorphous silicon.

[0085] Next, an insulating film IF2, such as an organic insulating film, is formed on the conductive film CF2, for example, by a coating method. Although there are unevennesses on the upper surface of the conductive film CF2 formed by CVD, the flatness can be improved by filling the unevennesses with the insulating film IF2. Such a planarization process makes it easier to perform subsequent polishing processes.

[0086] Next, as Figure 7 As shown, for example, a polishing process is performed on the conductive film CF2 using the CMP method. This polishing process is performed until the capping film CP is exposed. Through the polishing process, the conductive film CF2 is buried in a self-aligned manner between the gate pattern GP via the sidewall spacers SW. In addition, the insulating film IF2 is removed by this polishing process. Furthermore, in each of regions 1A to 4A, the extension regions EXP and EXN are directly connected to the conductive film CF2.

[0087] Next, as Figure 8 and Figure 9 As shown, a portion of the conductive film CF2 is patterned using photolithography and etching processes to form a pad layer PAD consisting of the remaining conductive film CF2 (i.e., a portion of the conductive film CF2 is retained without being patterned). At this time, an etching mask using photolithography is placed on the cap film CP. Therefore, in the etching process, not only is the conductive film CF2 exposed from the etching mask etched, but the sidewall spacers SW are also etched. However, there is no particular problem if the sidewall spacers SW are retained and not completely removed. Note that... Figure 9 The lines AA and BB shown correspond to Figure 2 The positions of lines AA and BB are shown.

[0088] Next, as Figure 10 As shown, an insulating film IF3, made of, for example, silicon oxide, is formed in each of regions 1A to 4A by, for example, CVD. Next, the insulating film IF3 is polished, for example, by CMP. This polishing process is performed until the pad layer PAD is exposed. Through this polishing process, the portion of the conductive film CF2 that has been removed is filled with the insulating film IF3. Note that the portion of the conductive film CF2 that has been removed is located on the component isolation portion STI. Therefore, the insulating film IF3 is located on the component isolation portion STI.

[0089] Next, as Figure 11As shown, for example, a polishing process is performed on the cap film CP, sidewall spacers SW, insulating film IF3, and pad layer PAD using the CMP method. This polishing process is performed until the cap film CP is removed and the gate pattern GP is exposed.

[0090] Next, as Figure 12 As shown, impurities are implanted into the gate pattern GP and pad layer PAD using photolithography and ion implantation. p-type impurities are implanted into the gate pattern GP and pad layer PAD in regions 1A and 3A, while n-type impurities are implanted into the gate pattern GP and pad layer PAD in regions 2A and 4A.

[0091] Here, in memory cell MC (see Figure 2 In the above, at gate electrode GE1, a portion of load transistor Lo2 becomes p-type and a portion of drive transistor Dr2 becomes n-type. Furthermore, at gate electrode GE2, a portion of load transistor Lo1 becomes p-type and a portion of drive transistor Dr1 becomes n-type. Additionally, gate electrodes GE3 and GE4 of access transistors Acc1 and Acc2 become n-type. Furthermore, gate electrode GE5 of region 3A becomes p-type and gate electrodes GE6 and GE7 of region 4A become n-type.

[0092] Furthermore, in each of regions 1A to 4A, the pad layer PAD, which has been injected with impurities, together with the extended region EXP and the extended region EXN, constitutes the source and drain regions of each transistor.

[0093] From the viewpoint of easily preventing the channeling effect during ion implantation, it is preferable that the conductive film CF2 is amorphous silicon when forming the pad layer PAD (conductive film CF2).

[0094] Next, in each of regions 1A to 4A, a silicide layer SI is formed on each upper surface of the gate pattern GP and the pad layer PAD using a self-aligned silicide technique. First, in each of regions 1A to 4A, and in regions where other semiconductor elements such as resistors are formed, a silicon oxide film is formed, for example, by CVD. Next, the silicon oxide film is patterned to cover only the regions where the silicide process was not performed.

[0095] Next, a metal film for forming the silicide layer SI is formed to cover regions 1A to 4A. Then, by performing a heat treatment on the semiconductor substrate SUB, the materials contained in the gate pattern GP and the pad layer PAD react with the metal film. Thus, the silicide layer SI is formed on each upper surface of the gate pattern GP and the pad layer PAD. Thereafter, the unreacted metal film is removed. Note that the metal film is made, for example, of cobalt, nickel, or a nickel-platinum alloy, while the silicide layer SI is made, for example, of cobalt silicide (CoSi2), nickel silicide (NiSi), or nickel-platinum silicide (NiPtSi).

[0096] Each transistor is formed in each of regions 1A to 4A using the above process.

[0097] Figure 13 The process for forming the interlayer insulating film IL0, the plug PG, and the shared contact plug SPG is shown.

[0098] First, in each of regions 1A to 4A, an interlayer insulating film IL0 made of, for example, silicon oxide is formed on the silicide layer SI and the insulating film IF3 by CVD to cover each transistor.

[0099] Next, multiple contact holes are formed in the interlayer insulating film IL0 using photolithography, dry etching, and other techniques. Multiple plugs PG are then formed in the interlayer insulating film IL0 by filling the contact holes with a stacked film, which includes a barrier metal film and a metal film formed on the barrier metal film. Note that the barrier metal film can be formed, for example, by CVD and is made of, for example, titanium nitride or tungsten nitride. The metal film can be formed, for example, by CVD and is made of, for example, tungsten. Furthermore, the multiple plugs PG include a shared contact plug SPG, which has a larger planar dimension than the other plugs PG.

[0100] For example, such as Figure 2 and 9 As shown, the gate pattern GP (gate electrode GE1) in the active region AcN2 extends on the device isolation portion STI to be adjacent to the pad layer PAD in the active region AcN1 via the sidewall spacer SW in the active region AcN2.

[0101] like Figure 14 As shown, the shared contact plug SPG is connected to both the gate pattern GP (gate electrode GE1) in the active region AcN2 and the pad layer PAD in the active region AcN1.

[0102] Next, an interlayer insulating film IL1 is formed on the interlayer insulating film IL0, in which multiple plugs PG are embedded. Then, after forming wiring trenches in the interlayer insulating film IL1, a conductive film, for example, mainly composed of copper, is embedded in the wiring trenches, thereby forming multiple wirings M1 connected to the multiple plugs PG in the interlayer insulating film IL. The structure of the wirings M1 is a so-called inlaid wiring structure.

[0103] Next, as Figure 15 As shown, an interlayer insulating film IL2 is formed on an interlayer insulating film IL1 in which multiple wirings M1 are embedded. Then, after forming holes and wiring trenches in the interlayer insulating film IL2, a conductive film, for example, primarily composed of copper, is embedded in the holes and trenches, thereby forming multiple wirings M2 connected to the multiple wirings M1 in the interlayer insulating film IL2. The structure of the wirings M2 is a so-called dual damascene wiring structure. Afterwards, wiring for the third and subsequent layers is formed, but illustrations and explanations are omitted here.

[0104] The semiconductor device according to the first embodiment was manufactured using the above process.

[0105] As described above, in semiconductor devices using SOI substrates, if the contact hole is misaligned, the contact hole penetrates the element isolation portion STI, and in some cases the following defects may occur: the source and drain regions formed in the semiconductor layer SL and the well region formed in the semiconductor substrate SUB are short-circuited via plugs formed in the contact hole.

[0106] In the first embodiment, the pad layer PAD is formed on the semiconductor layer SL, so this defect is unlikely to occur. That is, even if the position of the plug PG is misaligned with the pad layer PAD, the contact hole (plug PG) is unlikely to reach the component isolation portion STI because the insulating film IF3 is formed in the portion where the pad layer PAD is not present.

[0107] Furthermore, when an epitaxial layer is formed on the semiconductor layer SL, it is difficult to grow the epitaxial layer stably, and the shape of the epitaxial layer becomes unstable in many cases. In the first embodiment, the pad layer PAD can be formed by CVD, and its shape can be stabilized by patterning. In addition, since the conductive film CF2 is buried between the gate pattern GP in a self-aligned manner via the sidewall spacers SW, the pad layer PAD can be easily formed.

[0108] As described above, according to the first embodiment, the reliability of semiconductor devices can be improved by applying a pad layer (PAD).

[0109] Furthermore, in memory cells (MC), there are also plug PGs that connect to both the gate pattern GP and the pad layer PAD, similar to the shared contact plug SPG. However, since the height of the gate pattern GP is the same as the height of the pad layer PAD, there is almost no difference in height between the gate pattern GP and the impurity regions (source and drain regions). Therefore, the shared contact plug SPG can be easily formed, and the gate pattern GP and the pad layer PAD (source and drain regions) can be easily connected. This further improves the reliability of the semiconductor device.

[0110] In addition, such as Figure 14 As shown, among the multiple pad layers PAD formed in the memory cell MC, pad layer PAD1 corresponds to Figure 1 In the node N1, the pad layer PAD2 corresponds to Figure 1 In the node N2, the pad layer PAD3 corresponds to Figure 1 The reference voltage Vss is used in the active region AcP2. Specifically, the extended regions EXN and EXP in the active region AcN2 are connected via the same pad layer PAD1, and the extended regions EXN and EXP in the active region AcP1 are connected via the same pad layer PAD2. Furthermore, the pad layer PAD3 is shared by all four memory cells MC.

[0111] In conventional cases, wiring M1, etc., is used as a structure corresponding to these pad layers PAD1 to PAD3. In the first embodiment, pad layers PAD1 to PAD3 can be used as local wiring, thus omitting wiring in one layer for the wire connection of the memory cell MC. Since the omitted wiring can be used for wire connections of other circuits, the flexibility of wiring design is increased.

[0112] Figure 16 The structural features of the semiconductor device according to the first embodiment are shown, and are along... Figure 2 A cross-sectional view of line CC (straight line) in the diagram. For example... Figure 16 As shown, the lower surface of the gate electrode GE1 (gate pattern GP) is positioned higher than the lower surface of the pad layer PAD and the lower surface of the insulating film IF3. Furthermore, as... Figure 16 As shown, the lower surface of the pad layer PAD is positioned higher than the lower surface of the insulating film IF3. In other words, the distance L1 from the lower surface of the gate electrode GE1 to the lower surface of the pad layer PAD is less than the distance L2 from the lower surface of the gate electrode GE1 to the lower surface of the insulating film IF3.

[0113] Figure 5 The etching process used to form the sidewall spacers SW, and Figure 8The etching process used to pattern the conductive film CF2 is presented as the main factor contributing to this difference. The upper surface of the component isolation portion STI, corresponding to the lower surface of the insulating film IF3, is not only through... Figure 5 The etching process in the middle and also through Figure 8 The etching process in the middle is reversed.

[0114] Furthermore, compared to the sidewall spacer SW between the gate electrode GE1 and the pad layer PAD, the sidewall spacer SW between the gate electrode GE1 and the insulating film IF3 is... Figure 8 The etching process removes or thins the material.

[0115] (Second Embodiment)

[0116] The following will refer to Figures 17 to 25 A method for manufacturing a semiconductor device according to a second embodiment is described. In the following description, the differences from the first embodiment will be primarily described.

[0117] In the first embodiment described above, gate electrodes GE1 to GE5 are formed by implanting impurities into a gate pattern GP made of silicon. In the second embodiment, gate electrodes GE1 to GE5 are formed by replacing the gate pattern GP made of silicon with a metal film.

[0118] In the second embodiment, Figures 3 to 10 The manufacturing process is the same as that of the first embodiment. Figure 17 It shows Figure 10 Subsequent manufacturing processes.

[0119] First, such as Figure 17 As shown, dry etching is performed under conditions where the silicon oxide film is difficult to etch, and the upper surface of the pad layer PAD is selectively retracted, so that the upper surface of the pad layer PAD is lower than the upper surface of the gate pattern GP. At this time, the sidewall spacers SW are also etched together with the pad layer PAD.

[0120] Next, impurities are implanted into the gate pattern GP and pad layer PAD using photolithography and ion implantation. p-type impurities are implanted into the gate pattern GP and pad layer PAD in regions 1A and 3A, while n-type impurities are implanted into the gate pattern GP and pad layer PAD in regions 2A and 4A. Therefore, the gate pattern in region 4A becomes n-type gate electrodes GE6 and GE7.

[0121] Next, as Figure 18 As shown, for example, an insulating film IF4 made of silicon oxide is formed on the pad layer PAD by CVD to cover the gate pattern GP, ​​the capping film CP, and the sidewall spacers SW.

[0122] Next, an anisotropic etching process is performed on the insulating film IF4 and the cover film CP to remove the cover film CP, and the insulating film IF4 on the side surface of the gate pattern GP is left as a sidewall spacer.

[0123] Next, through the above references Figure 12 The same method is used to form a silicide layer SI on each of the upper surface of the gate pattern GP exposed from the insulating film IF4, which is in the shape of a sidewall spacer, and the upper surface of the pad layer PAD.

[0124] Next, as Figure 19 As shown, for example, an insulating film IF5 made of silicon oxide is formed on a silicide layer SI formed on the upper surface of the gate pattern GP and the upper surface of the pad layer PAD by CVD.

[0125] Next, as Figure 20 As shown, a polishing process is performed on the insulating film IF5. This polishing process covers the silicide layer SI formed on the upper surface of the pad layer PAD with the insulating film IF5, and removes the silicide layer SI formed on the upper surface of the gate pattern GP. Furthermore, the gate pattern GP is partially polished, and the height of the gate pattern GP is reduced.

[0126] Next, as Figure 21 As shown, a resist pattern RP is formed, which has a pattern covering regions 1A and 4A and opening regions 2A and 3A. Next, using the resist pattern RP as a mask, an etching process is performed under conditions where the silicon oxide film is difficult to etch, thereby removing the gate pattern GP in regions 2A and 3A. Subsequently, the resist pattern RP is removed by an ashing process or the like.

[0127] Next, as Figure 22 As shown, a metal film is deposited, for example by sputtering or CVD, to fill the portion of the gate pattern GP that has been removed. Then, the metal film, except for the buried metal film, is removed by a CMP process. In this way, in regions 2A and 3A, the gate pattern GP is replaced with gate electrodes GE3 to GE5 made of metal films.

[0128] Next, as Figure 23 As shown, the same process is performed on region 1A. A resist pattern is used as a mask to remove the gate pattern GP in region 1A. This resist pattern has a pattern that covers regions 2A to 4A and opens region 1A. Subsequently, a metal film is used to fill the portion where the gate pattern GP has been removed, thereby forming gate electrodes GE1 and GE2 made of metal films.

[0129] In this way, in regions 1A to 3A, the gate pattern GP is removed and the portion in which the gate pattern GP is removed is filled with a metal film, thereby forming gate electrodes GE1 to GE5 made of a metal film.

[0130] Note that, depending on the circumstances, the aforementioned metal film may consist of a single-layer metal film, such as a tantalum nitride film, a titanium aluminum film, a titanium nitride film, a tungsten film, or an aluminum film, or may consist of a stacked film in which these films are stacked. Furthermore, as the metal film for p-type transistors or n-type transistors, a suitable material may be appropriately selected taking into account the characteristics of each transistor.

[0131] Although not shown here, a high-dielectric-constant film can also be formed before depositing a metal film to be used as part of the gate insulating film of each transistor. The high-dielectric-constant film is an insulating film with a dielectric constant higher than that of a silicon oxide film, and is composed, for example, of hafnium oxide (HfO) or hafnium silicate (HfSiO).

[0132] Next, as Figure 24 As shown, through reference above Figure 12 The same method described herein is used to selectively form a silicide layer SI on each of the upper surfaces of the gate electrodes GE6 and GE7 in region 4A.

[0133] Next, as Figure 25 As shown, an interlayer insulating film IL0, plugs PG, and shared contact plugs SPG are formed. The arrangement of plugs PG and shared contact plugs SPG in the memory cell MC is similar to... Figure 14 The process is the same as shown in the first embodiment. Furthermore, the subsequent manufacturing process is the same as in the first embodiment. Figure 16 The same as shown.

[0134] As described above, the same effect as in the first embodiment can be achieved even if the gate electrodes GE1 to GE5 are formed by using a metal film instead of the gate pattern GP made of silicon.

[0135] (Third Embodiment)

[0136] The following will refer to Figure 26 A method for manufacturing a semiconductor device according to a third embodiment is described. In the following description, the differences from the second embodiment will be primarily described.

[0137] In the second embodiment described above, the memory cell MC of the SRAM circuit is formed on an SOI substrate. In the third embodiment, the memory cell MC is formed in a body region (a semiconductor substrate SUB in which the semiconductor layer SL and the insulating layer BOX have been removed). Figure 26 It is along Figure 2 The cross-sectional view of lines AA and BB is shown.

[0138] The method for manufacturing a semiconductor device according to the third embodiment is the same as that in the second embodiment, except that the bulk region is formed by removing the semiconductor layer SL and the insulating layer BOX from regions 1A and 2A, as shown in... Figure 3 In zones 3A and 4A.

[0139] exist Figure 26 In the second embodiment, the case of using metal films as gate electrodes GE1 to GE5 is shown as an example, but as in the first embodiment, gate electrodes GE1 to GE5 can be formed by implanting impurities into the gate pattern GP made of silicon.

[0140] (First revision)

[0141] The following will refer to Figure 27 A method for manufacturing a semiconductor device according to a first modification of the third embodiment is described. In the following description, the differences from the third embodiment will be primarily described.

[0142] In the third embodiment described above, the pad layer PAD is made of silicon implanted with impurities and forms part of the source or drain region. Furthermore, a silicide layer SI is formed on the upper surface of the pad layer PAD.

[0143] In the first modification, such as Figure 27 As shown, a metal pad layer MPAD is formed instead of the pad layer PAD. Furthermore, diffusion regions (impurity regions) PD and ND with impurity concentrations higher than those of the extended regions EXP and EXN are formed in the semiconductor substrate SUB, and the diffusion regions PD and ND, together with the extended regions EXP and EXN, constitute part of the source or drain region. Then, a silicide layer SI is formed on each upper surface of the diffusion regions PD and ND.

[0144] exist Figure 5 The process of forming sidewall spacers SW in the middle Figure 6 Between the processes of forming the conductive film CF2, the processes of forming the diffusion regions PD and ND are performed. That is, impurities are implanted into the semiconductor substrate SUB located on both sides of the gate pattern GP through photolithography and ion implantation via the sidewall spacers SW.

[0145] Therefore, a p-type diffusion region PD is formed in region 1A of the semiconductor substrate SUB, and an n-type diffusion region ND is formed in region 2A of the semiconductor substrate SUB. Although not shown, the p-type diffusion region PD is formed in region 3A of the semiconductor substrate SUB, and the n-type diffusion region ND is formed in region 4A of the semiconductor substrate SUB.

[0146] Subsequently, through references above Figure 12 The same method described is used to selectively form a silicide layer SI on each upper surface of the diffusion regions PD and ND.

[0147] Then, as Figure 6 As shown, a conductive film CF2 is formed, such as Figure 7 The polished conductive film CF2 shown is as follows: Figure 8 The patterned conductive film CF2 is shown, thereby forming the metal pad layer MPAD.

[0148] In the first modification, a laminated film including a barrier metal film and a metal film formed on the barrier metal film is used as a conductive film CF2 to serve as the basis for the metal pad layer MPAD. The barrier metal film can be formed, for example, by a CVD method and is made, for example, of titanium nitride or tungsten nitride. The metal film can be formed, for example, by a CVD method and is made, for example, of tungsten.

[0149] As described above, when forming the memory cell MC in the bulk region, the problem of difficulty in silicide formation due to the thin semiconductor layer SL of the SOI substrate does not occur. Therefore, the metal pad layer MPAD can be formed after the silicide layer SI is formed. Furthermore, the metal pad layer MPAD can function in the same manner as the pad layer PAD in the third embodiment.

[0150] (Second revision)

[0151] The following will refer to Figure 28 and Figure 29 A second modified method for manufacturing a semiconductor device according to the third embodiment is described below. In the following description, the differences from the third embodiment will be primarily described. Figure 28 and Figure 29 They are along Figure 2 The cross-sectional view of line DD (straight line) and line EE (straight line) is shown.

[0152] In the third embodiment described above, each transistor is a planar transistor, but in the second modification, each transistor is a finned transistor.

[0153] like Figure 28 and 29 As shown, fins (protrusions) FA protruding from the upper surface of a semiconductor substrate SUB are formed in the substrate. Each active region, including active regions AcP1 and Acn1, is formed as a fin FA. These fins FA can be formed by performing an etching process on a portion of the semiconductor substrate SUB.

[0154] like Figure 28 and Figure 29 As shown in the plan view, in a direction orthogonal to the extending directions of the active regions AcP1 and AcN1 (X direction), each gate pattern GP (each gate electrode) and each pad layer PAD are formed on the upper surface of the semiconductor substrate SUB to cover the upper and side surfaces of the fin FA. Note that, as Figure 8As shown, when patterning the conductive film CF2, the sidewall spacer SW between the gate electrode GE1 and the insulating film IF3 can be removed or left.

[0155] Note the cross-sectional view along the extension direction (Y direction) of the active regions AcP1 and AcN1. Figure 26 The cross-sectional views shown are almost identical, although there are some differences, such as the depth of the component isolation section (STI).

[0156] As described above, since each gate pattern GP (each gate electrode) covers the upper and side surfaces of the fin FA, the effective channel width of each transistor is increased, thereby increasing the current of each transistor.

[0157] Furthermore, since each pad layer PAD covers the upper and side surfaces of the fin FA, the contact area between the extension regions EXP and EXN and the pad layer PAD is increased, thereby reducing the diffusion resistance.

[0158] The present invention has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made without departing from its spirit.

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps: (a) Providing an SOI substrate, the SOI substrate having a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer; (b) After (a), a first conductive film is formed on the semiconductor layer; (c) After (b), a first insulating film is formed on the first conductive film; (d) After (c), the first conductive film and the first insulating film are patterned to form a gate pattern and a capping film; (e) After (d), impurities are implanted into the semiconductor layers located on both sides of the gate pattern to form a first impurity region; (f) After (e), a first sidewall spacer made of a second insulating film is formed on the side surface of the gate pattern; (g) After (f), a second conductive film is formed on the first impurity region to cover the gate pattern, the capping film, and the first sidewall spacer; (h) After (g), a polishing process is performed on the second conductive film until the cover film is exposed; (i) After (h), a portion of the second conductive film is patterned to form a pad layer made of the remaining second conductive film; (j) After (i), the portion of the second conductive film that has been removed is filled with a third insulating film, and (k) After (j), a polishing process is performed on the cover film, the first sidewall spacer, the third insulating film and the pad layer until the cover film is removed and the gate pattern is exposed.

2. The method for manufacturing a semiconductor device according to claim 1, further comprising the following steps: (l) After (k), impurities are implanted into the gate pattern and the pad layer; as well as (m) After (l), a silicide layer is formed on each upper surface of the gate pattern and the pad layer.

3. The method for manufacturing a semiconductor device according to claim 1, further comprising the following steps: (n) Between (a) and (b), a trench is formed that penetrates the semiconductor layer and the insulating layer and reaches the semiconductor substrate, and the trench is filled with a fourth insulating film to form a device isolation portion. The semiconductor layer, the insulating layer, and the semiconductor substrate are divided into multiple active regions by the element isolation portion. The plurality of active regions includes a first active region and a second active region, wherein the second active region is adjacent to the first active region in the plan view via the element isolation portion, and The first impurity region formed in the semiconductor layer in the first active region and the first impurity region formed in the semiconductor layer in the second active region are connected by the same pad layer.

4. The method for manufacturing a semiconductor device according to claim 3, The third insulating film is located on the isolation portion of the element.

5. The method for manufacturing a semiconductor device according to claim 3, further comprising the following steps: (o) Following (k), a plurality of plugs are formed on the gate pattern and the pad layer. The plurality of active regions includes a third active region, which is adjacent to the first active region in the plan view via the element isolation portion. The gate pattern in the third active region extends over the device isolation portion to be adjacent to the pad layer in the first active region via the first sidewall spacer in the third active region. The plurality of plugs includes a shared contact plug connected to both the gate pattern in the third active region and the pad layer in the first active region.

6. The method for manufacturing a semiconductor device according to claim 1, The step (g) further includes the step of forming a fifth insulating film on the second conductive film by a coating method, and The fifth insulating film is removed by the polishing process described in (h).

7. The method for manufacturing a semiconductor device according to claim 1, The second conductive film is made of silicon.

8. The method for manufacturing a semiconductor device according to claim 1, The first insulating film and the third insulating film are made of silicon oxide, and The second insulating film is made of silicon nitride.

9. A method for manufacturing a semiconductor device, comprising the following steps: (a) Providing an SOI substrate, the SOI substrate having a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer; (b) After (a), a first conductive film is formed on the semiconductor layer; (c) After (b), a first insulating film is formed on the first conductive film; (d) After (c), the first conductive film and the first insulating film are patterned to form a gate pattern and a capping film; (e) After (d), impurities are implanted into the semiconductor layers located on both sides of the gate pattern to form a first impurity region; (f) After (e), a first sidewall spacer made of a second insulating film is formed on the side surface of the gate pattern; (g) After (f), a second conductive film is formed on the first impurity region to cover the gate pattern, the capping film, and the first sidewall spacer; (h) After (g), a polishing process is performed on the second conductive film until the cover film is exposed; (i) After (h), a portion of the second conductive film is patterned to form a pad layer made of the remaining second conductive film; (j) After (i), the portion of the second conductive film that has been removed is filled with a third insulating film, and (p) After (j), the upper surface of the pad layer is moved back such that the upper surface of the pad layer becomes lower than the upper surface of the gate pattern; (q) After (p), a sixth insulating film is formed on the pad layer to cover the gate pattern, the capping film and the first sidewall spacer; (r) After (q), anisotropic etching is performed on the sixth insulating film and the cover film to remove the cover film and form a second sidewall spacer made of the sixth insulating film on the side surface of the gate pattern; (s) After (r), a first silicide layer and a second silicide layer are formed on the upper surface of the gate pattern exposed from the second sidewall spacer and on the upper surface of the pad layer, respectively. (t) After (s), a seventh insulating film is formed on the first silicide layer and the second silicide layer; (u) After (t), a polishing process is performed on the seventh insulating film, such that the second silicide layer formed on the upper surface of the pad layer is covered by the seventh insulating film, and the first silicide layer formed on the upper surface of the gate pattern is removed. (v) After (u), the gate pattern is removed and the portion where the gate pattern has been removed is filled with a metal film; as well as (w) After (v), a polishing process is performed on the seventh insulating film until the second silicide layer is exposed.

10. The method for manufacturing a semiconductor device according to claim 9, further comprising the following steps: (n) Between (a) and (b), a trench is formed that penetrates the semiconductor layer and the insulating layer and reaches the semiconductor substrate, and the trench is filled with a fourth insulating film to form a device isolation portion. The third insulating film is located on the isolation portion of the element. The semiconductor layer, the insulating layer, and the semiconductor substrate are divided into multiple active regions by the element isolation portion. The plurality of active regions includes a first active region and a second active region, wherein the second active region is adjacent to the first active region in the plan view via the element isolation portion, and The first impurity region formed in the semiconductor layer in the first active region and the first impurity region formed in the semiconductor layer in the second active region are connected by the same pad layer.

11. The method for manufacturing a semiconductor device according to claim 10, further comprising the following steps: (x) Following (w), a plurality of plugs are formed on the metal film and the second silicide layer. The plurality of active regions includes a third active region, which is adjacent to the first active region in the plan view via the element isolation portion. The metal film of the third active region extends over the component isolation portion to be adjacent to the pad layer in the first active region via the first sidewall spacer in the third active region. The plurality of plugs includes a shared contact plug connected to both the metal film in the third active region and the second silicide layer in the first active region.

12. The method for manufacturing a semiconductor device according to claim 9, further comprising the following steps: (y) Between (a) and (b), a portion of the semiconductor layer and the insulating layer of the SOI substrate are removed to form a bulk region. The steps (b) to (j) and (p) to (w) are also performed on the semiconductor substrate in the body region. In (v), the gate pattern in the body region is left intact, and The following step is performed after (w): a third silicide layer is formed on the upper surface of the gate pattern in the body region.

13. A method for manufacturing a semiconductor device, comprising the following steps: (a) Forming a first conductive film on a semiconductor substrate; (b) After (a), a first insulating film is formed on the first conductive film; (c) After (b), the first conductive film and the first insulating film are patterned to form a gate pattern and a capping film; (d) After (c), impurities are implanted into the semiconductor substrate located on both sides of the gate pattern to form a first impurity region; (e) After (d), a first sidewall spacer made of a second insulating film is formed on the side surface of the gate pattern; (k) After (e), impurities are implanted into the semiconductor substrate located on both sides of the gate pattern via the first sidewall spacer, thereby forming a second impurity region with an impurity concentration higher than that of the first impurity region; (l) After (k), a silicide layer is formed on the second impurity region; (f) After (e), a second conductive film is formed on the first impurity region to cover the gate pattern, the capping film and the first sidewall spacer; (g) After (f), a polishing process is performed on the second conductive film until the cover film is exposed; (h) After (g), a portion of the second conductive film is patterned to form a pad layer; as well as (i) After (h), the portion where the second conductive film has been removed is filled with a third insulating film, and In (f), the second conductive film is formed on the silicide layer, and The second conductive film is made of a laminated film, which includes a barrier metal film and a metal film formed on the barrier metal film.

14. The method for manufacturing a semiconductor device according to claim 13, further comprising the following steps: (j) Following (i), a silicide layer is formed on the upper surface of the pad layer. Each of the first and second conductive films is made of silicon.

15. The method of manufacturing the semiconductor device according to claim 13, further comprising the following steps: (m) Prior to (a), an etching process is performed on a portion of the semiconductor substrate to form a protrusion extending from the upper surface of the semiconductor substrate. The gate pattern and the pad layer are formed on the upper surface of the semiconductor substrate to cover the upper and side surfaces of the protrusion.

16. The method of manufacturing the semiconductor device according to claim 13, further comprising the following steps: (n) Prior to (a), trenches are formed in the semiconductor substrate and the trenches are filled with a fourth insulating film to form a device isolation portion. The third insulating film is located on the element isolation portion. The third insulating film is located on the element isolation portion.

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