A highly efficient programming semi-floating gate transistor and its manufacturing method

Abstract

The invention discloses a highly efficient programming semi-floating gate transistor and a preparation method thereof. The highly efficient programming semi-floating gate transistor comprises: a substrate, which is formed with a P-well region, an N-well region and a U-shaped groove, wherein the N-well region is located above the P-well region and the U-shaped groove runs through the N-well region; a semi-floating gate dielectric layer, which is formed on the surface of the U-shaped groove and extends to cover part of the surface of the N-well region on one side, and a window is formed on the other side; a semi-floating gate, which covers the semi-floating gate dielectric layer and completely fills the U-shaped groove, and contacts the N-well region at the window; a control gate dielectric layer, a control gate and a mask layer, wherein the control gate dielectric layer covers the semi-floating gate, and the control gate and the mask layer are sequentially formed on the control gate dielectric layer; a separation gate dielectric layer and a separation gate, wherein the separation gate dielectric layer is formed on the surface of the N-well region and extends to cover part of the surface of the mask layer, and the separation gate covers the separation gate dielectric layer and fills the separation gate region; a source region and a drain region, which are respectively formed on both sides of the control gate and the separation gate, in the N-well region.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a highly efficient programmed semi-floating gate transistor and a preparation method thereof. Background Art

[0002] As the device size becomes smaller and smaller, the 1T1C structure DRAM devices used in integrated circuit chips are facing more and more problems, such as the refresh time of 64ms, and the capacitance value of the capacitor must be kept above a certain value to ensure a sufficiently long charge retention time. However, as the feature size of integrated circuits shrinks, the manufacture of large capacitors becomes more and more difficult and occupies a huge manufacturing cost. As a new type of memory device, the semi-floating gate transistor is different from the traditional 1T1C structure DRAM device. It integrates an embedded tunneling transistor in the CMOS process. Under the appropriate operating voltage, the charge programming and erasing of the semi-floating gate area are completed through the channel of the embedded tunneling transistor and the semi-floating gate window. The entire erasing process can realize all the functions of the traditional 1T1C structure DRAM without capacitors, greatly reducing the cost and faster reading and writing speed. It is one of the most competitive devices in the future DRAM field.

[0003] From the working principle of the semi-floating gate transistor, it can be seen that the window structure and size of the semi-floating gate have an important impact on the programming efficiency of the device. Since there is no selectivity between polysilicon and silicon etching, generally when etching the semi-floating gate window, the remaining silicon oxide at the window will be used as the etching end point of the polysilicon, but the residual silicon oxide seriously reduces the programming efficiency. Therefore, how to remove the residual silicon oxide is the key to improving programming efficiency. Summary of the invention

[0004] The invention discloses a method for preparing a highly efficient programmed semi-floating gate transistor, comprising the following steps: ion implantation in a substrate forms a P-well region and an N-well region, the N-well region is formed above the P-well region, etching forms a U-shaped groove, the U-shaped groove penetrates the N-well region; forming a first silicon oxide layer and a semi-floating gate, the first silicon oxide layer covers the surface of the U-shaped groove and part of the surface of the N-well region, and a window is formed on the surface of the N-well region outside the U-shaped groove; the semi-floating gate covers the first silicon oxide layer, and the window is in contact with the surface of the N-well region; a second silicon oxide layer, a second polysilicon layer and a mask layer are deposited, and edge etching is performed to etch out a control gate region and a separation gate region, and part of the first oxide layer remains at the window. silicon layer; oxidizing the polysilicon and silicon exposed to the air to form a third silicon oxide layer, and then etching away the first silicon oxide layer and the third silicon oxide layer remaining at the window, completely opening up the programming channel between the embedded tunneling transistor channel and the semi-floating gate storage layer; depositing a separation gate dielectric layer to cover the device surface, depositing a third polysilicon layer to cover the separation gate dielectric layer and completely fill the separation gate area, performing edge etching and middle etching to form a control gate, a separation gate and a source and drain area; forming a side wall, performing source and drain ion implantation, and simultaneously performing N-type ion doping on the third polysilicon layer and the second polysilicon layer to form a highly efficient programmed semi-floating gate transistor.

[0005] In the method for preparing a highly efficient programmed semi-floating gate transistor of the present invention, preferably, the steps of forming a first silicon oxide layer and a semi-floating gate include: depositing a first silicon oxide layer and a first polysilicon layer in the semi-floating gate region; then etching away a portion of the first silicon oxide layer outside the U-shaped groove to expose a portion of the surface of the N-well region to form a window; then backfilling a portion of the first polysilicon layer, performing ion implantation in the semi-floating gate region, and performing chemical mechanical polishing on the first polysilicon layer to form a semi-floating gate.

[0006] In the method for preparing a highly efficient programmed semi-floating gate transistor of the present invention, preferably, edge etching and middle etching are performed to form a control gate, a separation gate and a source and drain region, the steps comprising: performing edge etching to remove the third polysilicon layer and the separation gate dielectric layer at the edge to expose the source and drain regions on both sides, and simultaneously etching away the third polysilicon layer and the separation gate dielectric layer in the middle region to expose part of the surface of the mask layer; continuing to perform middle etching to remove part of the mask layer, the second polysilicon layer, the second silicon oxide layer, the first polysilicon layer, and the first gate oxide layer to expose part of the surface of the N-well region in the middle region.

[0007] In the method for preparing a highly efficient programmed semi-floating gate transistor of the present invention, preferably, the third silicon oxide layer is removed by wet etching using a buffered oxide etching solution.

[0008] The present invention also discloses a highly efficient programmed semi-floating gate transistor, comprising: a substrate, which is formed with a P-well region, an N-well region and a U-shaped groove, wherein the N-well region is located above the P-well region and the U-shaped groove runs through the N-well region; a semi-floating gate dielectric layer, which is formed on the surface of the U-shaped groove and extends to cover part of the surface of the N-well region on one side, and is provided with a window on the other side; a semi-floating gate, which covers the semi-floating gate dielectric layer and completely fills the U-shaped groove, and is in contact with the N-well region at the window; a control gate dielectric layer, a control gate and a mask layer, wherein the control gate dielectric layer covers the semi-floating gate, and the control gate and the mask layer are sequentially formed on the control gate dielectric layer; a separation gate dielectric layer and a separation gate, wherein the separation gate dielectric layer is formed on the surface of the N-well region and extends to cover part of the surface of the mask layer, and the separation gate covers the separation gate dielectric layer and fills the separation gate region; a source region and a drain region, which are respectively formed on both sides of the control gate and the separation gate, in the N-well region.

[0009] In the highly efficient programmed semi-floating gate transistor of the present invention, preferably, the separation gate dielectric layer is silicon nitride, and the separation gate is polysilicon.

[0010] In the highly efficient programmed semi-floating gate transistor of the present invention, preferably, the separation gate dielectric layer is a high-K dielectric, and the separation gate is a metal.

[0011] By overall oxidation and then etching with a buffered oxide etchant, the residual silicon oxide at the window is removed, so that the channel of the embedded tunneling transistor is completely connected to the semi-floating gate area, thereby effectively improving programming efficiency and reducing operating voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a flow chart of a method for preparing a semi-floating gate transistor with high efficiency programming.

[0013] Figure 2 to Figure 13 It is a schematic diagram of the staged structure of each step of the method for preparing a semi-floating gate transistor with efficient programming. DETAILED DESCRIPTION

[0014] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. The described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0015] In the description of the present invention, it should be noted that the terms "upper", "lower", "vertical", "horizontal", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0016] In addition, many specific details of the present invention are described below, such as the structure, materials, dimensions, processing technology and techniques of the device, so that the present invention can be more clearly understood. However, as can be understood by those skilled in the art, the present invention can be implemented without following these specific details. Unless otherwise specified below, the various parts of the device can be made of materials known to those skilled in the art, or can be made of materials with similar functions developed in the future.

[0017] Figure 1 This is a flow chart of a method for preparing a semi-floating gate transistor with high efficiency programming. Figure 1 As shown, the method for preparing a semi-floating gate transistor with high efficiency programming includes the following steps:

[0018] Step S1, after completing the basic shallow trench isolation (STI) process on the substrate, a pad oxide layer 101 is deposited, and ion implantation is performed to form a P-well region 100 and an N-well region 102. The N-well region 102 is formed above the P-well region 100. The resulting structure is as shown in FIG. Figure 2 Afterwards, a first silicon nitride layer is deposited to form a hard mask, and then a U-shaped groove is etched. The formed U-shaped groove penetrates the N-well region 102, and then the hard mask is removed. The resulting structure is as shown in FIG. Figure 3 shown.

[0019] Step S2, depositing a first silicon oxide layer 103 as a semi-floating gate dielectric layer, depositing a first polysilicon layer 104 in the semi-floating gate region thereon, and then etching the semi-floating gate window to remove a portion of the first polysilicon layer 104 and the first silicon oxide layer 103 outside the U-shaped groove, exposing a portion of the surface of the N-well region to form a window. The resulting structure is shown in FIG. Figure 4 Then, a portion of the first polysilicon is backfilled, ion implantation is performed in the semi-floating gate region, and chemical mechanical polishing (CMP) is performed on the first polysilicon layer 104 to a certain height to form a semi-floating gate. The resulting structure is shown in FIG. Figure 5 shown.

[0020] Step S3, such as Figure 6 and Figure 7As shown, after the semi-floating gate region is formed, a second silicon oxide layer 105 and a second polysilicon layer 106 are deposited to form a control gate dielectric layer and a control gate, and then a second silicon nitride layer is deposited as a mask layer, and edge etching is performed to remove the second polysilicon layer 106, the second silicon oxide layer 105, the first polysilicon layer 104 and the first silicon oxide layer 103 at the edge, and the control gate region and the separation gate region are etched out. Since there is no selectivity between the etching of polysilicon and silicon, part of the first silicon oxide layer 103 will remain at the window, and the residual silicon oxide here has a serious impact on the programming efficiency of the semi-floating gate transistor.

[0021] Step S4, such as Figure 8-Figure 9 As shown, the polysilicon and silicon exposed to the air are oxidized to form a third silicon oxide layer 108. Then, a buffered oxide etchant (BOE) is used to remove the silicon oxide including the first silicon oxide layer 103 remaining at the window, and the programming channel between the embedded tunneling transistor channel and the semi-floating gate storage layer is completely opened, thereby improving the programming efficiency of the semi-floating gate transistor and reducing the operating voltage.

[0022] Step S5, then depositing a separation gate dielectric layer, first depositing a fourth silicon oxide layer 109 of a certain thickness, and then depositing a third silicon nitride layer 110 to form a separation gate dielectric layer. After the separation gate dielectric layer is formed, the third polysilicon layer 111 is filled, and the resulting structure is as shown in FIG. Fig.10 As shown. Fig.11 and Fig.12 As shown, edge etching and middle etching are performed to form independent control gates, separation gates, and source and drain regions. Specifically, edge etching is first performed to remove the third polysilicon layer 111 and the separation gate dielectric layer at the edge, so that the source and drain regions on both sides are exposed. At the same time, the third polysilicon layer 111 and the separation gate dielectric layer in the middle area are etched and removed to expose part of the surface of the second silicon nitride layer 107. The middle etching is continued to remove part of the second silicon nitride layer 107, the second polysilicon layer 106, the second silicon oxide layer 105, the first polysilicon layer 104, and the first silicon oxide layer 103, so that part of the surface of the N-well region 102 in the middle area is exposed. After that, silicon oxide and silicon nitride are isotropically deposited and anisotropically etched to form a sidewall 112.

[0023] Step S6, perform source-drain ion implantation to form source regions 113, 114 outside the separation gate, i.e., in the edge region, and form a drain region 115 between the control gates, i.e., in the middle region. At the same time, N-type ion doping is performed on the second polysilicon layer and the third polysilicon layer, and finally a highly efficient programmable semi-floating gate transistor is formed. The resulting structure is as shown in FIG. Fig.13 shown.

[0024] The above description is made by taking the separation gate using polysilicon as an example, but the present invention is not limited thereto. The separation gate dielectric layer may also use a high-K dielectric and the separation gate may use metal.

[0025] like Fig.13 As shown, the highly efficient programmed semi-floating gate transistor comprises: a substrate, which is formed with a P-well region 100, an N-well region 102 and a U-shaped groove, wherein the N-well region 102 is located above the P-well region 100, and the U-shaped groove penetrates the N-well region 102; a first silicon oxide layer 103, which is formed on the surface of the U-shaped groove and extends to cover a portion of the surface of the N-well region 102 on one side, and a window is formed on the other side; a semi-floating gate 104, which covers the first silicon oxide layer 103 and completely fills the U-shaped groove, and contacts the N-well region 102 at the window; a control gate dielectric layer 105, a control gate 106 and the second silicon nitride layer 107, the control gate dielectric layer 105 covers the semi-floating gate 104, the control gate 106 and the second silicon nitride layer 107 are sequentially formed on the control gate dielectric layer 105; the separation gate dielectric layer includes a fourth silicon oxide layer 109 and a third silicon nitride layer 110, which are formed on the surface of the N-well region 102 and extend to cover a portion of the surface of the second silicon nitride layer 107, the separation gate 111 covers the separation gate dielectric layer and fills the separation gate region; the source region 113, 114 and the drain region 115 are respectively formed in the N-well region 102 on both sides of the control gate and the separation gate.

[0026] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A method for preparing a highly efficient programmed semi-floating gate transistor, characterized in that: The following steps are involved: Ion implantation is performed in the substrate to form a P-well region and an N-well region, wherein the N-well region is formed above the P-well region, and etching is performed to form a U-shaped groove, wherein the U-shaped groove passes through the N-well region; A first silicon oxide layer and a semi-floating gate are formed, wherein the first silicon oxide layer covers the surface of the U-shaped groove and a part of the surface of the N-well region, and a window is formed on the surface of the N-well region outside the U-shaped groove; the semi-floating gate covers the first silicon oxide layer and contacts the surface of the N-well region in the window; Depositing a second silicon oxide layer, a second polysilicon layer and a mask layer, performing edge etching, etching out a control gate region and a separation gate region, and leaving part of the first silicon oxide layer at the window; The polysilicon and silicon exposed to the air are oxidized to form a third silicon oxide layer, and then the first silicon oxide layer and the third silicon oxide layer remaining at the window are etched away to completely open up the programming channel between the embedded tunneling transistor channel and the semi-floating gate storage layer; Depositing a separation gate dielectric layer to cover the device surface, depositing a third polysilicon layer to cover the separation gate dielectric layer and completely fill the separation gate region, performing edge etching and middle etching to form a control gate, a separation gate, and a source and drain region; The sidewalls are formed, source and drain ion implantation is performed, and N-type ion doping is performed on the third polysilicon layer and the second polysilicon layer at the same time, so as to form a highly efficient programmed semi-floating gate transistor.

2. The method for preparing a highly efficient programmed semi-floating gate transistor according to claim 1, characterized in that: The steps of forming a first silicon oxide layer and a semi-floating gate include: Depositing a first silicon oxide layer and a first polysilicon layer in the semi-floating gate region; Then, a portion of the first silicon oxide layer outside the U-shaped groove is removed by etching to expose a portion of the surface of the N-well region to form a window; Then, a portion of the first polysilicon layer is backfilled, ion implantation is performed in the semi-floating gate region, and chemical mechanical polishing is performed on the first polysilicon layer to form a semi-floating gate.

3. The method for preparing a highly efficient programmed semi-floating gate transistor according to claim 1, characterized in that: The steps of performing edge etching and middle etching to form a control gate, a separation gate and a source and drain region include: Performing edge etching to remove the third polysilicon layer and the separation gate dielectric layer at the edge to expose the source and drain regions on both sides, and at the same time, etching to remove the third polysilicon layer and the separation gate dielectric layer in the middle region to expose part of the surface of the mask layer; The middle etching is continued to remove part of the mask layer, the second polysilicon layer, the second silicon oxide layer, the first polysilicon layer, and the first gate oxide layer, so that a part of the surface of the N-well region in the middle area is exposed.

4. The method for preparing a highly efficient programmable semi-floating gate transistor according to claim 1, characterized in that: The third silicon oxide layer is removed by wet etching using a buffered oxide etching solution.

5. A highly efficient programmed semi-floating gate transistor, characterized in that: include: A substrate having a P-well region, an N-well region and a U-shaped groove, wherein the N-well region is located above the P-well region and the U-shaped groove runs through the N-well region; A semi-floating gate dielectric layer is formed on the surface of the U-shaped groove and only extends to cover a portion of the surface of the N-well region on one side, and does not cover the surface of the N-well region on the other side to form a window; a semi-floating gate covers the semi-floating gate dielectric layer and completely fills the U-shaped groove, and contacts the surface of the N-well region at the window, so that the programming channel of the embedded tunneling transistor channel and the semi-floating gate storage layer are completely connected; A control gate dielectric layer, a control gate and a mask layer, wherein the control gate dielectric layer covers the semi-floating gate, and the control gate and the mask layer are sequentially formed on the control gate dielectric layer; A separation gate dielectric layer and a separation gate, wherein the separation gate dielectric layer is formed on the surface of the N-well region and extends to cover a portion of the surface of the mask layer, and the separation gate covers the separation gate dielectric layer and fills the separation gate region; The source region and the drain region are respectively formed on both sides of the control gate and the separation gate and in the N-well region.

6. The highly efficient programmed semi-floating gate transistor according to claim 5, characterized in that: The separation gate dielectric layer is silicon nitride, and the separation gate is polysilicon.

7. The highly efficient programmed semi-floating gate transistor according to claim 5, characterized in that: The separation gate dielectric layer is a high-K dielectric, and the separation gate is a metal.

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