Semiconductor structure and its fabrication method

Abstract

This application provides a semiconductor structure and its fabrication method, relating to the field of semiconductor technology, to solve the technical problems of difficult capacitor fabrication and difficulty in improving aspect ratio. The fabrication method includes: forming a capacitor on a substrate, wherein a first support layer is disposed between a portion of a first electrode in the capacitor that is away from the substrate; removing a portion of a second electrode and a first dielectric layer to expose the surface of the first support layer facing away from the substrate; forming a second support layer having a first hole structure on this surface; forming a third electrode on the side of the first hole structure, the third electrode being in contact with the first electrode; forming a second dielectric layer covering the third electrode, the second dielectric layer being in contact with the first dielectric layer; and forming a fourth electrode on the side of the second dielectric layer, the fourth electrode being in contact with the second electrode. By providing the third electrode, the second dielectric layer, and the fourth electrode, the capacitor is increased in height along the direction away from the substrate, making it easier to fabricate and improving the aspect ratio of the capacitor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With the continuous development of semiconductor technology, the application of semiconductor structures is becoming increasingly widespread. In fields such as computers and communications, semiconductor structures with different functions are required. Capacitors, as an important semiconductor structure, are widely used in integrated circuits due to their voltage regulation and filtering functions, for example, in Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM).

[0003] Dynamic random access memory (DRAM) typically consists of multiple memory cells, each usually including a transistor and a capacitor. The capacitor stores data, while the transistor controls the reading and writing of data from the capacitor. The gate of the transistor is electrically connected to the word line (WL) of the DRAM, and the voltage on the word line controls the transistor's on / off state. One of the transistor's source and drain is electrically connected to the bit line (BL), and the other is electrically connected to the capacitor. Data is stored or output via the bit line.

[0004] In dynamic random access memory (DRAM), the capacitance of the capacitors has a significant impact on the DRAM's performance. To increase the capacitance, capacitors are typically designed with a large aspect ratio to increase the area of ​​the capacitor plates. However, high aspect ratio capacitors are difficult to manufacture, and it is difficult to further increase the aspect ratio. Summary of the Invention

[0005] In view of the above problems, embodiments of this application provide a semiconductor structure and a method for fabricating the same, which can improve the aspect ratio of a capacitor and reduce the difficulty of manufacturing the capacitor.

[0006] A first aspect of this application provides a method for fabricating a semiconductor structure, comprising: forming a capacitor on a substrate, the capacitor including a plurality of spaced-apart first electrodes, a first dielectric layer covering the side and top surfaces of each of the first electrodes, and a second electrode covering the first dielectric layer, wherein a first support layer is disposed between the portions of the first electrodes away from the substrate; removing a portion of the second electrode and a portion of the first dielectric layer to expose a surface of the first support layer away from the substrate; forming a second support layer on the surface of the first support layer away from the substrate, the second support layer having a first hole structure; the first support layer and the second support layer forming a new first support layer; forming a third electrode on a side surface of the first hole structure, the third electrode being in contact with the first electrode; the first electrode and the third electrode forming a new first electrode; forming a second dielectric layer covering the third electrode, the second dielectric layer being in contact with the first dielectric layer; the first dielectric layer and the second dielectric layer forming a new first dielectric layer; forming a fourth electrode on a side surface of the second dielectric layer, the fourth electrode being in contact with the second electrode, the second electrode and the fourth electrode forming a new second electrode.

[0007] The method for fabricating the semiconductor structure provided in this application has at least the following advantages:

[0008] In the semiconductor structure fabrication method of this application embodiment, the surface of the first support layer between the first electrodes away from the substrate is exposed, and a second support layer is formed on this surface. The second support layer has a first hole structure, i.e., the first hole structure is opposite to the capacitor. A third electrode, a second dielectric layer, and a fourth electrode are sequentially formed within the first hole structure. The third electrode is in contact with the first electrode, forming a new first electrode; the second dielectric layer is in contact with the first dielectric layer, forming a new first dielectric layer; and the fourth electrode is in contact with the second electrode, forming a new second electrode. The new first electrode, the new first dielectric layer, and the new second electrode form a new capacitor. The newly formed capacitor has an increased height along the direction perpendicular to the substrate, while its width remains unchanged, thus increasing its aspect ratio. Furthermore, by adding the third electrode, the second dielectric layer, and the fourth electrode to the top of the capacitor to increase its aspect ratio, the fabrication difficulty is reduced compared to etching to form a capacitor with a larger aspect ratio.

[0009] The second aspect of this application provides a semiconductor structure formed using the above-described semiconductor structure fabrication method, which has at least the advantages of a large aspect ratio and reduced fabrication difficulty. The specific effects are as described above and will not be repeated here. Attached Figure Description

[0010] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of this application;

[0011] Figure 2 This is a schematic diagram of a capacitor structure in an embodiment of this application;

[0012] Figure 3 for Figure 2 A magnified view of a section at point A in the middle;

[0013] Figure 4 This is a schematic diagram of a structure after removing part of the first dielectric layer in an embodiment of this application;

[0014] Figure 5 This is a schematic diagram of a structure after the extension layer is formed in an embodiment of this application;

[0015] Figure 6 This is a schematic diagram of a structure after the insulating layer is formed in an embodiment of this application;

[0016] Figure 7 This is a schematic diagram of a structure after the third electrode layer is formed in an embodiment of this application;

[0017] Figure 8 This is a schematic diagram of a structure after removing part of the third electrode in an embodiment of this application;

[0018] Figure 9 This is a schematic diagram of another structure after removing part of the third electrode in the embodiments of this application;

[0019] Figure 10 This is a schematic diagram of a structure after the second dielectric layer is formed in an embodiment of this application;

[0020] Figure 11 This is a schematic diagram of a structure after removing part of the second dielectric layer in an embodiment of this application;

[0021] Figure 12 This is a schematic diagram of a structure after the fourth electrode is formed in an embodiment of this application;

[0022] Figure 13 This is a schematic diagram of another structure after the fourth electrode is formed in an embodiment of this application;

[0023] Figure 14 This is a schematic diagram of a structure after the first conductive layer is formed in an embodiment of this application;

[0024] Figure 15 This is a schematic diagram of another structure after removing part of the first dielectric layer in an embodiment of this application;

[0025] Figure 16 This is a schematic diagram of another structure after the extension layer is formed in the embodiments of this application;

[0026] Figure 17This is a schematic diagram of another structure after the insulating layer is formed in an embodiment of this application;

[0027] Figure 18 This is a schematic diagram of another structure after the formation of the third electrode layer in an embodiment of this application;

[0028] Figure 19 This is a schematic diagram of another structure after removing part of the third electrode in the embodiments of this application;

[0029] Figure 20 This is a schematic diagram of another structure after the second dielectric layer is formed in an embodiment of this application;

[0030] Figure 21 This is a schematic diagram of another structure after removing part of the second dielectric layer in an embodiment of this application;

[0031] Figure 22 This is a schematic diagram of another structure after the fourth electrode is formed in the embodiments of this application;

[0032] Figure 23 This is a schematic diagram of another structure after the first conductive layer is formed in an embodiment of this application;

[0033] Figure 24 This is a schematic diagram of another structure of the capacitor in an embodiment of this application.

[0034] Explanation of reference numerals in the attached figures:

[0035] 10-Substrate; 11-Bit line; 12-Capacitor plug; 13-Contact pad; 21-First electrode; 22-Third electrode; 23-Top surface of the third electrode; 31-First dielectric layer; 32-Second dielectric layer; 41-Second electrode; 42-Fourth electrode; 50-First support layer; 51-Top surface of the first support layer; 60-Second support layer; 61-Extension layer; 62-Insulating layer; 63-First hole structure; 64-Second hole structure; 65-Side surface of the second hole structure; 66-Third hole structure; 67-Fourth hole structure; 68-Fifth hole structure; 69-Top surface of the second support layer; 70-First conductive layer; 80-Second conductive layer. Detailed Implementation

[0036] To improve the aspect ratio of the capacitor and reduce its fabrication difficulty, the semiconductor structure fabrication method in this application exposes the surface of the first support layer between the first electrodes away from the substrate, and forms a second support layer on this surface. The second support layer has a first hole structure, within which a third electrode, a second dielectric layer, and a fourth electrode are sequentially formed. The third electrode is in contact with the first electrode, the second dielectric layer is in contact with the first dielectric layer, and the fourth electrode is in contact with the second electrode. This increases the height of the capacitor in the direction perpendicular to the substrate while maintaining the same width, thereby increasing its aspect ratio. Furthermore, by adding the third electrode, the second dielectric layer, and the fourth electrode to the top of the capacitor to increase its aspect ratio, the fabrication difficulty is reduced compared to etching to form a capacitor with a larger aspect ratio.

[0037] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0038] refer to Figure 1 , Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application is provided. The method includes the following steps:

[0039] Step S100: A capacitor is formed on a substrate. The capacitor includes a plurality of spaced first electrodes, a first dielectric layer covering the side and top surfaces of each first electrode, and a second electrode covering the first dielectric layer. A first support layer is disposed between the first electrodes away from the substrate.

[0040] refer to Figure 2 and Figure 3 The substrate 10 has multiple bit lines 11 extending along a first direction and spaced apart, and multiple word lines (not shown) extending along a second direction and spaced apart. The first and second directions form an angle; for example, they may be perpendicular. The word lines may be embedded word lines, extending along a direction perpendicular to the substrate 10. Figure 2 and Figure 3 (As shown in the Z direction), the word line is located below the bit line 11, that is, the word line is located deeper in the substrate 10 than the bit line 11.

[0041] Multiple capacitor plugs 12 are spaced apart between adjacent bit lines 11, and each capacitor plug 12 is insulated from the others. A contact pad 13 is provided on the side of each capacitor plug 12 away from the substrate 10, and the contact pad 13 is exposed on the surface of the substrate 10 to facilitate contact with a capacitor for electrical connection. The capacitor plug 12 can be made of polycrystalline silicon, and the contact pad 13 can be made of tungsten. At least one diffusion barrier layer is provided between the contact pad 13 and the capacitor plug 12 to prevent tungsten diffusion; the diffusion barrier layer can be made of titanium nitride.

[0042] like Figure 2 As shown, taking the surface perpendicular to the extension direction of bit line 11 as a cross-section, the cross-sectional shape of contact pad 13 can be approximately Z-shaped. This configuration allows for adjustments to the size of the surface of contact pad 13 facing away from substrate 10, ensuring that the area of ​​this surface is larger than the area of ​​the contact surface between contact pad 13 and capacitor plug 12. Specifically, the area of ​​the top surface of contact pad 13 is larger than the area of ​​its bottom surface. This results in a faster alignment speed between the capacitor on substrate 10 and contact pad 13 compared to the alignment speed between the capacitor and capacitor plug 12, improving the fabrication efficiency of the semiconductor structure. Furthermore, contact pad 13 allows for the formation of hexagonally close-packed capacitors on the rectangular array of capacitor plugs 12, increasing the capacitor density and thus improving the storage capacity of the semiconductor structure.

[0043] Continue to refer to Figure 2 and Figure 3 A capacitor is formed on a substrate 10. The capacitor includes a first electrode 21 and a second electrode 41 disposed opposite to each other, and a first dielectric layer 31 disposed between the first electrode 21 and the second electrode 41. Specifically, there can be multiple first electrodes 21, which are disposed at intervals. Each first electrode 21 is opposite to and in contact with a contact pad 13, that is, the bottom surface of each first electrode 21 is in direct contact with the contact pad 13.

[0044] Each first electrode 21 has a first dielectric layer 31 covering its side surface and top surface. The top surface of the first electrode 21 refers to the surface of the first electrode 21 facing away from the substrate 10, and the side surface of the first electrode 21 refers to the surface between the top surface and the bottom surface of the first electrode 21. When the first electrode 21 is a columnar electrode, the side surface of the first electrode 21 refers to the outer peripheral surface of the columnar electrode; when the first electrode 21 is a cylindrical electrode, the side surface of the first electrode 21 refers to the outer peripheral surface and the inner peripheral surface of the cylindrical electrode.

[0045] The first dielectric layer 31 is covered with a second electrode 41, that is, the first dielectric layer 31 corresponding to each first electrode 21 forms a whole, and the second electrode 41 corresponding to each first electrode 21 also forms a whole, so as to facilitate the formation of the first dielectric layer 31 and the second electrode 41 and reduce the number of steps in the capacitor manufacturing process.

[0046] Continue to refer to Figure 2 and Figure 3 To reduce or prevent the collapse of the first electrode 21 and to prevent contact between multiple first electrodes 21 due to instability, a first support layer 50 is provided between the portions of the first electrodes 21 furthest from the substrate 10; that is, a first support layer 50 is provided between the top regions of the first electrodes 21. Of course, there can be multiple first support layers 50, and the first support layers 50 can also be provided in the middle and bottom regions of the first electrodes 21. Figure 2 As shown, a first support layer 50 is provided in the bottom region, middle region and top region of the outer side of the first electrode 21 to further improve the stability of the first electrode 21.

[0047] In one possible example, such as Figure 3 As shown, the surface of the first support layer 50 facing away from the substrate 10 is flush with the surface of the first electrode 21 facing away from the substrate 10. That is, as... Figure 3 As shown, the top surface 51 of the first support layer is flush with the top surface of the first electrode 21.

[0048] Step S200: Remove part of the second electrode and part of the first dielectric layer to expose the surface of the first support layer away from the substrate.

[0049] refer to Figure 3 and Figure 4 The second electrode 41 and the first dielectric layer 31 located above the first support layer 50 are removed to expose the top surface 51 of the first support layer. The top surface 51 of the first support layer refers to the surface of the first support layer 50 that faces away from the substrate 10. Figure 3 and 4 The upper surface is shown. By exposing the top surface 51 of the first support layer as a support surface, a second support layer 60 (see reference) is subsequently formed on this surface. Figure 6 The second support layer 60 and the first support layer 50 form a new first support layer to increase the height of the first support layer. Exemplarily, the first electrode 21, the second electrode 41, and the first dielectric layer 31 are removed by dry etching with a chlorine-based gas. For example, the chlorine-based gas may include at least one of chlorine, chloromethane, or dichloromethane.

[0050] In one possible example, such as Figure 3 and Figure 4 As shown, after removing part of the second electrode 41 and part of the first dielectric layer 31, the top surface of the remaining second electrode 41 can be flush with the top surface 51 of the first support layer, and the top surface 51 of the remaining first support layer can be flush with the top surface 51 of the first support layer. Figure 4 As shown, only the top surface of the first support layer 50 is exposed.

[0051] Step S300: A second support layer is formed on the surface of the first support layer away from the substrate, the second support layer having a first hole structure; the first support layer and the second support layer form a new first support layer.

[0052] refer to Figures 4 to 6 A second support layer 60 is formed on the top surface 51 of the first support layer. The second support layer 60 can be aligned with the first support layer 50, and the second support layer 60 and the first support layer 50 form a new first support layer. Taking a plane parallel to the substrate 10 as a cross-section, the cross-sectional shape of the second support layer 60 is the same as that of the first support layer 50. The second support layer 60 has a first hole structure 63, which exposes the first electrode 21, the first dielectric layer 31, and the second electrode 41.

[0053] In one possible example, such as Figure 5 and Figure 6 As shown, the second support layer 60 includes an extension layer 61 and an insulating layer 62 covering the extension layer 61. This configuration allows the extension layer 61 to be insulated from other structures, ensuring the normal operation of the capacitor. Forming the second support layer on the surface of the first support layer away from the substrate, the second support layer having a first porous structure, can include the following process:

[0054] An extension layer is formed on the exposed surface of the first support layer, and the extension layer has a second porous structure. For example... Figure 5 As shown, an extension layer 61 is formed on the first support layer 50 by a selective epitaxial growth process, so that the extension layer 61 grows in a direction perpendicular to the substrate 10.

[0055] Specifically, the material of the extension layer 61 includes group III or group V elements, such as silicon. The material of the first support layer 50 contains the same group III or group V elements as the material of the extension layer 61, that is, the first support layer 50 contains silicon, for example, the material of the first support layer 50 is silicon nitride, silicon oxide, or silicon oxynitride. The materials of the first electrode 21 and the second electrode 41 can be conductive materials with a certain strength and easy etching, and the material of the first dielectric layer 31 can be an insulating material. Furthermore, the materials of the first electrode 21, the second electrode 41, and the first dielectric layer 31 do not contain the same group III or group V elements as the material of the extension layer 61. For example, the materials of the first electrode 21, the second electrode 41, and the first dielectric layer 31 may not contain group III or group V elements, or may contain other group III or group V elements besides silicon. For example, the first electrode 21 and the second electrode 41 can be made of titanium nitride, molybdenum nitride, ruthenium nitride, or their alloys, and the first dielectric layer 31 can be made of hafnium oxide, zirconium oxide, calcium titanate, or barium titanate, etc. This arrangement allows the extension layer 61 to be formed on the first support layer 50, preventing it from forming on the first electrode 21, the second electrode 41, and the first dielectric layer 31.

[0056] After forming the extension layer, the sides of the second hole structure are etched to expose the portion of the first support layer facing away from the substrate. For example... Figure 5 and Figure 6 As shown, the side surface 65 of the second hole structure is etched to remove part of the extension layer 61, thereby increasing the diameter of each hole in the second hole structure 64 to expose part of the top surface of the first support layer 50. The orthographic projection of the remaining extension layer 61 on the substrate 10 lies within the range of the orthographic projection of the first support layer 50 on the substrate 10, and there is a gap between the edges of these two orthographic projections, i.e., there is no intersection between the two orthographic projections.

[0057] An insulating layer is formed on the sides and extension layer of the etched second hole structure, and the insulating layer located within the second hole structure encloses the first hole structure. For example... Figure 6 As shown, an insulating layer 62 is formed on the side 65 of the etched second hole structure and on the extension layer 61. The insulating layer 62 covers the extension layer 61, meaning that each surface of the extension layer 61 is covered by the insulating layer 62, so that there are no exposed parts of the extension layer 61, thereby insulating the extension layer 61. For example, a passivation film is formed on the surface of the extension layer 61 by a passivation process; the passivation film is the insulating layer 62. For instance, the passivation film is formed on the surface of the extension layer 61 by a deposition process or a thermal oxidation process.

[0058] Step S400: A third electrode is formed on the side of the first hole structure, and the third electrode is in contact with the first electrode; the first electrode and the third electrode form a new first electrode.

[0059] refer to Figures 6 to 8 The material of the third electrode 22 can be the same as that of the first electrode 21, so that the third electrode 22 and the first electrode 21 are integrated, reducing delamination and contact resistance between the third electrode 22 and the first electrode 21. The third electrode 22 can be aligned with the first electrode 21, thereby reducing the obstruction of the first dielectric layer 31. The first electrode 21 and the third electrode 22 form a new first electrode, the height of which is increased compared to the first electrode 21.

[0060] In some possible examples, forming a third electrode on the side of the first aperture structure, the third electrode being in contact with the first electrode, may include the following process:

[0061] A third electrode is deposited on the sides and bottom of the first porous structure, as well as on the second support layer. The third electrode, located within the first porous structure, forms a third porous structure. Figure 6 and Figure 7 As shown, a third electrode 22 is deposited on the side and bottom surfaces of the first porous structure 63 and on the second support layer 60 using processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The third electrode 22 located within the first porous structure 63 forms a third porous structure 66.

[0062] After depositing the third electrode, the third electrode is etched to remove it from the second support layer and the bottom surface of the third hole structure. For example... Figure 7 and Figure 8 As shown, dry etching or wet etching removes the third electrode 22 located on the second support layer 60 and the bottom surface of the third hole structure 66, leaving the third electrode 22 located on the side of the second support layer 60 exposed. The second support layer 60, the first dielectric layer 31, and the second electrode 41 are then exposed. In some possible examples, refer to... Figure 9 The surface of the third electrode 22 facing away from the substrate is lower than the surface of the second support layer 60 facing away from the substrate 10, that is, the top surface 69 of the second support layer is higher than the top surface 23 of the third electrode. This arrangement facilitates the subsequent formation of the second dielectric layer 32 on the top surface 23 of the third electrode, thereby facilitating the insulation between the third electrode 22 and the fourth electrode 42.

[0063] Step S500: A second dielectric layer is formed covering the third electrode, and the second dielectric layer is in contact with the first dielectric layer; the first dielectric layer and the second dielectric layer form a new first dielectric layer.

[0064] refer to Figures 9 to 11The second dielectric layer 32 covers the third electrode 22 and is in contact with the first dielectric layer 31, forming a new first dielectric layer 31. The second dielectric layer 32 is aligned with the first dielectric layer 31, and the material of the second dielectric layer 32 can be the same as that of the first dielectric layer 31.

[0065] In one possible example, forming a second dielectric layer covering the third electrode, the second dielectric layer being in contact with the first dielectric layer, may include:

[0066] A second dielectric layer is deposited on the sides and bottom of the third porous structure, the third electrode, and the second support layer. The second dielectric layer located within the third porous structure forms a fourth porous structure. Figure 9 and Figure 10 As shown, the second dielectric layer 32 covers the bottom and side surfaces of the third hole structure 66, the third electrode 22, and the second support layer 60. After the second dielectric layer 32 is formed, the third electrode 22 is covered. The second dielectric layer 32 located within the third hole structure 66 forms a fourth hole structure 67.

[0067] After depositing the second dielectric layer, the second dielectric layer is etched to remove the second dielectric layer located on the second support layer and the bottom surface of the fourth pore structure. For example... Figure 10 and Figure 11 As shown, anisotropic etching is used to remove a portion of the second dielectric layer 32 along a direction perpendicular to the substrate 10. After etching the second dielectric layer 32, the top surface of the second dielectric layer 32 can be flush with the top surface of the second support layer 60, exposing the second support layer 60 and the second electrode 41. The top and side surfaces of the first electrode 21 are still covered by the second dielectric layer 32 to ensure that the first electrode 21 is insulated. Of course, after etching the second dielectric layer 32, the top surface of the second dielectric layer 32 can also be higher than the top surface of the second support layer 60, that is, the second support layer 60 is also covered by the second dielectric layer 32.

[0068] Step S600: A fourth electrode is formed on the side of the second dielectric layer. The fourth electrode is in contact with the second electrode, and the second electrode and the fourth electrode form a new second electrode.

[0069] refer to Figure 11 and Figure 12 A fourth electrode 42 is formed on the side of the second dielectric layer 32, and the fourth electrode 42 is in contact with the second electrode 41, forming a new second electrode. The fourth electrode 42 and the second electrode 41 can be aligned, and the material of the fourth electrode 42 can be the same as that of the second electrode 41.

[0070] In some possible examples, a fourth electrode is formed on the side of the second dielectric layer, and the fourth electrode is in contact with the second electrode, including: depositing the fourth electrode within the fourth pore structure, on the second dielectric layer, and on the second support layer. For example, Figure 11 and Figure 12 As shown, the fourth electrode 42 can fill the fourth hole structure 67; or, as Figure 11 and Figure 13 As shown, the fourth electrode 42 covers the side and bottom surfaces of the fourth hole structure 67, and the fourth electrode 42 located inside the fourth hole structure 67 forms a fifth hole structure 68.

[0071] In some possible examples, a fourth electrode is formed on the side of the second dielectric layer, the fourth electrode is in contact with the second electrode, and after the second electrode and the fourth electrode form a new second electrode, the method further includes: depositing a first conductive layer on the fourth electrode, the surface of the first conductive layer facing away from the substrate being higher than the surface of the fourth electrode facing away from the substrate.

[0072] refer to Figure 14 The first conductive layer 70 is used to connect the fourth electrode 42 to the peripheral circuit, and its material can be silicon germanide, etc. When the fourth electrode 42 can fill the fourth hole structure 67, the first conductive layer 70 covers the top surface of the fourth electrode 42. When the fourth electrode 42 does not fill the fourth hole structure 67, the first conductive layer 70 fills the fifth hole structure 68 and covers the top surface of the fourth electrode 42. In this case, the material of the first conductive layer 70 is a material with a certain degree of fluidity to facilitate filling the fifth hole structure 68. The first conductive layer 70 can also provide support for the fourth electrode 42, providing stability to the fourth electrode 42.

[0073] In summary, in the semiconductor structure fabrication method of this application embodiment, the surface of the first support layer 50 between the first electrodes 21 away from the substrate 10 is exposed, and a second support layer 60 is formed on this surface. The second support layer 60 has a first hole structure 63, that is, the first hole structure 63 is opposite to the capacitor. A third electrode 22, a second dielectric layer 32, and a fourth electrode 42 are sequentially formed in the first hole structure 63. The third electrode 22 is in contact with the first electrode 21, and the two form a new first electrode 21. The second dielectric layer 32 is in contact with the first dielectric layer 31, and the two form a new first dielectric layer 31. The fourth electrode 42 is in contact with the second electrode 41, and a new second electrode 41 is formed. The new first electrode 21, the new first dielectric layer 31, and the new second electrode 41 form a new capacitor. The height of the newly formed capacitor is increased in the direction perpendicular to the substrate 10, while the width remains unchanged, thereby increasing its aspect ratio. Furthermore, by adding a third electrode 22, a second dielectric layer 32, and a fourth electrode 42 to the top of the capacitor, the aspect ratio of the capacitor is increased, which reduces the manufacturing difficulty compared to etching to form a capacitor with a larger aspect ratio.

[0074] In one possible example of this application, removing a portion of the second electrode and a portion of the first dielectric layer to expose the surface of the first support layer away from the substrate includes: removing a portion of the second electrode, a portion of the first dielectric layer, and a portion of the first electrode to expose the surface of the first support layer away from the substrate, and a portion of the side of the first support layer away from the substrate. Reference Figure 3 and Figure 15 The top surface 51 of the first support layer and the side surface connected to the top surface are exposed. The top surface of the first electrode 21, the top surface of the first dielectric layer 31, and the top surface of the second electrode 41 are all lower than the top surface 51 of the first support layer, which increases the exposed area of ​​the first support layer 50 and makes it easier to form the second support layer 60 on the first support layer 50.

[0075] refer to Figure 15 and Figure 16 By controlling the growth rate of the extended layer 61 in different directions, the extended layer 61 is made to grow along a direction perpendicular to the substrate 10. Figure 16 The growth rate in the Z direction (as shown) is greater than its growth rate in the direction parallel to the substrate ( 10). Figure 16 The growth rate (shown in the X direction) is such that the thickness of the extension layer 61 on the surface of the first support layer 50 away from the substrate 10 is greater than the thickness of the extension layer 61 on the side of the first support layer 50, so as to ensure that each hole in the second hole structure 64 has a certain diameter, which facilitates the subsequent processing of the side of the second hole structure 64.

[0076] Understandably, the extension layer 61 has a second hole structure 64, and along a direction perpendicular to the substrate 10, the bottom of the second hole structure 64 is lower than the top surface 51 of the first support layer. (Reference) Figure 16 After the extension layer 61 is formed, when the side surface 65 of the second hole structure is etched, not only is part of the surface of the first support layer 50 away from the substrate 10 exposed, but also part of the side surface of the first support layer 50 is exposed.

[0077] refer to Figure 17 An insulating layer 62 is formed on the side surface 65 and the extension layer 61 of the etched second hole structure. The insulating layer 62 covers the extension layer 61 but does not cover the side surface of the first support layer 50. Exemplarily, the orthographic projections of the insulating layer 62 and the extension layer 61 onto the substrate 10 coincide with the orthographic projection of the first support layer 50 onto the substrate 10. (See reference...) Figures 18 to 23 The subsequent production steps can be referred to steps S400 to S600, and will not be repeated here.

[0078] In one possible example of this application, after removing a portion of the second electrode and a portion of the first dielectric layer to expose the surface of the first support layer facing away from the substrate, the following steps are further repeated at least twice:

[0079] A second support layer is formed on the surface of the first support layer away from the substrate, and the second support layer has a first hole structure; the first support layer and the second support layer form a new first support layer;

[0080] A third electrode is formed on the side of the first hole structure, and the third electrode is in contact with the first electrode; the first electrode and the third electrode form a new first electrode;

[0081] A second dielectric layer is formed on the side of the third electrode, and the second dielectric layer is in contact with the first dielectric layer; the first dielectric layer and the second dielectric layer form a new first dielectric layer.

[0082] A fourth electrode is formed on the side of the second dielectric layer, and the fourth electrode is in contact with the second electrode, forming a new second electrode with the second electrode;

[0083] Until the total height of the first electrode and the repeatedly formed third electrode along the direction perpendicular to the substrate reaches a preset value.

[0084] In other words, the new first electrode, the new first dielectric layer, and the new second electrode can be continuously increased in height to achieve the required height, further improving the aspect ratio of the capacitor and reducing the fabrication difficulty of the capacitor. Taking repetition twice as an example, the fabrication process of the semiconductor structure in this application embodiment may include:

[0085] Step S001: A capacitor is formed on a substrate. The capacitor includes a plurality of spaced first electrodes, a first dielectric layer covering the side and top surfaces of each first electrode, and a second electrode covering the first dielectric layer. A first support layer is disposed between the first electrodes away from the substrate.

[0086] Step S002: Remove part of the second electrode and part of the first dielectric layer to expose the surface of the first support layer away from the substrate.

[0087] Step S003: A second support layer is formed on the surface of the first support layer away from the substrate, the second support layer having a first hole structure; the first support layer and the second support layer form a new first support layer.

[0088] Step S004: A third electrode is formed on the side of the first hole structure, and the third electrode is in contact with the first electrode; the first electrode and the third electrode form a new first electrode.

[0089] Step S005: A second dielectric layer is formed on the side of the third electrode, and the second dielectric layer is in contact with the first dielectric layer; the first dielectric layer and the second dielectric layer form a new first dielectric layer;

[0090] Step S006: A fourth electrode is formed on the side of the second dielectric layer. The fourth electrode is in contact with the second electrode, and the second electrode and the fourth electrode form a new second electrode.

[0091] Step S007: A second support layer is formed on the surface of the first support layer away from the substrate, the second support layer having a first hole structure; the first support layer and the second support layer form a new first support layer.

[0092] Step S008: A third electrode is formed on the side of the first hole structure, and the third electrode is in contact with the first electrode; the first electrode and the third electrode form a new first electrode.

[0093] Step S009: A second dielectric layer is formed on the side of the third electrode, and the second dielectric layer is in contact with the first dielectric layer; the first dielectric layer and the second dielectric layer form a new first dielectric layer.

[0094] Step S010: A fourth electrode is formed on the side of the second dielectric layer. The fourth electrode is in contact with the second electrode, and the second electrode and the fourth electrode form a new second electrode.

[0095] It should be noted that during the process of forming a fourth electrode on the side of the second dielectric layer, the fourth electrode being in contact with the second electrode, and the second electrode and the fourth electrode forming a new second electrode (step S600), if the fourth electrode still covers the second support layer and the second dielectric layer, the fourth electrode located on the second support layer and the second dielectric layer is removed, while the fourth electrode located on the side of the second dielectric layer is retained, so that the second support layer is exposed, that is, the surface of the newly formed first support layer facing away from the substrate is exposed.

[0096] The structure of the capacitor in this embodiment is not limited. The capacitor can be a single-sided capacitor or a double-sided capacitor. The first electrode 21 can be cylindrical or cylindrical. In some possible examples, the first electrode 21 is cylindrical, the second electrode 41 is cylindrical, the second electrode 41 is sleeved on the first electrode 21, and a first dielectric layer 31 is formed between the first electrode 21 and the second electrode 41. In this case, the capacitor is a single-sided capacitor.

[0097] In some other possible examples, refer to Figure 1 and Figure 24 The first electrode 21 includes a bottom wall and side walls circumferentially surrounding the bottom wall, the bottom wall and side walls forming a first space, i.e., the first electrode 21 is cylindrical. To increase the capacitance of the capacitor, a portion of the second electrode 41 is disposed opposite to the inner surface of the first electrode 21, and a portion of the second electrode 41 is disposed opposite to the outer surface of the first electrode 21. For example... Figure 24 As shown, the second electrode 41 located in the first space can fill the first space after the formation of the first dielectric layer 31, or as... Figure 1 As shown, a third space is also formed between the second electrodes 41 located in the second space.

[0098] Among them, continue to refer to Figure 1 A capacitor is formed on the substrate 10. The capacitor includes a plurality of spaced first electrodes 21, a first dielectric layer 31 covering the first electrodes 21, and a second electrode 41 covering the first dielectric layer 31. A first support layer 50 is also disposed between the portions of the first electrodes 21 away from the substrate 10, and may include:

[0099] A substrate 10 is provided, and a plurality of spaced contact pads 13 are formed therein. The contact pads 13 are exposed on the surface of the substrate 10.

[0100] Multiple spaced first electrodes 21 are formed on a substrate 10, with the bottom wall of each first electrode 21 electrically connected to a contact pad 13. Specifically, a stacked structure is first formed on the substrate 10, the stacked structure having a sixth hole structure that exposes the contact pad 13; then, first electrodes 21 are deposited on the side and bottom surfaces of the sixth hole structure, with the bottom wall of the first electrode 21 contacting the contact pad 13 to achieve electrical connection between the first electrode 21 and the contact pad 13. The stacked structure may include a sacrificial layer and a first support layer 50 arranged alternately in sequence, with the outermost layer of the stacked structure away from the substrate 10 being the first support layer 50. After forming the first electrodes 21, the sacrificial layer is removed, leaving only the first support layer 50. For example, an etch hole is formed in the first support layer 50, exposing the sacrificial layer, through which the sacrificial layer can be removed.

[0101] A first dielectric layer 31 is formed covering the first electrode 21 and the substrate 10, and the first dielectric layer 31 located in the first space surrounds the second space. The first dielectric layer 31 is formed by a deposition process, and the first dielectric layer 31 is a single layer. The first dielectric layer 31 covers the substrate 10, the side and bottom surfaces of the first space, and the outer peripheral surface of the first electrode 21.

[0102] A second electrode 41 is formed covering the first dielectric layer 31, and the second electrode 41 located in the second space surrounds a third space. The second electrode 41 is formed by a deposition process, and the second electrode 41 covers the first dielectric layer 31. Figure 1 As shown, the second electrode 41 is located on the side of the second space and is not formed into a solid column shape, so that the size of the semiconductor structure can be further miniaturized.

[0103] It should be noted that after the second electrode 41 covering the first dielectric layer 31 is formed, and the second electrode 41 located in the second space surrounds the third space, the system further includes: forming a second conductive layer 80 covering the second electrode 41, the second conductive layer 80 filling the third space and covering the surface of the second electrode 41 facing away from the substrate 10. For example... Figure 1As shown, the second conductive layer 80 fills the spaces between the second electrodes 41 and covers the second electrodes 41. The second conductive layer 80 serves two purposes: firstly, to connect the second electrodes 41 to the external circuit; and secondly, to support the second electrodes 41, prevent them from collapsing, and improve their stability.

[0104] Correspondingly, such as Figure 3 and Figure 4 As shown, removing a portion of the second electrode 41 and a portion of the first dielectric layer 31 to expose the surface of the first support layer 50 away from the substrate 10 includes: removing a portion of the second conductive layer 80, a portion of the second electrode 41, and a portion of the first dielectric layer 31 to expose the surface of the first support layer 50 away from the substrate 10.

[0105] In one possible example, the second conductive layer 80 may include a first material layer adjacent to the substrate 10 and a second material layer disposed on the side of the first material layer away from the substrate 10. The material of the second material layer does not contain the same group III or group V elements as the material of the extension layer 61, the material of the first support layer 50 contains the same group III or group V elements as the material of the extension layer 61, and the materials of the first electrode 21, the second electrode 41, and the first dielectric layer 31 do not contain the same group III or group V elements as the material of the extension layer 61.

[0106] For example, the extension layer 61 contains silicon, the first support layer 50 is made of a silicon-containing compound, the second material layer is a germanium layer, the first material layer is a silicon germanide layer, and the materials of the first electrode 21, the second electrode 41, and the first dielectric layer 31 do not contain silicon. When removing part of the second conductive layer 80, a fluorine-based gas dry etching process is used to etch part of the second material layer until the second electrode 41 is exposed. Then, the second electrode 41 is removed until the first support layer 50 is exposed. At this time, the second material layer still covers the first material layer so that when the extension layer 61 is subsequently formed, the extension layer 61 will not grow on the second material layer. The fluorine-based gas may include carbon tetrafluoride or sulfur hexafluoride, etc.

[0107] This application also provides a semiconductor structure formed using the above-described semiconductor structure fabrication method, which has at least the advantages of a large aspect ratio and reduced fabrication difficulty. The specific effects are as described above and will not be repeated here.

[0108] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0109] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0110] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A capacitor is formed on a substrate, the capacitor including a plurality of spaced first electrodes, a first dielectric layer covering the side and top surfaces of each first electrode, and a second electrode covering the first dielectric layer, with a first support layer disposed between the first electrodes away from the substrate. Remove a portion of the second electrode and a portion of the first dielectric layer to expose the surface of the first support layer facing away from the substrate; A second support layer is formed on the surface of the first support layer opposite to the substrate, the second support layer having a first hole structure; the first support layer and the second support layer form a new first support layer; A third electrode is formed on the side of the first hole structure, and the third electrode is in contact with the first electrode; The first electrode and the third electrode form a new first electrode; A second dielectric layer is formed to cover the third electrode, and the second dielectric layer is in contact with the first dielectric layer; The first dielectric layer and the second dielectric layer form a new first dielectric layer; A fourth electrode is formed on the side of the second dielectric layer, the fourth electrode being in contact with the second electrode, and the second electrode and the fourth electrode forming a new second electrode.

2. The manufacturing method according to claim 1, characterized in that, The surface of the first support layer facing away from the substrate is flush with the surface of the first electrode facing away from the substrate.

3. The manufacturing method according to claim 1, characterized in that, The second support layer includes an extension layer and an insulating layer covering the extension layer; A second support layer is formed on the surface of the first support layer facing away from the substrate, the second support layer having a first porous structure, including: An extension layer is formed on the exposed surface of the second support layer, the extension layer having a second porous structure; The sidewalls of the second hole structure are etched to expose a portion of the surface of the first support layer that faces away from the substrate; An insulating layer is formed on the side of the etched second hole structure and on the extended layer, and the insulating layer located within the second hole structure encloses the first hole structure.

4. The manufacturing method according to claim 3, characterized in that, The extension layer is formed on the first support layer by a selective epitaxial growth process.

5. The manufacturing method according to claim 4, characterized in that, The material of the first support layer contains the same group III or group V elements as the material of the extension layer, and the materials of the first electrode, the second electrode, and the first dielectric layer do not contain the same group III or group V elements as the material of the extension layer.

6. The manufacturing method according to claim 3, characterized in that, Removing a portion of the second electrode and a portion of the first dielectric layer to expose the surface of the first support layer facing away from the substrate includes: A portion of the second electrode, a portion of the first dielectric layer, and a portion of the first electrode are removed to expose the surface of the first support layer facing away from the substrate, and a portion of the side of the first support layer away from the substrate.

7. The manufacturing method according to claim 1, characterized in that, A third electrode is formed on the side of the first hole structure, the third electrode being in contact with the first electrode, including: The third electrode is deposited on the side and bottom surfaces of the first hole structure and on the second support layer, and the third electrode located within the first hole structure forms a third hole structure. The third electrode is etched to remove the third electrode located on the second support layer and the bottom surface of the third hole structure.

8. The manufacturing method according to claim 7, characterized in that, The surface of the third electrode facing away from the substrate is lower than the surface of the second support layer facing away from the substrate.

9. The manufacturing method according to claim 7, characterized in that, Forming a second dielectric layer covering the third electrode, the second dielectric layer being in contact with the first dielectric layer, comprising: A second dielectric layer is deposited on the side and bottom surfaces of the third hole structure, the third electrode, and the second support layer. The second dielectric layer located within the third hole structure forms a fourth hole structure. The second dielectric layer is etched to remove the second dielectric layer located on the second support layer and the bottom surface of the fourth hole structure.

10. The manufacturing method according to claim 9, characterized in that, A fourth electrode is formed on the side surface of the second dielectric layer, the fourth electrode being in contact with the second electrode, comprising: The fourth electrode is deposited within the fourth porous structure, on the second dielectric layer, and on the second support layer.

11. The manufacturing method according to claim 10, characterized in that, The fourth electrode fills the fourth hole structure; Alternatively, the fourth electrode covers the side and bottom surfaces of the fourth hole structure, and the fourth electrode located within the fourth hole structure forms a fifth hole structure.

12. The manufacturing method according to any one of claims 1-11, characterized in that, A fourth electrode is formed on the side surface of the second dielectric layer. After the fourth electrode comes into contact with the second electrode, the layer further includes: A first conductive layer is deposited on the fourth electrode, wherein the surface of the first conductive layer facing away from the substrate is higher than the surface of the fourth electrode facing away from the substrate.

13. The manufacturing method according to any one of claims 1-11, characterized in that, After removing a portion of the second electrode and a portion of the first dielectric layer to expose the surface of the first support layer facing away from the substrate, the method further includes: Repeat the following steps at least twice: A second support layer is formed on the surface of the first support layer opposite to the substrate, the second support layer having a first hole structure; the first support layer and the second support layer form a new first support layer; A third electrode is formed on the side of the first hole structure, and the third electrode is in contact with the first electrode; the first electrode and the third electrode form a new first electrode; A second dielectric layer is formed to cover the third electrode, and the second dielectric layer is in contact with the first dielectric layer; the first dielectric layer and the second dielectric layer form a new first dielectric layer; A fourth electrode is formed on the side of the second dielectric layer, the fourth electrode is in contact with the second electrode, and the second electrode and the fourth electrode form a new second electrode; Until the total height of the first electrode and the repeatedly formed third electrode along the direction perpendicular to the substrate reaches a preset value.

14. The manufacturing method according to any one of claims 3-6, characterized in that, The first electrode includes a bottom wall and a side wall that surrounds the bottom wall circumferentially, the bottom wall and the side wall forming a first space; A capacitor is formed on a substrate, the capacitor including a plurality of spaced-apart first electrodes, a first dielectric layer covering the first electrodes, and a second electrode covering the first dielectric layer. A first support layer is further disposed between the first electrodes away from the substrate, including: A substrate is provided, wherein a plurality of spaced contact pads are formed therein; A plurality of first electrodes are formed on the substrate at intervals, and the bottom wall of each first electrode is electrically connected to a contact pad; A first dielectric layer is formed covering the first electrode and the substrate, and the first dielectric layer located in the first space encloses a second space; A second electrode is formed to cover the first dielectric layer, and the second electrode located in the second space surrounds a third space.

15. The manufacturing method according to claim 14, characterized in that, After the second electrode covering the first dielectric layer is formed, and the second electrode located in the second space encloses the third space, the third space is further included: A second conductive layer is formed to cover the second electrode, the second conductive layer filling the third space and covering the surface of the second electrode away from the substrate; Accordingly, a portion of the second electrode and a portion of the first dielectric layer are removed to expose the surface of the first support layer facing away from the substrate, including: A portion of the second conductive layer, a portion of the second electrode, and a portion of the first dielectric layer are removed to expose the surface of the first support layer facing away from the substrate.

16. The manufacturing method according to claim 15, characterized in that, The material of the first support layer and the material of the extension layer contain the same group III or group V elements, and the materials of the first electrode, the second electrode and the first dielectric layer do not contain the same group III or group V elements as the material of the extension layer. The second conductive layer includes a first material layer and a second material layer disposed on the side of the first material layer away from the substrate; the material of the second material layer does not contain any Group III or Group V elements that are the same as the material of the extended layer. Removing part of the second conductive layer means removing part of the second material layer.

17. A semiconductor structure, characterized in that, The semiconductor structure is formed using the semiconductor structure fabrication method according to any one of claims 1-16.

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