半导体结构的制作方法及半导体结构
By setting word line structures made of different materials in the semiconductor structure, the problem of gate-induced drain leakage was solved, improving performance and yield.
CN114141712BActive Publication Date: 2026-07-17CHANGXIN MEMORY TECH INC +1
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2021-11-30
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
As semiconductor device dimensions shrink, gate-induced drain leakage (GIDL) negatively impacts semiconductor structure performance and yield.
Method used
In a semiconductor structure, by forming a gate oxide layer on the sidewall of the second segment and the bottom surface of the third segment, and setting a first word line structure and a second word line structure of different materials, the potentials at both ends of the second segment are different, thereby controlling the turn-off current and reducing gate-induced drain leakage current and inter-band tunneling.
Benefits of technology
It effectively improves the performance and yield of semiconductor structures and reduces gate-induced drain leakage current and interband tunneling problems.
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Figure CN114141712B_ABST
Abstract
本公开提供了一种半导体结构的制作方法及半导体结构，涉及半导体技术领域。该半导体结构的制作方法包括：提供基底；于基底上形成硅柱；对硅柱预设处理，形成具有第一段、第二段和第三段的有源柱，第二段包括第一子段和第二子段，第二子段的横截面面积小于第一子段的横截面面积；形成栅氧化层；形成环绕第二段设置的字线结构，字线结构包括材料不同的第一字线结构和第二字线结构。本公开通过在栅氧化层上设置不同材料的第一字线结构和第二字线结构，且第一子段和第二子段上形成字线结构的厚度不同，使得第二段两端的电势不同，有利于控制半导体结构的关断电流，减少栅极诱导漏极泄漏电流和带间隧穿的问题，有效提高半导体结构的性能和良率。
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