Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a semiconductor structure manufacturing method and a semiconductor structure, and relates to the technical field of semiconductor. The semiconductor structure manufacturing method comprises the following steps: providing a substrate; forming a plurality of silicon columns on the substrate, wherein the plurality of silicon columns are arranged in an array; performing a preset treatment on the silicon columns to form active columns, wherein, along a first direction, the active columns comprise a first segment, a second segment and a third segment connected in sequence; forming a gate oxide layer on the sidewalls of the second segment and the third segment; and forming a gate dielectric layer on the gate oxide layer, wherein, along the first direction, the length of the gate dielectric layer is less than the length of the gate oxide layer, and the top surface of the gate dielectric layer is flush with the top surface of the third segment. By forming the gate dielectric layer on the sidewalls of the gate oxide layer, the length of the gate dielectric layer is less than the length of the gate oxide layer, and the top surface of the gate dielectric layer is flush with the top surface of the third segment, which is conducive to controlling the off current of the semiconductor structure, reducing the gate-induced drain leakage current and the interband tunneling problem, and thus effectively improving the performance and yield of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] Dynamic random access memory (DRAM) is a semiconductor memory that allows for high-speed, random data writing and reading, and is widely used in data storage devices. DRAM consists of multiple repeatedly arranged memory cells, each including a transistor and a capacitor. The capacitor is connected to the source and drain of the transistor through capacitor contact areas and structures. As electronic products increasingly strive for lighter, thinner, shorter, and smaller designs, the design of DRAM components is also evolving towards higher integration, higher density, and miniaturization.

[0003] With the development of semiconductor technology, the size of semiconductor devices is getting smaller and smaller. Problems such as gate-induced drain leakage (GIDL) will have a significant adverse impact on the formation of semiconductor structures, reducing the performance and yield of semiconductor structures. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself.

[0006] A first aspect of this disclosure provides a method for fabricating a semiconductor structure, the method comprising:

[0007] Provide a base;

[0008] A plurality of silicon pillars are formed on the substrate, and the plurality of silicon pillars are arranged in an array;

[0009] The silicon pillar is subjected to a preset process to form an active pillar, wherein, along the first direction, the active pillar includes a first segment, a second segment, and a third segment connected in sequence;

[0010] A gate oxide layer is formed on the sidewalls of the second and third segments;

[0011] A gate dielectric layer is formed on the gate oxide layer. Along the first direction, the length of the gate dielectric layer is less than the length of the gate oxide layer, and the top surface of the gate dielectric layer is flush with the top surface of the third segment.

[0012] According to some embodiments of this disclosure, the pre-processing of the silicon pillar to form an active pillar includes:

[0013] The silicon pillar is subjected to an oxidation process, wherein the cross-section of the active pillar is a plane perpendicular to the first direction, and the cross-sectional shape of the active pillar includes a circle.

[0014] According to some embodiments of this disclosure, forming a plurality of silicon pillars on the substrate includes:

[0015] Multiple bit line isolation trenches are formed in the substrate, and the multiple bit line isolation trenches are spaced apart along the second direction. The substrate between adjacent bit line isolation trenches forms a strip.

[0016] Multiple word line isolation trenches are formed within the substrate, and the multiple word line isolation trenches are spaced apart along a third direction to divide the strip into multiple silicon pillars, wherein, along the first direction, the depth of the word line isolation trenches is less than the depth of the bit line isolation trenches.

[0017] According to some embodiments of this disclosure, the method for fabricating the semiconductor structure further includes:

[0018] A first isolation layer is formed within the bit line isolation trench, wherein the top surface of the first isolation layer is flush with the bottom surface of the word line isolation trench;

[0019] An ion implantation process is performed within the word line isolation trench to form a bit line on the bottom surface of the first segment, wherein there are multiple bit lines, and the multiple bit lines are spaced apart along a second direction.

[0020] According to some embodiments of this disclosure, the method for fabricating the semiconductor structure further includes:

[0021] A bit line isolation structure is formed within the substrate, and a plurality of the bit line isolation structures are spaced apart along the second direction.

[0022] According to some embodiments of this disclosure, forming a bit-line isolation structure within the substrate includes:

[0023] A second initial isolation layer is formed on the top surface of the first isolation layer and within the word line isolation groove;

[0024] Along the first direction, a portion of the second initial isolation layer is removed, and the remaining second initial isolation layer forms the second isolation layer;

[0025] In this configuration, along the first direction, the first isolation layer and the second isolation layer located within the bit line isolation trench form a bit line isolation structure, and the top surface of the second isolation layer is flush with the junction of the first segment and the second segment.

[0026] According to some embodiments of this disclosure, forming a gate oxide layer on the sidewalls of the second segment and the third segment includes:

[0027] An initial gate oxide layer is formed on the active pillar using an atomic layer deposition process. The initial gate oxide layer encapsulates the sidewalls of the second segment, as well as the sidewalls and top surface of the third segment.

[0028] A portion of the initial gate oxide layer is removed to expose the top surface of the second isolation layer, and the remaining initial gate oxide layer forms the gate oxide layer.

[0029] According to some embodiments of this disclosure, a filling region is formed between the top surface of the second isolation layer and the sidewall of the gate oxide layer;

[0030] The formation of a gate dielectric layer on the gate oxide layer includes:

[0031] A first initial word line is formed within the filled area;

[0032] A portion of the first initial bit line is removed, and the remaining first initial word line forms a first word line, wherein the top surface of the first word line is flush with the preset position of the second segment, and a first trench is formed between the first word line and the adjacent gate oxide layer.

[0033] Remove the gate oxide layer located on the top surface of the third segment;

[0034] A gate dielectric layer is formed on the sidewall of the first trench.

[0035] According to some embodiments of this disclosure, a second trench is formed between the top surface of the first word line and the sidewall of the gate dielectric layer;

[0036] The method for fabricating the semiconductor structure further includes:

[0037] A second initial character line is formed within the second groove;

[0038] A portion of the second initial character line is removed, and the remaining second initial character line forms the second character line. The top surface of the second character line is flush with the boundary between the second segment and the third segment. The first character line and the second character line form the initial character line structure.

[0039] According to some embodiments of this disclosure, the method for fabricating the semiconductor structure further includes:

[0040] A third initial isolation layer is formed on the initial word line structure;

[0041] A portion of the third initial isolation layer and a portion of the initial word line structure are removed to form a plurality of third trenches on the substrate, the bottom of the third trenches exposing the second isolation layer, the plurality of third trenches being spaced apart along a third direction, and the plurality of third trenches corresponding one-to-one with the plurality of initial word line structures;

[0042] A fourth isolation layer is formed within the third trench;

[0043] The retained initial word line structure forms two word lines, the retained third initial isolation layer forms a third isolation layer, and the third isolation layer and the fourth isolation layer form a word line isolation structure.

[0044] According to some embodiments of this disclosure, a filling region is formed between the top surface of the second isolation layer and the sidewall of the gate oxide layer;

[0045] The formation of a gate dielectric layer on the gate oxide layer includes:

[0046] A sacrificial layer is formed within the filling area, and the top surface of the sacrificial layer is flush with the preset position of the second segment;

[0047] Remove part of the gate oxide layer to expose the top surface of the active pillar;

[0048] A gate dielectric layer is formed, the bottom surface of which is connected to the top surface of the sacrificial layer, and the gate dielectric layer is located outside the gate oxide layer that wraps around a portion of the sidewalls of the second and third segments;

[0049] After removing the sacrificial layer, the sidewall of the gate dielectric layer forms a fourth trench with the sidewall of the gate oxide layer that was originally covered by the sacrificial layer.

[0050] According to some embodiments of this disclosure, the method for fabricating the semiconductor structure further includes:

[0051] A word line isolation structure is formed in the fourth groove, and multiple word line isolation structures are spaced apart along a third direction.

[0052] According to some embodiments of this disclosure, forming a word line isolation structure within the fourth trench includes:

[0053] An initial word line is formed in the fourth groove, and multiple initial word lines are spaced apart along a third direction;

[0054] Along the first direction, a portion of the initial word line is removed, and the remaining initial word line forms an intermediate word line. A fifth trench is formed between the intermediate word line and the sidewall of the gate dielectric layer.

[0055] A fifth initial isolation layer is formed within the fifth trench;

[0056] Along the first direction, a portion of the fifth initial isolation layer and a portion of the intermediate word line are removed to form a plurality of sixth grooves spaced apart along the third direction. The bottom of the sixth groove exposes the top surface of the second isolation layer. The remaining fifth initial isolation layer forms the fifth isolation layer, and the remaining intermediate word line forms two word lines.

[0057] A sixth isolation layer is formed within the sixth trench, and the sixth isolation layer and the fifth isolation layer form the word line isolation structure.

[0058] A second aspect of this disclosure provides a semiconductor structure, the semiconductor structure comprising:

[0059] Base;

[0060] An active column, wherein there are multiple active columns arranged in an array within the substrate, wherein, along a first direction, the active column comprises a first segment, a second segment, and a third segment connected in sequence;

[0061] A gate oxide layer, which wraps around the sidewalls of the second and third segments;

[0062] A gate dielectric layer is disposed outside the gate oxide layer. Along a first direction, the length of the gate dielectric layer is less than the length of the gate oxide layer, and the top surface of the gate dielectric layer is flush with the top surface of the third segment.

[0063] According to some embodiments of this disclosure, the semiconductor structure further includes a plurality of bit lines, which are spaced apart along a second direction, and the bit lines are located at the bottom end of the active pillar.

[0064] According to some embodiments of this disclosure, the semiconductor structure further includes a bit line isolation structure;

[0065] The bit line isolation structure includes a first isolation layer and a second isolation layer. The first isolation layer is located between the substrate and the bottom surface of the bit line, and the second isolation layer is located on the first isolation layer, with the top surface of the second isolation layer flush with the top surface of the first segment.

[0066] According to some embodiments of this disclosure, the semiconductor structure further includes word lines, which include a first word line and a second word line. The first word line is disposed close to the first segment, and the second word line is disposed close to the third segment. The longitudinal section of the first word line is a plane perpendicular to the second direction, and the area of ​​the longitudinal section of the first word line is greater than the area of ​​the longitudinal section of the second word line.

[0067] According to some embodiments of this disclosure, the semiconductor structure further includes a plurality of word line isolation structures, each word line isolation structure including a third isolation layer and a fourth isolation layer, wherein the third isolation layer is located on the top surface of the second word line and the fourth isolation layer is located between adjacent word lines.

[0068] In the semiconductor structure fabrication method and semiconductor structure provided in this disclosure, a gate oxide layer is formed on the sidewalls of the second and third segments of the active pillar, and then a gate dielectric layer is formed on the sidewalls of the gate oxide layer. The length of the gate dielectric layer is less than the length of the gate oxide layer, and the top surface of the gate dielectric layer is flush with the top surface of the third segment. This results in different capacitances at the two ends of the second segment, which in turn leads to different potentials at the two ends of the second segment. This is beneficial for controlling the turn-off current of the semiconductor structure, reducing gate-induced drain leakage current and inter-band tunneling problems, and improving the performance and yield of the semiconductor structure.

[0069] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0070] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0071] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0072] Figure 2 This is a schematic diagram illustrating the formation of a strip in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0073] Figure 3 This is a top view of a method for fabricating a semiconductor structure according to an exemplary embodiment, showing the formation of a silicon pillar.

[0074] Figure 4 This is a top view of a method for fabricating a semiconductor structure according to an exemplary embodiment, showing the formation of an active pillar.

[0075] Figure 5 yes Figure 4 A cross-sectional view of the bit line and the second initial isolation layer formed in the AA direction.

[0076] Figure 6 yes Figure 4 A cross-sectional view of the bit line and the second initial isolation layer formed in the BB direction.

[0077] Figure 7 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment, in which a second isolation layer is formed along the Z direction.

[0078] Figure 8 This is a schematic diagram illustrating a method for fabricating a semiconductor structure in accordance with an exemplary embodiment, in which a bit line isolation structure is formed along the Y direction.

[0079] Figure 9 This is a schematic diagram illustrating the formation of an initial gate oxide layer along the Z-direction in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0080] Figure 10 This is a schematic diagram illustrating the formation of an initial gate oxide layer along the Y direction in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0081] Figure 11 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment, in which a gate oxide layer is formed along the Z-direction.

[0082] Figure 12 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment, in which a gate oxide layer is formed along the Y direction.

[0083] Figure 13 This is a schematic diagram illustrating the formation of a first word line along the Z direction in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0084] Figure 14 This is a schematic diagram illustrating the formation of a first word line along the Y direction in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0085] Figure 15 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment, in which a gate dielectric layer is formed along the Z-direction.

[0086] Figure 16 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment, in which a gate dielectric layer is formed along the Y direction.

[0087] Figure 17 This is a schematic diagram illustrating the formation of an initial word line structure along the Z direction in a semiconductor structure fabrication method according to an exemplary embodiment.

[0088] Figure 18 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment, in which an initial word line structure is formed along the Y direction.

[0089] Figure 19This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment, in which a third initial isolation layer is formed along the Z direction.

[0090] Figure 20 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment, in which a third initial isolation layer is formed along the Y direction.

[0091] Figure 21 This is a schematic diagram illustrating the formation of word lines along the Z-direction in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0092] Figure 22 This is a schematic diagram illustrating a method for fabricating a semiconductor structure in which a word line isolation structure is formed along the Z direction, according to an exemplary embodiment.

[0093] Figure 23 This is a schematic diagram illustrating the formation of a sacrificial layer along the Z-direction in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0094] Figure 24 This is a schematic diagram illustrating the formation of a sacrificial layer along the Y direction in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0095] Figure 25 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment, in which a gate dielectric layer is formed along the Z-direction.

[0096] Figure 26 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment, in which a gate dielectric layer is formed along the Y direction.

[0097] Figure 27 This is a schematic diagram illustrating the formation of a fourth trench along the Z-direction in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0098] Figure 28 This is a schematic diagram illustrating the formation of a fourth trench along the Y direction in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0099] Figure 29 This is a schematic diagram illustrating the formation of an intermediate word line along the Z direction in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0100] Figure 30 This is a schematic diagram illustrating the formation of an intermediate word line along the Y direction in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0101] Figure 31 This is a schematic diagram illustrating the formation of a fifth initial isolation layer along the Z direction in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0102] Figure 32 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment, in which five initial isolation layers are formed along the Y direction.

[0103] Figure 33 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment, in which a fifth isolation layer, a sixth trench, and a word line are formed along the Z direction.

[0104] Figure 34 This is a schematic diagram illustrating the formation of a sixth isolation layer along the Z direction in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0105] Figure label:

[0106] 10. Substrate; 20. Silicon pillar; 30. Bit line isolation trench; 40. Strip; 50. Word line isolation trench; 60. Active pillar; 70. Bit line; 80. Bit line isolation structure; 81. First isolation layer; 82. Second isolation layer; 82a. Second initial isolation layer; 90. Gate oxide layer; 91. Initial gate oxide layer; 100. Gate dielectric layer; 110. Fill region; 120. Word line; 121. First word line; 122. Second word line; 12a. Initial word line structure; 12b. 130. Middle character line; 140. First groove; 150. Character line isolation structure; 160. Second groove; 161. Third isolation layer; 170. Third groove; 180. Fourth isolation layer; 190. Sacrificial layer; 200. Fourth groove; 210. Fifth groove; 220. Fifth isolation layer; 221. Fifth initial isolation layer; 230. Sixth groove; 240. Sixth isolation layer; 601. First segment; 602. Second segment; 603. Third segment. Detailed Implementation

[0107] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0108] Dynamic random access memory (DRAM) is a semiconductor memory that allows for high-speed, random data writing and reading, and is widely used in data storage devices. DRAM consists of multiple repeatedly arranged memory cells, each including a transistor and a capacitor. The capacitor is connected to the source and drain of the transistor through capacitor contact areas and structures. As electronic products increasingly strive for lighter, thinner, shorter, and smaller designs, the design of DRAM components is also evolving towards higher integration, higher density, and miniaturization.

[0109] In related technologies, a transistor can be understood as a current-switching structure made of semiconductor materials. A metal gate is placed between the source and drain of the transistor, and the metal gate is used to control the switching of current between the source and drain. One type of transistor is the GAA transistor (Gate-All-Around), which uses gate-all-around technology. With the development of semiconductor technology, the size of semiconductor devices is becoming smaller and smaller. During the formation of the GAA transistor structure, there is a problem of gate-induced drain leakage (GIDL). This GIDL in GAA transistors reduces the performance and yield of the semiconductor structure.

[0110] To address one of the aforementioned technical problems, a method for fabricating a semiconductor structure is provided in an exemplary embodiment, which is described below in conjunction with... Figures 1-34 The methods for fabricating semiconductor structures are introduced.

[0111] This embodiment does not limit the semiconductor structure. The following description will take dynamic random access memory (DRAM) as an example, but this embodiment is not limited to this. The semiconductor structure in this embodiment can also be other structures, such as GAA transistors or vertical gate ring transistors.

[0112] like Figure 1 As shown, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:

[0113] Step S100: Provide a substrate.

[0114] Step S200: Multiple silicon pillars are formed on the substrate, and the multiple silicon pillars are arranged in an array.

[0115] Step S300: Perform a preset process on the silicon pillar to form an active pillar. Along the first direction, the active pillar includes a first segment, a second segment, and a third segment connected in sequence.

[0116] Step S400: Form a gate oxide layer on the sidewalls of the second and third segments.

[0117] Step S500: A gate dielectric layer is formed on the gate oxide layer. Along the first direction, the length of the gate dielectric layer is less than the length of the gate oxide layer, and the top surface of the gate dielectric layer is flush with the top surface of the third segment.

[0118] In this embodiment, a gate oxide layer is formed on the sidewalls of the second and third segments of the active pillar, and then a gate dielectric layer is formed on the sidewalls of the gate oxide layer. The length of the gate dielectric layer is less than the length of the gate oxide layer, and the top surface of the gate dielectric layer is flush with the top surface of the third segment. This results in different capacitances at the two ends of the second segment, which in turn leads to different potentials at the two ends of the second segment. This helps to control the turn-off current of the semiconductor structure, reduce gate-induced drain leakage current and inter-band tunneling problems, and improve the performance and yield of the semiconductor structure.

[0119] According to an exemplary embodiment, this embodiment is a further explanation of step S100 above.

[0120] like Figure 2 As shown, in step 2100, the substrate 10 serves as a support component for the dynamic random access memory (DRAM), supporting other components disposed thereon. The substrate 10 can be made of a semiconductor material, which can be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbide compounds. In this embodiment, silicon is used as the substrate 10. The use of silicon as the substrate 10 in this embodiment is for the convenience of those skilled in the art in understanding the subsequent formation method and does not constitute a limitation. In practical applications, a suitable substrate material can be selected according to requirements.

[0121] According to an exemplary embodiment, this embodiment is a further explanation of step S200 above.

[0122] like Figure 2 and Figure 3 As shown, in step S200, silicon pillars 20 are formed on the substrate 10. There are multiple silicon pillars 20, which are arranged in an array on the substrate 10, that is, the multiple silicon pillars 20 can be arranged in a multi-row, multi-column manner.

[0123] In this embodiment, refer to Figure 2 As shown in the figure, the description in this embodiment takes the orientation shown in the figure as an example. The third direction Z is the extension direction parallel to the front side of the base 10. The second direction Y and the third direction Z intersect on the same horizontal plane. The second direction Y can be set to intersect the third direction Z at a predetermined angle. For example, the second direction Y and the third direction Z can be set to be perpendicular to each other.

[0124] In some embodiments, the silicon pillar 20 can be formed on the substrate 10 using the following methods:

[0125] First, a plurality of bit line isolation trenches 30 are formed within the substrate 10, and the plurality of bit line isolation trenches 30 are spaced apart along the second direction Y. (Refer to...) Figure 2 As shown in the figure, taking the orientation shown as an example, the second direction Y is an extension direction perpendicular to the front side of the base 10. The base 10 between adjacent isolation trenches 30 forms a strip 40.

[0126] During the process of forming bit line isolation trenches 30 on the substrate 10, a mask layer with a mask pattern can be formed on the substrate 10. The direction from the top surface of the substrate 10 to the bottom surface of the substrate 10 is taken as the extension direction. Along the extension direction, a portion of the substrate 10 is removed according to the mask pattern to form a plurality of bit line isolation trenches 30 spaced apart along the second direction Y.

[0127] Then, refer to Figure 3 As shown, a plurality of word line isolation trenches 50 are formed within the substrate 10. The plurality of word line isolation trenches 50 are spaced apart along a third direction Z. The strip 40 is divided into a plurality of silicon pillars 20 by the word line isolation trenches 50 arranged along the third direction Z. In this embodiment, the depth of the word line isolation trenches 50 along the first direction X is less than the depth of the bit line isolation trenches 30.

[0128] During the process of forming word line isolation trenches 50 on the substrate 10, a mask layer with a mask pattern can be formed on the substrate 10. The direction from the top surface of the substrate 10 to the bottom surface of the substrate 10 is taken as the extension direction. Along the extension direction, a portion of the substrate 10 is removed according to the mask pattern to form a plurality of word line isolation trenches 50 spaced at intervals along the third direction Z.

[0129] In this embodiment, bit line isolation trenches 30 spaced apart along the second direction Y and a plurality of word line isolation trenches 50 spaced apart along the third direction Z are formed on the substrate 10. Silicon pillars 20 are formed on the substrate 10 between adjacent bit line isolation structures 30 and adjacent word line isolation trenches 50. The formation process of these silicon pillars 20 is simple and easy to control and operate. In one example, the second direction Y is perpendicular to the third direction Z, thereby forming an array of silicon pillars 20 on the substrate 10 with a cross-section perpendicular to the first direction X. The cross-sectional shape of the silicon pillars 20 includes square shapes.

[0130] It should be noted that in some embodiments, the silicon pillars 20 may be formed on the top surface of the substrate 10 by a silicon epitaxial growth process, or they may be formed by depositing multiple functional layers on the top surface of the substrate 10 and then etching away some of the functional layers, so that multiple silicon pillars 20 are arranged in multiple rows and columns on the substrate 10.

[0131] According to an exemplary embodiment, this embodiment is a further explanation of step S300 above.

[0132] In step S300, as Figure 4 As shown, the silicon pillar 20 undergoes a pre-processing step to form an active pillar 60. Specifically, after an oxidation process, the silicon pillar 20 is etched or cleaned to form the active pillar 60. The oxidation process passivates the edges of the silicon pillar 20, changing its cross-sectional shape from square to circular. The cross-sectional shape of the active pillar 60 may also include an ellipse.

[0133] It should be noted that, in some embodiments, the oxidation process includes thermal oxidation or steam oxidation. In the oxidation process, the silicon pillar 20 is exposed to the outside world, and an oxide layer, such as silicon oxide, is formed on the surface of the silicon pillar 20 through thermal oxidation or steam oxidation. The oxide layer can then be removed by etching or cleaning processes, thereby passivating the edges of the silicon pillar 20.

[0134] After the oxidation process of the silicon pillar 20 is completed, the circular cross-sectional shape of the silicon pillar 20 is then processed by ion implantation to form an active pillar 60. For example, firstly, the ion implantation energy and the type of implanted dopant ions can be controlled in the ion implantation process to form a first part at the bottom of the silicon pillar 20; then, the ion implantation energy and the type of implanted dopant ions can be controlled in the ion implantation process to form a second part in the middle of the silicon pillar 20; finally, the ion implantation energy and the type of implanted dopant ions can be controlled in the ion implantation process to form a third part at the top of the silicon pillar 20.

[0135] The dopant ions in the first part of the silicon pillar 20 can be of the same type as those in the third part; for example, the dopant ions in both the first and third parts can include N-type ions. The dopant ions in the second part are different from those in the first or third part; for example, the dopant ions in the second part can include P-type ions.

[0136] It should be noted that the first part of the silicon pillar 20 can form the first segment 601 of the active pillar 60, the second part of the silicon pillar 20 can form the second segment 602 of the active pillar 60, and the third part of the silicon pillar 20 can form the third segment 603 of the active pillar 60.

[0137] As an example, the first segment 601 can serve as either the source region or the drain region. The second segment 602 can serve as the channel region. The third segment 603 can serve as either the source region or the drain region. For example, in this embodiment, the first segment 601 serves as the drain region, and the third segment 603 serves as the source region.

[0138] In this embodiment, the edges of the silicon pillar 20 are passivated by an oxidation process, which can improve the adhesion of the subsequent active pillar 60, so that the functional layers formed later, such as dielectric layers, word lines, bit lines, etc., can be well connected with the active pillar 60, thereby improving the performance and yield of the semiconductor structure.

[0139] like Figures 5 to 6 As shown, after the active column 60 is formed, the bit line 70 is formed in the substrate 10.

[0140] In some embodiments, bit line 70 may employ the following methods:

[0141] Reference Figure 6 As shown, a first isolation layer 81 is formed within the bit line isolation trench 30 using atomic layer deposition, physical vapor deposition, or chemical vapor deposition. In some examples, a first initial isolation layer (not shown) may be formed first within the bit line isolation trench 30, with the top surface of the first initial isolation layer flush with the top surface of the silicon pillar 20. Along a first direction, a portion of the first initial isolation layer is removed by etching, so that the top surface of the retained first initial isolation layer is flush with the bottom surface of the word line isolation trench 50. The retained first initial isolation layer forms the first isolation layer 81. The material of the first isolation layer 81 includes, but is not limited to, silicon nitride, silicon dioxide, or silicon oxynitride.

[0142] Then, an ion implantation process is performed in the word line isolation trench 50 to form bit lines 70 on the bottom surface of the first segment 601. There are multiple bit lines 70, and the multiple bit lines 70 are spaced apart along the second direction Y.

[0143] In some embodiments, cobalt (Co) or nickel-platinum alloy (NiPt) can be implanted into the bottom of the word line isolation trench 50 using an ion implantation process. The cobalt (Co) or nickel-platinum alloy (NiPt) reacts with the substrate 10 to form cobalt silicide (CoSi) or platinum-nickel silicide (PtNiSi). Then, after annealing, the cobalt silicide (CoSi) or platinum-nickel silicide (PtNiSi) diffuses to the bottom surface of the active pillar 20 within the substrate 10, thereby forming a bit line 70. The bit line 70 can be connected to the first segment of a plurality of subsequently formed active pillars extending in the third direction Z and lying on the same straight line.

[0144] In this embodiment, the bit line formation method is simple and easy to control and operate. It should be noted that the bit line can be connected to the drain of the subsequently formed active pillar, the transistor's gate is connected to the word line, and the source is connected to the capacitor structure. The voltage signal on the word line is transmitted to the transistor's gate, thereby controlling the transistor's on or off state. Data information stored in the capacitor structure can be read through the bit line, or data information can be written into the capacitor structure for storage through the bit line.

[0145] like Figures 5 to 8 As shown, after the bit lines 70 are formed, in order to achieve insulation between adjacent bit lines 70, bit line isolation structures 80 are formed in the substrate 10. There are multiple bit line isolation structures 80, which are spaced apart along the second direction Y.

[0146] In some embodiments, the bit line isolation structure 80 may employ the following methods:

[0147] Reference Figure 5 and Figure 6 As shown, a second initial isolation layer 82a is formed on the top surface of the first isolation layer 81 and within the word line isolation trench 50 by atomic layer deposition, physical vapor deposition or chemical vapor deposition.

[0148] Reference Figure 7 and Figure 8 As shown, a portion of the second initial isolation layer 82a is removed by etching along the first direction X. The etching endpoint of the second initial isolation layer 82a is located at the boundary between the first segment 201 and the second segment 202. The remaining second initial isolation layer 82a forms the second isolation layer 82, meaning that the top surface of the second isolation layer 82 is flush with the top surface of the first segment 201.

[0149] The material of the second isolation layer 82 may include, but is not limited to, silicon nitride, silicon dioxide, or silicon oxynitride. The materials of the first isolation layer 81 and the second isolation layer 82 may be the same or different. In some embodiments, the second isolation layer 82 and the first isolation layer 81 are made of the same material, reducing the deposition process of the bit line isolation structure 80.

[0150] Reference Figure 8 As shown, along the first direction X, the first isolation layer 81 and the second isolation layer 82 located in the bit line isolation trench 30 form a bit line isolation structure 80.

[0151] According to an exemplary embodiment, this embodiment is a further explanation of step S400 above.

[0152] In step S400, as Figures 9 to 12 As shown, a gate oxide layer 90 is formed on the sidewalls of the second segment 602 and the third segment 603 of the active pillar 60.

[0153] The gate oxide layer 90 can be formed using the following methods:

[0154] After the steps described above for forming the bit-line isolation structure 80, the second segment 602 and the third segment 603 of the active pillar 60 are exposed to the outside. Then, an initial gate oxide layer 91 is formed on the exposed active pillar 60 using an atomic layer deposition process. The initial gate oxide layer 91 covers the sidewalls of the second segment 602, the sidewalls and top surface of the third segment 603 of the active pillar 60, and the top surface of the second isolation layer 82.

[0155] Then, along the first direction X, the initial gate oxide layer 91 on the top surface of the second isolation layer 82 is etched away. The retained initial gate oxide layer 91 forms the gate oxide layer 90.

[0156] The gate oxide layer 90 formed using atomic layer deposition (ALD) can effectively isolate and protect the second segment 602 of the active pillar 60 even with a relatively thin thickness, avoiding the occupation of a large space and facilitating the subsequent filling or formation of other structural layers. The material of the gate oxide layer 90 may include, but is not limited to, silicon dioxide, silicon monoxide, hafnium oxide, or titanium oxide.

[0157] According to an exemplary embodiment, this embodiment is a further explanation of step S500 above.

[0158] In step S500, as Figures 13 to 16 As shown, a gate dielectric layer 100 is formed on the gate oxide layer 90. Along the first direction X, the length of the gate dielectric layer 100 is less than the length of the gate oxide layer 90, and the top surface of the gate dielectric layer 100 is flush with the top surface of the third segment 603.

[0159] The gate dielectric layer 100 can be formed using the following methods:

[0160] Reference Figure 12 As shown, after the gate oxide layer 90 is formed, a filling region 110 is formed between the top surface of the second isolation layer 82 and the sidewall of the gate oxide layer 90.

[0161] First, a first initial word line (not shown in the figure) is deposited in the fill region 110 using atomic layer deposition, physical vapor deposition, or chemical vapor deposition.

[0162] Then, refer to Figure 13 and Figure 14As shown, a portion of the first initial word line is etched away along the first direction X. The etching endpoint of the first initial word line is flush with a predetermined position of the second segment 602. The retained first initial word line forms the first word line 121. In this step, the predetermined position of the second segment 602 can be one-third to two-thirds of its height along the first direction X. In one example, the predetermined position of the second segment is at half its height, that is, the top surface of the first word line 121 is flush with the height of the second segment 602 at half its height along the first direction X. The first word line 121 forms a first trench 130 with its adjacent gate oxide layer 90. The material of the first word line 121 can be, but is not limited to, tungsten or polysilicon.

[0163] Then, the top surface of the gate oxide layer 90 is treated by chemical mechanical polishing to remove the gate oxide layer 90 located on the top surface of the third segment 603 of the active pillar 60.

[0164] Finally, refer to Figure 15 and Figure 16 As shown, a gate dielectric layer 100 is formed on the sidewall of the first trench 130. During the formation of the gate dielectric layer 100, an initial gate dielectric layer (not shown) can be formed within the first trench 130 using atomic layer deposition (ALD). The initial gate dielectric layer covers the sidewall of the gate oxide layer 90, the top surface of the third segment 603, and the top surface of the first word line 121. Then, the initial gate dielectric layer located on the top surface of the third segment 603 and the top surface of the first word line 121 is removed by etching, leaving the initial gate dielectric layer on the sidewall of the first trench 130. The retained initial gate dielectric layer forms the gate dielectric layer 100, with the bottom surface of the gate dielectric layer 100 connected to the first word line 121 and the top surface of the gate dielectric layer 100 flush with the top surface of the third segment 603.

[0165] The gate dielectric layer 100 can be made of, but is not limited to, dielectric materials or high-k materials. The gate oxide layer 90 formed from dielectric or high-k materials is beneficial for improving the capacitance of the subsequently formed capacitor. It should be noted that the dielectric material can be formed from high-k dielectric materials such as silicon nitride, or the dielectric material can be, but is not limited to, tantalum oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate. High-k materials include, but are not limited to, zirconium oxide, hafnium oxide, zirconium titanate, ruthenium oxide, or aluminum oxide.

[0166] Because a first word line 121 is formed in the filling region 110 before the gate dielectric layer 100 is formed, and the first word line 121 blocks part of the second segment 602, the length of the gate dielectric layer 100 in the first direction X is less than the length of the gate oxide layer 90.

[0167] In related technologies, GAA transistors suffer from gate-induced drain current (GIDL). The reason for this GIDL is that the thin gate oxide layer reduces its charge storage capacity. When the GAA transistor is static, electrons generated at the gate or a small number of carriers can pass through the gate oxide layer into the drain, creating a high electric field and causing leakage current. In this embodiment, a gate oxide layer 90 is formed on the sidewalls of the second segment 602 and the third segment 603 of the active pillar 60. Then, a gate dielectric layer 100 is formed on the sidewalls of the gate oxide layer 90. The gate dielectric layer 100 is made of a dielectric material or a high-k material, effectively increasing the capacitance of the subsequent capacitor and preventing electrons generated at the gate or a small number of carriers from passing through the gate oxide layer 90 into the source or drain. This effectively reduces the gate-induced drain current and improves the performance and yield of the semiconductor structure.

[0168] like Figures 15 to 22 As shown, in some embodiments, in order to achieve insulation between adjacent word lines 120 formed subsequently, a word line isolation structure 140 is formed in the substrate 10.

[0169] In some embodiments, the word line isolation structure 140 can be formed using the following methods:

[0170] Reference Figure 15 and Figure 16 As shown, after the gate dielectric layer 100 is formed, a second trench 150 is formed between the top surface of the first word line 121 and the sidewall of the gate dielectric layer 100.

[0171] First, a second initial word line (not shown in the figure) is formed in the second trench 150 using an atomic layer deposition process, a physical vapor deposition process, or a chemical vapor deposition process. The second initial word line fills the second trench 150 completely, and there are multiple second initial word lines, which are spaced apart along the third direction Z.

[0172] Reference Figure 17 and Figure 18 As shown, a portion of the second initial word line is etched away along the first direction X. The etching endpoint of the second initial word line is flush with the boundary between the second segment 602 and the third segment 603. The retained second initial word line forms the second word line 122. The material of the second word line 122 includes, but is not limited to, tungsten or polysilicon.

[0173] Among them, the second character line 122 and the first character line 121 form the initial character line structure 12a.

[0174] Then, refer to Figure 19 and Figure 20As shown, a third initial isolation layer 161 is formed on the top surface of the initial word line structure 12a using atomic layer deposition, physical vapor deposition, or chemical vapor deposition. The top surface of the third initial isolation layer 161 is flush with the top surface of the active pillar 60.

[0175] Reference Figure 21 As shown, along the first direction X, a portion of the third initial isolation layer 161 and a portion of the initial word line structure 12a are etched away, thereby forming a plurality of third trenches 170 on the substrate 10. The bottom of the third trenches 170 exposes the top surface of the second isolation layer 82. The plurality of third trenches 170 are spaced apart along the third direction Z, and each of the plurality of third trenches 170 corresponds one-to-one with a plurality of initial word line structures 12a.

[0176] Finally, refer to Figure 22 As shown, a fourth isolation layer 180 is formed in the third trench 170 by atomic layer deposition, physical vapor deposition or chemical vapor deposition, and the top surface of the fourth isolation layer 180 is flush with the top surface of the active pillar 60.

[0177] After the fourth isolation layer 180 is formed, it divides the initial word line structure 12a within the word line isolation trench 50 into two word lines 120. The retained third initial isolation layer 161 forms the third isolation layer 160, and the third isolation layer 160 and the fourth isolation layer 180 form the word line isolation structure 140. The material of the third isolation layer 160 may include, but is not limited to, silicon nitride, silicon dioxide, or silicon oxynitride. The material of the fourth isolation layer 180 includes nitrides, oxides, high-k dielectric materials, or other suitable insulating materials.

[0178] In related technologies, the gate structure of a duplex function is generally obtained by depositing word line metal layers of different materials at the gate. However, the process required to deposit metal layers of different materials is relatively complex, and an isolation layer is required between metal layers of different materials due to diffusion issues.

[0179] In this embodiment, the word line 120 is formed by two depositions, both using tungsten metal or polysilicon. The thickness of the word line formed by tungsten metal or polysilicon does not affect the potential of the word line 120. Simultaneously, by forming gate oxide layers 90 on the sidewalls of the second segment 602 and the third segment 603, and then forming gate dielectric layers 100 on the gate oxide layers 90 corresponding to the second sub-segment of the second segment 602 and the sidewalls corresponding to the third segment 603, the charge storage capacity at different locations in the second segment 602 is different. The charge storage capacity of the third segment 603 and the portion of the second segment 602 connected to the third segment 603 is greater than the charge storage capacity of the portion of the second segment 602 connected to the first segment 601. This forms a gate structure that conforms to the duplex function, which is not only simple to fabricate but also easier to control and implement.

[0180] Therefore, when the transistor formed by the semiconductor structure of this embodiment, such as the GAA transistor, is used, the capacity of the stored charge in the channel region near the source increases. In order for the transistor to conduct, the turn-on voltage VT applied at that end will increase, which will correspondingly increase the potential of the word line 120 near the third segment 603, thereby forming a potential difference between the corresponding word lines 120 at both ends of the second segment 602.

[0181] Furthermore, as the turn-on voltage VT of the source terminal increases, the source voltage Vs at the source terminal will also increase. The turn-off current (Ioff) and the source voltage Vs are related as shown in the following formula:

[0182] I off ∝e -(Vs*ε / kt)

[0183] Where ε / kt is a constant, approximately 0.0256. Therefore, when the source voltage Vs at the source terminal increases, the turn-off current (Ioff) decreases. Since the turn-off current and the source voltage Vs satisfy an exponential relationship of e, when the thickness of the gate oxide layer at the source terminal of the transistor increases, the turn-off current decreases exponentially. This facilitates the control of the turn-off current of the semiconductor structure, thereby reducing the gate-induced drain leakage current and inter-band tunneling of the semiconductor structure, and improving the performance and yield of the semiconductor structure.

[0184] like Figures 23 to 34 As shown, in some other embodiments, the gate dielectric layer 100 can also be formed using the following methods:

[0185] After the gate oxide layer 90 in the above embodiment is formed, a filling region 110 is formed between the top surface of the second isolation layer 82 and the sidewall of the gate oxide layer 90.

[0186] Reference Figure 23 and Figure 24As shown, a sacrificial layer 190 is formed within the fill region 110 using atomic layer deposition, physical vapor deposition, or chemical vapor deposition. In some embodiments, an initial sacrificial layer (not shown) may be formed first within the fill region 110, completely filling the fill region 110. Then, a portion of the initial sacrificial layer is removed by etching, wherein the etching endpoint of the initial sacrificial layer is flush with a predetermined position of the second segment 602. The retained initial sacrificial layer forms the sacrificial layer 190. The material of the sacrificial layer 190 may include, but is not limited to, nitrides or oxides of nitrogen.

[0187] It should be noted that the preset position of the second segment 602 in this embodiment can be one-third to two-thirds of its height. In one embodiment, the preset position of the second segment 602 is at half its height. That is, the top surface of the sacrificial layer 190 is flush with the height of the second segment 602 at half its height along the first direction X.

[0188] The top surface of the gate oxide layer 90 is treated by chemical mechanical polishing to remove the gate oxide layer 90 located on the top surface of the third segment 603 of the active pillar 60.

[0189] Then, refer to Figure 25 and Figure 26 As shown, a gate dielectric layer 100 is formed on the sidewall of the gate oxide layer 90. During the formation of the gate dielectric layer 100, an initial gate dielectric layer (not shown) can be formed within the first trench 130 using atomic layer deposition (ALD). The initial gate dielectric layer covers the sidewall of the gate oxide layer 90, the top surface of the third segment 603, and the top surface of the sacrificial layer 190. Then, the initial gate dielectric layer located on the top surface of the third segment 603 and the top surface of the first word line 121 is removed by etching, leaving the initial gate dielectric layer on the sidewall of the gate oxide layer 90. The retained initial gate dielectric layer forms gate dielectric layer 100. The bottom surface of gate dielectric layer 100 is connected to sacrificial layer 190, and the top surface of gate dielectric layer 100 is flush with the top surface of third segment 603. This results in different capacitances at both ends of second segment 602, which in turn leads to different potentials at both ends of second segment 602. This helps to control the turn-off current of the semiconductor structure, reduce gate-induced drain leakage current and inter-band tunneling problems, and improve the performance and yield of the semiconductor structure.

[0190] Then, refer to Figure 27 and Figure 28 As shown, the sacrificial layer 190 is removed by etching along the first direction X. A fourth trench 200 is formed between the sidewall of the gate dielectric layer 100 and the sidewall of the gate oxide layer 90 originally covered by the sacrificial layer 190.

[0191] Finally, a word line isolation structure 140 is formed within the fourth trench 200. Multiple word line isolation structures 140 are arranged at intervals along the third direction Z.

[0192] In some embodiments, the word line isolation structure 140 may employ the following methods:

[0193] Reference Figure 29 and Figure 30 As shown, initial word lines (not shown in the figure) are formed in the fourth trench 200 using atomic layer deposition, physical vapor deposition, or chemical vapor deposition. Multiple initial word lines are spaced apart along the third direction Z.

[0194] Then, along the first direction X, a portion of the initial word line is removed by etching, and the remaining initial word line forms the intermediate word line 12b. It should be noted that the etching endpoint of the initial word line is flush with the boundary between the second segment 602 and the third segment 603. A fifth trench 210 is formed between the intermediate word line 12b and the sidewall of the gate dielectric layer 100.

[0195] Then, refer to Figure 31 and Figure 32 As shown, a fifth initial isolation layer 221 is formed within the fifth trench 210 using atomic layer deposition, physical vapor deposition, or chemical vapor deposition. It should be noted that, in one embodiment, the fifth initial isolation layer 221 may be the same as the third initial isolation layer 161 in the above embodiments.

[0196] Reference Figure 33 As shown, along the first direction X, a portion of the second initial isolation layer 221 and a portion of the intermediate word line 12b are etched away to form a plurality of sixth trenches 230 spaced apart along the third direction Z. The bottom of the sixth trenches 230 exposes the top surface of the second isolation layer 82. The retained fifth initial isolation layer 221 forms the fifth isolation layer 220. The retained intermediate word line 12b forms two word lines 120.

[0197] Finally, refer to Figure 34 As shown, a sixth isolation layer 240 is formed within the sixth trench 230 using atomic layer deposition, physical vapor deposition, or chemical vapor deposition. The sixth isolation layer 240 and the fifth isolation layer 220 form a word line isolation structure 140. The material of the sixth isolation layer 240 includes nitrides, oxides, high-k dielectric materials, or other suitable insulating materials.

[0198] In this embodiment, the word line 120 is formed by a single deposition process, which is simple and facilitates control over the formation quality of the word line 120. The material of the word line 120 may include, but is not limited to, tungsten metal or polycrystalline silicon.

[0199] like Figure 20 and Figure 22As shown, an exemplary embodiment of this disclosure provides a semiconductor structure, wherein the semiconductor structure includes: a substrate 10, an active pillar 60, a gate oxide layer 90, and a gate dielectric layer 100.

[0200] The active pillar 60 comprises multiple active pillars 60 arranged in an array within the substrate 10. Along a first direction, each active pillar 60 includes a first segment 601, a second segment 602, and a third segment 603 connected in sequence. The first segment 601 is connected to the substrate 10 and forms the drain of the active pillar 60; the second segment 602 forms the channel region of the active pillar 60; and the third segment 603 forms the source of the active pillar 60.

[0201] The gate oxide layer 90 is disposed on the sidewalls of the second section 602 and the third section 603.

[0202] The gate dielectric layer 100 is disposed outside the gate oxide layer 90. Along the first direction X, the length of the gate dielectric layer 100 is less than the length of the gate oxide layer 90, wherein the top surface of the gate dielectric layer 100 is flush with the top surface of the third segment 603.

[0203] In this embodiment, a gate oxide layer is formed on the sidewalls of the second and third segments of the active pillar, and then a gate dielectric layer is formed on the sidewalls of the gate oxide layer. The length of the gate dielectric layer is less than the length of the gate oxide layer, and the top surface of the gate dielectric layer is flush with the top surface of the third segment. This results in different capacitances at the two ends of the second segment, which in turn leads to different potentials at the two ends of the second segment. This helps to control the turn-off current of the semiconductor structure, reduce gate-induced drain leakage current and inter-band tunneling problems, and improve the performance and yield of the semiconductor structure.

[0204] like Figure 20 and Figure 22 As shown, in some embodiments, the semiconductor structure further includes a plurality of bit lines 70. The plurality of bit lines 70 are spaced apart along a second direction Y. The bit lines 70 are disposed below the active pillars 60 and are used to connect the first segments 601 of the plurality of active pillars 60 disposed along a third direction Z and on the same straight line.

[0205] like Figure 20 As shown, in some embodiments, the semiconductor structure further includes a plurality of bit line isolation structures 80. The plurality of bit line isolation structures 80 are spaced apart along the second direction Y. Each bit line isolation structure 80 includes a first isolation layer 81 and a second isolation layer 82. The first isolation layer 81 is located between adjacent bit lines 70, and the second isolation layer 82 is disposed on the first isolation layer 81, with its top surface flush with the boundary between the second segment 602 and the first segment 601. The bit line isolation structures 80 are used to achieve insulation between adjacent bit lines 70.

[0206] like Figure 20 , Figure 22and Figure 34 As shown, in some embodiments, the semiconductor structure further includes a word line 120. The word line 120 is disposed around the second segment 602 of the active pillar 60, thereby forming a GAA transistor structure. The word line 120 includes a first word line structure and a second word line structure, the bottom surface of the first word line structure being close to the first segment 601, and the top surface of the second word line structure being close to the third segment 603. Taking a plane perpendicular to the second direction Y as a longitudinal section, the area of ​​the longitudinal section of the first word line structure is larger than the area of ​​the longitudinal section of the second word line structure.

[0207] It should be noted that, in one embodiment, the first word line structure and the second word line structure can be formed by one deposition or by two depositions. At the same time, the area of ​​the longitudinal section of the first word line structure is larger than the area of ​​the longitudinal section of the second word line structure, which facilitates the formation of stored charges of different capacities at both ends of the second segment 602.

[0208] like Figure 22 As shown, in some embodiments, the semiconductor structure further includes a plurality of word line isolation structures 140. The word line isolation structures 140 are used to achieve insulation between adjacent word lines 120. The word line isolation structures 140 include a third isolation layer 160 and a fourth isolation layer 180. The third isolation layer 160 is located on the top surface of the second word line structure, and the fourth isolation layer 180 is located between adjacent word lines 120.

[0209] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0210] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0211] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0212] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method for fabricating the semiconductor structure includes: Provide a base; A plurality of silicon pillars are formed on the substrate, and the plurality of silicon pillars are arranged in an array; The silicon pillar is subjected to a preset process to form an active pillar, wherein, along the first direction, the active pillar includes a first segment, a second segment, and a third segment connected in sequence; A gate oxide layer is formed on the sidewalls of the second and third segments; A gate dielectric layer is formed on the gate oxide layer. The gate dielectric layer is located outside the gate oxide layer that wraps around the sidewalls of the second and third segments. The gate dielectric layer is made of a high-K material. Along the first direction, the length of the gate dielectric layer is less than the length of the gate oxide layer. The top surface of the gate dielectric layer is flush with the top surface of the third segment.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The step of pre-processing the silicon pillar to form an active pillar includes: The silicon pillar is subjected to an oxidation process, wherein the cross-section of the active pillar is a plane perpendicular to the first direction, and the cross-sectional shape of the active pillar includes a circle.

3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The formation of a plurality of silicon pillars on the substrate includes: Multiple bit line isolation trenches are formed in the substrate, and the multiple bit line isolation trenches are spaced apart along the second direction. The substrate between adjacent bit line isolation trenches forms a strip. Multiple word line isolation trenches are formed within the substrate, and the multiple word line isolation trenches are spaced apart along a third direction to divide the strip into multiple silicon pillars, wherein, along the first direction, the depth of the word line isolation trenches is less than the depth of the bit line isolation trenches.

4. The method for fabricating a semiconductor structure according to claim 3, characterized in that, The method for fabricating the semiconductor structure further includes: A first isolation layer is formed within the bit line isolation trench, wherein the top surface of the first isolation layer is flush with the bottom surface of the word line isolation trench; An ion implantation process is performed within the word line isolation trench to form a bit line on the bottom surface of the first segment, wherein there are multiple bit lines, and the multiple bit lines are spaced apart along a second direction.

5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, The method for fabricating the semiconductor structure further includes: A bit line isolation structure is formed within the substrate, and a plurality of the bit line isolation structures are spaced apart along the second direction.

6. The method for fabricating a semiconductor structure according to claim 5, characterized in that, The formation of a bit-line isolation structure within the substrate includes: A second initial isolation layer is formed on the top surface of the first isolation layer and within the word line isolation groove; Along the first direction, a portion of the second initial isolation layer is removed, and the remaining second initial isolation layer forms the second isolation layer; In this configuration, along the first direction, the first isolation layer and the second isolation layer located within the bit line isolation trench form a bit line isolation structure, and the top surface of the second isolation layer is flush with the junction of the first segment and the second segment.

7. The method for fabricating a semiconductor structure according to claim 6, characterized in that, The formation of a gate oxide layer on the sidewalls of the second and third segments includes: An initial gate oxide layer is formed on the active pillar using an atomic layer deposition process. The initial gate oxide layer encapsulates the sidewalls of the second segment, as well as the sidewalls and top surface of the third segment. A portion of the initial gate oxide layer is removed to expose the top surface of the second isolation layer, and the remaining initial gate oxide layer forms the gate oxide layer.

8. The method for fabricating a semiconductor structure according to claim 7, characterized in that, A filling region is formed between the top surface of the second isolation layer and the sidewall of the gate oxide layer; The formation of a gate dielectric layer on the gate oxide layer includes: A first initial word line is formed within the filled area; A portion of the first initial bit line is removed, and the remaining first initial word line forms a first word line, wherein the top surface of the first word line is flush with the preset position of the second segment, and a first trench is formed between the first word line and the adjacent gate oxide layer. Remove the gate oxide layer located on the top surface of the third segment; A gate dielectric layer is formed on the sidewall of the first trench.

9. The method for fabricating a semiconductor structure according to claim 8, characterized in that, A second trench is formed between the top surface of the first word line and the sidewall of the gate dielectric layer; The method for fabricating the semiconductor structure further includes: A second initial character line is formed within the second groove; A portion of the second initial character line is removed, and the remaining second initial character line forms the second character line. The top surface of the second character line is flush with the boundary between the second segment and the third segment. The first character line and the second character line form the initial character line structure.

10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, The method for fabricating the semiconductor structure further includes: A third initial isolation layer is formed on the initial word line structure; A portion of the third initial isolation layer and a portion of the initial word line structure are removed to form a plurality of third trenches on the substrate, the bottom of the third trenches exposing the second isolation layer, the plurality of third trenches being spaced apart along a third direction, and the plurality of third trenches corresponding one-to-one with the plurality of initial word line structures; A fourth isolation layer is formed within the third trench; The retained initial word line structure forms two word lines, the retained third initial isolation layer forms a third isolation layer, and the third isolation layer and the fourth isolation layer form a word line isolation structure.

11. The method for fabricating a semiconductor structure according to claim 7, characterized in that, A filling region is formed between the top surface of the second isolation layer and the sidewall of the gate oxide layer; The formation of a gate dielectric layer on the gate oxide layer includes: A sacrificial layer is formed within the filling area, and the top surface of the sacrificial layer is flush with the preset position of the second segment; Remove part of the gate oxide layer to expose the top surface of the active pillar; A gate dielectric layer is formed, wherein the bottom surface of the gate dielectric layer is connected to the top surface of the sacrificial layer; After removing the sacrificial layer, the sidewall of the gate dielectric layer forms a fourth trench with the sidewall of the gate oxide layer that was originally covered by the sacrificial layer.

12. The method for fabricating a semiconductor structure according to claim 11, characterized in that, The method for fabricating the semiconductor structure further includes: A word line isolation structure is formed in the fourth groove, and multiple word line isolation structures are spaced apart along a third direction.

13. The method for fabricating a semiconductor structure according to claim 12, characterized in that, The formation of a word line isolation structure within the fourth trench includes: An initial word line is formed in the fourth groove, and multiple initial word lines are spaced apart along a third direction; Along the first direction, a portion of the initial word line is removed, and the remaining initial word line forms an intermediate word line. A fifth trench is formed between the intermediate word line and the sidewall of the gate dielectric layer. A fifth initial isolation layer is formed within the fifth trench; Along the first direction, a portion of the fifth initial isolation layer and a portion of the intermediate word line are removed to form a plurality of sixth grooves spaced apart along the third direction. The bottom of the sixth groove exposes the top surface of the second isolation layer. The remaining fifth initial isolation layer forms the fifth isolation layer, and the remaining intermediate word line forms two word lines. A sixth isolation layer is formed within the sixth trench, and the sixth isolation layer and the fifth isolation layer form the word line isolation structure.

14. A semiconductor structure, characterized in that, include: Base; An active column, wherein there are multiple active columns arranged in an array within the substrate, wherein, along a first direction, the active column comprises a first segment, a second segment, and a third segment connected in sequence; A gate oxide layer, which wraps around the sidewalls of the second and third segments; A gate dielectric layer is disposed outside the gate oxide layer. The gate dielectric layer is made of a high-K material. Along the first direction, the length of the gate dielectric layer is less than the length of the gate oxide layer. The top surface of the gate dielectric layer is flush with the top surface of the third segment.

15. The semiconductor structure according to claim 14, characterized in that, The semiconductor structure further includes a plurality of bit lines, which are spaced apart along a second direction and are located at the bottom of the active pillar.

16. The semiconductor structure according to claim 15, characterized in that, The semiconductor structure also includes a bit line isolation structure; The bit line isolation structure includes a first isolation layer and a second isolation layer. The first isolation layer is located between the substrate and the bottom surface of the bit line, and the second isolation layer is located on the first isolation layer, with the top surface of the second isolation layer flush with the top surface of the first segment.

17. The semiconductor structure according to claim 14, characterized in that, The semiconductor structure further includes word lines, which include a first word line and a second word line. The first word line is disposed close to the first segment, and the second word line is disposed close to the third segment. The longitudinal section is a plane perpendicular to the second direction, and the area of ​​the longitudinal section of the first word line is greater than the area of ​​the longitudinal section of the second word line.

18. The semiconductor structure according to claim 17, characterized in that, The semiconductor structure further includes multiple word line isolation structures, each word line isolation structure including a third isolation layer and a fourth isolation layer. The third isolation layer is located on the top surface of the second word line, and the fourth isolation layer is located between adjacent word lines.

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