A planarization method for three-dimensional semiconductor structures

Abstract

This application provides a planarization method for a three-dimensional semiconductor structure, comprising: providing a three-dimensional semiconductor structure, including: a substrate, on which at least one step region and at least one core region are defined; at least one memory stack structure, including a step structure located in a first sub-step region and a stack structure located in the core region; forming a fill layer, wherein a portion of the fill layer in the core region is higher than a portion in the step region; coating a protective layer on the fill layer; etching a portion of the protective layer in the core region to expose the top of the portion of the fill layer in the core region; etching the fill layer; and removing the protective layer. The planarization method for a three-dimensional semiconductor structure provided by this application, by coating a protective layer on the fill layer, etching away the portion of the protective layer in the core region, and then etching the portion of the fill layer in the core region, reduces the height difference between the portion of the fill layer in the core region and the portion of the fill layer in the step region, which is beneficial for subsequent planarization processing of the fill layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method for planarizing a three-dimensional semiconductor structure. Background Technology

[0002] Currently, two-dimensional memory has reached its practical expansion limit. To further increase storage capacity and reduce the cost per bit, three-dimensional memory has been proposed. This technology overcomes the limitations of two-dimensional memory by vertically stacking multiple layers of data charge capture. It boasts superior accuracy and higher storage capacity in a smaller space, effectively reducing cost and energy consumption, and fully meeting the needs of numerous electronic devices. The more layers a three-dimensional memory has, the higher its integration level and storage density.

[0003] As the number of stacked layers in 3D memory increases, more stacked layers need to be etched to form step areas (SSarea) and core areas. This requires filling the step areas with more oxide as an isolation layer between word lines (WL) and word lines. As a result, the oxide layer covering the core area becomes too thick, and the height difference between the oxide layer covering the core area and the oxide layer covering the step area becomes too large. This makes it easy to damage the oxide filling the step area when using a polishing process to remove the oxide layer covering the core area. Furthermore, the polishing process can easily affect the performance of the core area. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a planarization method for a three-dimensional semiconductor structure. By coating a protective layer on a filler layer, etching away the portion of the protective layer in the core region, and then etching away the portion of the filler layer in the core region, the height difference between the portion of the filler layer in the core region and the portion of the filler layer in the step region is reduced, which is beneficial for subsequent planarization of the filler layer.

[0005] This application provides a planarization method for a three-dimensional semiconductor structure, the method comprising the following steps: providing a three-dimensional semiconductor structure, wherein the three-dimensional semiconductor structure includes: a substrate, wherein at least one step region and at least one core region are defined on the substrate, the step region and the core region being disposed adjacent to each other; at least one memory stack structure formed on the substrate, the memory stack structure including a step structure and a stacked structure, the step structure being located in a first sub-step region of the step region, and the stacked structure being located in the core region; forming a filling layer on the three-dimensional semiconductor structure, wherein the height of the filling layer in the core region is higher than the height of the filling layer in the step region; coating a protective layer on the filling layer; etching the protective layer in the core region to expose the top of the filling layer in the core region; etching the filling layer; and removing the protective layer in the step region.

[0006] The planarization method for a three-dimensional semiconductor structure provided in this application involves coating a protective layer on a filler layer, etching away the portion of the protective layer in the core region, and etching away the portion of the filler layer in the core region. This significantly reduces the thickness of the filler layer in the core region, thereby reducing the height difference between the portion of the filler layer in the core region and the portion of the filler layer in the step region. This facilitates the subsequent planarization process of the filler layer, ensuring that the portion of the filler layer in the step region is not damaged during the planarization process, and also avoiding damage to the core region that could affect its performance. Attached Figure Description

[0007] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0008] Figure 1 A flowchart of a planarization method for a three-dimensional semiconductor structure provided in an embodiment of this application.

[0009] Figures 2-7 To and Figure 1 A schematic diagram of the cross-sectional structure of the three-dimensional semiconductor structure corresponding to the intermediate step.

[0010] Figure 8 This is a flowchart of a method for manufacturing the three-dimensional semiconductor structure provided in step S101.

[0011] Figures 9-10 To and Figure 8 A schematic diagram of the cross-sectional structure of the three-dimensional semiconductor structure corresponding to the intermediate step.

[0012] Figure 11 for Figure 1 The sub-flowchart of step S105.

[0013] Figures 12-16 To and Figure 11 A schematic diagram of the cross-sectional structure of the three-dimensional semiconductor structure corresponding to the intermediate step.

[0014] Figure 17 This is a schematic cross-sectional view of a three-dimensional semiconductor structure after planarization of the filling layer, provided in an embodiment of this application.

[0015] Figure label:

[0016] Three-dimensional semiconductor structure 100; substrate 10; core region 20; memory stack structure 21; step region 30; first sub-step region 31; second sub-step region 32; step structure 211; stacked structure 212; first insulating layer 213; first sacrificial layer 214; stacked layer 24; second insulating layer 241; second sacrificial layer 242; protective layer 40; filling layer 50. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0018] In the description of this application, the terms "first," "second," etc., are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "upper," "inner," "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0019] It should be noted that the illustrations provided in the embodiments of the present invention are merely schematic representations of the basic concept of the present invention. Although the illustrations only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation, the form, quantity, and proportion of each component in actual implementation can be arbitrarily changed, and the layout of the components may also be more complex. In addition, some well-known parts may not be shown in the figures.

[0020] As the number of stacked layers in 3D memory increases, more stacked layers need to be etched to form step areas (SSarea) and core areas. This requires filling the step areas with more oxide as an isolation layer between word line (WL) areas. As a result, the oxide layer covering the core area becomes too thick. When using polishing processes to remove the oxide layer covering the core area, the oxide filling the step areas is easily damaged. Furthermore, when the oxide layer is too thick, planarization processes such as chemical mechanical polishing can easily affect the performance of the core area.

[0021] This disclosure provides a processing method for three-dimensional semiconductor structures, which you may also refer to. Figures 1 to 7 , Figure 1 A flowchart of a planarization method for a three-dimensional semiconductor structure provided in an embodiment of this application. Figures 2 to 7 To and Figure 1 A schematic diagram of the cross-sectional structure of the three-dimensional semiconductor structure corresponding to the steps in the Chinese method. (Example) Figure 1 As shown, the planarization method for the three-dimensional semiconductor structure includes the following steps:

[0022] S101: Provides, for example Figure 2 The three-dimensional semiconductor structure 100 shown includes: a substrate 10, on which at least one core region 20 and at least one step region 30 are defined, the step region 30 being disposed adjacent to the core region 20, the step region 30 including a first sub-step region 31 and a second sub-step region 32; and at least one memory stack structure 21 disposed on the substrate 10, the memory stack structure 21 including a step structure 211 and a stacked structure 212, the step structure 211 being located in the first sub-step region 31, and the stacked structure 212 being located in the core region 20.

[0023] S102: A filling layer 50 is formed on the three-dimensional semiconductor structure 100, wherein the height of the filling layer 50 in the core region 20 is higher than the height of the filling layer 50 in the step region 30, as shown in the schematic structure. Figure 3 As shown.

[0024] S103: A protective layer 40 is coated on the filler layer 50, as shown in the schematic diagram. Figure 4 As shown.

[0025] S104: Etch the protective layer 40 in the portion of the core region 20 to expose the top of the filler layer 50 in the portion of the core region 20, as shown in the schematic diagram. Figure 5 As shown.

[0026] S105: Etch the filler layer 50, as shown in the schematic structure. Figure 6 As shown.

[0027] S106: Remove the portion of the protective layer 40 in the step area 30, as shown in the schematic diagram. Figure 7 As shown.

[0028] The planarization method for a three-dimensional semiconductor structure 100 provided in this application embodiment involves coating a protective layer 40 onto the filling layer 50; removing a portion of the protective layer 40 in the core region 20; and etching a portion of the filling layer 50 in the core region 20 to significantly reduce the thickness of that portion, thereby reducing the height difference between the portion of the filling layer 50 in the core region 20 and the portion of the filling layer 50 in the step region 30. This facilitates subsequent planarization of the filling layer 50, ensuring that the portion of the filling layer 50 in the step region 30 is not damaged during the planarization process, and also preventing damage to the core region 20 that could affect its performance.

[0029] It should be noted that the protective layer 40 in the accompanying drawings provided in this application embodiment is not drawn according to the shape and size of the protective layer 40 in actual implementation. In order to show the protective layer 40 more intuitively, the protective layer 40 is illustrated in an exaggerated manner in the accompanying drawings. In actual application scenarios, the thickness of the protective layer 40 is generally smaller than the thickness of the filling layer 50.

[0030] In some embodiments, the substrate 10 may be made of a semiconductor material, such as silicon, germanium, etc. The filling layer 50 may be a silicon dioxide layer.

[0031] In some embodiments, the three-dimensional semiconductor structure 100 may be a three-dimensional semiconductor structure centered on a step region or a three-dimensional semiconductor structure centered on a core region. For ease of explanation, the embodiments of this disclosure have been described with a three-dimensional semiconductor structure centered on a step region; however, it is understood that the three-dimensional semiconductor structure of the embodiments of this disclosure may also be configured with a core region as the center.

[0032] In some embodiments, the planarization method for the three-dimensional semiconductor structure 100 according to the embodiments of this disclosure can be applied to any three-dimensional semiconductor memory with a stepped structure, including but not limited to, for example, three-dimensional NAND memory, three-dimensional ferroelectric memory, DRAM, etc.

[0033] In some embodiments, such as the processing of three-dimensional semiconductor structures in 3D NAND flash memory, the height of the step regions increases as the number of stacked layers of the 3D NAND flash memory increases. When depositing oxide on the step regions, oxide is also deposited on the core regions accordingly, resulting in an excessively large thickness difference between the oxide layer covering the core regions and the oxide layer covering the step regions. This excessively thick oxide layer on the core regions is difficult to planarize using conventional polishing processes (e.g., chemical mechanical polishing, CMP). If conventional CMP processes are used for planarization, defects may be introduced into the core region surface, affecting the performance of the core regions.

[0034] In some embodiments, such as Figure 2 As shown, the memory stack structure 21 includes at least one first insulating layer 213 and at least one first sacrificial layer 214, which are alternately stacked. In some embodiments, the number of layers of the at least one first insulating layer 213 may be greater than or equal to the number of layers of the at least one first sacrificial layer 214. For example, the number of layers of the at least one first insulating layer 213 may be one more than the number of layers of the at least one first sacrificial layer 214, but this disclosure is not limited thereto.

[0035] Please refer to the following: Figure 2 , Figures 8 to 11 , Figure 8 This is a flowchart of a manufacturing method for the three-dimensional semiconductor structure 100 provided in step S101. Figure 9 , Figure 10 and Figure 2 To and Figure 8 A schematic diagram of the cross-sectional structure of the three-dimensional semiconductor structure 100 corresponding to the intermediate step. (See attached diagram.) Figure 8 As shown, the method for manufacturing the three-dimensional semiconductor structure 100 provided in step S101 includes the following steps:

[0036] S1011: A substrate 10 is provided, on which at least one core region 20 and at least one step region 30 are defined, the core region 20 and the step region 30 being disposed adjacent to each other, the step region 30 including a first sub-step region 31 and a second sub-step region 32, as shown in the schematic structure. Figure 9 As shown.

[0037] S1012: A stacked layer 24 is formed on the substrate 10. Forming the stacked layer 24 includes forming a second insulating layer 241 on the substrate 10, forming a second sacrificial layer 242 on the side of the second insulating layer 241 facing away from the substrate 10, and repeatedly and alternately forming the second insulating layer 241 and the second sacrificial layer 242 to form at least one layer of the second insulating layer 241 and at least one layer of the second sacrificial layer 242. The number of layers of the at least one second insulating layer 241 is one more than the number of layers of the at least one second sacrificial layer 242. A schematic structure is shown below. Figure 10 As shown.

[0038] S1013: The stacked layer 24 is etched to form at least one memory stacked structure 21. The at least one memory stacked structure 21 is spaced apart. Each memory stacked structure 21 includes at least one first insulating layer 213 and at least one first sacrificial layer 214. Each memory stacked structure 21 includes the step structure 211 and the stacked structure 212. The step structure 211 is located in the first sub-step region 31, and the stacked structure 212 is located in the core region 20. A schematic structure is shown below. Figure 2 As shown.

[0039] In some embodiments, the second insulating layer 241 may be a silicon dioxide layer, and the second sacrificial layer 242 may be a silicon nitride layer. In this embodiment, silicon dioxide may be deposited on the substrate 10 to form the second insulating layer 241 by deposition methods such as chemical vapor deposition or atomic layer deposition, and silicon nitride may be deposited on the side of the second insulating layer 241 opposite to the substrate 10 to form the second sacrificial layer 242.

[0040] Please refer to it again. Figure 3 , Figure 3 This is a schematic diagram of the cross-sectional structure of the three-dimensional semiconductor structure obtained after step S102. Figure 3 As shown, a filling layer 50 is formed on the three-dimensional semiconductor structure 100, the filling layer 50 covering the at least one memory stack structure 21 and the second sub-step region 32, wherein the height of the filling layer 50 in the core region 20 is higher than the height of the filling layer 50 in the step region 30.

[0041] In some embodiments, the filling layer 50 may be a silicon dioxide layer. In this embodiment, silicon dioxide can be deposited on the three-dimensional semiconductor structure 100 to form the filling layer 50 by deposition methods such as chemical vapor deposition and atomic layer deposition. For example, silicon dioxide can be generated by the thermal decomposition of TEOS (tetraethyl orthosilicate) and deposited on the three-dimensional semiconductor structure 100 to form the filling layer 50.

[0042] In some embodiments, an insulating dielectric layer (not shown) is further formed between the filling layer 50 and the memory stack structure 21. The insulating dielectric layer may be a silicon dioxide layer. In this embodiment, silicon dioxide can be deposited on the three-dimensional semiconductor structure 100 to form the insulating dielectric layer by deposition methods such as chemical vapor deposition and atomic layer deposition. For example, silicon dioxide can be deposited on the memory stack structure 21 by HDP (high-density plasma) deposition to form the insulating dielectric layer. The HDP deposition method has better hole-filling capability, making the formed insulating dielectric layer less prone to defects such as voids and pinch-offs. Then, the filling layer 50 is formed on the insulating dielectric layer.

[0043] Please refer to it again. Figure 4 , Figure 4 This is a schematic diagram of the cross-sectional structure of the three-dimensional semiconductor structure obtained after step S103. Figure 4 As shown, a protective layer 40 is coated on the filler layer 50.

[0044] In some embodiments, the thickness of the protective layer 40 in the core region 20 is less than the thickness of the protective layer 40 in the step region 30. In this embodiment, when the protective layer 40 in the core region 20 is etched away to expose the filler layer 50, the remaining protective layer 40 can effectively cover the filler layer 50 in the step region 30. On the one hand, the remaining protective layer 40 can protect the filler layer 50 from etching; on the other hand, the remaining protective layer 40 can provide good support to prevent collapse, defects, etc., in subsequent processes.

[0045] In some embodiments, the thickness of the protective layer 40 in the core region 20 is less than the thickness of the protective layer 40 in the second sub-step region 32. In some embodiments, the thickness of the protective layer 40 in the core region 20 is less than half the thickness of the protective layer 40 in the second sub-step region 32. In some embodiments, the thickness of the protective layer 40 in the core region 20 ranges from 1 / 6 to 1 / 2 of the thickness of the protective layer 40 in the second sub-step region 32. This allows the protective layer 40 to still cover the filler layer 50 in the second sub-step region 32 when the protective layer 40 is subsequently etched away in the core region 20, thereby protecting the filler layer 50 from being etched in the second sub-step region 32. Furthermore, the protective layer 40 in the first sub-step region 31 provides good support for the filler layer 50, preventing collapse or defects in subsequent processes.

[0046] In some embodiments, the protective layer 40 may be a fluid coating material. A fluid coating material can be well coated onto the fill layer 50 to serve as a protective layer for subsequent etching steps. For example, the protective layer 40 may be a photoresist, including positive and negative photoresists. For three-dimensional semiconductor structures with stepped regions, the inner walls of their trenches are not smooth and contain many stepped structures. Due to the complex stepped structure of the stepped regions themselves, forming a hard material on their sidewalls and top as an etching barrier layer using conventional deposition processes is cumbersome. The hard barrier layer is difficult to remove completely and may lead to defects in the semiconductor structure, especially as the number of memory stacked layers increases and the stepped regions become thicker, making this adverse effect particularly pronounced. According to embodiments of this disclosure, a fluid coating material can uniformly and sufficiently cover the fill layer 50 through a suitable coating process, avoiding insufficient coverage that could affect the accuracy of subsequent etching. In some embodiments, the material of the protective layer 40 may be a low-viscosity photoresist, for example, a photoresist with a viscosity greater than 0 and less than 2.0 cP. Low-viscosity photoresists have good fluidity and are easier to coat and remove.

[0047] In some embodiments, photoresist can be coated onto the filler layer 50 by spin coating. Since the coated photoresist is a low-viscosity photoresist with good fluidity, and the portion of the filler layer 50 in the step region 30 is lower than the portion of the filler layer 50 in the core region 20, the filler layer 50 is uneven and has grooves. During spin coating, the highly fluid photoresist can flow into the grooves under the action of gravity, so that the photoresist can not only cover the portion of the filler layer 50 in the core region 20, but also uniformly and fully cover the portion of the filler layer 50 in the step region 30. This ensures that the portion of the filler layer 50 in the second sub-step region 32 is completely covered by the photoresist, so that the portion of the filler layer 50 in the second sub-step region 32 can be well protected from etching during subsequent etching of the filler layer 50. Furthermore, the more fluid photoresist mainly flows into the groove, with less photoresist covering the portion of the filler layer 50 in the core region 20. This results in the photoresist thickness in the core region 20 being less than the photoresist thickness in the second sub-step region 32. Consequently, when the photoresist is subsequently etched to remove the portion in the core region 20, the portion in the step region 30 can still cover the portion of the filler layer 50 in the second sub-step region 32, thus protecting the portion of the filler layer 50 in the second sub-step region 32 from being etched. Moreover, when etching to remove the portion of the photoresist in the core region 20, the reduced photoresist coverage in the core region 20 shortens the etching time and reduces etching costs. Additionally, it makes the top of the filler layer 50 in the core region 20 easier to expose.

[0048] In some embodiments, after coating the photoresist, the method further includes curing the photoresist. Specifically, the photoresist is cured by heating it to remove the solvent. The cured photoresist can stably and reliably cover the filler layer 50, so that when the filler layer 50 is subsequently etched, the photoresist is not easily detached from the portion of the second sub-step region 32, thereby stably covering the portion of the filler layer 50 in the second sub-step region 32 and preventing it from being etched.

[0049] Please refer to it again. Figure 5 , Figure 5 This is a schematic diagram of the cross-sectional structure of the three-dimensional semiconductor structure obtained after step S104. Figure 5 As shown, the protective layer 40 is removed from the portion of the core region 20 to expose the top of the filling layer 50 in the portion of the core region 20.

[0050] In some embodiments, the protective layer 40 in the core region 20 can be removed by etching using a first dry etching process. Specifically, the three-dimensional semiconductor structure 100 is placed in the reaction chamber of an ICP (inductively coupled plasma) device, and a first gas, such as at least one of C2F6 and CHF3, is introduced into the reaction chamber. The first gas etches the protective layer 40, and the etching time is controlled so that the portion of the protective layer 40 in the core region 20 is etched away. The top surface of the etched protective layer 40 is flush with the top surface of the portion of the filler layer 50 in the core region 20. The etching rate of the first gas on the filler layer 50 is much lower than the etching rate on the protective layer 40, and the etching of the filler layer 50 by the first gas can even be ignored.

[0051] Please refer to it again. Figure 6 , Figure 6 This is a schematic diagram of the cross-sectional structure of the three-dimensional semiconductor structure obtained after step S105. (See diagram below.) Figure 6 As shown, etching the filler layer 50 includes etching the portion of the filler layer 50 in the core region 20 and the portion of the filler layer 50 in the first sub-step region 31.

[0052] In some embodiments, the filling layer 50 can be etched using a second dry etching process. Specifically, the three-dimensional semiconductor structure 100 is placed in the reaction chamber of an ICP (inductively coupled plasma) device, and a second gas, such as C2F8, is introduced into the reaction chamber. The second gas etches the portion of the filling layer 50 in the core region 20 and the portion of the filling layer 50 in the first sub-step region 31. The etching rate of the second gas on the protective layer 40 is much lower than the etching rate on the filling layer 50, and the etching of the protective layer 40 by the second gas can even be ignored.

[0053] In other embodiments, the filling layer 50 can also be etched using a first wet etching process. Specifically, a wet etching machine is used for etching. The wet etching machine includes an etching tank containing a hydrofluoric acid solution. The three-dimensional semiconductor structure 100 is completely immersed in the hydrofluoric acid solution, allowing the hydrofluoric acid solution to selectively etch the filling layer 50. For example, the hydrofluoric acid solution can be prepared by mixing hydrofluoric acid (40 wt%) with deionized water at a volume ratio of 1:90 to 1:110. During etching, the temperature of the hydrofluoric acid solution is 22 to 24°C.

[0054] According to an embodiment of this application, by etching away a portion of the protective layer 40 in the core region 20, the top of the filling layer 50 in that portion of the core region 20 is completely exposed. Then, the filling layer 50 is etched again, reducing the height difference between the portion of the filling layer 50 in the core region 20 and the portion of the filling layer 50 in the second sub-step region 32. This allows for effective planarization of the three-dimensional semiconductor structure 100. However, in the prior art, photolithography patterning is used to open the core region. Due to exposure alignment misalignment, in order to prevent the filling layer in the step region from being etched, the exposed area is smaller than the core region area. This results in the edges of the filling layer in the core region not being etched away, forming residual protrusions that are difficult to remove in subsequent planarization processes. The method provided in this application embodiment can completely open the core region 20, so that when the filling layer 50 is etched, the entire top surface of the filling layer 50 in the core region 20 is etched, thereby avoiding the formation of protrusions, which is beneficial to the subsequent planarization process and improves the production yield of the three-dimensional semiconductor structure 100. Since the production yield is improved, more qualified three-dimensional semiconductor structures 100 can be produced in the same time, thus improving production efficiency.

[0055] Please refer to the following: Figures 11 to 15 , Figure 11 for Figure 1 The sub-flowchart of step S105, Figures 12 to 15 To and Figure 11 A schematic diagram of the cross-sectional structure of the three-dimensional semiconductor structure 100 corresponding to the intermediate step. (See attached diagram.) Figure 11 As shown, in some embodiments, etching the fill layer 50 includes the following steps:

[0056] S1051: Etch the filler layer 50 at a first rate, as shown in the schematic structure. Figure 12 As shown.

[0057] S1052: Etch the protective layer 40 at a second rate in a portion of the step region 30, wherein the first rate is greater than or equal to the second rate, as shown in the schematic structure. Figure 13 As shown.

[0058] S1053: Alternately etch the filler layer 50 and the protective layer 40 in the step region 30. That is, alternately perform steps S1051 and S1052, as shown in the schematic structure. Figures 14 to 16 As shown.

[0059] In some embodiments, etching of the filler layer 50 is stopped when the thickness of the filler layer 50 in the core region 20 is less than or equal to a first preset thickness, wherein the first preset thickness can be set according to actual needs. Etching is stopped when the filler layer 50 in the core region 20 is completely etched away.

[0060] In some embodiments, steps S1051 and S1052 are performed simultaneously. In some embodiments, the first rate is greater than the second rate, such that, under the same etching time, the thickness of the portion of the fill layer 50 etched away is greater than the thickness of the portion of the protective layer 40 etched away. This ensures that when the fill layer 50 is etched until its thickness in the core region 20 is less than or equal to the first preset thickness, the protective layer 40 in the second sub-step region 32 still covers the portion of the fill layer 50 in the second sub-step region 32, thus ensuring that the portion of the fill layer 50 in the second sub-step region 32 is always covered by the protective layer 40 and not etched. Furthermore, because the first rate is greater than the second rate, the portion of the etched protective layer 40 in the first sub-step region 31 is higher than the portion of the etched fill layer 50 in the core region 20.

[0061] In some other embodiments, the first rate is equal to the second rate, that is, the etching rate of the protective layer 40 is equal to the etching rate of the filler layer 50, such that, under the same etching time, the thickness of the portion of the filler layer 50 etched away is equal to the thickness of the portion of the protective layer 40 etched away. When the portion of the protective layer 40 in the second sub-step region 32 is completely etched away, and the thickness of the filler layer 50 in the core region 20 is greater than the first preset thickness, steps S103 to S105 are repeated until, when etching of the filler layer 50 stops, the thickness of the protective layer 40 in the second sub-step region 32 is greater than zero, thereby ensuring that the portion of the filler layer 50 in the second sub-step region is always covered by the protective layer 40 and is not etched. Since the first rate is equal to the second rate, the portion of the etched protective layer 40 in the first sub-step region 31 is flush with the portion of the etched filler layer 50 in the core region 20.

[0062] In some embodiments, the filling layer 50 is etched in the core region 20 and portions of the first sub-step region 31 using the second dry etching process, the protective layer 40 is etched in the step region 30 using the first dry etching process, and the etching of the filling layer 50 in the core region 20 and portions of the first sub-step region 31 using the second dry etching process is performed simultaneously with the etching of the protective layer 40 in the step region 30 using the first dry etching process. Specifically, the three-dimensional semiconductor structure 100 is placed in the reaction chamber of an ICP (inductively coupled plasma) device, and the first gas and the second gas are introduced into the reaction chamber. The first gas etches the protective layer 40, and the second gas etches the filling layer 50 in the core region 20 and portions of the first sub-step region 31. The second gas etches the filling layer 50 at a first rate, and the first gas etches the protective layer 40 at a second rate.

[0063] Obviously, in other embodiments, steps S1051 and S1052 can be performed separately. By controlling the etching time and rate of the protective layer 40 and the etching time and rate of the filling layer 50, the thickness of the protective layer 40 in the second sub-step region 32 is greater than zero during steps S1051 to S1053. Thus, when the filling layer 50 is etched, the portion of the filling layer 50 in the second sub-step region 32 is always covered by the protective layer 40 and is not etched.

[0064] In other embodiments, the filling layer 50 may also be etched in the core region 20 and in the first sub-step region 31 by the aforementioned first wet etching process.

[0065] According to an embodiment of this application, by repeatedly and alternately etching the portion of the filling layer 50 in the core region 20 and the portion in the first sub-step region 31, as well as the portion of the protective layer 40 in the step region 30, excessive etching of the filling layer 50 in the core region 20 during the etching process can be avoided. This prevents the protective layer 40 from becoming too thick protruding from the filling layer 50, collapsing and falling onto the top of the filling layer 50 in the core region 20, thus hindering the etching process of the filling layer 50 in the core region 20. Furthermore, because the protective layer 40 is formed by coating with a highly fluid material, its thickness in the second sub-step region 32 is very thick. Therefore, even if the protective layer 40 is etched multiple times during the repeated etching of the filling layer 50 and the protective layer 40, it still covers the portion of the filling layer 50 in the second sub-step region 32, preventing the filling layer 50 in the second sub-step region 32 from being etched.

[0066] Please refer to it again. Figure 7 , Figure 7 This is a schematic diagram of the cross-sectional structure of the three-dimensional semiconductor structure obtained after step S106. (See diagram below.) Figure 7 As shown, the protective layer 40 is removed from a portion of the step area 30.

[0067] In some embodiments, a first dry etching process can be used to etch and remove a portion of the protective layer 40 in the step region 30. For the specific process, please refer to the aforementioned process for removing a portion of the protective layer 40 in the core region 20, which will not be repeated here.

[0068] In other embodiments, the protective layer 40 in the step region 30 can also be removed by a second wet etching process. Specifically, a wet etching machine is used, which includes an etching tank containing a mixed solution of concentrated sulfuric acid and hydrogen peroxide. The three-dimensional semiconductor structure 100 is completely immersed in the mixed solution, which selectively etches away the protective layer 40 in the step region 30. The mixed solution can be prepared by mixing 98 wt% sulfuric acid and 30 wt% hydrogen peroxide in a volume ratio of 3:1 to 5:1. Preferably, the volume ratio is 5:1, and the temperature of the mixed solution during etching is in the range of 100-150°C.

[0069] Please see Figure 17 , Figure 17 This is a schematic cross-sectional view of the three-dimensional semiconductor structure after planarization of the filling layer 50, as provided in an embodiment of this application. Figure 17As shown, in some embodiments, the planarization method of the three-dimensional semiconductor structure 100 further includes: planarizing the filling layer 50 and the memory stack structure 21 so that the top of the filling layer 50 is flush with the top of the memory stack structure 21.

[0070] In some embodiments, the filling layer 50 and the memory stack structure 21 are planarized, such that the top of the filling layer 50 is flush with the top first sacrificial layer of the memory stack structure 21, as shown below. Figure 17 As shown. The top first sacrificial layer is the first sacrificial layer 212 that is furthest from the substrate 10 among the at least one first sacrificial layer 212. By removing part of the fill layer 50 and the top first insulating layer of the memory stack structure 21, the top first insulating layer being the first insulating layer 211 that is furthest from the substrate 10 among the at least one first insulating layer 211, the fill layer 50 is flush with the top first sacrificial layer of the memory stack structure 21.

[0071] In some embodiments, the filler layer 50 and the memory stack structure 21 can be planarized by chemical mechanical polishing (CMP). Specifically, a CMP machine is used for polishing. The CMP machine includes a polishing table, a polishing pad, a polishing head, and a liquid feeder. The polishing pad is fixedly mounted on the polishing table. The polishing head is located above the polishing pad and is used to fix the three-dimensional semiconductor structure 100. The polishing head and the polishing pad can move relative to each other. The liquid feeder is located above the polishing pad and is used to hold polishing fluid. The liquid feeder includes a supply port, through which the polishing fluid in the liquid feeder is supplied to the polishing pad. The three-dimensional semiconductor structure 100 is fixed using the polishing head, and the side of the filler layer 50 away from the substrate 10 is brought into contact with the polishing pad. Polishing slurry in the feeder is supplied to the polishing pad through the feed port. Simultaneously, the polishing stage and the polishing head are controlled to move relative to each other, for example, by rotating relative to each other, causing the polishing pad to rotate relative to the three-dimensional semiconductor structure 100. This allows the polishing pad to polish the filler layer 50 and the side of the memory stack structure 21 away from the substrate 10. The polishing slurry selectively removes a portion of the filler layer 50 and the top first insulating layer of the memory stack structure 21. The polishing process stops at the top first sacrificial layer of the memory stack structure 21.

[0072] According to an embodiment of this application, by etching the portion of the filling layer 50 in the core region 20, the height difference between the portion of the filling layer 50 in the core region 20 and the portion of the filling layer 50 in the step region 30 is greatly reduced. This makes the planarization process easier to perform when the filling layer 50 is planarized, and it does not damage the portion of the filling layer 50 in the step region 30. It also avoids damage to the core region 20 and affecting its performance.

[0073] In some embodiments, the abrasive pad may be made of polyurethane, nonwoven fabric, or porous resin.

[0074] In some embodiments, the polishing slurry may include silica, an organic acid or an inorganic acid, and water, wherein the organic acid may include at least one of acetic acid, propionic acid, butyric acid, citric acid, tartaric acid, oxalic acid, maleic acid, and phthalic acid, and the inorganic acid may include at least one of hydrochloric acid, nitric acid, and phosphoric acid; or the first polishing slurry may include cerium oxide, a water-soluble organic polymer, and water, wherein the water-soluble organic polymer has a carboxylic acid group or a carboxylate group.

[0075] In summary, the planarization method for the three-dimensional semiconductor structure 100 provided in this application involves coating a protective layer 40 on the filling layer 50; removing the portion of the protective layer 40 in the core region 20; and etching the portion of the filling layer 50 in the core region 20 to significantly reduce the height difference between the portion of the filling layer 50 in the core region 20 and the portion of the filling layer 50 in the second sub-step region 32. This facilitates the subsequent planarization process of the filling layer 50, ensuring that the portion of the filling layer 50 in the step region 30 is not damaged during the planarization process, and also avoiding damage to the core region 20 that could affect its performance.

[0076] It should be noted that, for the sake of simplicity, the aforementioned method embodiments are described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps may be performed in other orders or simultaneously.

[0077] The above are the implementation methods of the embodiments of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the embodiments of this application, and these improvements and modifications are also considered to be within the protection scope of this application.

Claims

1. A planarization method for a three-dimensional semiconductor structure, characterized in that, The method includes the following steps: A three-dimensional semiconductor structure is provided, wherein the three-dimensional semiconductor structure includes: a substrate, wherein at least one step region and at least one core region are defined on the substrate, the step region and the core region being disposed adjacent to each other; and at least one memory stack structure formed on the substrate, the memory stack structure including a step structure and a stacked structure, wherein the step structure is located in a first sub-step region of the step region, and the stacked structure is located in the core region. A filling layer is formed on the three-dimensional semiconductor structure, wherein the height of the filling layer in the core region is higher than the height of the filling layer in the step region; A protective layer is applied to the filler layer; The protective layer is etched in the core region to expose the top of the filler layer in the core region. Etching the filling layer; and Remove a portion of the protective layer in the step area; The etching of the fill layer includes: First, etch the filling layer at a first rate; Then the protective layer is etched at a second rate in the step region, wherein the first rate is greater than the second rate; The filler layer is etched alternately at a first rate and the protective layer is etched at a second rate in portions of the step region.

2. The method according to claim 1, characterized in that, The thickness of the protective layer in the core area is less than the thickness of the protective layer in the second sub-step area of ​​the step area.

3. The method according to claim 1, characterized in that, The etching of the fill layer includes: When the thickness of the filler layer in the core region is less than or equal to a first preset thickness, etching of the filler layer is stopped.

4. The method according to claim 1, characterized in that, The method further includes: The filling layer and the memory stack structure are planarized so that the top of the filling layer is flush with the top of the memory stack structure.

5. The method according to claim 4, characterized in that, The planarization process for the filling layer and the memory stack structure includes: The filler layer was planarized using chemical mechanical polishing.

6. The method according to claim 1, characterized in that, The etching of the protective layer in the core region to expose the top of the filler layer in the core region includes: The protective layer in the core region is removed by etching using a first dry etching process to expose the top of the filling layer in the core region.

7. The method according to claim 1, characterized in that, The protective layer is made of a low-viscosity photoresist.

8. The method according to claim 1, characterized in that, The etching of the fill layer includes: The filling layer is etched using a second dry etching process.

9. The method according to claim 1, characterized in that, The filling layer is a silicon dioxide layer.

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