A three-valued logic transistor device structure and a preparation method thereof

Abstract

The present invention provides a three - valued logic transistor device structure and a preparation method thereof. The structure includes: a substrate to provide support; a heavily doped tunneling region; a buried oxide layer located above the heavily doped tunneling region; a top silicon film located on the buried oxide layer; source regions and drain regions on both sides of the heavily doped tunneling region; a gate oxide layer and a gate located on the source regions, drain regions, and the top silicon film. The present invention uses a silicon - on - insulator structure, that is, a buried oxide layer is added above the heavily doped tunneling region. While realizing the three - valued logic of CMOS devices, it can effectively avoid the influence of high - concentration doping on the threshold voltage (VT) above the channel.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a three-valued logic transistor device structure and a preparation method thereof. Background Art

[0002] The realization of ternary CMOS devices can be based on multi-threshold voltage schemes and single threshold voltage schemes. The commonly used method at present is to use the band-to-band tunneling effect (BTBT) of quantum mechanics to obtain multi-threshold or single threshold voltage, thereby realizing three-valued logic. The principle of quantum tunneling effect is that when negative high voltage and positive voltage are applied to the gate and source respectively and the substrate is grounded, a high longitudinal electric field is established at the intersection of the gate and source, and the PN junction of the source junction and the substrate is biased under a high reverse electric field. Under the joint action of the transverse and longitudinal electric fields, the energy band on the surface of the source junction bends upward, and deep depletion occurs. When the energy band bending is greater than the bandgap width, the electrons in the valence band can tunnel through the bandgap barrier to the conduction band to form a current, that is, the band-to-band tunneling effect (BTBT) occurs. The electrons generated by BTBT will be collected by the source, and most of the holes will be collected by the substrate across the junction region under the acceleration of the transverse electric field of the PN junction to form a band-to-band tunneling current (IBTBT). IBTBT is mainly controlled by high-concentration doping inside the body, while low-concentration doping near the surface determines the threshold voltage (VT).

[0003] A three-valued logic transistor device structure in the prior art is as follows: Figure 1 As shown, its structure includes a gate 1, a gate oxide layer 2, a source region 3, a drain region 4, a heavily doped tunneling region 7 disposed between the source region 3 and the drain region 4, and a substrate 8. This T-CMOS (Ternary CMOS, hereinafter referred to as T-CMOS) structure generates an inter-band tunneling current (IBTBT) through high-concentration ion implantation, generates a third voltage state between a high threshold voltage and a low threshold voltage, and thus realizes a three-valued logic.

[0004] However, the BTBT caused by high-concentration doping will lead to an increase in leakage current and affect the channel doping concentration, resulting in fluctuations in the threshold voltage (VT), which will reduce the on-current, slow down the voltage boost, and slow down the speed of the T-CMOS device, thus affecting the overall performance of the chip. On the other hand, since T-CMOS is a local dielectric isolation, high-concentration doping can easily cause a latch effect in the device, and the isolation area between devices occupies too large a chip area, which will also lead to an increase in parasitic capacitance and is not conducive to device integration. Summary of the invention

[0005] In view of this, the present invention provides a three-valued logic transistor device structure and a preparation method thereof. Based on the Silicon on Insulator (SOI) structure, combined with the T-CMOS technology, a novel transistor with three-valued logic (SOI T-CMOS) is obtained. Based on the T-CMOS technology, the existing commercial SOI is utilized, which is beneficial to enhancing the channel controllability compared with the same type of devices, has better performance in maintaining the stability of the threshold voltage (VT), and is also beneficial to eliminating the latch-up effect and reducing the influence of parasitic capacitance.

[0006] To solve the above technical problems, the technical solution adopted by the present invention is: a three-valued logic transistor device structure, which includes:

[0007] A substrate to provide support;

[0008] A heavily doped tunneling region;

[0009] A buried oxide layer located above the heavily doped tunneling region;

[0010] A top silicon film located on the buried oxide layer;

[0011] Source and drain regions on both sides of the heavily doped tunneling region;

[0012] A gate oxide layer and a gate located on the source region, the drain region and the top silicon film.

[0013] Preferably, the depths of the source region and the drain region extending towards the bottom of the substrate are deeper than the depth of the buried oxide layer to form a tunneling structure.

[0014] Preferably, the thickness of the buried oxide layer is greater than the thickness of the gate oxide layer to achieve isolation between the heavily doped tunneling region and the gate.

[0015] A preparation method of a three-valued logic transistor device structure, including:

[0016] Select an SOI wafer;

[0017] Etch the SOI wafer;

[0018] Perform heavy doping to form a heavily doped tunneling region, and selectively epitaxially grow silicon to obtain the source region and the drain region;

[0019] Deposit a gate oxide layer and fabricate a gate on the gate oxide layer.

[0020] Preferably, the SOI wafer includes a substrate, a buried oxide layer and a top silicon film.

[0021] Preferably, during the process of etching the SOI wafer, the etching depth is deeper than the top silicon film and the buried oxide layer.

[0022] Preferably, ensure that the thickness of the heavily doped tunneling region is greater than that of the gate oxide layer.

[0023] Preferably, the doping concentrations of the source region and the drain region need to be high enough to form a tunneling structure.

[0024] The advantages and positive effects of the present invention are as follows: The present invention uses a semiconductor-on-insulator structure, that is, a buried oxide layer is added above the heavily doped tunneling region. While realizing the ternary logic of CMOS devices, it can effectively avoid the influence of high-concentration doping on the threshold voltage (VT) above the channel. Description of the Drawings

[0025] Figure 1 is a schematic diagram of the structure of a ternary logic transistor device in the prior art;

[0026] Figure 2 is a schematic diagram of the structure of a ternary logic transistor device in the present invention;

[0027] Figure 3 is a schematic diagram of the structure of the SOI wafer selected in the present invention;

[0028] Figure 4 is a schematic diagram of the structure of the SOI wafer after etching in the present invention;

[0029] Figure 5 is a schematic diagram of the structure after forming the heavily doped tunneling region and the source region and the drain region in the present invention. Detailed Embodiments

[0030] To better understand the present invention, the present invention will be further described below in conjunction with specific embodiments and drawings.

[0031] As Figure 2 shown, the present invention provides a ternary logic transistor device structure, which includes:

[0032] a substrate 8;

[0033] a heavily doped tunneling region 7;

[0034] a buried oxide layer 6 located above the heavily doped tunneling region 7;

[0035] a top silicon film 5 located on the buried oxide layer 6;

[0036] source regions 3 and drain regions 4 epitaxially grown on both sides of the heavily doped tunneling region 7;

[0037] a gate oxide layer 2 and a gate 1 located on the source regions 3, the drain regions 4 and the top silicon film 5.

[0038] Among them, the substrate 8 plays a supporting role for the entire structure. It can be a conventional semiconductor substrate, such as a silicon substrate, or a sapphire substrate, etc.; the source region 3, the drain region 4, and the heavily doped tunneling region 7 provide conditions for manufacturing the T-CMOS device. The high-concentration source-drain doping forms a tunneling structure to obtain a ternary logic system; the buried oxide layer 6 is an effective isolation layer (Channel-on-Box), which can avoid the influence of the heavy doping below on the threshold voltage (VT). The buried oxide layer 6 can be a silicon dioxide, silicon oxide, or silicon nitride composite dielectric layer; the gate oxide layer 2 and the top silicon film 5 can provide physical support for the gate 1, serve as a mask for diffusion and ion implantation, and prevent the loss of doped impurities. The gate oxide layer 2 can be SiO2 or a high-k dielectric; the gate 1 controls the on-resistance and carries information. The gate 1 can be polysilicon or a metal gate.

[0039] The present invention uses a silicon-on-insulator structure, that is, a buried oxide layer 6 is added above the heavily doped tunneling region 7. While realizing the ternary logic of the CMOS device, it can effectively avoid the influence of high-concentration doping on the threshold voltage (VT) above the channel.

[0040] Specifically, the addition of the buried oxide layer 6 reduces the parasitic capacitance of the source region 3 and the drain region 4, reduces the leakage current. Under the same external voltage, a larger interband tunneling current (IBTBT) can be obtained and the power consumption can be reduced, and the device delay is also reduced. Since the SOI T-CMOS is a fully dielectric isolation structure, it can completely eliminate the latch-up effect in traditional T-CMOS devices and improve the radiation resistance characteristics of the device. Therefore, this structure has a better isolation effect, can reduce the influence of the tunneling structure on the threshold voltage (VT) and eliminate the latch-up effect, and improve the overall performance of the device.

[0041] Furthermore, the depths of the source region 3 and the drain region 4 extending towards the bottom of the substrate are deeper than the depths of the top silicon film 5 and the buried oxide layer 6 to form a tunneling structure; the thickness of the buried oxide layer 6 is greater than the thickness of the gate oxide layer 2 to achieve the isolation between the heavily doped tunneling region 7 and the gate 1.

[0042] The second aspect of the present invention provides a method for manufacturing a ternary logic transistor device structure, and the method includes:

[0043] Select an SOI wafer, and the SOI wafer includes a substrate 8, a buried oxide layer 6, and a top silicon film 5, specifically as Figure 3 shown;

[0044] Etch the SOI wafer, and the etching depth is deeper than the top silicon film 5 and the buried oxide layer 6, specifically as Figure 4 shown;

[0045] Perform heavy doping to form a heavily doped tunneling region 7, and selectively epitaxially grow silicon to obtain the source region 3 and the drain region 4, as Figure 5 shown;

[0046] Deposit the gate oxide layer 2, and fabricate the gate 1 on the gate oxide layer 2.

[0047] In one embodiment of the present invention, a high-resistance wafer close to intrinsic silicon is selected as the substrate 8. The etching depth of the source region 3 and the drain region 4 needs to be greater than the depths of the top silicon film 5 and the buried oxide layer 6. The doping concentrations of the source region 3 and the drain region 4 need to be high enough to form a tunneling structure. The methods for forming the tunneling structure include, but are not limited to, increasing the ion implantation concentration of the source region 3 and the drain region 4 and reducing the applied energy.

[0048] In the present invention, the SOI T-CMOS structure can be integrated with the traditional CMOS process. The SOI T-CMOS is directly fabricated on the existing commercial SOI wafer, and does not require structures such as field oxidation and wells in the traditional CMOS process, reducing some processes. At the same time, the minimum pitch of the device is reduced, greatly improving the integration density, and it can be better applied in integrated circuits.

[0049] The SOI T-CMOS is a partially depleted silicon-on-insulator structure. The width of its depletion region is not affected by the thickness of the silicon film, and the threshold voltage is less affected by the back-gate bias. The adjustment of its threshold voltage and the control of the short-channel effect can adopt the control methods of traditional bulk silicon devices, which are relatively easy to control.

[0050] The above has described the embodiments of the present invention in detail, but the described content is only the preferred embodiments of the present invention and cannot be considered as limiting the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope covered by this patent.

Claims

1. A three - valued logic transistor device structure, characterized in that: The structure includes: A substrate to provide support; A heavily doped tunneling region; A buried oxide layer located above the heavily doped tunneling region; A top silicon film located on the buried oxide layer; Source and drain regions on both sides of the heavily doped tunneling region; A gate oxide layer and a gate located on the source region, drain region, and top silicon film. The source region and drain region extend from the top surface of the SOI wafer to both sides of the heavily doped tunneling region and are in contact with the heavily doped tunneling region.

2. The three - valued logic transistor device structure according to claim 1, characterized in that: The depth of the source region and drain region extending towards the bottom of the substrate is deeper than the depth of the buried oxide layer to form a tunneling structure.

3. The three - valued logic transistor device structure according to claim 1, characterized in that: The thickness of the buried oxide layer is greater than the thickness of the gate oxide layer to achieve isolation between the heavily doped tunneling region and the gate.

4. A method for manufacturing a three - valued logic transistor device structure, characterized in that: It includes: Select an SOI wafer; Etch the SOI wafer; Perform heavy doping to form a heavily doped tunneling region, and selectively epitaxially grow silicon to obtain source and drain regions; Deposit a gate oxide layer and fabricate a gate on the gate oxide layer. The source region and drain region extend from the top surface of the SOI wafer to both sides of the heavily doped tunneling region and are in contact with the heavily doped tunneling region. The heavily doped tunneling region is located below the buried oxide layer of the SOI wafer.

5. The method for manufacturing a three - valued logic transistor device structure according to claim 4, characterized in that: The SOI wafer includes a substrate, a buried oxide layer, and a top silicon film.

6. The method for manufacturing a three - valued logic transistor device structure according to claim 5, characterized in that: During the process of etching the SOI wafer, the etching depth is deeper than the top silicon film and the buried oxide layer.

7. The method for manufacturing a three - valued logic transistor device structure according to claim 4, characterized in that: Ensure that the thickness of the heavily doped tunneling region is greater than the thickness of the gate oxide layer.

8. The method for manufacturing a three - valued logic transistor device structure according to claim 4, characterized in that: The doping concentration of the source region and drain region needs to be high enough to form a tunneling structure.

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