An array substrate and a display panel

Abstract

This invention discloses an array substrate and a display panel. The array substrate includes: a substrate, a first metal layer located on one side of the substrate, the first metal layer including a plurality of spaced-apart first metal blocks; and a conductive shielding structure electrically connected to a fixed potential to shield the coupling capacitance between two adjacent first metal blocks, the conductive shielding structure being insulated between two adjacent first metal blocks. The technical solution provided by the embodiments of this invention reduces the parasitic capacitance between adjacent metal lines in the capacitance compensation area, thereby improving the display effect of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an array substrate and a display panel. Background Technology

[0002] In the display panel, the array substrate includes a capacitance compensation area, which includes multiple scan lines and multiple data lines.

[0003] In the prior art, parasitic capacitance is formed between adjacent metal lines located in the capacitance compensation area, which has an adverse effect on the display effect of the display panel. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide an array substrate and a display panel to reduce the parasitic capacitance between adjacent metal lines in the capacitance compensation area, thereby improving the display effect of the display panel.

[0005] This invention provides an array substrate, comprising: a substrate, the array substrate including a first metal layer located on one side of the substrate, the first metal layer including a plurality of spaced first metal blocks;

[0006] A conductive shielding structure is electrically connected to a fixed potential to shield the coupling capacitance between two adjacent first metal blocks. The conductive shielding structure is insulated between the two adjacent first metal blocks.

[0007] In this technical solution, the conductive shielding structure is electrically connected to a fixed potential, and insulation is provided between two adjacent first metal blocks. This avoids the formation of parasitic capacitance between the two adjacent first metal blocks, thus achieving the effect of reducing parasitic capacitance between the two adjacent first metal blocks and improving the display effect of the display panel. For example, when the first metal block is a data line, the conductive shielding structure is insulated between two adjacent data lines, and its conductivity is superior to that of the polycrystalline silicon active layer. This avoids the formation of parasitic capacitance between two adjacent data lines, thereby reducing the parasitic capacitance between two adjacent data lines in the capacitance compensation area and improving the display effect of the display panel.

[0008] Optionally, the fixed potential includes any one of the potential of the first power line, the potential of the second power line, the potential of the initialization signal line, and the ground potential.

[0009] In this technical solution, the first power line is an ELVSS power line, and the second power line is an ELVDD power line. The ELVSS and ELVDD power lines provide power signals to the display panel. The initialization signal line provides initialization signals to the pixel circuits of the display panel. Specifically, the conductive shielding structure is electrically connected to a fixed potential, which is equivalent to the conductive shielding structure being an equipotential body, thus providing electromagnetic shielding. The fixed potential includes any one of the potentials of the first power line, the second power line, the initialization signal line, and ground potential in the array substrate of the display panel. This eliminates the need for additional fixed potential lines, saving process steps and reducing manufacturing costs.

[0010] Optionally, the first metal blocks extend along a first direction and are spaced apart along a second direction;

[0011] The array substrate further includes a first insulating layer, which covers the first metal layer;

[0012] The first insulating layer located between two adjacent first metal blocks includes a groove or a through hole, and at least a portion of the conductive shielding structure is located within the groove or through hole.

[0013] In this technical solution, part of the conductive shielding structure is located in the through hole or groove of the first insulating layer between two adjacent first metal blocks, so as to realize that the conductive shielding structure is insulatingly set between two adjacent first metal blocks, thereby avoiding the formation of parasitic capacitance between two adjacent first metal blocks, thus achieving the effect of shielding the parasitic capacitance between two adjacent first metal blocks, and improving the display effect of the display panel.

[0014] Preferably, in the second direction, the width of the conductive shielding structure located in the groove or through hole is smaller than the spacing between two adjacent first metal blocks.

[0015] This technical solution achieves an insulating conductive shielding structure between two adjacent first metal blocks, thereby ensuring the display effect of the display panel.

[0016] Preferably, the conductive shielding structure includes a vertical portion located within the groove or through hole.

[0017] In this technical solution, the groove or through hole is used to accommodate the vertical part of the conductive shielding structure, so as to realize that the conductive shielding structure is insulated between two adjacent first metal blocks, thereby ensuring the display effect of the display panel.

[0018] Preferably, the first metal block is a data cable.

[0019] In this technical solution, the conductivity of the conductive shielding structure is superior to that of the polycrystalline silicon active layer, which can prevent two adjacent data lines from forming parasitic capacitance, thereby reducing the parasitic capacitance between two adjacent data lines and improving the display effect of the display panel.

[0020] Optionally, the conductive shielding structure further includes a strip-shaped portion located on the side of the first insulating layer opposite to the first metal layer;

[0021] In the second direction, the edge of the strip protrudes beyond the vertical portion by a first preset distance.

[0022] In this technical solution, the edge of the strip protrudes beyond the vertical part by a first preset distance, increasing the area of ​​the conductive shielding structure, thereby further reducing the parasitic capacitance between two adjacent first metal blocks (such as data lines), and further improving the display effect of the display panel.

[0023] Optionally, the conductive shielding structure further includes a strip-shaped portion located on the side of the first insulating layer opposite to the first metal layer;

[0024] The projection of the strip portion onto the substrate covers the first metal block.

[0025] In this technical solution, the portion of the strip-shaped part projecting onto the substrate and covering the first metal block together constitutes a parasitic capacitance. This capacitance can compensate for the storage capacitance in the driving circuit of the sub-pixels in the display panel, thereby improving the display effect of the display panel. Furthermore, the above technical solution increases the area of ​​the conductive shielding structure, which further reduces the parasitic capacitance between two adjacent first metal blocks (e.g., data lines), and further improves the display effect of the display panel.

[0026] Optionally, the array substrate further includes a second insulating layer and a second metal layer, wherein the second insulating layer is located between the first metal layer and the substrate.

[0027] The second metal layer is located on the surface of the second insulating layer away from the first metal layer;

[0028] The second insulating layer includes a groove or a through hole, and the vertical portion is located within the groove or through hole.

[0029] In this technical solution, the vertical part of the conductive shielding structure is located in the groove or through hole of the second insulating layer, which increases the area of ​​the vertical part used for capacitor shielding. This can prevent adjacent first metal blocks (such as data lines) from forming parasitic capacitance, thereby improving the display effect of the display panel.

[0030] Preferably, the projection of the second metal layer onto the substrate covers the first metal block.

[0031] In this technical solution, the second metal layer can form a capacitor structure with the first metal block (e.g., a data line) to compensate for the storage capacitance in the driving circuit of the sub-pixel, thereby further improving the display effect of the display panel.

[0032] Preferably, the second insulating layer includes a through hole, the vertical portion is located within the through hole, and is connected to the second metal layer.

[0033] Preferably, the conductive shielding structure further includes a strip-shaped portion located on the side of the first insulating layer opposite to the first metal layer; the projection of the strip-shaped portion on the substrate covers the first metal block.

[0034] In this technical solution, the vertical portion of the conductive shielding structure is connected to the second metal layer. The conductive shielding structure and the second metal layer surround the side surface of the first metal block (e.g., a data cable) and the surface of the first metal block adjacent to the substrate. Alternatively, when the first insulating layer includes a through-hole, a portion of the conductive shielding structure is located within the through-hole. The second insulating layer also includes a through-hole, with the vertical portion located within the through-hole. One end of the vertical portion is connected to the strip portion of the conductive shielding structure, and the orthographic projection of the strip portion onto the substrate covers the first metal block. The other end of the vertical portion is connected to the second metal layer. While surrounding the side surface of the first metal block (e.g., a data cable), the conductive shielding structure and the second metal layer also surround the surface of the first metal block adjacent to the substrate and the surface away from the substrate, increasing the capacitive shielding area. This prevents adjacent first metal blocks (e.g., data cables) from forming parasitic capacitance, thereby improving the display effect of the display panel.

[0035] Optionally, the first insulating layer includes a stack of a first sub-insulating layer and a second sub-insulating layer;

[0036] The array substrate further includes a third metal layer, which is located between the first sub-insulating layer and the second sub-insulating layer, and the first sub-insulating layer is located between the third metal layer and the first metal layer.

[0037] The through hole penetrates the second sub-insulating layer, the third metal layer, and the first sub-insulating layer. The vertical portion is located inside the through hole and is connected to the third metal layer.

[0038] In this technical solution, the structure formed by the third metal layer and the conductive shielding structure surrounds the side of the data line and the surface away from the substrate, increasing the area of ​​the structure that realizes the capacitor shielding function. This can prevent adjacent first metal blocks (such as data lines) from forming parasitic capacitance, thereby improving the display effect of the display panel.

[0039] Preferably, the projection of the third metal layer onto the substrate covers the first metal block.

[0040] In this technical solution, the third metal layer can form a capacitor structure with the first metal block (e.g., a data line) to compensate for the storage capacitance in the driving circuit of the sub-pixel, thereby further improving the display effect of the display panel.

[0041] Optionally, the array substrate further includes a fourth metal layer;

[0042] The fourth metal layer is located on the surface of the first insulating layer away from the first metal layer; the fourth metal layer includes a plurality of second metal blocks extending along a second direction, the second metal blocks being spaced apart along a first direction;

[0043] The orthographic projection of the conductive shielding structure onto the substrate and the orthographic projection of the second metal block onto the substrate are offset.

[0044] In this technical solution, the fourth metal layer is located on the surface of the first insulating layer away from the first metal layer, and can be used to form lines that provide driving signals for thin-film transistors. Furthermore, the fourth metal layer and the strip portion of the conductive shielding structure are located on the same layer, simplifying the process flow and reducing manufacturing costs. Specifically, the orthographic projection of the conductive shielding structure onto the substrate and the orthographic projection of the second metal block onto the substrate are staggered, ensuring that the second metal block and the conductive shielding structure remain insulated. This avoids the influence of the electrical signal of the second metal block on the fixed potential of the conductive shielding structure, thereby ensuring that the conductive shielding structure can avoid forming parasitic capacitances with adjacent first metal blocks (e.g., data lines), thus improving the display effect of the display panel.

[0045] Preferably, the second metal block is a scan line.

[0046] In this technical solution, the second metal block is a scan line, which is used to provide drive signals to the thin-film transistors, the data line is used to provide data signals to the thin-film transistors, and the storage capacitor is used to control and maintain the stability of the data, thereby keeping the brightness of the display panel constant within one frame.

[0047] Preferably, the second metal block and the portion of the conductive shielding structure excluding the vertical portion are located on the same layer.

[0048] In this technical solution, the scan lines and conductive shielding structure, excluding the vertical portion (i.e., the strip portion), are located on the same layer, simplifying the process and reducing manufacturing costs. Furthermore, the orthographic projections of the conductive shielding structure and the scan lines onto the substrate are staggered, ensuring that the scan lines and conductive shielding structure remain insulated. This avoids the influence of the scan line's electrical signal on the fixed potential of the conductive shielding structure, thus preventing the conductive shielding structure from forming parasitic capacitances with adjacent first metal blocks (e.g., data lines), thereby improving the display effect of the display panel.

[0049] Optionally, in the first direction, the conductive shielding structure and the second metal block are spaced apart by a second preset distance.

[0050] In this technical solution, the second preset distance between the conductive shielding structure and the second metal block (e.g., the scan line interval) is less than or equal to 3.5 micrometers. If the process conditions permit, this technical solution can further increase the area of ​​the conductive shielding structure, thereby further reducing the parasitic capacitance between adjacent data lines and further improving the display effect of the display panel. Conversely, if the second preset distance between the conductive shielding structure and the second metal block (e.g., the scan line interval) is greater than or equal to 3 micrometers, it can reduce the difficulty of the process and ensure that the conductive shielding structure and the second metal block (e.g., the scan line) are electrically insulated, thus avoiding any impact on the display effect of the display panel.

[0051] This invention also provides a display panel, including any of the array substrates described in the above technical solutions.

[0052] The technical solution provided by this invention involves a conductive shielding structure electrically connected to a fixed potential. Insulation is provided between two adjacent first metal blocks, preventing the formation of parasitic capacitance between them and thus achieving the effect of reducing parasitic capacitance between adjacent first metal blocks, thereby improving the display effect of the display panel. For example, when the first metal block is a data line, the conductive shielding structure is insulated between two adjacent data lines, and its conductivity is superior to that of the polycrystalline silicon active layer. This prevents the formation of parasitic capacitance between two adjacent data lines, thereby reducing the parasitic capacitance between adjacent data lines in the capacitance compensation area and improving the display effect of the display panel. Attached Figure Description

[0053] Figure 1 A top view of a display panel provided in an embodiment of the present invention;

[0054] Figure 2 for Figure 1 The layout of the array substrate located in the capacitance compensation region;

[0055] Figure 3 for Figure 2 A schematic diagram of the cross-sectional structure corresponding to the B1-B2 direction in the middle;

[0056] Figure 4 This is a schematic diagram of the structure of an array substrate provided in an embodiment of the present invention;

[0057] Figure 5 A layout of an array substrate provided in an embodiment of the present invention;

[0058] Figure 6 for Figure 5A schematic diagram of a cross-sectional structure along the B1-B2 direction;

[0059] Figure 7 for Figure 5 A schematic diagram of a cross-sectional structure along the C1-C2 direction;

[0060] Figure 8 A layout of another array substrate provided in an embodiment of the present invention;

[0061] Figure 9 for Figure 8 A schematic diagram of a cross-sectional structure along the C1-C2 direction;

[0062] Figure 10 A layout of another array substrate provided in an embodiment of the present invention;

[0063] Figure 11 for Figure 10 A schematic diagram of a cross-sectional structure along the C1-C2 direction;

[0064] Figure 12 for Figure 10 A schematic diagram of another cross-sectional structure along the C1-C2 direction;

[0065] Figure 13 for Figure 10 A schematic diagram of another cross-sectional structure along the C1-C2 direction. Detailed Implementation

[0066] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0067] As described in the background section above, parasitic capacitance is formed between adjacent metal lines in the capacitance compensation area of ​​the array substrate, which has an adverse effect on the display effect of the display panel. Figure 1 This is a top view of a display panel provided in an embodiment of the present invention. Figure 2 for Figure 1 The layout of the array substrate located in the capacitance compensation region. Figure 3 for Figure 2 A schematic diagram of the cross-sectional structure along the B1-B2 direction. (See attached diagram.) Figures 1-3The array substrate located in the capacitance compensation area includes: a substrate 001, which includes a display area A1 and a non-display area A2 located on at least one side of the display area A1. The non-display area A2 is provided with a capacitance compensation area A21, which includes multiple scan lines S0 and multiple data lines D0. The scan lines S0 are, for example, scan lines S1, S2, and S3, and the data lines D0 are, for example, data lines D1, D2, and D3. Display panels, especially... Figure 1 In circular or racetrack-shaped display panels, the small spacing L between data lines D0 in the capacitance compensation area A21 can easily lead to parasitic capacitance between adjacent data lines D0, such as data line D1 and data line D2, negatively impacting the display effect. The inventors, through careful research, incorporated a capacitance compensation metal layer 005 into the display panel. It should be noted that the array substrate also includes a buffer layer 002, a polysilicon active layer 10, a gate insulating layer 003, a capacitor insulating layer 004, a first interlayer insulating layer 006, and a second interlayer insulating layer 007. The capacitor insulating layer 004, the first interlayer insulating layer 006, and the second interlayer insulating layer 007 constitute the first insulating layer 20, used to separate the scan line S0 and the data line D0. The capacitance compensation metal layer 005 is located within the first insulating layer 20. To reduce parasitic capacitance between two adjacent data lines D0, such as data lines D1 and D2, the inventors disposed a polysilicon active layer 10 between the buffer layer 002 and the gate insulating layer 003, and provided a conductive structure to realize the connection between the polysilicon active layer 10 and the capacitor compensation metal layer 005. This conductive structure is intended to shield the two adjacent data lines D0, preventing them from forming parasitic capacitance. However, due to the poor conductivity of the polysilicon active layer 10, its placement did not reduce the parasitic capacitance between the two adjacent data lines D0, such as data lines D1 and D2; instead, it increased the parasitic capacitance between them. Therefore, the above technical solution is not ideal for reducing the parasitic capacitance between two adjacent data lines D0 within the capacitor compensation region A21.

[0068] To address the aforementioned technical problems, embodiments of the present invention provide the following array substrate, comprising: a substrate, the array substrate including a first metal layer located on one side of the substrate, the first metal layer including a plurality of spaced first metal blocks; and a conductive shielding structure electrically connected to a fixed potential for shielding the coupling capacitance between two adjacent first metal blocks, the conductive shielding structure being insulated between two adjacent first metal blocks.

[0069] Figure 4 This is a schematic diagram of an array substrate provided in an embodiment of the present invention. For example, see [link to example]. Figure 4 The array substrate includes: a substrate 001, the array substrate including a first metal layer M1 located on one side of the substrate 001, the first metal layer M1 including a plurality of spaced first metal blocks D0, such as first metal block D1 and first metal block D2; a conductive shielding structure 30, the conductive shielding structure 30 being electrically connected to a fixed potential E0 for shielding the coupling capacitance between two adjacent first metal blocks D1 and first metal blocks D2, the conductive shielding structure 30 being insulated between two adjacent first metal blocks D1 and first metal blocks D2.

[0070] The technical solution provided in this embodiment of the invention involves a conductive shielding structure 30 electrically connected to a fixed potential E0. This structure is insulated between two adjacent first metal blocks D0, preventing the formation of parasitic capacitance between them and thus reducing the parasitic capacitance between adjacent first metal blocks D0, thereby improving the display effect of the display panel. For example, when the first metal block D0 is a data line, the conductive shielding structure 30 is insulated between two adjacent data lines D0, and its conductivity is superior to that of the polysilicon active layer 10. This prevents the formation of parasitic capacitance between two adjacent data lines D0, thereby reducing the parasitic capacitance between two adjacent data lines D0 in the capacitance compensation area and improving the display effect of the display panel.

[0071] Optionally, the fixed potential E0 includes any one of the potential of the first power line, the potential of the second power line, the potential of the initialization signal line, and the ground potential.

[0072] For example, the first power line is an ELVSS power line, and the second power line is an ELVDD power line. The ELVSS and ELVDD power lines provide power signals to the display panel. The initialization signal line provides initialization signals to the pixel circuits of the display panel. Specifically, the conductive shielding structure 30 is electrically connected to a fixed potential E0, which is equivalent to the conductive shielding structure 30 being an equipotential body, thus providing electromagnetic shielding. The fixed potential E0 includes any one of the potentials of the first power line, the second power line, the initialization signal line, and ground potential in the array substrate of the display panel. This eliminates the need for additional fixed potential lines, saving process steps and reducing manufacturing costs.

[0073] Figure 5 This is a layout of an array substrate provided for an embodiment of the present invention. Figure 6 for Figure 5 A schematic diagram of a cross-sectional structure along the B1-B2 direction. Figure 7 for Figure 5A cross-sectional structural diagram along the C1-C2 direction is shown. Optionally, the first metal blocks extend along a first direction and are spaced apart along a second direction; the array substrate further includes a first insulating layer that covers the first metal layer; the first insulating layer located between two adjacent first metal blocks includes a groove or a through hole, and at least a portion of the conductive shielding structure is located within the groove or through hole.

[0074] For example, see Figure 5 First metal blocks D1, D2, and D3 extend along a first direction, such as the Y direction, and are spaced apart along a second direction, such as the X direction. (See also...) Figure 7 The array substrate also includes a first insulating layer 20, which covers the first metal layer M1. The first insulating layer 20 located between two adjacent first metal blocks D0 includes a through-hole 20A, and the conductive shielding structure 30 is entirely located within the through-hole 20A. See also Figure 8 and Figure 9 The first insulating layer 20 located between two adjacent first metal blocks D0 includes a through hole 20A. A portion of the conductive shielding structure 30 is located within the through hole 20A, and another portion of the conductive shielding structure 30 is located on the surface of the first insulating layer 20 away from the first metal layer M1. It should be noted that embodiments of the present invention also include a technical solution where the first insulating layer 20 located between two adjacent first metal blocks D0 includes a groove.

[0075] Specifically, part of the conductive shielding structure 30 is located in the through hole 20A or groove of the first insulating layer 20 between two adjacent first metal blocks D0, so that the conductive shielding structure 30 is insulated between two adjacent first metal blocks D0, thereby avoiding the formation of parasitic capacitance between two adjacent first metal blocks D0, thus achieving the effect of shielding the parasitic capacitance between two adjacent first metal blocks D0, and improving the display effect of the display panel.

[0076] Preferably, see Figure 5 and Figure 7 In the second direction, the width of the conductive shielding structure 30 located in the groove or through hole 20A is smaller than the distance L between two adjacent first metal blocks D1 and D2, so as to achieve the conductive shielding structure 30 being insulated between the two adjacent first metal blocks D1 and D2, thereby ensuring the display effect of the display panel.

[0077] Preferably, the conductive shielding structure includes a vertical portion located within a groove or through hole.

[0078] For example, Figure 5 and Figure 7The diagram shows a through-hole 20A in the first insulating layer 20, and a conductive shielding structure 30 including a vertical portion 30a located within the through-hole 20A. It should be noted that when the vertical portion 30a does not reach the surface of the first insulating layer 20 flush with the first metal block D0, the first insulating layer 20 includes a groove for accommodating the vertical portion 30a.

[0079] Preferably, the first metal block is a data cable. For example, Figure 5 Data lines D1, D2, and D3 are shown. The conductive shielding structure 30 has better conductivity than the polysilicon active layer 10, which can prevent two adjacent data lines D0 from forming parasitic capacitance, thereby reducing the parasitic capacitance between two adjacent data lines D0 and improving the display effect of the display panel.

[0080] For example, in the technical solution provided in the embodiment of the present invention, when the width of the groove or through hole 20A (the width of the vertical portion 30a of the conductive shielding structure 30) is 0 micrometers in the second direction, the parasitic capacitance between adjacent first metal blocks (e.g., data lines) is 0.7965 fF; when the width of the groove or through hole 20A (the width of the vertical portion 30a of the conductive shielding structure 30) is 1.8 micrometers, the parasitic capacitance between two adjacent first metal blocks (e.g., data lines) in the capacitance compensation area is 0.003 fF. The conductive shielding structure 30 is provided such that the percentage decrease in capacitance between two adjacent first metal blocks can reach 99.6%. It can be seen that the conductive shielding structure 30 can significantly reduce the parasitic capacitance formed by two adjacent first metal blocks (e.g., data lines D0), thereby improving the display effect of the display panel.

[0081] Optional, see Figure 8 and Figure 9 The conductive shielding structure 30 also includes a strip portion 30b located on the side of the first insulating layer 20 away from the first metal layer D0; in the second direction, the edge of the strip portion 30b protrudes from the vertical portion 30a by a first preset distance W1.

[0082] For example, the first preset distance W1 is greater than or equal to 0.5 micrometers and less than or equal to 3 micrometers.

[0083] Specifically, the edge of the strip portion 30b protrudes beyond the vertical portion 30a by a first preset distance W1, increasing the area of ​​the conductive shielding structure 30. This further reduces the parasitic capacitance between two adjacent first metal blocks (e.g., data line D0) and further improves the display effect of the display panel.

[0084] Optional, see Figure 10 and Figure 11The conductive shielding structure 30 also includes a strip-shaped portion 30b located on the side of the first insulating layer 20 away from the first metal layer D0; the projection of the strip-shaped portion 30b onto the substrate 001 covers the first metal block D0.

[0085] Specifically, the projection of the strip portion 30b onto the substrate 001, covering the portion of the first metal block D0, and the first metal block D0 together form a parasitic capacitance. This capacitance can compensate for the storage capacitance in the driving circuit of the sub-pixels in the display panel, thereby improving the display effect of the display panel. Furthermore, the above technical solution increases the area of ​​the conductive shielding structure 30, which further reduces the parasitic capacitance between two adjacent first metal blocks (e.g., data lines D0), and further improves the display effect of the display panel.

[0086] Optional, see Figure 10 and Figure 12 The array substrate further includes a second insulating layer 40 and a second metal layer M2. The second insulating layer 40 is located between the first metal layer M1 and the substrate 001. The second metal layer M2 is located on the surface of the second insulating layer 40 away from the first metal layer M1. The second insulating layer 40 includes a groove or through-hole 40A, and a vertical portion 30a is located within the groove or through-hole 40A. It should be noted that when the through-hole 40A does not penetrate the second insulating layer 40, the embodiments of the present invention also include a solution where the second insulating layer 40 includes a groove.

[0087] Specifically, the vertical portion 30a of the conductive shielding structure 30 is located in the groove or through hole 40A of the second insulating layer 40, which increases the area of ​​the vertical portion 30a used for capacitor shielding. This can prevent adjacent first metal blocks (such as data lines) from forming parasitic capacitance, thereby improving the display effect of the display panel.

[0088] Preferably, see Figure 12 The projection of the second metal layer M2 onto the substrate 001 covers the first metal block D0. The second metal layer M2 can form a capacitor structure with the first metal block (e.g., a data line D0) to compensate for the storage capacitance in the driving circuit of the sub-pixel, thereby further improving the display effect of the display panel.

[0089] Preferably, see Figure 12The second insulating layer 40 includes a through-hole 40A, and a vertical portion 30a is located within the through-hole 40A and connected to the second metal layer M2. Specifically, the vertical portion 30a of the conductive shielding structure 30 is connected to the second metal layer M2, and the conductive shielding structure 30 and the second metal layer M2 surround the side of the first metal block (e.g., data line D0) and the surface of the first metal block D0 adjacent to the substrate 001. Alternatively, when the first insulating layer 20 includes a through-hole 20A, a portion of the conductive shielding structure 30 is located within the through-hole 20A, the second insulating layer 40 includes a through-hole 40A, and the vertical portion 30a is located within the through-hole 40A. One end of the vertical portion 30a is connected to the strip portion 30b of the conductive shielding structure 30, and the orthographic projection of the strip portion 30b on the substrate 001 covers the first metal block D0. The other end of the vertical portion 30a is connected to the second metal layer M2. The conductive shielding structure 30 and the second metal layer M2 surround the side of the first metal block (e.g., the data line D0), and also surround the surface of the first metal block adjacent to the substrate 001 and the surface away from the substrate 001, increasing the capacitor shielding area and preventing adjacent first metal blocks (e.g., the data line) from forming parasitic capacitance, thereby improving the display effect of the display panel.

[0090] Optional, see Figure 10 and Figure 13 The first insulating layer 20 includes a stack of a first sub-insulating layer 21 and a second sub-insulating layer 22; the array substrate also includes a third metal layer M3, which is located between the first sub-insulating layer 21 and the second sub-insulating layer 22, and the first sub-insulating layer 21 is located between the third metal layer M3 and the first metal layer M1; the through hole 20A penetrates the second sub-insulating layer 22, the third metal layer M3 and the first sub-insulating layer 21, and the vertical portion 30a is located in the through hole 20A and is connected to the third metal layer M3.

[0091] Specifically, the structure formed by the third metal layer M3 and the conductive shielding structure 30 surrounds the side of the data line D0 and the surface away from the substrate 001, increasing the area of ​​the structure that realizes the capacitor shielding function. This can prevent adjacent first metal blocks (such as the data line D0) from forming parasitic capacitance, thereby improving the display effect of the display panel.

[0092] Preferably, see Figure 13 The projection of the third metal layer M3 onto the substrate 001 covers the first metal block D0.

[0093] Specifically, the third metal layer M3 can form a capacitor structure with the first metal block (e.g., data line D0) to compensate for the storage capacitance in the driving circuit of the sub-pixel, thereby further improving the display effect of the display panel.

[0094] Optional, see Figure 5 and Figure 6The array substrate also includes a fourth metal layer M4; the fourth metal layer M4 is located on the surface of the first insulating layer 20 away from the first metal layer M1; the fourth metal layer M4 includes a plurality of second metal blocks S0 extending along a second direction, the second metal blocks S0 being spaced apart along a first direction; the orthographic projection of the conductive shielding structure 30 on the substrate 001 and the orthographic projection of the second metal blocks S0 on the substrate 001 are offset.

[0095] Specifically, the fourth metal layer M4 is located on the surface of the first insulating layer 20 away from the first metal layer M1, and can be used to form lines that provide drive signals to thin-film transistors. Figure 8 and Figure 10 In this design, the fourth metal layer M4 and the strip portion 30b of the conductive shielding structure 30 are located on the same layer, simplifying the process and reducing manufacturing costs. The orthographic projection of the conductive shielding structure 30 onto the substrate 001 and the orthographic projection of the second metal block S0 onto the substrate 001 are staggered, ensuring that the second metal block S0 and the conductive shielding structure 30 remain insulated. This avoids the influence of the electrical signal of the second metal block S0 on the fixed potential E0 of the conductive shielding structure 30, thereby ensuring that the conductive shielding structure 30 can avoid forming parasitic capacitances with adjacent first metal blocks (e.g., data lines D0), thus improving the display effect of the display panel.

[0096] Preferably, the second metal block is a scan line.

[0097] As is known, the array substrate also includes thin-film transistors and storage capacitors. The array substrate also includes a buffer layer 002 and a gate insulating layer 003. The buffer layer 002 protects the thin-film transistors on one side of the substrate 001. The gate insulating layer 003 provides electrical insulation between the gate of the thin-film transistor and other film layers. The second metal block is a scan line S0, which provides a drive signal to the thin-film transistors. The data line D0 provides a data signal to the thin-film transistors. The storage capacitor controls and maintains data stability, thereby keeping the brightness of the display panel constant within one frame.

[0098] Preferably, the second metal block and the portion of the conductive shielding structure excluding the vertical part are located in the same layer.

[0099] Specifically, the scan line S0 and the conductive shielding structure 30, excluding the vertical portion 30a (i.e., the strip portion 30b), are located on the same layer, simplifying the process and reducing manufacturing costs. The orthographic projection of the conductive shielding structure 30 onto the substrate 001 is staggered with the orthographic projection of the scan line S0 onto the substrate 001, ensuring that the scan line S0 and the conductive shielding structure 30 remain insulated. This avoids the influence of the electrical signal of the scan line S0 on the fixed potential of the conductive shielding structure, thus ensuring that the conductive shielding structure 30 can avoid forming parasitic capacitances with adjacent first metal blocks (e.g., data lines D0), thereby improving the display effect of the display panel. See also... Figure 5 and Figure 6 Scan line S0 includes scan S1, scan S2 and scan S1.

[0100] Optionally, the thin-film transistor 50 in the sub-pixel of the array substrate includes a polysilicon active layer 51, a gate 52, a source 53 and a drain 54, and the storage capacitor 60 includes a first electrode 61 and a second electrode 62.

[0101] Figure 12 In this configuration, the polysilicon active layer 51 is located between the gate insulating layer 003 and the buffer layer 002. The gate 52 and the second metal layer M2 are located in the same layer and are made of the same material. The source 53 and the drain 54 are located in the same layer as the fourth metal layer M4 and are made of the same material. The first electrode 61 of the storage capacitor 60 is located on the surface of the capacitor insulating layer 004 near the second metal layer M2. The second electrode 62 and the data line D0 are located in the same layer and are made of the same material. The capacitor insulating layer 004 and the second insulating layer 40 are located in the same layer and are made of the same material. The first interlayer insulating layer 006 and the second interlayer insulating layer 007 are located in the same layer as the first insulating layer 20 and are made of the same material. This technical solution can ensure that the thin-film transistor 50 and the storage capacitor 60 are fabricated simultaneously with the scan line S0, the data line D0, and the conductive shielding structure 30, reducing the process difficulty and saving the fabrication cost.

[0102] Figure 13 In this configuration, the polysilicon active layer 51 is located between the gate insulating layer 003 and the buffer layer 002. The gate 52 and the data line D0 are located on the same layer and are made of the same material. The source 53 and the drain 54 are located on the same layer as the fourth metal layer M4 and are made of the same material. The first electrode 61 of the storage capacitor 60 is located on the surface of the capacitor insulating layer 004 near the data line D0. The second electrode 62 and the third metal layer M3 are located on the same layer and are made of the same material. The capacitor insulating layer 004 and the first sub-insulating layer 21 are located on the same layer and are made of the same material; the first interlayer insulating layer 006, the second interlayer insulating layer 007, and the second sub-insulating layer 22 are located on the same layer and are made of the same material. The above technical solution can ensure that the thin-film transistor 50 and the storage capacitor 60 are fabricated simultaneously with the scan line S0, the data line D0, and the conductive shielding layer 30, reducing the process difficulty and saving the fabrication cost.

[0103] Optional, see Figure 5 In the first direction, the conductive shielding structure 30 and the second metal block S0 are spaced apart by a second preset distance W2.

[0104] See Figure 5 The second preset distance W2 is greater than or equal to 3 micrometers and less than or equal to 3.5 micrometers.

[0105] If the conductive shielding structure 30 and the second metal block, for example, are separated by a second preset distance W2 of less than or equal to 3.5 micrometers, the above technical solution can further increase the area of ​​the conductive shielding structure 30, provided that the process conditions permit, thereby further reducing the parasitic capacitance between two adjacent data lines D0 and further improving the display effect of the display panel. If the conductive shielding structure 30 and the second metal block, for example, are separated by a second preset distance W2 of greater than or equal to 3 micrometers, the process difficulty can be reduced, ensuring that the conductive shielding structure 30 and the second metal block, for example, are electrically insulated from the scan line S0, thus avoiding any impact on the display effect of the display panel.

[0106] It should be noted that the insulating layer in the embodiments of the present invention can be silicon nitride, silicon oxide, or a stack of silicon nitride and silicon oxide. In the embodiments of the present invention, the first metal block and the data line use the same reference numerals, and the second metal block and the scan line use the same reference numerals.

[0107] This invention also provides a display panel, including any of the array substrates described in the above technical solutions. The display panel provided by this invention can be applied to display devices with display functions, such as mobile phones, computers, and smart wearable devices; however, this invention does not limit its application in this regard.

[0108] The display panel provided in this embodiment of the invention includes the array substrate provided in this embodiment of the invention and has the same function and effect, which will not be described again here.

[0109] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. An array substrate, characterized by, The array substrate comprises a substrate, a first metal layer on one side of the substrate, the first metal layer comprising a plurality of first metal blocks arranged at intervals; A conductive shielding structure is electrically connected to a fixed potential, and is used to shield the coupling capacitance between two adjacent first metal blocks, the conductive shielding structure being arranged insulatively between the two adjacent first metal blocks; The first metal blocks extend in a first direction and are arranged at intervals in a second direction; The array substrate further comprises a first insulating layer covering the first metal layer; The first insulating layer between two adjacent first metal blocks comprises a groove or a through hole, at least part of the conductive shielding structure being arranged in the groove or the through hole; wherein the through hole penetrates the first insulating layer; The conductive shielding structure comprises a vertical portion and a strip-shaped portion, the vertical portion being arranged in the groove or the through hole, and the strip-shaped portion being arranged on a side of the first insulating layer away from the first metal layer; The array substrate further comprises a fourth metal layer; the fourth metal layer is arranged on a surface of the first insulating layer away from the first metal layer; the fourth metal layer is provided with scan lines; and the fourth metal layer and the strip-shaped portion of the conductive shielding structure are arranged in the same layer. The fixed potential comprises any one of the potential of a first power supply line, the potential of a second power supply line, the potential of an initialization signal line, and a ground potential.

2. The array substrate of claim 1, wherein, In the second direction, the width of the conductive shielding structure arranged in the groove or the through hole is smaller than the interval between two adjacent first metal blocks.

3. The array substrate of claim 1, wherein the first and second gate lines are formed of a same material. The conductive shielding structure comprises a vertical portion, the vertical portion being arranged in the groove or the through hole; and the first metal blocks are data lines.

4. The array substrate of claim 3, wherein, In the second direction, the edge of the strip-shaped portion protrudes from the vertical portion by a first preset distance.

5. The array substrate of claim 3, wherein the first and second sub-pixels are arranged in a matrix form. The projection of the strip-shaped portion on the substrate covers the first metal blocks.

6. The array substrate of claim 3, wherein the first and second sub-pixels are arranged in a matrix form. The array substrate further comprises a second insulating layer and a second metal layer, the second insulating layer being arranged between the first metal layer and the substrate; 7. The array substrate of claim 3, wherein, The second metal layer is arranged on a surface of the second insulating layer away from the first metal layer; The second insulating layer comprises a groove or a through hole, the vertical portion being arranged in the groove or the through hole. The projection of the second metal layer on the substrate covers the first metal blocks.

8. The array substrate of claim 7, wherein, The second insulating layer comprises a through hole, the vertical portion being arranged in the through hole and connected to the second metal layer.

9. The array substrate of claim 7, wherein, The conductive shielding structure further comprises a strip-shaped portion arranged on a side of the first insulating layer away from the first metal layer; the projection of the strip-shaped portion on the substrate covers the first metal blocks; one end of the vertical portion is connected to the strip-shaped portion, and the other end of the vertical portion is connected to the second metal layer.

10. The array substrate of claim 7, wherein, The first insulating layer comprises a stack of a first sub-insulating layer and a second sub-insulating layer; 11. The array substrate according to any one of claims 3-10, wherein, The array substrate further comprises a third metal layer arranged between the first sub-insulating layer and the second sub-insulating layer, the first sub-insulating layer being arranged between the third metal layer and the first metal layer; ​ The through hole penetrates the second sub-insulating layer, the third metal layer and the first sub-insulating layer, and the vertical part is located in the through hole and connected with the third metal layer.

12. The array substrate of claim 11, wherein, The third metal layer projects on the substrate and covers the first metal block.

13. The array substrate according to any one of claims 3-10, wherein, The fourth metal layer includes a plurality of second metal blocks extending along a second direction, and the second metal blocks are arranged at intervals along a first direction. The conductive shielding structure and the second metal block are staggered in the orthographic projection of the substrate.

14. The array substrate of claim 13, wherein, The second metal block is the scan line.

15. The array substrate of claim 13, wherein, The second metal block and the conductive shielding structure, except for the vertical part, are located in the same layer.

16. The array substrate of claim 13, wherein, In the first direction, the conductive shielding structure and the second metal block are spaced apart by a second preset distance.

17. A display panel, characterized by The array substrate includes any one of claims 1-16.

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