Display device

Abstract

A display device is provided. The display device includes a circuit layer having a drive circuit layer with a plurality of clock signal lines, a touch detection unit having a touch detection portion and a plurality of touch signal lines electrically connected to the touch detection unit, and a conductive portion disposed between the plurality of clock signal lines and the plurality of touch signal lines and configured to cover a superposition region in which the plurality of clock signal lines and the plurality of touch signal lines are superposed.

Description

[0001] This application is a divisional application of the invention patent application with application number 201710617342.1 filed with the State Intellectual Property Office of China on July 26, 2017, entitled "Display Device". Technical Field

[0002] The present invention generally relates to a display device, and more specifically, to a display device capable of providing substantially uniform touch sensitivity. Background Technology

[0003] Various display devices are being developed for multimedia devices such as televisions, mobile phones, tablets, navigators, and game consoles. Keyboards or mice are included as input devices for these display devices. Furthermore, recent display devices have incorporated touch detection units as input devices.

[0004] For example, touch detection units can be extremely sensitive in order to detect very slight touches or the differences between the valleys and ridges of a fingerprint for identification applications. When very close to signals emitted from a display device, even a sensitive touch detection unit can be affected and produce erroneous or inaccurate results.

[0005] The information disclosed in this background section is only intended to enhance the understanding of the background of the inventive concept. Therefore, the background section may contain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0006] One or more exemplary embodiments of the present invention provide a display device including a touch detection unit having uniform or more uniform touch sensitivity, the touch sensitivity being unaffected or minimally affected by noise in the touch sensor lines (e.g., noise emanating from a signal in a clock line of the display device).

[0007] Other aspects will be set forth in the following detailed description and will be apparent in part from this disclosure, or may be learned by practicing the inventive concept.

[0008] According to one aspect of the present invention, a display device includes: a substrate layer; a circuit layer disposed on the substrate layer and including a pixel circuit layer and a driving circuit layer, wherein the driving circuit layer is configured to provide signals for driving the pixel circuit layer and includes a plurality of clock signal lines; an organic light-emitting diode disposed on the circuit layer and including a first electrode electrically connected to the pixel circuit layer, an organic light-emitting layer disposed on the first electrode, and a second electrode disposed on the organic light-emitting layer; a thin film sealing layer disposed on the organic light-emitting diode; a touch detection unit disposed on the thin film sealing layer and including a touch detection portion and a plurality of touch signal lines electrically connected to the touch detection portion; and a conductive portion disposed between the plurality of clock signal lines and the plurality of touch signal lines and extending through an overlay region, wherein at least some of the plurality of clock signal lines and at least some of the touch signal lines are overlaid on each other in the overlay region.

[0009] In one embodiment, the conductive portion may be disposed on the same layer as the second electrode.

[0010] In an embodiment, the second electrode may extend toward the conductive portion, and the second electrode and the conductive portion may be connected to each other.

[0011] In an embodiment, the second electrode may be separated from the conductive portion.

[0012] In an embodiment, the display device may further include non-overlapping areas of at least one of the clock signal lines and at least one of the touch signal lines that do not overlap with each other.

[0013] In an embodiment, the plurality of through holes may be defined in the conductive portion and may not overlap with the overlapping region.

[0014] In an embodiment, the conductive portion may be disposed on the same layer as one of the first electrode and the second electrode.

[0015] In this embodiment, the multiple vias may not be superimposed on the multiple clock signal lines.

[0016] In this embodiment, the multiple vias may not overlap with the multiple touch signal lines.

[0017] In an embodiment, the conductive portion may include: a first region, superimposed on at least one of the clock signal lines and at least one of the touch signal lines, wherein a plurality of vias are not defined in the first region; a second region, wherein the region exposed by the plurality of vias has vias of a first region density; and a third region, wherein the region exposed by the plurality of vias has vias of a second region density lower than the first region density.

[0018] In an embodiment, the number of first through holes defined in each first surface region of the second region may be greater than the number of second through holes defined in each first surface region of the third region.

[0019] In an embodiment, the size of the first through hole defined in the second region may be larger than the size of the second through hole defined in the third region.

[0020] In an embodiment, the conductive portion may include: a first conductive layer disposed on the same layer as the first electrode and having a plurality of first through holes defined therethrough; and a second conductive layer disposed on the same layer as the second electrode.

[0021] In an embodiment, the second conductive layer may be stacked with a plurality of first vias.

[0022] In an embodiment, a plurality of second vias may be defined in a second conductive layer, and a plurality of first vias and a plurality of second vias may not overlap each other.

[0023] In an embodiment, multiple vias can be disposed in the second conductive layer, and the multiple second vias can be separate from multiple touch signal lines and multiple clock signal lines.

[0024] In an embodiment, the plurality of first vias may not be superimposed on the plurality of clock signal lines.

[0025] In an embodiment, the plurality of first vias may not overlap with the plurality of touch signal lines.

[0026] In an embodiment, the second electrode may extend toward the second conductive layer and the second electrode and the second conductive layer may be connected to each other.

[0027] In one embodiment, the second electrode may be separated from the second conductive layer.

[0028] In one embodiment, a constant voltage can be provided to the conductive portion.

[0029] According to another aspect of the present invention, a display device includes: a substrate layer; a circuit layer disposed on the substrate layer and including a pixel circuit layer and a driving circuit layer, wherein the driving circuit layer is configured to provide signals for driving the pixel circuit layer and includes a plurality of clock signal lines; an organic light-emitting diode disposed on the circuit layer and including a first electrode electrically connected to the pixel circuit layer, an organic light-emitting layer disposed on the first electrode, and a second electrode disposed on the organic light-emitting layer; a thin film sealing layer disposed on the organic light-emitting diode; a touch detection unit directly disposed on the thin film sealing layer and including a touch detection part and a plurality of touch signal lines electrically connected to the touch detection part; and a conductive part disposed between the plurality of clock signal lines and the plurality of touch signal lines.

[0030] In an embodiment, the conductive portion may include a first conductive layer disposed on the same layer as the first electrode and having a plurality of first through holes defined therethrough, and a second conductive layer disposed on the same layer as the second electrode.

[0031] In an embodiment, the second conductive layer may be stacked with a plurality of first vias.

[0032] In an embodiment, the plurality of first vias may not be superimposed on the plurality of clock signal lines.

[0033] In an embodiment, the plurality of first vias may not overlap with the plurality of touch signal lines. Attached Figure Description

[0034] The accompanying drawings illustrate exemplary embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. The drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification.

[0035] Figure 1A This is a perspective view of the first position of the display device DD according to the first embodiment constructed according to the principle of the present invention;

[0036] Figure 1B yes Figure 1A A perspective view of the second position of the display device;

[0037] Figure 1C yes Figure 1A A perspective view of the display device from the third position;

[0038] Figure 2 yes Figure 1A A cross-sectional side view of the display device;

[0039] Figure 3A and Figure 3B This is a perspective view of the second embodiment of the display device DD-1 constructed according to the principles of the present invention;

[0040] Figure 4A This is a perspective view of the third embodiment of the display device DD-2 constructed according to the principles of the present invention;

[0041] Figure 4B This is a perspective view of the fourth embodiment of the display device DD-3 constructed according to the principles of the present invention;

[0042] Figure 5A This is a plan view of an embodiment of an organic light-emitting display panel that can be used in the display device of the present invention;

[0043] Figure 5B This is a block diagram of an embodiment of a drive stage of a gate drive circuit that can be used in the display device of the present invention;

[0044] Figure 5C This is a schematic cross-sectional side view of an embodiment of a display module that can be used in the display device of the present invention;

[0045] Figure 6AThis is an equivalent circuit diagram of an embodiment of pixels that can be used in the display device of the present invention;

[0046] Figure 6B This is a partial cross-sectional side view of an embodiment of an organic light-emitting display panel that can be used in the display device of the present invention;

[0047] Figure 6C This is a partial cross-sectional side view of an embodiment of an organic light-emitting panel that can be used in the display device of the present invention;

[0048] Figures 7A to 7C This is a cross-sectional side view of an embodiment of a thin-film sealing layer that can be used in the display device of the present invention;

[0049] Figure 8A This is a cross-sectional side view of an embodiment of a touch detection unit that can be used in the display device of the present invention;

[0050] Figures 8B to 8E yes Figure 8A A partial top cross-sectional view of the touch detection unit in each layer;

[0051] Figure 8F yes Figure 8E A magnified view of region BB;

[0052] Figure 9A yes Figure 5C An enlarged section cross-sectional view of an embodiment of region AA;

[0053] Figure 9B yes Figure 9A An enlarged section sectional view of the WW region;

[0054] Figure 9C Is with Figure 9A A diagram similar to, but with the dashed outline of region WW removed;

[0055] Figure 9D yes Figure 5C An enlarged section sectional view of another embodiment of region AA;

[0056] Figure 10A yes Figure 5C An enlarged section sectional view of another embodiment of region AA;

[0057] Figure 10B yes Figure 10A An enlarged section sectional view of region XX;

[0058] Figure 10C yes Figure 5C An enlarged section sectional view of another embodiment of region AA;

[0059] Figure 10Dyes Figure 10C An enlarged section sectional view of region YY;

[0060] Figure 11A yes Figure 5C An enlarged section sectional view of another embodiment of region AA;

[0061] Figure 11B yes Figure 11A An enlarged section sectional view of region ZZ;

[0062] Figure 11C yes Figure 5C An enlarged section sectional view of another embodiment of region AA;

[0063] Figure 12A yes Figure 5C An enlarged section sectional view of another embodiment of region AA;

[0064] Figure 12B yes Figure 12A An enlarged plan view of a portion of an embodiment;

[0065] Figure 12C yes Figure 12A An enlarged fragment plan view of another embodiment of a display device;

[0066] Figure 13A yes Figure 5C An enlarged section sectional view of another embodiment of region AA;

[0067] Figure 13B yes Figure 13A An enlarged plan view of a portion of an embodiment;

[0068] Figure 14A yes Figure 5C An enlarged fragment sectional view of another embodiment of region AA; and

[0069] Figure 14B yes Figure 14A An enlarged fragment plan view of an embodiment. Detailed Implementation

[0070] In the following description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of the various exemplary embodiments. However, it will be apparent that the various exemplary embodiments may be practiced without these specific details, or may be practiced with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments.

[0071] In the accompanying drawings, for clarity and descriptive purposes, the dimensions and relative dimensions of layers, films, panels, areas, etc., may be exaggerated. Furthermore, the same reference numerals indicate the same elements.

[0072] When an element or layer is referred to as being "on," "connected to," or "bonded to" another element or layer, the element or layer may be directly on, directly connected to, or directly bonded to the other element or layer, or intermediate elements or layers may exist. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly bonded to" another element or layer, no intermediate elements or layers exist. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. The same reference numerals always denote the same element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0073] Although the terms first, second, etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, and / or portion from another element, component, region, layer, and / or portion. Therefore, without departing from the teachings of this disclosure, the first element, first component, first region, first layer, and / or first portion discussed below may be designated as a second element, second component, second region, second layer, and / or second portion.

[0074] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “above,” and “above” may be used herein to describe the relationship between one element or feature as shown in the figure and another element or feature. Spatial relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture other than those depicted in the figure. For example, if the device in the figure were flipped, an element described as “below” or “under” another element or feature would subsequently be positioned “above” said other element or feature. Thus, the exemplary term “below” can encompass both “above” and “below” orientations. Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), thus interpreting the spatial relative descriptive terms used herein accordingly.

[0075] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the” are intended to include the plural forms as well. Furthermore, when the terms “comprising” and variations thereof and / or “including” and variations thereof are used in this specification, it indicates the presence of the described features, integrals, steps, operations, elements, components, and / or groups thereof, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0076] Various exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized exemplary embodiments and / or intermediate structures. Thus, variations in the shapes shown will be expected, for example, due to manufacturing techniques and / or tolerances. Therefore, the exemplary embodiments disclosed herein should not be construed as limited to the specific shapes shown for the regions, but will include deviations in shape, for example, due to manufacturing processes. For example, an implanted region shown as rectangular will typically have rounded or curved features at its edges and / or a gradient of implanted concentration, rather than a binary variation from an implanted region to a non-implanted region. Similarly, the buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to be limiting.

[0077] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Unless so explicitly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formalized sense.

[0078] like Figure 1AAs shown, in the first operating mode of the display device DD, the display surface IS of the displayed image IM is a surface extending along the first direction DR1 and the second direction DR2. The display surface IS has a thickness in a third direction DR3 perpendicular to the first two directions. The front surface (or upper surface) and rear surface (lower surface) of each component are separated in the third direction DR3. However, since the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 can be rearranged or redefined. In the following, the first direction to the third direction, which are the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 respectively, will be indicated by the same reference numerals.

[0079] Figures 1A to 1C as well as Figures 3A to 4B A flexible, foldable display device is shown as an example of a display device DD. However, the inventive concept can relate to rollable or bendable display devices and is not specifically limited thereto. Furthermore, although flexible display devices are shown in these embodiments, the inventive concept is not limited thereto. The display device DD can be a flat rigid display device or a curved rigid display device. In addition to being used in large-sized electronic devices such as televisions and monitors, the display device DD can also be used in small and medium-sized electronic devices such as mobile phones, tablets, car navigation systems, game consoles, and smartwatches.

[0080] like Figure 1A As shown, the display surface IS of the display device DD may include multiple areas. The display device DD may include a display area DD-DA for displaying an image IM and a non-display area DD-NDA adjacent to the display area DD-DA. The non-display area DD-NDA may be an area where no image is displayed. Figure 1A An example of using a vase as an image IM is shown. The display area DD-DA can have a rectangular form as shown. The non-display area DD-NDA can surround the display area DD-DA. However, the inventive concept is not limited thereto, and in other embodiments, the form or shape of the display area DD-DA and the non-display area DD-NDA can be changed.

[0081] like Figures 1A to 1C As shown, the display device DD may include multiple regions defined according to the mode of operation. The display device DD may include a curved region BA that bends around the bending axis BX, a first non-curved region NBA1, and a second non-curved region NBA2.

[0082] like Figure 1BAs shown, the display device DD can be bent inward so that the display surface IS of the first non-bent region NBA1 and the display surface IS of the second non-bent region NBA2 face each other. Figure 1C As shown, the display device DD can be bent outward so that the display surface IS is exposed to the outside.

[0083] Although Figures 1A to 1C Only one curved region BA is shown in the diagram, but the inventive concept is not limited thereto. For example, according to an embodiment of the inventive concept, the display device DD may include multiple curved regions BA.

[0084] According to an embodiment of the present invention, the display device DD can be configured to repeat only Figure 1A and Figure 1B The operating mode is shown in the diagram. However, the inventive concept is not limited thereto, and the curved region BA can be defined as the position where the user operates the display device DD. For example, different from... Figure 1B and Figure 1C The curved region BA can be defined as parallel to the first direction DR1 and can be defined as diagonally. The area of ​​the curved region BA is not fixed and can be determined according to the radius of curvature.

[0085] Figure 2 A cross-sectional view is shown, taken in the plane of the first direction DR1 and the third direction DR3.

[0086] like Figure 2 As shown, the display device DD includes a protective film PM, a display module DM, an optical component LM, a window WM, a first adhesive component AM1, a second adhesive component AM2, and a third adhesive component AM3. The display module DM is disposed between the protective film PM and the optical component LM. The optical component LM is disposed between the display module DM and the window WM. The first adhesive component AM1 bonds the display module DM and the protective film PM; the second adhesive component AM2 bonds the display module DM and the optical component LM; and the third adhesive component AM3 bonds the optical component LM and the window WM.

[0087] The protective film PM protects the display module DM. The protective film PM provides a first outer surface OS-L exposed to the outside and provides an adhesive surface for adhesion to the first adhesive member AM1. The protective film PM prevents external moisture from penetrating the display module DM and absorbs forces from external impacts.

[0088] The protective film PM may include a plastic film as a substrate. The protective film PM may include a plastic film comprising one selected from the group consisting of polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), poly(arylene ethersulfone), and combinations thereof.

[0089] The materials constituting the protective film PM are not limited to plastic resins and may include organic / inorganic composite materials. The protective film PM may include an inorganic material filling the pores of a porous organic layer and the organic layer. The protective film PM may also include a functional layer formed on the plastic film. The functional layer may include a resin layer. The functional layer may be formed by a coating method. The protective film PM may also be omitted.

[0090] The window WM protects the display module DM from damage caused by external impacts and provides an input surface for the user. The window WM provides a second external surface OS-U exposed to the outside and also provides an adhesive surface for adhesion to the second adhesive member AM2. Figures 1A to 1C The display surface IS shown can be the second outer surface OS-U.

[0091] Window WM may include a plastic film. Window WM may have a multi-layer structure. Window WM may have a multi-layer structure selected from glass substrate, plastic film, and plastic substrate. Window WM may also include a frame pattern. The multi-layer structure can be formed by a continuous process or by an adhesive process using adhesive layers.

[0092] Optical component LM reduces the reflection of external light. Optical component LM may at least include a polarizing film. Optical component LM may also include a retardation film. In embodiments of the present invention, optical component LM may be omitted.

[0093] The display module DM may include an organic light-emitting display panel (or display panel) DP and a touch detection unit TS. The touch detection unit TS may be directly disposed on the organic light-emitting display panel DP. In this specification, "directly disposed" means "formed" by a continuous process, excluding "attached" by an additional adhesive layer.

[0094] The organic light-emitting display panel (DP) generates an image IM corresponding to the input image data (see...). Figure 1A The organic light-emitting display panel DP provides a first display panel surface BS1-L and a second display panel surface BS1-U opposite to each other on the third-direction DR3. In this embodiment, although the organic light-emitting display panel DP is described exemplarily, the display panel is not limited thereto.

[0095] The touch detection unit TS obtains the coordinate information of external input. The touch detection unit TS can detect external input using a capacitive method.

[0096] The display module DM according to an embodiment of the present invention may further include an anti-reflective layer (not shown). The anti-reflective layer may include a color filter or a stacked structure of conductive / insulating / conductive layers. The anti-reflective layer reduces the reflection of external light by absorbing externally incident light, causing destructive interference of externally incident light, or polarizing externally incident light. The anti-reflective layer can replace the function of the optical component LM.

[0097] Each of the first adhesive component AM1, the second adhesive component AM2, and the third adhesive component AM3 can be an organic adhesive layer such as an optically transparent adhesive (OCA) film, an optically transparent resin (OCR), or a pressure-sensitive adhesive (PSA) film. The organic adhesive layer can include adhesive materials such as polyurethane, polyacrylate, polyester, polyepoxy resin, and polyvinyl acetate.

[0098] The display device DD may also include a supporting functional layer to maintain Figures 1A to 1C The frame structure (not shown) is located at the position indicated. The frame structure may include a hinge structure or a hinge chain structure.

[0099] Figure 3A The display device DD-1 in its unfolded state is shown. Figure 3B The display device DD-1 is shown in a bent state.

[0100] Display device DD-1 may include a curved region BA and a non-curved region NBA. The non-display region DD-NDA of display device DD-1 may be flexible. In other embodiments, the curved region of display device DD-1 may be different.

[0101] Unlike Figures 1A to 1C The display device DD shown herein, display device DD-1, can be fixed in a certain shape and operated. For example... Figure 3B As shown, the display device DD-1 can operate in a bent state. The display device DD-1 can be fixed to the frame in a bent state, and the frame can be attached to the housing of the electronic device.

[0102] The display device DD-1 can have the same Figure 2 The cross-sectional structure shown is the same as the cross-sectional structure. However, the non-curved region NBA and the curved region BA can have different stacked structures. The non-curved region NBA can have the same cross-sectional structure as... Figure 2 The cross-sectional structure shown is the same as the cross-sectional structure shown, and the curved region BA can have the same cross-sectional structure. Figure 2The cross-sectional structures shown are different. Optical components LM and WM may not be located in the curved region BA. For example, optical components LM and WM may only be located in the non-curved region NBA. Similarly, the second adhesive component AM2 and the third adhesive component AM3 may also not be located in the curved region BA.

[0103] Now refer to Figure 4A The display device DD-2 includes a non-curved area (or flat area) NBA on its front surface that displays a main image and curved areas (or side areas) on its side surfaces that display sub-images. Although not shown in the figures, the sub-images may include icons for providing predetermined information. In this embodiment, the terms "non-curved area NBA" and "curved area BA" define the display device DD-2 by using multiple areas divided by curved forms or states.

[0104] The curved area BA, which curves from the non-curved area NBA, displays a sub-image on the fourth direction DR4, which intersects with the first direction DR1, the second direction DR2, and the third direction DR3. However, other relative directions can also be used.

[0105] Reference Figure 4B The display device DD-3 includes a non-curved area NBA on its front surface that displays a main image and a first curved area BA1 and a second curved area BA2 on its side surfaces that display a sub-image. The first curved area BA1 and the second curved area BA2 can be curved from opposite sides of the non-curved area NBA.

[0106] like Figure 5A As shown, the organic light-emitting display panel DP includes a display area DA and a non-display area NDA located in a plane. The display area DA and the non-display area NDA of the organic light-emitting display panel DP can be respectively connected to the display device DD (see...). Figure 1A The display area DD-DA (see) Figure 1A ) and non-display area DD-NDA (see Figure 1A The display area DA and non-display area NDA of an organic light-emitting display panel DP do not necessarily need to correspond with the display device DD (see...). Figure 1A The display area DD-DA (see) Figure 1A ) and non-display area DD-NDA (see Figure 1A It is the same as that of the organic light-emitting display panel (DP), and can be changed according to the structure / design of the DP.

[0107] An organic light-emitting display panel (DP) includes multiple pixels (PX). The area where the multiple pixels (PX) are located can be defined as a display area (DA). In this embodiment, a non-display area (NDA) can be defined along the contour surrounding the display area (DA).

[0108] An organic light-emitting display panel (DP) includes gate lines (GL), data lines (DL), light-emitting lines (EL), control signal lines (SL-D), initialization voltage lines (SL-Vint), voltage lines (SL-VDD), power supply lines (E-VSS), and pads (PD).

[0109] Gate lines GL are connected to corresponding pixels PX among a plurality of pixels PX, and data lines DL are connected to corresponding pixels PX among a plurality of pixels PX. Each light-emitting line EL can be arranged parallel to the corresponding gate line GL among the gate lines GL. Control signal lines SL-D can provide control signals to the gate drive circuit GDC. Initialization voltage line SL-Vint can provide an initialization voltage to the plurality of pixels PX. Voltage line SL-VDD can be connected to the plurality of pixels PX and provide a first voltage to the plurality of pixels PX. Voltage line SL-VDD can include multiple lines extending in a first direction DR1 and multiple lines extending in a second direction DR2. Power supply line E-VSS can surround three sides of display area DA and can be disposed in non-display area NDA. A common voltage (e.g., a second voltage) can be provided to the plurality of pixels PX of power supply line E-VSS. The common voltage can have a voltage level lower than the first voltage.

[0110] The gate drive circuit GDC at the connection between the gate line GL and the light-emitting line EL can be located on the side of the non-display area NDA. Some of the gate line GL, data line DL, light-emitting line EL, control signal lines SL-D, initialization voltage line SL-Vint, voltage line SL-VDD, and power supply line E-VSS are located on the same layer, while others are located on another layer.

[0111] The pad section PD can be connected to the ends of the data line DL, control signal line SL-D, initialization voltage line SL-Vint, and voltage line SL-VDD.

[0112] Figure 5B An example of a drive stage GDSi connected to the i-th gate line GLi and the i-th light-emitting line ELi in a drive stage of a plurality of gate drive circuits GDC is shown.

[0113] The driver stage GDSi may include an emission control stage EC-Ci and a gate driver stage GC-Ci. Emission control signals CLK1, CLK2, VGL, VGH, and EMFLM can be provided to the emission control stage EC-Ci via a first clock signal line CL1, a second clock signal line CL2, a first voltage line VL1, a second voltage line VH1, and a first start signal line EF1. Gate control signals CLK3, CLK4, VGH1, VGL1, and FLM can be provided to the gate driver stage GC-Ci via a third clock signal line CL3, a fourth clock signal line CL4, a third voltage line VL2, a fourth voltage line VH2, and a second start signal line EF2.

[0114] Although, as described, the gate drive stage GC-Ci of the light emission control stage EC-Ci is included in a drive stage GDSi, the inventive concept is not limited thereto. For example, the light emission control stage EC-Ci and the gate drive stage GC-Ci may be included in another drive stage.

[0115] The light control level EC-Ci may include a first clock terminal CK1, a second clock terminal CK2, a first voltage input terminal VPL1, a second voltage input terminal VPH1, an input terminal IN, a carry terminal CR, and an output terminal OUT1.

[0116] The first clock terminal CK1 receives the first clock signal CLK1, and the second clock terminal CK2 receives the second clock signal CLK2. The first clock signal CLK1 and the second clock signal CLK2 may have different phases. The second clock signal CLK2 may be obtained by reversing or delaying the phase of the first clock signal CLK1.

[0117] The first voltage input terminal VPL1 receives the first voltage VGL, and the second voltage input terminal VPH1 receives the second voltage VGH. The voltage level of the first voltage VGL can be lower than the voltage level of the second voltage VGH.

[0118] The input terminal IN can receive the carry signal from the previous light-emitting control stage EC-Ci-1 (not shown), and the carry terminal CR can output the carry signal from the next light-emitting control stage EC-Ci+1 (not shown). The output terminal OUT1 can provide the light-emitting control signal generated from the light-emitting control stage EC-Ci to the light-emitting line ELi.

[0119] The start signal EMFLM can be input to the input terminal IN of the first light control stage EC-C1 in the light control stage.

[0120] The gate driver stage GC-Ci may include a third clock terminal CK3, a fourth clock terminal CK4, a third voltage input terminal VPL2, a fourth voltage input terminal VPH2, an input terminal IN, a carry terminal CR, and an output terminal OUT2.

[0121] The third clock terminal CK3 receives the third clock signal CLK3, and the fourth clock terminal CK4 receives the fourth clock signal CLK4. The third clock signal CLK3 and the fourth clock signal CLK4 can have different phases. The fourth clock signal CLK4 can be obtained by reversing or delaying the phase of the third clock signal CLK3.

[0122] The third voltage input terminal VPL2 receives the third voltage VGL1, and the fourth voltage input terminal VPH2 receives the fourth voltage VGH1. The voltage level of the third voltage VGL1 can be lower than the voltage level of the fourth voltage VGH1.

[0123] The input terminal IN can receive the carry signal from the previous gate driver stage GC-Ci-1 (not shown), and the carry terminal CR can output the carry signal from the next gate driver stage GC-Ci+1 (not shown). The output terminal OUT2 can provide the gate signal generated from the gate driver stage GC-Ci to the gate line GLi.

[0124] The start signal FLM can be input to the input terminal IN of the first gate drive stage GC-C1 (not shown) of multiple gate drive stages.

[0125] According to embodiments of the present invention, one of the following terminals may be omitted from the light emission control stage EC-Ci: the first clock terminal CK1, the second clock terminal CK2, the first voltage input terminal VPL1, the second voltage input terminal VPH1, the input terminal IN, the carry terminal CR, and the output terminal OUT1; or other terminals may be included. For example, the carry terminal CR may be omitted.

[0126] According to embodiments of the present invention, one of the following terminals of the gate drive stage GC-Ci—the third clock terminal CK3, the fourth clock terminal CK4, the third voltage input terminal VPL2, the fourth voltage input terminal VPH2, the input terminal IN, the carry terminal CR, and the output terminal OUT2—may be omitted, or other terminals may be included. For example, the carry terminal CR may be omitted.

[0127] Furthermore, although the example shows the input terminal IN of the light emission control stage EC-Ci and the input terminal IN of the gate drive stage GC-Ci respectively connected to the carry terminal of the previous stage, the inventive concept is not limited thereto. In other embodiments, the connections between the drive stages can be varied in various ways.

[0128] like Figure 5C As shown, the organic light-emitting display panel DP includes a substrate layer SUB, a circuit layer DP-CL disposed on the substrate layer SUB, a light-emitting element layer DP-OLED, and a thin film sealing layer TFE.

[0129] The substrate layer SUB can include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite substrate as a flexible substrate. The plastic substrate can include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0130] The DP-CL circuit layer may include a semiconductor layer, multiple insulating layers, and multiple conductive layers. The multiple conductive layers of the DP-CL circuit layer can constitute control circuitry for signal lines or pixels. The DP-CL circuit layer may include a pixel circuit layer DP-PCL disposed in the display area DA and a drive circuit layer DP-DCL disposed in the non-display area NDA. The pixel circuit layer DP-PCL may include the above-referenced... Figure 5A The circuitry described includes the gate line GL, data line DL, light-emitting line EL, initialization voltage line SL-Vint, voltage line SL-VDD, and pixel PX.

[0131] The driver circuit layer DP-DCL can include the above reference. Figure 5A The described gate drive circuit GDC and control signal line SL-D are described. The control signal line SL-D may include... Figure 5B The diagram shows a first clock signal line CL1, a second clock signal line CL2, a third clock signal line CL3, a fourth clock signal line CL4, a first voltage line VL1, a second voltage line VH1, a third voltage line VL2, a fourth voltage line VH2, a first start signal line EF1, and a second start signal line EF2. The first clock signal line CL1, the second clock signal line CL2, the third clock signal line CL3, and the fourth clock signal line CL4 can be collectively referred to as clock signal lines.

[0132] The light-emitting element layer of DP-OLED includes organic light-emitting diodes and a pixel-defining layer.

[0133] A thin-film sealing layer (TFE) seals the DP-OLED light-emitting element layer. The TFE layer may comprise at least two inorganic layers and an organic layer disposed between the two inorganic layers. The inorganic layers protect the DP-OLED light-emitting element layer from moisture and oxygen, while the organic film protects the DP-OLED light-emitting element layer from foreign matter such as dust particles.

[0134] The touch detection unit TS is disposed on the thin-film sealing layer TFE. The touch detection unit TS can be directly disposed on the thin-film sealing layer TFE. However, the inventive concept is not limited thereto; a buffer layer can be disposed on the thin-film sealing layer TFE, and the touch detection unit TS can be directly disposed on the buffer layer. The buffer layer can be an inorganic layer or an organic layer. The inorganic layer can include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide. The organic layer can include a polymer (e.g., an acrylic polymer) organic layer. However, this is exemplary and the inventive concept is not limited thereto. Although the buffer layer is described as a separate component, the buffer layer can be a component included in the thin-film sealing layer TFE.

[0135] The touch detection unit TS includes a touch detection section TSP and touch signal lines TSL. The touch detection section TSP and touch signal lines TSL can have a single-layer or multi-layer structure. The touch detection section TSP and touch signal lines TSL can include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, and graphene. The touch detection section TSP and touch signal lines TSL can include metal layers, such as molybdenum, silver, titanium, copper, aluminum, or alloys thereof. The touch detection section TSP and touch signal lines TSL can have the same or different layer structures. The specific details of the touch detection unit TS will be described later.

[0136] Figure 6A This illustrates how the i-th pixel PXi can be connected to multiple data lines DL (see...). Figure 5A The k-th data line DLk in ).

[0137] The i-th pixel PXi includes an organic light-emitting diode (OLED) and a pixel driving circuit for controlling the OLED. The pixel driving circuit may include seven thin-film transistors T1 to T7 and a capacitor Cst.

[0138] The driving transistor controls the driving current supplied to the organic light-emitting diode (OLED). The output electrode of the second transistor T2 is electrically connected to the OLED. The output electrode of the second transistor T2 can directly contact the first electrode of the OLED or can be connected to the OLED via another transistor (e.g., the sixth transistor T6 in this embodiment).

[0139] The control electrode of the control transistor can receive control signals. The control signal applied to the i-th pixel PXi may include the (i-1)-th gate signal Si-1, the i-th gate signal Si, the (i+1)-th gate signal Si+1, the data signal Dk, and the i-th light emission control signal Ei. According to an embodiment of the present invention, the control transistor may include a first transistor T1 and third transistors T3 to seventh transistors T7.

[0140] The first transistor T1 includes an input electrode connected to the k-th data line DLk, a control electrode connected to the i-th gate line GLi, and an output electrode connected to the output electrode of the second transistor T2. The first transistor T1 is turned on by a gate signal Si (hereinafter referred to as the i-th gate signal) applied to the i-th gate line GLi and provides the data signal DK applied to the k-th data line DLk to the capacitor Cst.

[0141] Figure 6B yes Figure 6A The diagram shows a cross-sectional view of the first transistor T1 in the equivalent circuit. Figure 6C yes Figure 6A The diagram shows a cross-sectional view of the second transistor T2, the sixth transistor T6, and the organic light-emitting diode (OLED) in the equivalent circuit.

[0142] Reference Figure 6B and Figure 6C A buffer layer BFL can be disposed on the substrate layer SUB. The buffer layer BFL improves the bonding strength between the substrate layer SUB and the conductive or semiconductor pattern. The buffer layer BFL may include an inorganic layer. Although not shown in the figures, a barrier layer for preventing foreign matter ingress may also be disposed on the upper surface of the substrate layer SUB. In various exemplary embodiments, the buffer layer BFL and the barrier layer may be selectively included or omitted.

[0143] Semiconductor pattern OSP1 (hereinafter referred to as the first semiconductor pattern), semiconductor pattern OSP2 (hereinafter referred to as the second semiconductor pattern), and semiconductor pattern OSP6 (hereinafter referred to as the sixth semiconductor pattern) of the first transistor T1 and the sixth transistor T6 are disposed on the buffer layer BFL. The first semiconductor pattern OSP1, the second semiconductor pattern OSP2, and the sixth semiconductor pattern OSP6 can be fabricated from materials selected from amorphous silicon, polycrystalline silicon, and metal oxide semiconductors.

[0144] The first insulating layer 10 can be disposed on the first semiconductor pattern OSP1, the second semiconductor pattern OSP2, and the sixth semiconductor pattern OSP6. Although Figure 6B and Figure 6C The diagram shows that the first insulating layer 10 is configured as an unpatterned layer for covering the first semiconductor pattern OSP1, the second semiconductor pattern OSP2, and the sixth semiconductor pattern OSP6. However, the first insulating layer 10 may be configured as a patterned layer corresponding to the first semiconductor pattern OSP1, the second semiconductor pattern OSP2, and the sixth semiconductor pattern OSP6.

[0145] The first insulating layer 10 may include multiple inorganic thin films. The multiple inorganic thin films may include a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer.

[0146] The control electrode GE1 (hereinafter referred to as the first control electrode), the control electrode GE2 (hereinafter referred to as the second control electrode), and the control electrode GE6 (hereinafter referred to as the sixth control electrode) of the first transistor T1, the second transistor T2, and the sixth transistor T6 are disposed on the first insulating layer 10. This can be connected to the gate line GL (see...). Figure 5A The first control electrode GE1, the second control electrode GE2, and the sixth control electrode GE6 are manufactured using the same photolithography process.

[0147] A second insulating layer 20 for covering the first control electrode GE1, the second control electrode GE2, and the sixth control electrode GE6 may be disposed on the first insulating layer 10. The second insulating layer 20 may provide a flat upper surface. The second insulating layer 20 may include organic and / or inorganic materials.

[0148] The input electrode SE1 (hereinafter referred to as the first input electrode) and output electrode DE1 (hereinafter referred to as the first output electrode) of the first transistor T1, the input electrode SE2 (hereinafter referred to as the second input electrode) and output electrode DE2 (hereinafter referred to as the second output electrode) of the second transistor T2, and the input electrode SE6 (hereinafter referred to as the sixth input electrode) and output electrode DE6 (hereinafter referred to as the sixth output electrode) of the sixth transistor T6 are disposed on the second insulating layer 20.

[0149] Each of the first output electrode DE1 and the first input electrode SE1 is connected to the first semiconductor pattern OSP1 through a first via CH1 penetrating the first insulating layer 10 and the second insulating layer 20 or a second via CH2 penetrating the first insulating layer 10 and the second insulating layer 20. Each of the second input electrode SE2 and the second output electrode DE2 is connected to the second semiconductor pattern OSP2 through a third via CH3 penetrating the first insulating layer 10 and the second insulating layer 20 or a fourth via CH4 penetrating the first insulating layer 10 and the second insulating layer 20. Each of the sixth input electrode SE6 and the sixth output electrode DE6 is connected to the sixth semiconductor pattern OSP6 through a fifth via CH5 penetrating the first insulating layer 10 and the second insulating layer 20 or a sixth via CH6 penetrating the first insulating layer 10 and the second insulating layer 20. Alternatively, according to other embodiments of the present invention, some of the first transistor T1, the second transistor T2, and / or the sixth transistor T6 can be modified and implemented as a bottom-gate structure.

[0150] A third insulating layer 30 is disposed on the second insulating layer 20 to cover the first input electrode SE1, the second input electrode SE2, the sixth input electrode SE6, the first output electrode DE1, the second output electrode DE2, and the sixth output electrode DE6. The third insulating layer 30 may include an organic layer and / or an inorganic layer. The third insulating layer 30 may include an organic material for providing a flat surface.

[0151] In various exemplary embodiments, one or more of the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30 may be omitted. Each of the second insulating layer 20 and the third insulating layer 30 may be defined as an interlayer insulating layer. The interlayer insulating layer is disposed between the conductive pattern disposed at the lower part and the conductive pattern disposed at the upper part to insulate the conductive patterns from each other.

[0152] The pixel-defining layer (PDL) and the organic light-emitting diode (OLED) are disposed on the third insulating layer 30. (See reference) Figure 6C Each organic light-emitting diode (OLED) may include a first electrode AE, a second electrode CE, a hole control layer HCL, an organic light-emitting layer EML, and an electronic control layer ECL. Specifically, the first electrode AE ​​may be disposed in the circuit layer DP-CL (see...). Figure 5C The organic light-emitting layer (EML) can be disposed on the first electrode AE. The second electrode CE can be disposed on the organic light-emitting layer (EML).

[0153] A first electrode AE ​​is disposed on the third insulating layer 30. Here, the first electrode AE ​​can be configured as an anode or a cathode. In the following description, the first electrode AE ​​is described as an anode. The first electrode AE ​​is connected to the sixth output electrode DE6 via a seventh through-hole CH7 penetrating the third insulating layer 30. An opening OP is defined in the pixel defining layer PDL. The opening OP of the pixel defining layer PDL exposes at least a portion of the first electrode AE.

[0154] Pixel PX can be disposed in a pixel region on a plane. The pixel region may include a light-emitting region PXA and a non-light-emitting region NPXA adjacent to the light-emitting region PXA. The non-light-emitting region NPXA may surround the light-emitting region PXA. According to this embodiment, the light-emitting region PXA corresponds to the portion of the first electrode AE ​​exposed through the opening OP.

[0155] A hole control layer (HCL) can be set in the emitting region PXA and the non-emitting region NPXA. Although not shown in the figure, a common layer such as the hole control layer HCL can be formed in multiple pixels PX (see figure). Figure 5A )middle.

[0156] An organic light-emitting layer (EML) is disposed on a hole control layer (HCL). The EML can be disposed in the region corresponding to the opening (OP). That is, the EML can be separated and formed at each of multiple pixels. Using a patterned EML as shown in this embodiment, the EML can be disposed at multiple pixels (PX), where the EML can generate white light. Furthermore, the EML can have a multilayer structure.

[0157] An electronic control layer (ECL) is disposed on the organic light-emitting layer (EML). Although not shown in the figure, the ECL can be formed over multiple pixel PXs (see figure). Figure 5A ) place.

[0158] The second electrode CE is disposed on the electronic control layer ECL at multiple pixel PX locations. Here, the second electrode CE can be set as an anode or a cathode. In the following text, the second electrode CE is described as a cathode. That is, when the first electrode AE ​​can be set as an anode, the second electrode CE can be set as a cathode. Furthermore, when the first electrode AE ​​can be set as a cathode, the second electrode CE can be set as an anode.

[0159] A thin-film sealing layer (TFE) is disposed on the second electrode (CE). The TFE is disposed at multiple pixels (PX). The TFE comprises at least one inorganic layer and at least one organic layer. The TFE may also comprise multiple inorganic layers and multiple organic layers stacked alternately.

[0160] In the exemplary embodiment shown, the thin-film sealing layer TFE directly covers the second electrode CE. A covering layer for covering the second electrode CE may also be disposed between the thin-film sealing layer TFE and the second electrode CE. The thin-film sealing layer TFE may directly cover the covering layer.

[0161] In the following text, refer to Figures 7A to 7C Describe the thin film sealing layers TFE1, TFE2 and TFE3.

[0162] like Figure 7A As shown, the thin-film sealing layer TFE1 may include n inorganic thin films IOL1 to IOLn, with the first inorganic thin film IOL1 contacting the second electrode CE (see...). Figure 6C The first inorganic film IOL1 can be defined as the lower inorganic film, and the other inorganic films among the n inorganic films IOL1 to IOLn, except for the first inorganic film IOL1, can be defined as the upper inorganic films.

[0163] The thin-film sealing layer TFE1 may include n-1 organic thin films OL1 to OLn-1, and the n-1 organic thin films OL1 to OLn-1 and the n inorganic thin films IOL1 to IOLn may be alternately arranged. The n-1 organic thin films OL1 to OLn-1 may have an average thickness that is greater than the average thickness of the n inorganic thin films IOL1 to IOLn.

[0164] Each of the n inorganic films IOL1 to IOLn can be a single layer comprising one material or multiple layers each comprising different materials. Each of the n-1 organic films OL1 to OLn-1 can be formed by depositing or printing organic monomers. For example, each of the n-1 organic films OL1 to OLn-1 can be formed by inkjet printing or by coating a composite containing acrylic monomers. In embodiments of the present invention, the film sealing layer TFE1 may further comprise the nth organic film.

[0165] like Figure 7B and Figure 7C As shown, the inorganic films included in each of the film sealing layers TFE2 and TFE3 may have the same or different inorganic materials and may have the same or different thicknesses. Similarly, the organic films included in each of the film sealing layers TFE2 and TFE3 may have the same or different organic materials and may have the same or different thicknesses.

[0166] like Figure 7B As shown, the thin film sealing layer TFE2 may include a first inorganic thin film IOL1, a first organic thin film OL1, a second inorganic thin film IOL2, a second organic thin film OL2 and a third inorganic thin film IOL3 stacked in sequence.

[0167] The first inorganic thin film IOL1 can have a two-layer structure. The first sublayer S1 and the second sublayer S2 can include different inorganic materials.

[0168] like Figure 7C As shown, the thin-film sealing layer TFE3 may include a first inorganic thin film IOL10, a first organic thin film OL1, and a second inorganic thin film IOL20 stacked sequentially. The first inorganic thin film IOL10 may have a two-layer structure. The first sublayer S10 and the second sublayer S20 may include different inorganic materials. The second inorganic thin film IOL20 may also have a two-layer structure. The second inorganic thin film IOL20 may include a first sublayer S100 and a second sublayer S200 deposited in different deposition environments and / or stages. The first sublayer S100 may be deposited under low-power conditions, and the second sublayer S200 may be deposited under high-power conditions. The first sublayer S100 and the second sublayer S200 may include the same inorganic material.

[0169] like Figure 8AAs shown, the touch detection unit TS includes a first conductive layer TS-CL1, a first insulating layer TS-IL1 (hereinafter referred to as the first touch insulating layer), a second conductive layer TS-CL2, and a second insulating layer TS-IL2 (hereinafter referred to as the second touch insulating layer). The first conductive layer TS-CL1 is directly disposed on the thin film sealing layer TFE. The invention is not limited thereto; another buffer layer (e.g., an inorganic or organic layer) may also be disposed between the first conductive layer TS-CL1 and the thin film sealing layer TFE. In another embodiment of the invention, a plastic film, a glass substrate, or a plastic substrate may be disposed between the first conductive layer TS-CL1 and the thin film sealing layer TFE.

[0170] Each of the first conductive layer TS-CL1 and the second conductive layer TS-CL2 may comprise a monolayer structure or a multilayer structure stacked on a third-direction DR3. The multilayer conductive layer may comprise at least two transparent conductive layers and a metal layer. The multilayer conductive layer may comprise metal layers with different metals. The transparent conductive layer may comprise indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, and graphene. The metal layer may comprise silver, titanium, copper, aluminum, and their alloys.

[0171] Each of the first conductive layer TS-CL1 and the second conductive layer TS-CL2 includes multiple patterns. Hereinafter, the first conductive layer TS-CL1 includes a first conductive pattern, and the second conductive layer TS-CL2 includes a second conductive pattern. Each of the first and second conductive patterns may include a touch electrode and a touch signal line.

[0172] Each of the first touch insulating layer TS-IL1 and the second touch insulating layer TS-IL2 may have a single-layer or multi-layer structure. Each of the first touch insulating layer TS-IL1 and the second touch insulating layer TS-IL2 may include at least one of an inorganic layer and an organic layer.

[0173] The first touch insulating layer TS-IL1 insulates the first conductive layer TS-CL1 and the second conductive layer TS-CL2, and its form is not limited to the exemplary embodiments described. In various exemplary embodiments, the form of the first touch insulating layer TS-IL1 may be varied. For example, the first touch insulating layer TS-IL1 may completely cover the thin-film sealing layer TFE and / or may include multiple insulating patterns. The multiple insulating patterns may be superimposed with the first connection portion CP1 and may be superimposed with the second connection portion CP2, which will be described later.

[0174] While an exemplary embodiment of a dual-layer touch detection unit has been shown, the inventive concept is not limited to this embodiment. A single-layer touch detection unit includes a conductive layer and an insulating layer for covering the conductive layer. The conductive layer includes a touch sensor and touch signal lines connected to the touch sensor. The single-layer touch detection unit can obtain coordinate information using a self-capture sensing method.

[0175] like Figure 8B As shown, the touch detection unit TS may include a touch detection section TSP (see...) Figure 5C ), Touch signal line TSL (see Figure 5C ) and the pad section PDA.

[0176] Touch detection unit (TSP) (see) Figure 5C The touch signal line (TSL) may include first touch electrodes TE1-1 to TE1-m and second touch electrodes TE2-1 to TE2-n. Figure 5C It may include first touch signal lines SL1-1 to SL1-m connected to first touch electrodes TE1-1 to TE1-m and second touch signal lines SL2-1 to SL2-n connected to second touch electrodes TE2-1 to TE2-n. The pad portion PDA may be electrically connected to the first touch signal lines SL1-1 to SL1-m and the second touch signal lines SL2-1 to SL2-n.

[0177] The connecting electrode TSD can be disposed between the first touch electrodes TE1-1 to TE1-m and the first touch signal lines SL1-1 to SL1-m, and between the second touch electrodes TE2-1 to TE2-n and the second touch signal lines SL2-1 to SL2-n. The connecting electrode TSD can be connected to the ends of the first touch electrodes TE1-1 to TE1-m and the ends of the second touch electrodes TE2-1 to TE2-n, respectively, to transmit signals. In various embodiments, the connecting electrode TSD can be omitted.

[0178] Each of the first touch electrodes TE1-1 to TE1-m may have a grid-like structure, defining a plurality of touch openings. Each of the first touch electrodes TE1-1 to TE1-m includes a plurality of first touch sensor sections SP1 and a plurality of first connection sections CP1. The first touch sensor sections SP1 are arranged in a first direction DR1. Each of the first connection sections CP1 connects two adjacent first touch sensor sections SP1. Although not shown in the figure, the first touch signal lines SL1-1 to SL1-m may also have a grid-like structure.

[0179] The second touch electrodes TE2-1 to TE2-n intersect with the first touch electrodes TE1-1 to TE1-m, and there is an insulating gap between them. Each of the second touch electrodes TE2-1 to TE2-n may have a grid pattern, defining a plurality of touch openings. Each of the second touch electrodes TE2-1 to TE2-n includes a plurality of second touch sensor sections SP2 and a plurality of second connecting sections CP2. The second touch sensor sections SP2 are arranged along a second direction DR2. Each of the second connecting sections CP2 connects two adjacent second touch sensor sections SP2. The second touch signal lines SL2-1 to SL2-n may also have a grid pattern.

[0180] The first touch electrodes TE1-1 to TE1-m are electrostatically bonded to the second touch electrodes TE2-1 to TE2-n. When a touch detection signal is applied to the first touch electrodes TE1-1 to TE1-m, a capacitor is formed between the first touch sensor section SP1 and the second touch sensor section SP2.

[0181] Multiple first touch sensor units SP1, multiple first connectors CP1, first touch signal lines SL1-1 to SL1-m, multiple second touch sensor units SP2, multiple second connectors CP2, and portions of the second touch signal lines SL2-1 to SL2-n can be made to Figure 8A The first conductive layer TS-CL1 shown is formed by patterning, and the other parts can be formed by making... Figure 8A The second conductive layer TS-CL2 shown in the figure is formed by patterning.

[0182] To electrically connect conductive patterns in one layer to conductive patterns in another layer, a... Figure 8A The contact hole penetrating the first touch insulating layer TS-IL1 is shown in the figure. Referring below, [the text continues with reference to...] Figures 8C to 8E A touch detection unit TS according to an embodiment of the present invention is described.

[0183] like Figure 8C As shown, the first conductive pattern is disposed on the thin film sealing layer TFE (see... Figure 8A The first conductive pattern may include a bridging pattern CP2. The bridging pattern CP2 is directly disposed on the thin-film sealing layer TFE. In the illustrated exemplary embodiment, the thin-film sealing layer TFE covers the display area DA. The bridging pattern CP2 is... Figure 8B Another name for the second connecting part CP2 shown in the figure.

[0184] like Figure 8DAs shown, a first touch insulating layer TS-IL1 for covering the bridging pattern CP2 is disposed on the thin film sealing layer TFE. A contact hole CH for partially exposing the bridging pattern CP2 is defined within the first touch insulating layer TS-IL1. The contact hole CH can be formed by a photolithography process.

[0185] like Figure 8E As shown, a second conductive pattern is disposed on the first touch insulating layer TS-IL1. The second conductive pattern may include a plurality of first touch sensor portions SP1 (see...). Figure 8B ), multiple first connection parts CP1, first touch signal lines SL1-1 to SL1-m, and multiple second touch sensor parts SP2 (see Figure 8B The second touch signal lines SL2-1 to SL2-n are shown in the figure. Although not shown, a second touch insulating layer TS-IL2 for covering the second conductive pattern is disposed on the first touch insulating layer TS-IL1.

[0186] The first conductive pattern may include first touch electrodes TE1-1 to TE1-m and first touch signal lines SL1-1 to SL1-m. The second conductive pattern may include second touch electrodes TE2-1 to TE2-n and second touch signal lines SL2-1 to SL2-n. In various exemplary embodiments, contact holes CH are not defined in the first touch insulating layer TS-IL1.

[0187] The first conductive pattern and the second conductive pattern can be interchanged. That is, the second conductive pattern may include the bridging pattern CP2.

[0188] like Figure 8F As shown, the first touch sensor unit SP1 is superimposed on the non-light-emitting region NPXA. The first touch sensor unit SP1 includes a plurality of first extensions SP1-A extending in a fifth direction DR5 intersecting the first direction DR1 and the second direction DR2, and a plurality of second extensions SP1-B extending in a sixth direction DR6 intersecting the fifth direction DR5. The plurality of first extensions SP1-A and the plurality of second extensions SP1-B may be defined by grid lines. The linewidth of the grid lines may be several micrometers.

[0189] Multiple first extensions SP1-A and multiple second extensions SP1-B are connected to each other to form multiple touch openings TS-OP. That is, the first touch sensor part SP1 has a grid pattern including multiple touch openings TS-OP. Although the touch openings TS-OP are shown in a one-to-one correspondence with the light-emitting areas PXA, other embodiments have other ratios of the correspondence. Therefore, in various exemplary embodiments, one touch opening TS-OP may correspond to two or more light-emitting areas PXA.

[0190] The size of the light-emitting region PXA can also be varied. For example, the size of the light-emitting region PXA for providing blue light and the size of the light-emitting region PXA for providing red light can be varied. Therefore, the size of the touch opening TS-OP can also be varied. Although Figure 8F The diagram shows variations in the size of the light-emitting region PXA, but the invention is not limited thereto. The sizes of the light-emitting regions PXA can be the same, and the sizes of the touch openings TS-OP can also be the same.

[0191] Reference Figure 9A and Figure 9B The image shows the touch signal line TSL. For example, the touch signal line TSL could be... Figure 8B The first touch signal lines SL1-1 to SL1-m are shown in the figure.

[0192] The conductive part EP can be disposed between the touch signal line TSL and multiple clock signal lines CL1, CL2, CL3, and CL4 (collectively referred to as CL below). The conductive part EP can be formed as a layer and can be disposed on the same layer as the second electrode CE. For example, the conductive part EP and the second electrode CE can both be disposed on the pixel defining layer PDL. "Disposed on the same layer (e.g., pixel defining layer PDL)" does not necessarily mean that they are disposed only on the same horizontal or height plane. For example, if a given layer has different horizontal or height so that the layer is at different heights in a third direction DR3 in a cross-sectional view, other elements disposed "on" the layer can be disposed at different horizontal or heights in the third direction DR3 or may not be disposed at different horizontal or heights in the third direction DR3. "Disposed on" refers to the relationship in which the layers touch each other and the relationship in which the layers are separated from each other by intermediate elements or intermediate layers.

[0193] The second electrode CE can extend toward the conductive portion EP, and the second electrode CE and the conductive portion EP can be connected to each other. That is, the second electrode CE and the conductive portion EP can be formed by the same process.

[0194] The conductive part EP can be electrically connected to the power supply line E-VSS. The conductive part EP can receive a second voltage ELVSS from the power supply line E-VSS (see...). Figure 6A ).

[0195] The conductive portion EP may extend over and cover all or part of the stacked region OA, wherein, for example... Figure 9B As shown in the overlay area OA, the touch signal line TSL and the clock signal line CL are stacked vertically in the overlay area OA. For example, as... Figure 9BAs shown, the conductive part EP can completely cover (traverse) the stacked area OA such that the conductive part EP is located between the clock signal line CL and the touch signal line TSL at the entire vertically stacked portion of the clock signal line CL and the touch signal line TSL. This vertical direction can also be referred to as the stacking direction (in...). Figure 9A and Figure 9B (This is indicated by a third party to DR3). The conductive part EP can guide the electrical signal laterally away from the touch signal line TSL, thereby reducing or preventing noise caused by the clock signal applied to the clock signal line CL from reaching the touch signal line TSL. Therefore, the conductive part EP can, in turn, reduce or prevent changes in touch sensitivity that would otherwise be caused by noise from the clock signal line CL.

[0196] The first dam-shaped portion DM1 and the second dam-shaped portion DM2 can be disposed in the non-display area NDA. The first dam-shaped portion DM1 and the second dam-shaped portion DM2 can be disposed around the display area DA, such that when organic monomers are printed to form the organic film OL1 of the film sealing layer TFE, the first dam-shaped portion DM1 and the second dam-shaped portion DM2 can prevent organic monomers from overflowing outside the non-display area NDA where the first dam-shaped portion DM1 and the second dam-shaped portion DM2 are disposed and surrounding the display area DA.

[0197] The first dam-shaped portion DM1 can be disposed on the power supply line E-VSS. The first dam-shaped portion DM1 can be formed by a single layer and can be formed simultaneously with the pixel limiting layer PDL.

[0198] The second dam-shaped portion DM2 can be located outside the first dam-shaped portion DM1. Therefore, the distance between the second dam-shaped portion DM2 and the display area DA can be greater than the distance between the first dam-shaped portion DM1 and the display area DA.

[0199] The second dam-shaped portion DM2 may cover a portion of the power supply line E-VSS. The second dam-shaped portion DM2 may be formed by multiple layers and includes a first dam-shaped layer DM2-1 and a second dam-shaped layer DM2-2. The first dam-shaped layer DM2-1 may be formed simultaneously with the third insulating layer 30; and the second dam-shaped layer DM2-2 may be formed simultaneously with the pixel defining layer PDL.

[0200] Although Figure 9AThe illustration shows the pixel defining layer PDL extending on the third-direction DR3 to overlap with all clock signal lines CL. However, in other embodiments, the pixel defining layer PDL does not overlap with all clock signal lines CL or does not completely overlap with them. Therefore, in various exemplary embodiments, the pixel defining layer PDL may extend only to the region overlapping with the gate drive circuit GDC, and / or may extend only to the region overlapping with some of the clock signal lines CL. For example, the pixel defining layer PDL may extend only to the region overlapping with the third clock signal line CL3, the fourth clock signal line CL4, the third voltage line VL2, the fourth voltage line VH2, and the second start signal line EF2.

[0201] Reference Figure 9C The conductive part EP-1 can be installed on the touch signal line TSL and multiple clock signal lines CL (see...). Figure 9B The conductive part EP-1 and the second electrode CE can be disposed on the same layer. For example, the conductive part EP-1 and the second electrode CE can both be disposed on the pixel defining layer PDL.

[0202] The conductive part EP-1 can be separated from the second electrode CE. That is, the conductive part EP-1 and the second electrode CE do not need to be physically connected to each other. The conductive part EP-1 can be electrically connected to the power supply line E-VSS. The conductive part EP-1 can receive the second voltage ELVSS from the power supply line E-VSS (see...). Figure 6A In other embodiments, a constant voltage may be applied to the conductive portion EP-1. For example, a first voltage ELVDD (see...). Figure 6A A voltage may be applied to conductive part EP-1, or a ground voltage may be applied to conductive part EP-1, or another constant voltage other than the voltages listed above may be applied to conductive part EP-1.

[0203] The second electrode CE can be electrically connected to the power supply line E-VSS via a pattern (not shown). Therefore, the second electrode CE can receive the second voltage ELVSS from the power supply line E-VSS (see...). Figure 6A ).

[0204] The conductive part EP-1 can reduce or prevent changes in the touch sensitivity of the touch detection unit caused by noise from the signal applied to the clock signal line CL.

[0205] Reference Figure 9D The conductive part EP-2 can be installed on the touch signal line TSL and multiple clock signal lines CL (see...). Figure 9B Between. The conductive part EP-2 can be disposed on the same layer as the second electrode CE.

[0206] Multiple vias HL can be defined within the conductive portion EP-2. These vias HL can be used to vent gases emerging from the layer including the organic layer. The multiple vias HL may not be connected to the stacked region OA (see...). Figure 9B The touch signal line TSL and the clock signal line CL are stacked in the stacking region OA. Figure 9D In the diagram, the via HL is not defined relative to the clock signal line CL (see...). Figure 9B In the region superimposed on the third-direction DR3. According to another embodiment of the invention, the via HL may not be limited to the region superimposed on the third-direction DR3 with the touch signal line TSL.

[0207] Since the via HL is not confined to the stacked region OA (see...) Figure 9B Therefore, even if the via HL is provided to the conductive part EP-2, the touch sensitivity of the touch detection unit can be prevented from changing in response to noise caused by the signal applied to the clock signal line CL, despite the presence of vias in other locations.

[0208] Reference Figure 10A and Figure 10B The conductive part EP-3 can be disposed between the touch signal line TSL and multiple clock signal lines CL. The conductive part EP-3 can be disposed on the same layer as the first electrode AE. For example, the conductive part EP-3 and the first electrode AE ​​can both be disposed on the third insulating layer 30. The first electrode AE ​​and the conductive part EP-3 can be formed by the same process.

[0209] The conductive part EP-3 can be electrically connected to the power supply line E-VSS. The conductive part EP-3 can receive a second voltage ELVSS from the power supply line E-VSS (see...). Figure 6A Alternatively, a constant voltage can be applied to the conductive part EP-3. For example, a first voltage ELVDD (see...). Figure 6A A voltage may be applied to the conductive part EP-3, or a ground voltage may be applied to the conductive part EP-3, or another constant voltage other than the voltages listed above may be applied to the conductive part EP-3.

[0210] Multiple vias HL-1 can be defined in the conductive portion EP-3. The multiple vias HL-1 can be used to discharge gases emerging from the layer including the organic layer. The multiple vias HL-1 may not be superimposed with the stacking region OA, wherein the touch signal line TSL and the clock signal line CL are superimposed on the third-direction DR3 in the stacking region OA. More specifically, refer to... Figure 10AThe via HL-1 is not limited to the region where the clock signal line CL is superimposed on the third direction upwards. Therefore, the conductive part EP-3 can completely cover the superimposed region OA, where the touch signal line TSL and the clock signal line CL are superimposed on the third direction DR3 in the superimposed region OA. The conductive part EP-3 can prevent noise generated on the touch signal line TSL by the signal applied to the clock signal line CL. That is, the presence of the conductive part EP-3 can reduce or even eliminate changes in touch sensitivity, thereby providing a touch detection unit with uniform touch sensitivity.

[0211] Now refer to Figure 10C and Figure 10D The conductive part EP-4 can be disposed between the touch signal line TSL and multiple clock signal lines CL. Multiple through holes HL-2 can be defined in the conductive part EP-4.

[0212] The via HL-2 may not be superimposed on the overlay region OA, wherein the touch signal line TSL and the clock signal line CL are superimposed on the overlay region OA on the third-direction DR3. For more details, see [reference needed]. Figure 10C The HL-2 via is not limited to the area where it overlaps with the touch signal line TSL on the third-direction DR3.

[0213] The conductive portion EP-4 beneath the touch signal line TSL can block signal interference applied to the clock signal line CL from passing through the touch signal line TSL. That is, since the via HL-2 is not defined in the area overlapping with the touch signal line TSL, noise caused by the influence of the signals from each clock signal line CL will not be generated in the touch signal line TSL.

[0214] Reference Figure 11A and Figure 11B The conductive portion EP-5 can be disposed between the touch signal line TSL and multiple clock signal lines CL. The conductive portion EP-5 may include a first conductive layer EP-L1 and a second conductive layer EP-L2. The first conductive layer EP-L1 can be disposed on the same layer as the first electrode AE, and the second conductive layer EP-L2 can be disposed on the same layer as the second electrode CE. For example, the first conductive layer EP-L1 and the first electrode AE ​​can be disposed on the third insulating layer 30, and the second conductive layer EP-L2 and the second electrode CE can be disposed on the pixel defining layer PDL. The first conductive layer EP-L1 and the first electrode AE ​​can be formed using the same process, and the second conductive layer EP-L2 and the second electrode CE can be formed using the same process.

[0215] Each of the first conductive layer EP-L1 and the second conductive layer EP-L2 can be electrically connected to the power supply line E-VSS. Each of the first conductive layer EP-L1 and the second conductive layer EP-L2 can receive a second voltage ELVSS from the power supply line E-VSS (see...). Figure 6A Alternatively, a constant voltage can be applied to the second conductive layer EP-L2. For example, a first voltage ELVDD (see...) Figure 6A A voltage may be applied to the second conductive layer EP-L2, or a ground voltage may be applied to the second conductive layer EP-L2, or another constant voltage other than the voltages listed above may be applied to the second conductive layer EP-L2.

[0216] Multiple first vias HL-3 can be defined within the first conductive layer EP-L1. These multiple first vias HL-3 can be used to discharge gases emerging from the layer including the organic layer. Although Figure 11A The diagram shows that multiple first through-holes HL-3 can be separated from each other at a predetermined spacing, but in other embodiments, the spacing between them is not constant.

[0217] The second conductive layer EP-L2 can cover all of the plurality of first vias HL-3 such that they are stacked on the third-direction DR3. According to this embodiment, double shielding can be provided between the touch signal line TSL and the plurality of clock signal lines CL through the first conductive layer EP-L1 and the second conductive layer EP-L2. Furthermore, because the second conductive layer EP-L2 covers the plurality of first vias HL-3 on the third-direction DR3, areas on the third-direction DR3 not shielded by the plurality of first vias HL-3 can also be shielded. Therefore, even if high and low voltage levels are alternately applied to the plurality of clock signal lines CL, the signals applied to the plurality of clock signal lines CL are blocked by the first conductive layer EP-L1 and the second conductive layer EP-L2, thus preventing noise from being generated on the touch signal line TSL.

[0218] Now refer to Figure 11C The conductive part EP-6 can be disposed between the touch signal line TSL and multiple clock signal lines CL. The conductive part EP-6 may include a first conductive layer EP-L1 and a second conductive layer EP-L2a. (Referring to the above...) Figure 11A When comparing the described conductive parts with EP-5, Figure 11C The conductive part EP-6 can take different forms in the second conductive layer EP-L2a.

[0219] Reference Figure 11A The second electrode CE can extend toward the second conductive layer EP-L2, and the second electrode CE and the second conductive layer EP-L2 can be physically connected to each other. However, referring to... Figure 11C The second conductive layer EP-L2a can be separated from the second electrode CE. That is, as in Figure 11C In this process, the conductive part EP-1 and the second electrode CE may not be physically connected to each other.

[0220] Now refer to Figure 12A The conductive portion EP-6a can be disposed between the touch signal line TSL and multiple clock signal lines CL. The conductive portion EP-6a may include a first conductive layer EP-L1a and a second conductive layer EP-L2. The first conductive layer EP-L1a can be disposed on the same layer as the first electrode AE, and the second conductive layer EP-L2 can be disposed on the same layer as the second electrode CE. For example, the first conductive layer EP-L1a and the first electrode AE ​​can be disposed on the third insulating layer 30, and the second conductive layer EP-L2 and the second electrode CE can be disposed on the pixel defining layer PDL. The first conductive layer EP-L1a and the first electrode AE ​​can be formed using the same process, and the second conductive layer EP-L2 and the second electrode CE can be formed using the same process.

[0221] Multiple first vias HL-4 may be defined within the first conductive layer EP-L1a. The multiple first vias HL-4 may be used to vent gases emerging from the layer including the organic layer. The multiple first vias HL-4 may not be defined in the region superimposed on the third-direction DR3 with the clock signal line CL.

[0222] Figure 12B The third clock signal line CL3, the fourth clock signal line CL4, the third voltage line VL2, the fourth voltage line VH2, and the second start signal line EF2 are shown. Multiple first vias HL-4 are not necessarily limited to the region overlapping with the third clock signal line CL3 and the fourth clock signal line CL4.

[0223] When displaying a frame of image, signals whose levels change continuously can be applied to the third clock signal line CL3 and the fourth clock signal line CL4. Therefore, if the upper portions of the third clock signal line CL3 and the fourth clock signal line CL4 are not shielded, these signals will cause noise to appear from the touch signal line TSL. However, returning to the reference... Figure 12A Because the multiple first vias HL-4 are not defined in the portion of the first conductive layer EP-L1a that overlaps with the third clock signal line CL3 and the fourth clock signal line CL4 on the third-direction DR3, the upper portions of the third clock signal line CL3 and the fourth clock signal line CL4 are completely shielded. Therefore, signals applied to the third clock signal line CL3 and the fourth clock signal line CL4 will not cause noise on the touch signal line TSL.

[0224] The first conductive layer EP-L1a may include a first region AR1, a second region AR2, and a third region AR3. Figure 12B The diagram shows the first region AR1, the second region AR2, and the third region AR3.

[0225] The first region AR1 may be a region superimposed on the clock signal line CL and without defining multiple first vias HL-4. Figure 12B A first region AR1 is shown, superimposed on a third clock signal line CL3 and a fourth clock signal line CL4. A second region AR2 is a region defining a plurality of first vias HL-4 and HL-4a, and may be a region with a first region density in the portions exposed through the plurality of first vias HL-4 and HL-4a. A third region AR3 is a region defining a plurality of first vias HL-4, and may be a region with a second region density in the portions exposed through the plurality of first vias HL-4. The second region density may be lower than the first region density. The exposed regions may be a third insulating layer 30. For example, the number of first vias HL-4 and HL-4a in each first surface region SA1 of the second region AR2 may be two, and the number of first vias HL-4 in each first surface region SA1 of the third region AR3 may be one.

[0226] Since the multiple first vias HL-4 are not defined in the first region AR1 that overlaps with the third clock signal line CL3 and the fourth clock signal line CL4, multiple first vias HL-4a can also be defined in the second region AR2 to compensate for this.

[0227] The form of the hole HLa is indicated by the dashed line in the first region AR1. This is for ease of description only and does not mean that the hole HLa is confined to the first region AR1. Rather, the dashed line indicates the theoretical location where the hole HLa should be, but is not actually confined. If multiple first through holes HL-4 are arranged at uniform intervals, then the hole HLa should be located in the first region AR1 as indicated by the dashed line. However, in reality, no hole is confined to the first region AR1. Therefore, the design condition that the layer below the first conductive layer EP-L1a (e.g., the third insulating layer 30) should be exposed by more area than the predetermined area of ​​the first through holes HL-4 in the first conductive layer EP-L1a may not be met. As a result, gases emerging from the layer including organic materials may not be able to escape smoothly. To prevent this, the first through holes HL-4a can be additionally confined in the second region AR2, corresponding to the number of holes HLa not confined to the first region AR1. Therefore, although the hole indicated by the dashed line is omitted in the first region AR1, the design condition that the layer below the first conductive layer EP-L1a (e.g., the third insulating layer 30) should be exposed by more area than predetermined by the first through-hole HL-4 in the first conductive layer EP-L1a can still be satisfied. To aid in understanding this concept, an arrow is shown between the virtual hole HLa and the first through-hole HL-4a to illustrate the hole movement relationship of the hole HLa. The arrow is not an actual component of the device. Rather, it is shown to aid in conceptual understanding.

[0228] Reference Figure 12C Since the hole HLa should be located in the first region AR1, but no hole is confined to the first region AR1, in order to compensate for this, in Figure 12C In an exemplary embodiment, the size of the first through-hole HL-4b disposed in the second region AR2 is enlarged.

[0229] Due to the third insulating layer 30 below the first through-hole HL-4b (see...) Figure 12A The exposed area of ​​the first through-hole HL-4b increases, thus enlarging its size has the same effect as described above. As a result, although the through-hole HLa in the first region AR1 is omitted, the first through-hole HL-4b can still meet the requirements of the conductive part EP-6 (see...). Figure 12A The area should have design conditions that are larger than the predetermined area.

[0230] Although Figure 12C The exemplary embodiment shown depicts an enlarged width of the first through hole HL-4 in the vertical direction, but the invention is not limited thereto. For example, with respect to the first through hole HL-4b, the width of the first through hole HL-4 may be enlarged in the horizontal direction, or the width may be enlarged in both the horizontal and vertical directions.

[0231] Reference Figure 13A The conductive portion EP-7 can be disposed between the touch signal line TSL and multiple clock signal lines CL. The conductive portion EP-7 may include a first conductive layer EP-L1b and a second conductive layer EP-L2. The first conductive layer EP-L1b can be disposed on the same layer as the first electrode AE, and the second conductive layer EP-L2 can be disposed on the same layer as the second electrode CE. For example, the first conductive layer EP-L1b and the first electrode AE ​​can be disposed on the third insulating layer 30, and the second conductive layer EP-L2 and the second electrode CE can be disposed on the pixel defining layer PDL. The first conductive layer EP-L1b and the first electrode AE ​​can be formed using the same process, and the second conductive layer EP-L2 and the second electrode CE can be formed using the same process.

[0232] Multiple first vias HL-5 may be defined within the first conductive layer EP-L1b. The multiple first vias HL-5 may be used to discharge gases emerging from the layer including the organic layer. The multiple first vias HL-5 may not be defined in the region superimposed on the third-direction DR3 with the touch signal line TSL.

[0233] exist Figure 13B Examples of touch signal lines TSL are shown. Multiple first vias HL-5 may not be limited to the area overlapping the touch signal lines TSL.

[0234] When multiple first vias HL-5 are not defined below the touch signal line TSL on the third-party DR3, the negative impact of the AC signal from the clock signal line CL applied to the third-party DR3 below the touch signal line TSL on the signal in the touch signal line TSL can be reduced. Therefore, noise is less likely to occur in the touch signal line TSL, and changes in touch sensitivity caused by noise can be reduced or prevented.

[0235] The first conductive layer EP-L1b may include a first region AR1, a second region AR2, and a third region AR3. Figure 13B The diagram shows the first region AR1, the second region AR2, and the third region AR3.

[0236] The first region AR1 may be a region superimposed on the touch signal line TSL and not defining a plurality of first vias HL-5. The second region AR2 may be a region defining a plurality of first vias HL-5 and HL-5a, and may be a region with a first region density in the portions exposed through the plurality of first vias HL-5 and HL-5a. The third region AR3 may be a region defining a plurality of first vias HL-5, and may be a region with a second region density in the portions exposed through the plurality of first vias HL-5. The second region density may be lower than the first region density. The exposed area may be a third insulating layer 30. The number of first vias HL-5 and HL-5a defined in each first surface region SA1 of the second region AR2 may be two, and the number of first vias HL-5 defined in each first surface region SA1 of the third region AR3 may be one.

[0237] Since multiple first vias HL-5 are not defined in the first region AR1 overlaid with the touch signal line TSL, multiple first vias HL-5a can also be defined in the second region AR2 to compensate for this. For example, the form of via HLa is indicated by the dashed line in the first region AR1. This is only for ease of description and does not mean that via HLa is actually defined in the first region AR1. When multiple first vias HL-5 are arranged at uniform intervals, via HLa should be located in the first region AR1 as shown by the dashed line; however, in reality, no via is defined in the first region AR1. Therefore, the design condition that the layer below the first conductive layer EP-L1b (e.g., the third insulating layer 30) is exposed by more area than the predetermined area of ​​the first vias HL-5 in the first conductive layer EP-L1b is not satisfied. As a result, gases emerging from the layer including organic materials may not be able to be discharged smoothly. To prevent this, first vias HL-5a omitted from the first region AR1 can be additionally defined in the second region AR2 corresponding to the number of vias HLa not defined in the first region AR1. Therefore, the design condition that the layer below the first conductive layer EP-L1b (e.g., the third insulating layer 30) should be exposed by more area than the predetermined area by the first via HL-5 in the first conductive layer EP-L1b can be met.

[0238] Although Figure 13B Not shown in the image, but related to Figure 12C Similarly, to compensate for holes not defined in the first region AR1, it can be combined as described above. Figure 12C The description involves increasing the size of the first through-hole HL-5 in the second region AR2 instead of adding an additional through-hole HL-5 in the second region AR2, or adding an additional through-hole HL-5 in the second region AR2 and combining it as described above. Figure 12C The description refers to increasing the size of the first through-hole HL-5 in the second region AR2.

[0239] Now for reference Figure 14A The conductive part EP-8 can be disposed between the touch signal line TSL and multiple clock signal lines CL. The conductive part EP-8 may include a first conductive layer EP-L1c and a second conductive layer EP-L2b. The first conductive layer EP-L1c can be disposed on the same layer as the first electrode AE, and the second conductive layer EP-L2b can be disposed on the same layer as the second electrode CE.

[0240] Multiple first vias HL-6 can be defined in a first conductive layer EP-L1c. The multiple first vias HL-6 can be used to discharge gases emerging from the layer including the organic layer. Multiple second vias HL-7 can be defined in a second conductive layer EP-L2b. The multiple second vias HL-7 can be used to discharge gases emerging from the layer including the organic layer.

[0241] The first via HL-6 and the second via HL-7 may not be superimposed on each other on the third-direction DR3. Therefore, the area forming the first via HL-6 can be covered by the second conductive layer EP-L2b on the third-direction DR3, and the area forming the second via HL-7 can be covered by the first conductive layer EP-L1c on the third-direction DR3. According to this embodiment, the overlapping area between the touch signal line TSL and the multiple clock signal lines CL can be shielded by at least one of the first conductive layer EP-L1c and the second conductive layer EP-L2b. That is, the conductive portion EP-8 can reduce the change in touch sensitivity caused by noise appearing in the touch signal line TSL due to signals in the clock signal line CL.

[0242] Although Figure 14B The illustration shows a plurality of first through holes HL-6 and a plurality of second through holes HL-7 arranged in the second direction DR2 and alternately disposed along the first direction DR1, but the inventive concept is not limited thereto. In various exemplary embodiments, the plurality of first through holes HL-6 and the plurality of second through holes HL-7 do not overlap each other in the third direction DR3, and these through holes HL-6, HL-7 have various other arrangements. For example, the plurality of first through holes HL-6 and the plurality of second through holes HL-7 may be alternately disposed in the first direction DR1 and the second direction DR2.

[0243] A display device constructed according to the principles of the present invention includes a conductive portion for covering an overlay area, wherein multiple clock signal lines and multiple touch signal lines are overlaid in the overlay area. The conductive portion can reduce or prevent noise from appearing on the touch signal lines due to changes in the level of the signal applied to the clock signal lines. That is, the conductive portion can reduce or prevent the touch sensitivity of the touch detection unit from being affected by noise.

[0244] While certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to these embodiments, but rather to the broader scope of the claims and various apparent modifications and equivalent arrangements.

Claims

1. A display device, the display device comprising: A display panel is defined in which a display area and a non-display area adjacent to the display area are defined. The display panel includes a light-emitting element layer, a first signal line, a shielding portion and an encapsulation layer. The light-emitting element layer is disposed in the display area. The first signal line is disposed in the non-display area and provides a signal for controlling the light-emitting element layer. The shielding portion is disposed in the non-display area and overlaps with the first signal line. The encapsulation layer seals the light-emitting element layer. An insulating layer is directly disposed on the encapsulation layer; Sensing electrodes are disposed on the insulating layer; as well as A second signal line is disposed on the insulating layer and electrically connected to the sensing electrode. in: The shielding part is disposed between the first signal line and the second signal line; The encapsulation layer, located on the upper surface of the non-display area, includes a curved shape; and The upper surface of the insulating layer bends along the curved shape of the upper surface of the encapsulation layer.

2. The display device according to claim 1, wherein, The light-emitting element layer includes a first electrode, an organic light-emitting layer disposed on the first electrode, and a second electrode disposed on the organic light-emitting layer. The shielding part and the second electrode are disposed on the same layer.

3. The display device according to claim 2, wherein, The second electrode extends toward the shielding portion, and the second electrode and the shielding portion are connected to each other.

4. The display device according to claim 2, wherein, The second electrode is spaced apart from the shielding portion.

5. The display device according to claim 1, wherein, The first signal line is the clock signal line to which the clock signal is applied.

6. The display device according to claim 1, wherein, The display panel further includes a gate driving circuit, and each of the first signal lines provides a clock signal to the gate driving circuit.

7. The display device according to claim 1, wherein, The encapsulation layer includes at least one inorganic layer and at least one organic layer.

8. The display device according to claim 1, wherein, Multiple through holes are defined within the shielding portion, and The plurality of vias are not overlapped with the first signal line or the second signal line.

9. The display device according to claim 8, wherein, The shielding part includes: A first region is superimposed on at least one of the first signal lines and at least one of the second signal lines, wherein the plurality of vias are not defined in the first region; The second region includes a region of holes having a first region density exposed by the plurality of through holes; and The third region includes the region of holes exposed by the plurality of through holes, having a second region density that is lower than that of the first region.

10. The display device according to claim 9, wherein, The number of first through holes in each first surface region of the second region is greater than the number of second through holes in each first surface region of the third region.

11. The display device according to claim 9, wherein, The size of the first through hole defined in the second region is larger than the size of the second through hole defined in the third region.

12. The display device according to claim 1, further comprising sensing pads disposed in the non-display area and electrically connected to the second signal line.

13. A display device, the display device comprising: A display panel is defined in which a display area and a non-display area adjacent to the display area are defined, and the upper surface of the display panel that overlaps with the non-display area includes an uneven shape portion; An insulating layer is directly disposed on the upper surface of the display panel; Sensing electrodes are disposed on the insulating layer; as well as Sensing lines are disposed on the insulating layer and electrically connected to the sensing electrodes, respectively. The display panel includes: a clock signal line disposed in the non-display area; a light-emitting element layer disposed in the display area, including a first electrode, an organic emitting layer disposed on the first electrode, and a second electrode disposed on the organic emitting layer; a shielding portion disposed in the non-display area, on the same layer as the second electrode, and disposed between the clock signal line and the sensing line; and an encapsulation layer disposed on the light-emitting element layer and the shielding portion, defining the upper surface of the display panel; and The upper surface of the insulating layer is curved along the uneven shape of the upper surface of the display panel.

14. The display device according to claim 13, wherein, The display panel also includes a gate driving circuit, and each of the clock signal lines provides a clock signal to the gate driving circuit.

15. The display device according to claim 14, wherein, Multiple through holes are defined within the shielding portion, and The plurality of vias are not overlapped with the clock signal line or the sensing line.

16. The display device according to claim 13, further comprising sensing pads disposed in the non-display area and electrically connected to the sensing lines.

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