Semiconductor device and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor device and a manufacturing method thereof. An IGBT capable of handling high-speed switching while reducing a leakage current of a semiconductor device including the IGBT is provided. A semiconductor device according to one embodiment includes an IGBT including a p-type collector layer on a back surface of a silicon substrate and a dislocation suppression layer for forming a heterojunction with silicon in the p-type collector layer. The dislocation suppression layer includes a silicon germanium (SiGe) layer.

Description

[0001] Cross-reference to related applications

[0002] The disclosure of Japanese Patent Application No. 2020-148586, filed on September 3, 2020, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] This invention relates to a semiconductor device and a method for manufacturing the same, and more specifically to a technique and method for manufacturing a semiconductor device having an IE (injection enhancement) type IGBT (insulated gate bipolar transistor). Background Technology

[0004] The disclosed technologies are listed below.

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2017-157733

[0006] An example of an IE-type IGBT structure is known, which includes a strip-patterned trench gate, a p-type floating layer, and an n-type hole barrier layer. The strip-patterned trench gate is formed to surround the n-type emitter layer and the p-type base layer in a plan view. The p-type floating layer is disposed outside the trench gate and has one end in contact with the side surface of the trench gate. The n-type hole barrier layer is formed below the p-type base layer (see, for example, Patent Document 1).

[0007] Patent Document 1 also discloses a structure including a strip-patterned trench emitter in contact with the other end of the p-type floating layer, the purpose of which is to provide a path for discharging positive holes accumulated in the p-type floating layer in order to suppress IGBT switching losses. Furthermore, Patent Document 1 discloses a structure including a p-type collector layer and an n-type field cutoff layer disposed on the lower surface of an n-type drift layer below the p-type base layer. Summary of the Invention

[0008] From the viewpoint of reducing leakage current during high-speed switching of IGBTs or reducing leakage current during reverse bias, the inventors have discovered the following problems regarding the n-type field cutoff layer and p-type collector layer on the back surface of the IGBT.

[0009] like Figure 1AAs shown, to form the n-type field-stop layer and p-type collector layer of an IGBT in the back surface BS of a substrate SUB made of n-type single-crystal silicon, phosphorus (P) as an n-type impurity and boron (B) as a p-type impurity are sequentially ion-implanted into the back surface BS of the silicon substrate to form an n-type impurity implantation layer NI and a p-type impurity implantation layer PI. Then, the back surface of the substrate SUB undergoes laser annealing LA to activate the impurity implantation layers NI and PI, thereby forming the n-type field-stop layer FSL and the p-type collector layer CL, as shown. Figure 1B As shown in the image.

[0010] During laser emission in laser annealing (LA), approximately 0.2 μm thick silicon on the outermost surface of the back surface (BS) of the substrate (SUB) is melted in one step to form a molten layer (ML). After laser emission, the temperature of the substrate (SUB) decreases, and the molten layer (ML) recrystallizes. The inventors have discovered that during recrystallization, particulate lattice (PTL) is present on the surface of the molten layer (ML), which leads to dislocation defects (DIL) in the back surface (BS) of the substrate (SUB) originating from the particulate PTL, such as… Figure 1C As shown in the image.

[0011] This dislocation defect DIL extending into the n-type field-stop layer FSL leads to the following concerns: leakage faults between the collector and emitter of the IGBT and reverse bias leakage faults. The problem of dislocation defects can be solved if particulate PTLs can be completely eliminated during the formation of the IGBT's back surface structure. However, IGBT chips, especially those handling high voltage and high current, have a larger area than ordinary LSI chips (e.g., equal to or greater than 10 mm²). 2 Therefore, it is actually very difficult to completely eliminate particulate PTL.

[0012] Furthermore, to reduce the on-resistance in IGBTs, the back surface of the n-type silicon substrate, which serves as the drift layer, is thinned through grinding and polishing. Therefore, after sequentially forming an n-type emitter layer, a p-type base layer, a p-type floating layer, and an n-type hole barrier layer on the main surface of the substrate, the n-type field-stop layer and the p-type collector layer, to be formed on the back surface of the substrate, are formed on the thinned back surface. To maintain the impurity distribution of the n-type emitter layer, p-type base layer, etc., the high-temperature heating process used to form the n-type field-stop layer and p-type collector layer is restricted to be performed on the entire substrate. Therefore, laser annealing, which allows for partial heat treatment of the substrate, has become an effective technique in IGBT manufacturing in recent years.

[0013] Other objects and novel features will become clear from the description in this specification and the accompanying drawings.

[0014] A semiconductor device according to one embodiment includes an IGBT, the IGBT including a p-type collector layer on the back surface of a silicon substrate, and a dislocation suppression layer forming a heterojunction with the silicon in the p-type collector layer. The dislocation suppression layer includes a silicon-germanium (SiGe) layer.

[0015] According to one embodiment of the semiconductor device, leakage current of the semiconductor device including the IGBT can be reduced, and an IGBT capable of handling high-speed switching can be provided. Attached Figure Description

[0016] Figure 1A This is a cross-sectional view illustrating a key part of the method for manufacturing the back surface region of the semiconductor device including IGBTs studied by the inventors.

[0017] Figure 1B It is a continuation Figure 1A A cross-sectional view used to illustrate the main parts of the same manufacturing method.

[0018] Figure 1C It is a continuation Figure 1B A cross-sectional view used to illustrate the main parts of the same manufacturing method.

[0019] Figure 2 This is a cross-sectional view showing the main part of the structure of the back surface region of a semiconductor device including an IGBT according to one embodiment.

[0020] Figure 3 This is a cross-sectional view showing a major portion of another structure including the back surface region of a semiconductor device comprising an IGBT according to one embodiment.

[0021] Figure 4 This is a cross-sectional view used to illustrate the main part of the cell structure of a semiconductor device including an IGBT according to one embodiment.

[0022] Figure 5 It is a planar diagram used to illustrate the planar structure of a semiconductor device including an IGBT according to one embodiment.

[0023] Figure 6 It is a diagram used to illustrate the region where the unit forms, i.e. Figure 5 A schematic enlarged plan view of region RR.

[0024] Figure 7 It is along Figure 5 A schematic cross-sectional view of line AA.

[0025] Figure 8 This is a cross-sectional view illustrating a manufacturing method for a region on the back surface of a semiconductor device including an IGBT.

[0026] Figure 9 It is a continuation Figure 8 A cross-sectional view used to illustrate the same manufacturing method.

[0027] Figure 10 It is a continuation Figure 9 A cross-sectional view used to illustrate the same manufacturing method.

[0028] Figure 11 It is a continuation Figure 10 A cross-sectional view used to illustrate the same manufacturing method.

[0029] Figure 12 This is a cross-sectional view illustrating a manufacturing method for a region on the back surface of a semiconductor device including an IGBT.

[0030] Figure 13 It is a continuation Figure 12 A cross-sectional view used to illustrate the same manufacturing method.

[0031] Figure 14 It is a cross-sectional view used to illustrate the structure of the region of the back surface of the semiconductor device including the IGBT according to the first modified example.

[0032] Figure 15 It is a plan view of a semiconductor device including an IGBT according to the first modified example.

[0033] Figure 16 It is a cross-sectional view used to illustrate a manufacturing method of a semiconductor device including the region of the back surface of an IGBT according to the first modified example.

[0034] Figure 17 It is a continuation Figure 16 A cross-sectional view used to illustrate the same manufacturing method.

[0035] Figure 18 It is a cross-sectional view used to illustrate the structure of the region of the back surface of the semiconductor device including the IGBT according to the second modified example.

[0036] Figure 19 It is a plan view of a semiconductor device including an IGBT according to the second modified example.

[0037] Figure 20 It is a cross-sectional view used to illustrate a manufacturing method of a semiconductor device including the region of the back surface of the IGBT according to the second modified example.

[0038] Figure 21 It is a continuation Figure 20 A cross-sectional view used to illustrate the same manufacturing method.

[0039] Figure 22It is a cross-sectional view used to illustrate the structure of the region of the back surface of the semiconductor device, including the IGBT according to the third modified example.

[0040] Figure 23 It is a plan view of a semiconductor device including an IGBT according to the third modified example.

[0041] Figure 24 It is a cross-sectional view used to illustrate the structure of the region of the back surface of the semiconductor device, including the IGBT according to the fourth modified example.

[0042] Figure 25 It is a plan view of a semiconductor device including an IGBT according to the fourth modified example.

[0043] Figure 26 This is a graph showing the output properties of three IGBTs with different back surface structures.

[0044] Figure 27 This is a circuit diagram representing a switching circuit used in an analog circuit.

[0045] Figure 28 It is a graph used to illustrate the switching loss values ​​calculated through simulation.

[0046] Figure 29 The output properties of each IGBT are calculated based on the change in the ratio (L1 / L2) between the width L1 and the width L2 of the dislocation suppression layer DSL1a.

[0047] Figure 30 This is a circuit block diagram showing an example of a motor drive circuit.

[0048] Figure 31 It is used to explain and Figure 30 The circuit diagram showing the operation of the IGBT and diode corresponding to the U phase.

[0049] Figure 32 This is a cross-sectional view used to illustrate the parasitic diodes that form part of an IGBT.

[0050] Figure 33 It is used to explain the composition in Figure 31 The equivalent circuit diagram of the parasitic diode in the IGBT on the high side. Detailed Implementation

[0051] A semiconductor device according to one embodiment will now be described in detail with reference to the accompanying drawings. In the specification and drawings, it is noted that the same or corresponding elements are designated by the same reference numerals, and repeated descriptions thereof will be omitted. Furthermore, at least some of each embodiment and modified example may optionally be combined with each other.

[0052] refer to Figure 2 The structure of the back surface region of the IGBT is explained. Figure 2 This is a cross-sectional view showing the main part of the structure of a region including the back surface of a semiconductor device including an IGBT according to one embodiment. The description will omit the n-type emitter layer, p-type base layer, trench gate, trench emitter, p-type floating layer, n-type hole barrier layer, etc., formed in the region of the front surface US of the substrate SUB. The front surface US of the substrate SUB can be considered as a first main surface, and the back surface BS of the substrate SUB can be considered as a second main surface facing the first main surface.

[0053] like Figure 2 As shown, a field cutoff layer FSL made of an n-type semiconductor layer and a collector layer CL made of a p-type semiconductor layer are formed on the back surface BS of a substrate SUB made of n-type silicon. Inside the collector layer CL, a dislocation suppression layer DSL1 made of silicon-germanium (SiGe) is formed. The dislocation suppression layer DSL1 is formed to provide a heterojunction HJ made of silicon and silicon-germanium (SiGe) layers in the collector layer CL. Through this heterojunction HJ, even when… Figure 1B When the particle PTL shown exists on the back surface BS of the substrate SUB, it can also suppress the extension of the dislocation defect DIL to the field cutoff layer FSL, and thus, current leakage between the emitter and collector and current leakage under reverse bias can be suppressed.

[0054] The dislocation suppression layer DSL1 is disposed at a depth of 0.2 μm or more from the outermost surface of the back surface BS of the substrate SUB. This is to avoid the influence of the melt layer ML, since approximately 0.2 μm thick silicon on the outermost surface of the back surface BS of the substrate SUB is melted in one step to form the melt layer ML. As described above, when the dislocation suppression layer DSL1 is disposed at a relatively deep location in the collector layer CL, the heterojunction HJ can be formed on both the upper and lower surfaces of the dislocation suppression layer DSL1, and therefore, the effect of suppressing dislocation defects DIL is very high.

[0055] Alternative locations, such as Figure 3 As shown, the dislocation suppression layer can be positioned near the back surface BS of the substrate SUB. In this case, the heterojunction is not formed on the side of the dislocation suppression layer DSL2 closer to the back surface BS because this side overlaps with the molten layer ML. However, since the impurity distribution of the dislocation suppression layer DSL2 can be set to be more... Figure 2 The dislocation suppression layer DSL1 shown has a sharper impurity distribution, which can improve the output properties of the IGBT.

[0056] The dislocation suppression layer was formed by implanting germanium (Ge) ions into a region of the back surface BS of the substrate SUB, and Figure 3 The dislocation suppression layer DSL2 shown is formed at a shallow distance from the back surface BS, and therefore can be formed by ion implantation with low accelerating energies (e.g., in the range of 150 to 500 keV). Thus, the dislocation suppression layer DSL2 can be formed thinner, thereby improving the output properties of the IGBT.

[0057] on the other hand, Figure 2 The dislocation suppression layer DSL1 shown is formed by ion implantation at a higher acceleration energy (e.g., in the range of 600 to 900 keV) than the dislocation suppression layer DSL2. Consequently, ion scattering increases, the impurity distribution broadens, and the output properties of the IGBT deteriorate. However, a heterojunction can be formed on both surfaces inside the collector layer CL, resulting in a high degree of leakage current suppression. In other words, a bandgap difference exists between silicon-germanium (SiGe) and silicon (Si), which prevents hole doping from the region on the back surface. The broadening of the impurity distribution in the ion-implanted germanium (Ge) corresponds to the expansion of the region with a non-uniform bandgap, thus enhancing the effect of blocking hole doping. Therefore, the output properties of the IGBT deteriorate.

[0058] Figure 4 It shows including references Figure 2 An example of an IE-type IGBT with a dislocation suppression layer DSL1 as described. For example... Figure 4 As shown, the IE-type IGBT 100 includes a trench gate TG, a trench emitter TE, a p-type base layer BL, an n-type emitter layer EL, a p-type floating layer FL, and an n-type hole barrier layer HBL, which are formed in regions of the main surface of a substrate SUB made of n-type silicon. The IE-type IGBT 100 also includes an n-type drift layer DL below the n-type hole barrier layer HBL, an n-type field-stop layer FSL below the n-type drift layer DL, a p-type collector layer CL below the n-type field-stop layer FSL, and a collector electrode CE below the p-type collector layer CL. In the collector layer CL, a dislocation suppression layer DSL1 made of silicon-germanium (SiGe) is formed. The emitter electrode EE is electrically connected to the p-type base layer BL and the n-type emitter layer EL via connection holes CH1 formed in the interlayer insulating film IL. Note that the term "BC" indicates a high-density p-type base contact layer formed in the surface of the p-type base layer BL. The emitter electrode EE is electrically connected to the trench emitter TE and the p-type base layer BL between the trench emitters TE via connecting holes CH2 formed in the interlayer insulating film IL. An insulating film FPF is formed on the upper side of the emitter electrode EE. The insulating film FPF is a final passivation film made of, for example, an organic insulating film primarily composed of polyimide.

[0059] The IE-type IGBT 100 includes a parasitic P-channel MOSFET, with a p-type floating layer FL as its source region, a p-type base layer BL as its drain region, and a trench emitter TE as its gate electrode. An n-type hole barrier layer HBL constitutes the channel formation region of the parasitic P-channel MOSFET. Through the parasitic P-channel MOSFET, holes accumulated in the p-type floating layer FL are discharged to the emitter electrode EE via a short path when the IGBT is turned off, thereby shortening the switching time. Furthermore, the potential shift of the p-type floating layer FL is suppressed, and therefore, the potential of the trench gate TG is stabilized, and switching losses can be suppressed. In addition to these effects, because the IE-type IGBT 100 includes a dislocation suppression layer DSL1, current leakage between the emitter and collector and current leakage during reverse bias can be suppressed.

[0060] The following is a brief description of the materials and shapes of the semiconductor layer, insulating film, and electrodes that constitute the IE type IGBT 100.

[0061] First, the substrate SUB is made of single-crystal silicon doped with n-type impurities such as phosphorus (P), and has, for example, approximately 2 × 10⁻⁶ ppm. 14 cm -3 The impurity concentration. This concentration is the impurity concentration of the drift layer DL. The thickness of the substrate SUB is, for example, approximately 450 μm to 1000 μm.

[0062] The n-type hole barrier layer HBL is formed by doping an n-type impurity from a region on the front surface US of the substrate SUB. As a preferred example of this n-type impurity doping, ion implantation using phosphorus as the ion species is preferred, having a doping density of approximately 6 × 10⁻⁶. 12 cm -2 The dose and injection energy of approximately 200 keV. The n-type hole barrier layer HBL suppresses positive holes from reaching the p-type base layer BL and being discharged during operation of the IE-type IGBT 100, and also acts as a barrier against positive holes. The impurity concentration of the n-type hole barrier layer HBL is set to be higher than that of the n-type drift layer DL but lower than that of the n-type emitter layer EL, as described later.

[0063] The p-type floating layer FL is formed by doping a region of p-type impurities from the front surface US of the substrate SUB. As a preferred example of this p-type impurity doping, boron (B) is used as the ion species for ion implantation, having a density of approximately 3.5 × 10⁻⁶ ions. 13 cm -2 The dose and the injection energy of approximately 75 keV.

[0064] The trench gate (TG) and trench emitter (TE) are made of a polysilicon layer doped with n-type impurities, which is formed to be buried inside a trench created by etching into the main surface of the substrate (SUB). The trench gate (TG) and trench emitter (TE) are electrically isolated from the semiconductor layer formed in the substrate (SUB) by a gate insulating film (GI). The thickness of the gate insulating film (GI) is, for example, approximately 0.12 μm.

[0065] The depth and width of each trench, for example, 3.0 μm and 0.5 to 1.0 μm, can be exemplified as preferred values, respectively. The trenches are arranged to form strips in a planar view, with the trench gate TG and trench emitter TE facing each other, such that a hole barrier layer HBL is interposed therebetween, and a p-type floating layer FL is disposed between the trench gate TG and the trench emitter TE. The thickness (or depth) of the p-type floating layer FL, for example, 4 to 5 μm, can be exemplified as a preferred value. The base of the p-type floating layer FL is formed to cover the base of the trenches to mitigate electric field concentration on the base surface of the trench gate TG.

[0066] The p-type base layer BL is formed by doping a region of p-type impurities from the front surface US of the substrate SUB. As such p-type impurity doping, ion implantation using boron as the ion species is preferably exemplified, having a doping density of approximately 3 × 10⁻⁶. 13 cm -2 The dose and the injection energy of approximately 75 keV.

[0067] On the n-type hole barrier layer HBL, the p-type base layer BL is formed to contact one side surface of the trench gate TG through the gate insulating film GI. Furthermore, on the n-type hole barrier layer HBL, the p-type base layer BL is formed to contact one side surface of the trench emitter TE through the gate insulating film GI.

[0068] The n-type emitter layer EL is formed by doping the surface of the p-type base layer BL with an n-type impurity. For example, ion implantation using arsenic as the ion species is preferably exemplified as the doping of this n-type impurity, having a doping density of approximately 5 × 10⁻⁶. 15 cm -2 The dose and the injection energy of approximately 80 keV.

[0069] An interlayer insulating film IL is formed on the main surface of the substrate SUB to cover the n-type emitter layer EL, the p-type base layer BL, and the p-type floating layer FL. The interlayer insulating film IL is a PSG (phosphosilicate glass) film formed by, for example, CVD. The thickness of the interlayer insulating film IL is, for example, about 0.6 μm. Examples of materials for the interlayer insulating film IL include not only PSG films, but also BPSG (borophosphosilicate glass) films, NSG (undoped silicate glass) films, SOG (spin-coated glass) films, and composite films made from these films and other films.

[0070] In the interlayer insulating film IL, connection holes CH1 and CH2 are formed. Connection holes CH1 and CH2 can be formed, for example, by anisotropic dry etching using Ar gas, CHF3 gas, etc. By anisotropic dry etching, the portion of the main surface of the substrate SUB exposed from the connection holes CH1 and CH2 is etched, and connection holes CH1 and CH2 are formed reaching the middle of the p-type base layer BL and the trench emitter TE.

[0071] The p-type base contact layer BC can be formed by doping the surface of the substrate SUB with p-type impurities, which connect holes CH1 and CH2. For example, boron can be preferably used as the ion species for doping with such p-type impurities, resulting in an ion implantation layer with approximately 1 × 10⁻⁶ ions. 15 cm -2 The dose and the injection energy of approximately 100 keV.

[0072] The emitter electrode EE is formed on an interlayer insulating film IL that includes the holes CH1 and CH2. The emitter electrode EE is formed as a deposition film by, for example, the following process: First, a titanium-tungsten film is formed as a barrier metal film on the main surface of the substrate SUB by, for example, sputtering. The thickness of the titanium-tungsten film is, for example, about 0.2 μm.

[0073] Next, after silicide annealing at, for example, approximately 600°C in a nitrogen atmosphere for about 10 minutes, an aluminum-based metal film is formed on the entire surface of the titanium-tungsten film by, for example, sputtering, to fill the interior of the connecting holes CH1 and CH2. The aluminum-based metal film is, for example, made of aluminum film with a few percent added silicon and has a thickness of approximately 5 μm.

[0074] Next, the emitter electrode EE, made of a deposited film of titanium-tungsten film and aluminum-based metal film, can be formed into a predetermined pattern by dry etching using a resist pattern as a mask. As a gas used for this dry etching, Cl2 / BCl3 gas is preferably exemplified, for example.

[0075] The emitter electrode EE is electrically connected to each of the following through the interlayer insulating film IL: the n-type emitter layer EL, the p-type base contact layer BC, and the trench emitter TE.

[0076] Next, a final passivation film FPF is formed on the upper side of the emitter electrode EE and the upper side of the interlayer insulating film IL. The final passivation film FPF is an organic film containing, for example, polyimide as the main component and has a thickness of, for example, approximately 10 μm. This organic film is formed by applying it to the entire upper surface of the emitter electrode EE and the entire upper surface of the interlayer insulating film IL, and then opening a portion of the emitter pad EP and a portion of the gate pad GP using conventional photolithography methods, as shown below. Figure 5 As shown, described later.

[0077] After the final passivation film FPF is formed, for example, the following process is performed on the region of the back surface BS of the substrate SUB.

[0078] By performing a back-side grinding process on the back surface BS of the substrate SUB, the initial thickness of the substrate SUB (approximately 800 μm) is reduced to, for example, approximately 30 μm to 200 μm as needed. To design the breakdown voltage of the IE type IGBT 100 to, for example, approximately 600 V, the final thickness of the substrate SUB is preferably set to approximately 70 μm. Furthermore, to remove damage from the back-side grinding process, chemical etching can be performed on the back surface BS as needed.

[0079] Next, for example, p-type impurities and germanium (Ge) are doped into the thinned back surface BS of the substrate SUB by ion implantation to form a p-type collector layer CL and a dislocation suppression layer DSL1. As for the ion implantation conditions for forming the p-type collector layer CL, for example, ion implantation using boron as the ion species is preferably exemplified, having approximately 1 × 10⁻⁶ ions. 12 Up to 3×10 13 cm -2 The dosage and implantation energy are approximately 100 keV to 500 keV. As conditions for ion implantation to form the dislocation suppression layer DSL1, for example, ion implantation using germanium (Ge) as the ion species can be preferably exemplified, having an ion implantation energy of approximately 1 × 10⁻⁶ keV. 16 Up to 1×10 17 cm -2 The dose and implantation energy are approximately 200 to 900 keV (more preferably approximately 600 to 900 keV). Then, if necessary, laser annealing is performed on the back surface BS of the substrate SUB to activate impurities.

[0080] Next, for example, an N-type impurity is doped into the back surface BS of the thinned substrate SUB by ion implantation to form a field stop layer FSL. As a condition for such ion implantation, for example, ion implantation using hydrogen (H) as the ion species can be preferably exemplified, having approximately 1 × 10⁻⁶ ions. 14 Up to 1×10 15 cm -2 The dose and implantation energy of approximately 300 to 400 keV are then used. The substrate SUB is then placed in a furnace and subjected to low-temperature annealing at approximately 350–550°C to form the field stop layer (FSL). Methods for forming the FSL also include similar low-temperature annealing methods using oxygen as the ion species to generate thermal donors.

[0081] Next, a collector electrode CE is formed on the surface of the P-type collector layer CL, for example, by sputtering. The collector electrode CE is formed from the back surface BS of the substrate SUB by, for example, a deposited film of aluminum (Al), titanium (Ti), nickel (Ni), gold (Au), etc., in this order.

[0082] Through the above process, it can be made Figure 4 The image shows an IE-type IGBT. To illustrate the device structure more specifically, an example of the main dimensions of each component of the device will be described here.

[0083] The gap "TPP" between the trench emitter TE and the trench gate TG is approximately 2 μm to 3 μm, and the width "FLP" of the p-type floating layer FL is approximately 6 to 9 μm; these are referred to as cell pitch and inter-cell pitch, respectively. Furthermore, the depth of the n-type emitter layer EL is approximately 200 nm, the depth of the p-type base layer BL is approximately 0.6 to 1.0 μm, and the depth of the p-type floating layer FL is approximately 4 to 5 μm. The thickness of the n-type field-stop layer FSL is approximately 2 to 5 μm, and the thickness of the p-type collector layer CL is approximately 1.0 μm. Note that the thickness of the substrate SUB can vary depending on the required breakdown voltage. For example, the thickness of the substrate SUB can preferably be approximately 120 μm at a breakdown voltage of 1200 volts, and approximately 70 μm at a breakdown voltage of 600 volts.

[0084] Figure 5 It is a plan view of a semiconductor device including an IGBT according to one embodiment. Figure 6 It is a diagram used to illustrate the region where the unit forms, that is Figure 5 A schematic enlarged plan view or region RR. Figure 7 It is along Figure 5 A schematic cross-sectional view of line AA.

[0085] In the IE type IGBT 100, such as Figure 5 As shown, an annular guard ring "GR" connected to an annular channel stop (PG) is formed on the upper surface of the peripheral portion (also known as the chip periphery) of a rectangular semiconductor chip (CHIP). Inside the guard ring GR, several (single or multiple) annular field plates FP (FP1, FP2, FP3, FP4, and FP5) connected to annular floating field rings (P1, P2, P3, P4, and P5) are formed. Each of the guard ring GR and the field plates FP is made of a metal film containing, for example, aluminum as the main element. Figure 5 To simplify the accompanying drawings, the illustrations of FP4 and FP5 of the annular field plate FP have been omitted.

[0086] Inside the annular field plate FP, a cell forming region "RCL" is formed in the main part of the active portion of the semiconductor chip CHIP, and an emitter electrode EE is formed in the upper surface of the active portion of the semiconductor chip CHIP to extend to the portion near the outer periphery PER of the semiconductor chip CHIP. The emitter electrode EE is made of a metal film, for example, containing aluminum as the main element. The central part of the emitter electrode EE is the emitter pad "EP" for connecting bonding wires, etc. The emitter pad EP is formed by forming an opening in the final passivation film FPF.

[0087] A gate wiring “GL” is arranged between emitter electrodes EE and GE, and the gate wiring GL is connected to the gate electrode GE via a gate resistor “Rg”. Each of the gate wiring GL and the gate electrode GE is made of a metal film containing, for example, aluminum as a main element. The central portion of the gate electrode GE is a gate pad “GP” for connecting bonding lines, etc. The gate pad GP is formed by forming an opening in the final passivation film FPF. The gate resistor Rg is made of a resistive film containing, for example, polysilicon doped with a desired concentration of impurities as a main element.

[0088] exist Figure 5 In the configuration example shown, three gate wirings GL are arranged such that they extend in a first direction "X", and the three gate wirings GL extending in the first direction X are connected to two gate wirings GL arranged such that they extend in a second direction "Y" intersecting the first direction X. Below the region forming the three gate wirings GL, the three gate wirings GL extending in the first direction X are electrically connected to a polysilicon layer doped with n-type impurities buried inside the trench of the trench gate TG, but are not shown.

[0089] Next, refer to Figure 6 This will illustrate an example of the configuration of the unit-forming region RCL. Along... Figure 6 The cross-sectional view taken by the BB line corresponds to Figure 4 The diagram shows a cross-sectional view of an IE-type IGBT. The cell forming region RCL includes an active cell region "RCa", a deactivated region "Ria", and a hole collector cell region "RCc". The active cell region RCa, the deactivated region Ria, and the hole collector cell region RCc are arranged in a strip pattern extending in the second direction Y. These four regions—active cell region RCa, deactivated region Ria, hole collector cell region RCc, and deactivated region Ria—form a layout cell group in this order and are repeated in the first direction X.

[0090] The activation unit "Ca" is formed in the activation unit region RCa. As the activation unit Ca, Figure 6The schematic diagram illustrates a pair of trench gates TG arranged as a stripe pattern extending in the second direction Y, and an n-type emitter layer EL disposed between the pair of trench gates TG. Hole collector cells "Cc" are formed in the hole collector cell region RCc. Figure 4 As described, the hole collector unit Cc is a parasitic P-channel MOSFET, with its source region being a p-type floating layer FL, its drain region being a p-type base layer BL, its channel formation region being an n-type hole barrier layer HBL, and its gate electrode being a trench emitter TE. As the hole collector unit Cc, Figure 6 A schematic map illustrates a pair of trench emitters TE arranged in a stripe pattern extending in the second direction Y, and a connecting trench emitter "Tea" connecting the pair of trench emitters TE. Ria serves as the deactivation region. Figure 6 A schematic map illustrates a p-type floating layer FL. In, as... Figure 4 In the case of the connection hole CH2 shown in the diagram, the connection trench emitter TEa is unnecessary. In the case that is not... Figure 4 In the case shown, where the contact hole CH2 is not the contact hole CH1, the contact hole TE is more suitable for the contact between the emitter trench TE and the emitter electrode EE.

[0091] Next, refer to Figure 7 This will illustrate the cross-sectional view of the IE type IGBT 100. Figure 7 Note that the final passivation film FPF and the collector electrode CE are omitted from the diagram. Regarding the cell formation region RCL, Figure 7 To avoid complicating the drawing, only the trench emitter (TE), trench gate (TG), and p-type floating layer (FL) are shown.

[0092] The outer region surrounding the cell formation region RCL has a portion “RP0” (e.g., also called the cell periphery junction region), in which an annular P-type well region “P0” is formed to surround the outer region, and this P-type well region P0 is electrically connected to the emitter electrode EE. Multiple annular p-type floating field rings P1, P2, P3, P4, and P5 are arranged outside the annular P-type well region P0. The floating field rings P1, P2, P3, P4, and P5 are connected to field plates FP1, FP2, FP3, FP4, and FP5. An annular n-type channel stop “PG” is formed outside the p-type floating field rings P1, P2, P3, P4, and P5. The channel stop PG is connected to the guard ring GR. The channel stop PG is set to the collector potential. The outer peripheral portion PER of the semiconductor chip and the cell periphery junction region RP0 can also be considered as being arranged such that they surround the outer region of the cell formation region RCL.

[0093] like Figure 7As shown in the diagram, the dislocation suppression layer DSL1 is formed inside the P-type collector layer CL. The dislocation suppression layer DSL1 is arranged in the plan view... Figure 5 The dislocation suppression layer DSL1 is arranged in the entire semiconductor chip CHIP. In other words, the dislocation suppression layer DSL1 is arranged in the outer peripheral portion PER, the cell peripheral junction region RP0, and the cell formation region RCL of the semiconductor chip CHIP. Figure 7 The dislocation suppression layer DSL1 shown can be replaced with Figure 3 The dislocation suppression layer DSL2 is shown in the figure.

[0094] (Methods for manufacturing semiconductor devices)

[0095] Next, a method for manufacturing semiconductor devices will be described. The method for manufacturing semiconductor devices includes the following steps.

[0096] (The step of preparing the substrate) is to prepare a silicon substrate SUB comprising an n-type emitter layer EL, a p-type base layer BL, a trench gate TG, a trench emitter TE, a p-type floating layer FL, an n-type hole barrier layer HBL, a gate electrode GE, and an emitter electrode EE formed in the region of the first main surface US.

[0097] (Steps for forming a p-type collector layer: First step) is to form a p-type collector layer CL on the second main surface BS of the first main surface US facing the silicon substrate SUB.

[0098] (Step for forming the dislocation suppression layer: second step) is the step of forming a dislocation suppression layer (DSL1, DSL2) in the p-type collector layer CL that forms a heterojunction with the silicon substrate SUB.

[0099] (Step for forming an n-type field stop layer: the third step) is to form an n-type field stop layer FSL on the p-type collector layer CL in the region of the first main surface US.

[0100] (Step for forming the collector electrode: Step 4) is the step of forming the collector electrode CE connected to the p-type collector layer CL.

[0101] In the above steps, the steps of forming the p-type collector layer and forming the dislocation suppression layer can be considered as a combined step. The manufacturing process of forming the p-type collector layer CL and the dislocation suppression layer will be described below.

[0102] (Method for manufacturing an IGBT including a dislocation suppression layer DSL1)

[0103] Next, refer to Figures 8 to 11 This paper will describe a method for manufacturing an IE-type IGBT including a dislocation suppression layer DSL1. Figure 8This is a cross-sectional view illustrating a manufacturing method for a region on the back surface of a semiconductor device including an IGBT. Figure 9 It is a continuation Figure 8 A cross-sectional view used to illustrate the same manufacturing method. Figure 10 It is a continuation Figure 9 A cross-sectional view used to illustrate the same manufacturing method. Figure 11 It is a continuation Figure 10 The cross-sectional view used to illustrate the same manufacturing method is shown below. In this description, the n-type emitter layer EL, p-type base layer BL, p-type base contact layer BC, trench gate TG, trench emitter TE, p-type floating layer FL, n-type hole barrier layer HBL, interlayer insulating film IL, emitter electrode EE, final passivation film FPF, etc., formed in the region of the front surface US of the substrate SUB are omitted.

[0104] like Figure 8 As shown, to form a P-type collector layer CL and a dislocation suppression layer DSL1 after the back-side grinding process, a P-type impurity implantation layer "PI" and a germanium implantation layer "GEI" are formed, for example, by ion implantation using P-type impurities and germanium (Ge) doped into the back surface BS of the substrate SUB. Then, the P-type impurity implantation layer PI and the germanium implantation layer GEI are activated by laser annealing of the back surface BS of the substrate SUB. As for the ion implantation conditions used to form the P-type collector layer CL, for example, an ion implantation method using boron as the ion species is designed with approximately 1 × 10⁻⁶ ions. 12 Up to 3×10 13 cm -2 The dosage and implantation energy are approximately 100 to 500 keV. As conditions for ion implantation to form the dislocation suppression layer DSL1, for example, ion implantation is designed using germanium (Ge) as the ion species, with an ion implantation energy of approximately 1 × 10⁻⁶ keV. 16 Up to 1×10 17 cm -2 The dose and the injection energy of approximately 600 to 900 keV.

[0105] like Figure 9 As shown, by performing laser annealing (LA) on the back surface of the substrate SUB, the impurity implantation layers PI and GEI are activated, resulting in the formation of a P-type collector layer CL and a dislocation suppression layer DSL1. During laser emission in the laser annealing (LA), approximately 0.2 μm thick silicon on the outermost surface of the back surface BS of the substrate SUB is melted in one step to form a melt layer ML. After laser emission, the temperature of the substrate SUB decreases, and the melt layer ML recrystallizes. A heterojunction HJ composed of silicon and silicon-germanium (SiGe) layers is formed on the upper and lower surfaces of the dislocation suppression layer DSL1.

[0106] In this step, such as Figure 10As shown, when the particle PTL is present on the surface of the molten layer ML, in some cases, a dislocation defect DIL is formed in the back surface BS of the substrate SUB during recrystallization, originating from the particle PTL. The heterojunction HJ formed on the upper and lower surfaces of the dislocation suppression layer DSL1 suppresses the portion of the dislocation defect DIL that extends below the dislocation suppression layer DSL1.

[0107] Next, for example, a field stop layer FSL is formed by ion implantation into the back surface BS of the substrate SUB, which is doped with N-type impurities. As a condition for this ion implantation, for example, an ion implantation method using hydrogen (H) as the ion species is designed, having approximately 1 × 10⁻⁶ ions. 14 Up to 1×10 15 cm -2 The dosage and injection energy are approximately 300 to 400 keV. Note that the dislocation suppression layer DSL1 can be formed after the formation of the field stop layer FSL. In other words, the laser annealing (LA) for forming the dislocation suppression layer DSL1 is preferably performed in the final stage of the manufacturing process.

[0108] Then, the substrate SUB is placed in a furnace and subjected to low-temperature annealing at approximately 350–550°C, resulting in the formation of... Figure 11 The field cutoff layer FSL is shown. Then, although not shown, a collector electrode CE is formed on the surface of the P-type collector layer CL by, for example, sputtering. In these processes, a semiconductor device including an IGBT is formed.

[0109] (Including the manufacturing method of IGBT with dislocation suppression layer DSL2)

[0110] Next, refer to Figures 12 to 13 This paper will describe a method for manufacturing an IE-type IGBT that includes a dislocation suppression layer DSL2. Figure 12 This is a cross-sectional view illustrating a manufacturing method for a region on the back surface of a semiconductor device including an IGBT. Figure 13 It is a continuation Figure 12 The cross-sectional view used to illustrate the same manufacturing method is shown below. In this description, the n-type emitter layer EL, p-type base layer BL, p-type base contact layer BC, trench gate TG, trench emitter TE, p-type floating layer FL, n-type hole barrier layer HBL, interlayer insulating film IL, emitter electrode EE, final passivation film FPF, etc., formed in the region on the surface US of the substrate SUB are omitted.

[0111] like Figure 12As shown, to form a P-type collector layer CL and a dislocation suppression layer DSL2 after a back-side grinding process, a P-type impurity implantation layer "PI" and a germanium implantation layer "GEI2" are formed, for example, by ion implantation method that dops P-type impurities and germanium (Ge) into the back surface BS of the substrate SUB. Then, the P-type impurity implantation layer PI and the germanium implantation layer GEI2 are activated by laser annealing of the back surface BS of the substrate SUB. As for the ion implantation conditions used to form the P-type collector layer CL, for example, an ion implantation method using boron as the ion species is designed with approximately 1 × 10⁻⁶ ions. 12 Up to 3×10 13 cm -2 The dosage and implantation energy are approximately 100 to 500 keV. As conditions for ion implantation to form the dislocation suppression layer DSL2, for example, ion implantation is designed using germanium (Ge) as the ion species, with an ion implantation energy of approximately 1 × 10⁻⁶ keV. 16 Up to 1×10 17 cm -2 The dose and implantation energy are approximately 150 to 500 keV, and this implantation energy can be lower than the implantation energy used to form the dislocation suppression layer DSL1 (e.g., approximately 600 to 900 keV). In other words, the dislocation suppression layer DSL2 is formed at a shallower location from the back surface BS, and therefore can be formed by ion implantation with low acceleration energy.

[0112] like Figure 13 As shown, by performing laser annealing (LA) on the back surface of the substrate SUB, the impurity implantation layers PI and GEI2 are activated, resulting in the formation of a p-type collector layer CL and a dislocation suppression layer DSL2. During laser emission in the laser annealing (LA), approximately 0.2 μm thick silicon on the outermost surface of the back surface BS of the substrate SUB is melted in one step to form a molten layer ML. After laser emission, the temperature of the substrate SUB decreases, and the molten layer ML recrystallizes. A portion of the dislocation suppression layer DSL2 in the region closer to the back surface BS (in...) Figure 13 No heterojunction is formed on the upper surface of the dislocation suppression layer DSL2 because this portion overlaps with the molten layer ML. However, a heterojunction HJ composed of silicon and silicon-germanium (SiGe) layers is formed on the portion of the dislocation suppression layer DSL2 away from the back surface BS. Figure 13 In the lower surface of the dislocation suppression layer DSL2.

[0113] In this step, when the particle PTL is present on the surface of the molten layer ML, in some cases, a dislocation defect DIL is formed in the back surface BS of the substrate SUB during recrystallization, originating from the particle PTL. A heterojunction HJ is formed on the lower surface of the dislocation suppression layer DSL2, which suppresses the portion of the dislocation defect DIL extending below the dislocation suppression layer DSL2.

[0114] exist Figure 13 After the process, with Figure 10 and Figure 11 The same manufacturing steps described herein are performed. Then, a collector electrode CE is formed on the surface of the P-type collector layer CL. In these processes, a semiconductor device including an IGBT is formed.

[0115] (Modified Example)

[0116] Next, some examples of modifications will be explained.

[0117] (First Modification Example)

[0118] Figure 14 It is a cross-sectional view used to illustrate the structure of the region of the back surface of a semiconductor device including an IGBT according to the first modified example. Figure 15 It is a plan view of a semiconductor device including an IGBT according to the first modified example. Figure 16 It is a cross-sectional view used to illustrate a manufacturing method of a semiconductor device including the region of the back surface of an IGBT according to the first modified example. Figure 17 It is a continuation Figure 16 A cross-sectional view used to illustrate the same manufacturing method.

[0119] Figure 14 and Figure 11 The difference lies in the fact that the dislocation suppression layer DSL1a is divided into multiple blocks, as shown in the figure. Figure 14 and Figure 15 As shown in the diagram, each of the dislocation suppression layers DSL1a has a width "L1" in the first direction X, and the plurality of dislocation suppression layers DSL1a are arranged such that there is a gap (space) of width "L2" between them. Figure 15 As shown in the diagram, in the planar view, each of the multiple dislocation suppression layers DSL1a is selectively formed inside the silicon substrate SUB. Figure 15 In the example, multiple dislocation suppression layers DSL1a are arranged such that a strip pattern extending in the second direction Y is formed and arranged in the first direction X. Figure 15 In the example shown, the planar shape of the multiple dislocation suppression layers DSL1a is stripe (bar), but it is not limited to this. The planar shape of the multiple dislocation suppression layers DSL1a can be rectangular, circular, elliptical, polygonal, etc.

[0120] Due to such Figure 6 The diagram shows the formation of multiple separate dislocation suppression layers DSL1a, with the germanium implantation layer GEI1a being divided into multiple blocks (the formation of the germanium implantation layer GEI1a can be referred to...). Figure 8(Explanation of the germanium implanted layer GEI). In this case, a mask for blocking impurity doping is formed by photolithography, and then the mask for blocking impurity doping is used as a mask for ion implantation to form the germanium implanted layer GEI1a by ion implantation of germanium (Ge). Then, a mask removal step is performed to remove the mask for blocking impurity doping.

[0121] In the formation of the P-type impurity implantation layer PI (see...) Figure 8 Following the description of the process and the germanium implantation layer GEI1a, the p-type impurity implantation layer PI and the germanium implantation layer GEI1a are activated by laser annealing of the back surface BS of the substrate SUB. Furthermore, as described... Figure 17 As shown, the P-type impurity implantation layer PI and the germanium implantation layer GEI1a are activated by laser annealing (LA) on the back surface of the substrate SUB, thereby forming each of the P-type collector layer CL and the dislocation suppression layer DSL1a, which are composed of silicon-germanium layers. Figure 17 After the process, execution and Figure 10 and Figure 11 The manufacturing steps are the same as those described in the previous section. Then, a collector electrode CE is formed on the surface of the P-type collector layer CL. During these processes, a semiconductor device including an IGBT is formed.

[0122] like Figure 17 As shown, when the particle PTL exists on the upper side of the dislocation suppression layer DIL1a, the portion of the dislocation defect extending below the dislocation suppression layer DIL1a from the particle PTL can be suppressed by the heterojunction HJ formed on the upper and lower surfaces of the dislocation suppression layer DIL1a.

[0123] However, when the particle PTL exists in the gap between the dislocation suppression layer DSL1a and the dislocation suppression layer DSL1a, it is conceivable that a dislocation defect originating from the particle PTL will undesirably extend through the gap between the dislocation suppression layer DSL1a and the dislocation suppression layer DSL1a (within the gap of width L2) to the portion below the P-type collector layer CL, leading to leakage failure. The second modification example described below is intended to address this issue.

[0124] (Second Modification Example)

[0125] Figure 18 It is a cross-sectional view used to illustrate the structure of the region of the back surface of a semiconductor device including an IGBT according to the second modified example. Figure 19 It is a plan view of a semiconductor device including an IGBT according to the second modified example. Figure 20 It is a cross-sectional view used to illustrate a manufacturing method of a semiconductor device including the region of the back surface of the IGBT according to the second modified example. Figure 21 It is a continuation Figure 20A cross-sectional view used to illustrate the same manufacturing method.

[0126] Figure 18 and Figure 14 The difference lies in that the dislocation suppression layer DSL2a is formed near the back surface BS of the substrate SUB in a region with a width L2 between the dislocation suppression layers DSL1a, as shown below. Figure 18 and Figure 19 As shown in the diagram. Each of the dislocation suppression layers DSL1a has a width L1 in the first direction X, and the plurality of dislocation suppression layers DSL1a are arranged such that they are spaced apart by a width L2. Each of the dislocation suppression layers DSL2a made of silicon-germanium layers has a width L2 in the first direction X, and the plurality of dislocation suppression layers DSL2a are arranged such that they are spaced apart by a width L1. Figure 9 As shown in the diagram, in the plan view, multiple dislocation suppression layers DSL1a and multiple dislocation suppression layers DSL2a are arranged such that they form strip patterns extending in the second direction Y and are alternately arranged in the first direction X.

[0127] These processes address problems such as the unwanted extension of dislocation defects originating from the particle PTL through the gap between the dislocation suppression layers DSL1a and DSL2a (within the gap of width L2) to the portion below the P-type collector layer CL. In other words, in the dislocation suppression layer DSL2a between the dislocation suppression layers DSL1a and DSL2a, on the portion of the dislocation suppression layer DSL2a furthest from the back surface BS (in... Figure 18 In this process, a heterojunction HJ composed of a silicon layer and a silicon-germanium (SiGe) layer is formed on the lower surface of the dislocation suppression layer DSL2a. The heterojunction HJ formed on the lower surface of the dislocation suppression layer DSL2a suppresses the portion of the dislocation defect that extends below the dislocation suppression layer DSL2a.

[0128] Therefore, by forming heterojunctions HJ on the upper and lower surfaces of the dislocation suppression layer DSL1a and on the lower surface of the dislocation suppression layer DSL2a, the portion of the dislocation defect extending below the dislocation suppression layers DSL1a and DSL2a, which originates from the particle PTL, is suppressed.

[0129] The planar shape of multiple dislocation suppression layers DSL1a can be triangular, rectangular, circular, elliptical, polygonal, etc. In this case, the planar shape of dislocation suppression layer DSL2a is a form that covers the region where multiple dislocation suppression layers DSL1a are not formed. The planar shape of multiple dislocation suppression layers DSL2a can be triangular, rectangular, circular, elliptical, polygonal, etc. In this case, the planar shape of dislocation suppression layer DSL1a is a form that covers the region where multiple dislocation suppression layers DSL2a are not formed.

[0130] Because multiple separate dislocation suppression layers DSL1a and DSL2a are formed as follows Figure 20 As shown, the germanium implanted layer GEI1a is therefore formed into multiple blocks, and the germanium implanted layer GEI2a is also formed into multiple blocks (the formation of the germanium implanted layer GEI2a can be found in [reference]). Figure 12 (Explanation of germanium implanted layer GEI2). Germanium implanted layers GEI1a and GEI2a are formed via photolithography using a mask to block impurity doping, as shown below. Figure 16 As shown in the image.

[0131] In the formation of the P-type impurity implantation layer PI (see...) Figure 8 (As explained), after the germanium implantation layers GEI1a and GEI2a, the p-type impurity implantation layer PI, germanium implantation layer GEI1a, and germanium implantation layer GEI2a are activated by laser annealing of the back surface BS of the substrate SUB. Furthermore, as... Figure 21 As shown, laser annealing (LA) is performed on the back surface of the substrate SUB to activate PI and germanium implantation into GEI1a and GEI2a, thereby forming dislocation suppression layers DSL1a and DSL2a and a P-type collector layer CL. Figure 21 After the process, execution and Figure 10 and Figure 11 The manufacturing steps are the same as those described in the previous section. Then, a collector electrode CE is formed on the surface of the P-type collector layer CL. During these processes, a semiconductor device including an IGBT is formed.

[0132] (Third Modification Example)

[0133] Figure 22 It is a cross-sectional view used to illustrate the structure of the region of the back surface of a semiconductor device including an IGBT according to the third modified example. Figure 23 It is a plan view of a semiconductor device including an IGBT according to the third modified example.

[0134] In the first modified example, a structural example of arranging multiple dislocation suppression layers DSL1a in a planar diagram to form a strip pattern in a semiconductor chip has been described. For example... Figure 22 As shown, the third modified example is configured such that the dislocation suppression layer DSL1b is selectively formed in a region other than the lower part of the cell formation region RCL, in other words, in the lower region of the chip peripheral region PER and the cell peripheral junction region RPO of the semiconductor chip. Figure 23As shown, the dislocation suppression layer DSL1b is formed below the cell peripheral junction region RP0 surrounding the cell formation region RCL, and inside the P-type collector layer CL formed below the chip peripheral region PER surrounding the cell peripheral junction region RP0. The fabrication method of the dislocation suppression layer DSL1b can be referred to the description of the first modified example.

[0135] Adopting such Figure 23 The dislocation suppression layer DSL1b shown can suppress leakage current under reverse bias. Furthermore, since the cell formation region RCL does not have the dislocation suppression layer DSL1b, its use does not affect the properties of the IGBT.

[0136] (Fourth modification example)

[0137] Figure 24 It is a cross-sectional view used to illustrate the structure of the region of the back surface of a semiconductor device including an IGBT according to the fourth modified example. Figure 25 It is a plan view of a semiconductor device including an IGBT according to the fourth modified example.

[0138] Figure 24 and Figure 22 The difference lies in the fact that the dislocation suppression layer DSL2b is formed inside the P-type collector layer CL below the cell formation region RCL. For example... Figure 25 As shown in the plan view, the dislocation suppression layer DSL2b is formed in the region below the cell formation region RCL. The method for manufacturing the dislocation suppression layer DSL2b can be referred to the description of the second modified example.

[0139] According to the fourth modified example, the IE type IGBT 100 includes dislocation suppression layers DSL1b and DSL2b, and therefore, current leakage between the emitter and collector, as well as current leakage under reverse bias, can be suppressed.

[0140] (Fifth revision example)

[0141] exist Figure 18 In this context, instead of the dislocation suppression layer DSL1a doped with germanium (Ge), a dislocation suppression layer based on a lattice spacing strain layer (extended defect) made of silicon (Si) can be formed in the substrate SUB by ion implantation using any type of ion, such as carbon (C), silicon (Si), argon (Ar), fluorine (F), nitrogen (N), etc. Figure 18 In this process, holes are injected through the dislocation suppression layer DSL2a, and therefore, even if a dislocation suppression layer doped with this type of ion is formed at a location outside the formation region of the dislocation suppression layer DSL2a, the output properties of the IGBT will not be deteriorated.

[0142] (Sixth Modification Example)

[0143] exist Figure 22 In this context, instead of the germanium-doped dislocation suppression layer DSL1b, a dislocation suppression layer based on a lattice spacing strain layer (extended defect) made of silicon Si can be formed in the substrate SUB by ion implantation using any type of ion such as carbon C, silicon Si, argon Ar, fluorine F, nitrogen N, etc. Figure 22 In this configuration, no dislocation suppression layer is formed below the cell formation region RCL. Therefore, even if a dislocation suppression layer doped with this type of ion (carbon C, silicon Si, argon Ar, fluorine F, nitrogen N) is formed at the location of the dislocation suppression layer DSL1b formation region, it will not degrade the output properties of the IGBT. Figure 24 Note that the dislocation suppression layer DSL1b is also made using a dislocation suppression layer with this type of ion.

[0144] (Explanation of the research conducted by the inventor)

[0145] Next, the inventor's research results will be explained.

[0146] Figure 26 This is a graph showing the output properties of three IGBTs with different back surface structures. Figure 26 It shows Figure 1C The IGBT shown is referred to as "Si". Figure 3 The IGBT shown (referred to as "Pattern 1") and Figure 2 The output properties of each of the IGBTs shown (referred to as "Pattern 2"). Figure 26 In the diagram, the horizontal axis indicates the collector potential (Vc) in volts "V", and the vertical axis indicates the collector current (Ic) in currents "A". Note the structure of the area on the front surface of each IGBT. Figure 4 The front surface regions of the IGBTs shown have the same structure.

[0147] like Figure 26 As shown, pattern 1 ( Figure 3 The properties of IGBTs in this context are almost identical to those of Si ( Figure 1C The IGBTs in pattern 2 are the same. However, in pattern 2 ( Figure 2 In the IGBT (in the context of the IGBT), a decrease in output was observed. For example, at a collector voltage Vc: 1.5V, compared to Si (… Figure 1C Compared to IGBTs in pattern 2, in pattern 2 Figure 2 A current reduction of approximately 20% was observed in the IGBT.

[0148] This is achieved by forming dislocation suppression layers DSL1 and DSL2, composed of SiGe layers, through ion implantation of Ge onto the back surface, which blocks hole doping from the back surface. This is because silicon (Si) and SiGe have different band structures.

[0149] Pattern 1 ( Figure 3 The dislocation suppression layer (DSL2) is formed relatively shallowly. In other words, the SiGe layer is formed in the surface region of the back surface BS. Therefore, ion implantation is performed with relatively low acceleration energies (150 to 500 keV). Thus, the width of the SiGe layer (dislocation suppression layer DSL2) in the depth direction can be reduced (in other words, the implanted Ge distribution can be sharpened).

[0150] In pattern 2 ( Figure 2 In the dislocation suppression layer DSL1, Ge ion implantation is performed at relatively high acceleration energies (600–900 keV). Therefore, the width of the SiGe layer increases in the depth direction. This is because higher acceleration energies result in greater ion scattering, leading to a wider distribution due to the nature of ion implantation. Consequently, pattern 2 (which causes the wide SiGe layer (dislocation suppression layer DSL1)) is observed. Figure 2 The degradation of output properties caused by the IGBT in the circuit is quite significant.

[0151] Next, the switching properties of the IGBT will be evaluated through simulation. An example of the main components of the switching circuit of the trench insulated gate bipolar transistor used in the simulation will be briefly described. Figure 27 This is a circuit diagram showing the switching circuit used for simulation. Figure 28 It is a graph used to illustrate the switching loss values ​​calculated through simulation.

[0152] like Figure 27 As shown, in the switching circuit SWC, IGBT 100 is connected in series with a motor, for example, serving as the main load MOL. A freewheeling diode Di is connected in parallel with this main load MOL. The main load MOL is also connected to the power supply voltage VCC. IGBT 100 is the target of evaluation. With a current of 200A flowing through the switching circuit SWC, IGBT 100 is turned on / off by controlling its gate potential Vg. The switching losses in this case are shown in... Figure 28 In. Figure 28 In this context, the term "Eon" indicates the switching loss when the circuit is turned on, and the term "Eoff" indicates the switching loss when the circuit is turned off.

[0153] This confirms pattern 1 ( Figure 3 The switching properties of the IGBT in the reference example are almost identical to those of the reference (Si): Figure 1C The switching properties of the IGBTs in the diagram are the same. On the other hand, Pattern 2 ( Figure 2 The Eoff of the IGBT in pattern 2 is about 15% better. This is because the on-state voltage of pattern 2 is high, such as... Figure 26As shown, this results in a low carrier density in the volume. A trade-off between output and switching properties is simply observed.

[0154] From the above results, it can be found that even with a SiGe layer on the back surface, the IGBT characteristics remain the same as in pattern 1 ( Figure 3 The IGBT (as shown in the diagram) can also be maintained during its formation.

[0155] However, among Pattern 1 and Pattern 2, Pattern 2 exhibits superior robustness compared to Pattern 1. This is because Pattern 2 incorporates a two-layer heterojunction HJ that acts as a dislocation stopper, as the upper and lower surfaces of the SiGe layer become heterojunction interfaces (heterojunction HJ). On the other hand, this is because only the lower surface of the SiGe layer in Pattern 1 becomes a heterojunction interface (heterojunction HJ).

[0156] First modification example ( Figure 14 The dislocation suppression layers DSL1a are configured such that a space with a width L2 is formed between the dislocation suppression layers DSL1a, and the plurality of dislocation suppression layers DSL1a are formed by dividing the dislocation suppression layers DSL1 of pattern 2. Figure 2 Since the holes output from the collector electrode CE in the region of the back surface BS of the substrate SUB pass through the space between the dislocation suppression layers DSL1a with a width of L2, an improvement in output properties can be expected. Figure 29 The output properties of each IGBT are calculated based on the change in the ratio (L1 / L2) between the width L1 and the width L2 of the dislocation suppression layer DSL1a. Figure 29 This shows the case of Si ( Figure 1C (IGBT in the middle), Case 2 () Figure 2 The four IGBTs are in the cases of "L1 / L2 = 1 / 1" (expressed as SiGeL / S = 1 / 1) and "L1 / L2 = 1 / 3" (expressed as SiGeL / S = 1 / 3).

[0157] It has been demonstrated that the output properties can be improved by having a space (L2) structure between the dislocation suppression layers DSL1a. Furthermore, it has been shown that the larger the space width (L2), the greater the improvement in output properties.

[0158] Meanwhile, in this structure, when a dislocation defect DIL occurs in the space (L2) region, leakage failure may occur because the space (L2) region does not have a heterojunction HJ to act as a dislocation stopper. Figure 26 In the study, it was found that pattern 1 does not worsen the output properties of the IGBT. Therefore, based on the above results, it is estimated that by... Figure 14Forming a dislocation suppression layer DSL2 of pattern 1 in the space (L2) can improve the output characteristics and robustness of the IGBT. Therefore, a new second modified example can be proposed ( Figure 18 Pattern 3 is shown in the diagram. Second modified example ( Figure 18 Pattern 3 shown in the diagram can remain consistent with... Figure 1C It offers almost the same performance (output characteristics and switching losses) as the IGBT in the original, while increasing robust performance.

[0159] (Regarding reverse bias)

[0160] Figure 30 This is a circuit block diagram representing an example of a motor drive circuit. Figure 31 It is used to explain and Figure 30 The circuit diagram showing the operation of the IGBT and diode corresponding to the U phase. Figure 32 This is a cross-sectional view used to illustrate the parasitic diode in an IGBT. Figure 33 It is used for explanation Figure 31 The equivalent circuit diagram of the parasitic diode in the IGBT on the high side.

[0161] like Figure 30 As shown, the motor drive circuit includes loads such as the motor MOT and the inverter INV. The motor MOT is a three-phase motor consisting of U-phase "U", V-phase "V", and W-phase "W". Therefore, the inverter INV also handles the three-phase motor consisting of U-phase "U", V-phase "V", and W-phase "W". This three-phase inverter INV consists of a total of six pairs of IGBT 100 and freewheeling diodes Di. In each of the three phases consisting of U-phase "U", V-phase "V", and W-phase "W", the IGBT 100 and the freewheeling diodes Di are connected in anti-parallel between the input potential of the motor MOT (corresponding to the output terminal of the inverter INV) and the power supply wiring VCL that supplies the power supply potential (VCC) to the inverter INV, in other words, on the high side. Furthermore, in each of the three phases consisting of phase U (U), phase V (V), and phase W (W), the IGBT 100 and the freewheeling diode Di are connected in anti-parallel between the input potential of the motor MOT (corresponding to the output terminal of the inverter INV) and the grounding line GNL that supplies ground potential (GND) to the inverter INV; in other words, on the low side. In this case, anti-parallel connection means a configuration in which the collector of the IGBT 100 is connected to the cathode of the freewheeling diode Di, and the emitter of the IGBT 100 is connected to the anode of the freewheeling diode Di.

[0162] For each freewheeling diode Di, a SiC-SBD (Silicon Carbide-Schottky Barrier Diode) can be used. In recent years, hybrid modules made of SiC-SBD and Si-IGBT have become popular. SiC-SBD is unipolar and therefore has a shorter reverse recovery time “trr”. Consequently, the “Vce” surge of the IGBT tends to be steep, and IGBT damage due to reverse bias leakage tends to occur. This is because “dV / dt” is steep, causing impact ionization in the high-side IGBT 100H, although this will be described in detail later. IGBT “Ices” failure and back-surface dislocation defects that increase reverse bias leakage have become non-negligible.

[0163] The inverter INV is provided with a dead time to prevent load short circuits in the upper and lower IGBTs of each phase, and the upper and lower IGBTs are turned off during this dead time period.

[0164] like Figure 31 As shown, during this dead time period, the current "Ii" does not flow into the upper IGBT 100H (on the high side) but instead flows into the high-side freewheeling diode DiH. Focusing on the upper IGBT 100H (on the high side), the operation of the freewheeling diode DiH causes a reverse bias state where the emitter voltage of the IGBT 100H is higher than the collector voltage. The reverse bias voltage (-VCE) is typically approximately -2 to -3V.

[0165] When IGBT 100L (on the low side) is turned on in the dead-time state, the collector voltage of IGBT 100L (equivalent to the emitter voltage of IGBT 100H) drops to the operating voltage. In other words, the state of IGBT 100H switches from reverse bias to forward bias. In this case, it has been found that IGBT 100H can be damaged in some situations due to the increase in the collector-emitter potential VCE at dV / dt: 10 to 40 kV / μs. Typically, in IGBTs, the collector-emitter potential VCE operates at approximately dV / dt: 2 to 7 kV / μs.

[0166] In the IGBT 100, the region of the back surface BS of the substrate SUB includes the p-type collector layer CL, and therefore there is no body diode such as a MOSFET. However, as Figure 32As shown, it was found that if the PN junction formed by the p-type collector layer CL and the n-type field-stop layer FSL in the region of the back surface BS of the substrate SUB leaks due to dislocation defects DIL starting from the particle PTL, the parasitic diode Ds operates under reverse bias. This parasitic diode Ds is formed by a PN junction between the annular p-type region P0 below the formation region of the embedded resistor Rg and the n-type drift layer DL. The anode of the parasitic diode Ds is connected to the emitter EE, which is connected to the left and right sides of the p-type region P0. Because the concentration of the n-type field-stop layer FSL is higher than that of the n-type drift layer DL, the cathode of the parasitic diode Ds is connected to the collector electrode CE through the n-type field-stop layer FSL from the n-type drift layer DL below the p-type region P0. In this way, a current path "PTH" including the parasitic diode Ds is formed between the emitter electrode EE and the collector electrode CE.

[0167] like Figure 33 As shown, the parasitic diode Ds is configured such that it is connected between the emitter and collector of the IGBT 100H. Focusing on the IGBT 100H, since current Ii flows in the freewheeling diode Di during the dead time period, the emitter voltage of the IGBT 100H is higher than the collector voltage (reverse bias state). If the PN junction on the back surface of the IGBT 100H has a leakage path, the parasitic diode Ds operates, and current "Is" also flows in the parasitic diode Ds of the IGBT 100H.

[0168] In this state, when the low-side IGBT 100L is turned on, the collector voltage of the low-side IGBT 100L, in other words, the emitter voltage of the high-side IGBT 100H, drops to that of the IGBT 100L. For example, the emitter voltage of the IGBT 100H drops from the inverter drive voltage (VCC) (such as 800V) to approximately 2V. In this situation, when the low-side IGBT 100L is turned on at a high dV / dt, the high-side IGBT 100H is damaged. The mechanism of damage to the high-side IGBT 100H is as follows.

[0169] 1. Due to the leakage path in the back surface area, the parasitic diode Ds of the high-side IGBT 100H operates in dead time.

[0170] 2. When the low-side IGBT 100L is turned on, the collector-emitter potential Vce is applied to the high-side IGBT 100H. In other words, the state of the collector-emitter potential Vce of the high-side IGBT 100H switches from reverse bias to forward bias (the gate voltage of the high-side IGBT 100H remains off).

[0171] 3. Under reverse bias, a large number of charge carriers are generated in the volume due to the operation of the parasitic diode Ds.

[0172] 4. In this state, since the collector-emitter potential Vce of the high-side IGBT 100H increases at high dV / dt, impact ionization is easily caused at the PN junction of the parasitic diode Ds.

[0173] 5. The large number of hole carriers caused by this collisional ionization flow to the emitter electrode EE through the P-type region P0 below the embedded resistor Rg and the emitter contact.

[0174] 6. At this time, due to the voltage drop in the P-type region P0, a high electric field is formed in the oxide film OXL between the P-type region P0 and the embedded resistor Rg, and dielectric breakdown occurs in the oxide film OXL.

[0175] The dielectric breakdown of the oxide film OXL occurs near the central portion "MID," which is located in the middle of the contact between the emitter electrode EE, which connects to the right and left sides of the P-type region P0. Figure 32 In the diagram, note the width of the peripheral junction region RP0 in the first direction X. In other words, the width of the P-type region P0 in the first direction X is, for example, approximately 1 to 3 mm, while the width of the outer peripheral portion PER in the first direction X is, for example, approximately 400 to 600 μm. In other words, the width of the P-type region P0 in the first direction X is relatively large, and the contact of the emitter electrode EE is wide. Therefore, the voltage drop caused by the P-type region P0 is relatively large. This results in a high electric field.

[0176] Therefore, as in the third modification example ( Figure 22 ) and the fourth modification example ( Figure 24 As explained in [reference needed], by forming a dislocation suppression layer DSL1b or dislocation suppression layers DSL1b and DSL2b, current leakage under reverse bias can be suppressed. As explained in the fourth modified example, by forming dislocation suppression layers DSL1b and DSL2b, current leakage between the emitter and collector and current leakage under reverse bias can be suppressed. The third and fourth modified examples can provide IGBTs capable of handling high-speed switching while suppressing current leakage under reverse bias.

[0177] The IGBT 100 with a dislocation suppression layer disclosed in this application is more suitable for use as... Figure 30 Each IGBT in the motor drive circuit shown, and including a hybrid module with an inverter made of SiC-SBD, is more suitable for being configured as Figure 30The diagram shows each freewheeling diode Di in the motor drive circuit. This configuration provides a motor drive circuit capable of handling high-speed switching while preventing damage from current leakage during reverse bias in the IGBT.

[0178] The present invention has been described in detail above based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made within the scope of the present invention.

[0179] For example, the semiconductor substrate SUB can be a substrate comprising a low-impurity N-type epitaxial layer formed on a high-impurity N-type semiconductor substrate.

Claims

1. A semiconductor device, comprising: A silicon substrate, the silicon substrate including a first main surface and a second main surface facing the first main surface; A p-type base layer is formed on the first main surface; An n-type emitter layer is formed in the p-type base layer; A p-type collector layer is formed on the second main surface; and A dislocation suppression layer is formed in the p-type collector layer and forms a heterojunction with the silicon substrate. The dislocation suppression layer includes a silicon-germanium layer. The dislocation suppression layer includes a first dislocation suppression layer and a second dislocation suppression layer. In the cross-sectional view, the first dislocation suppression layer is closer to the first main surface than the second dislocation suppression layer, and In the plan view, the second dislocation suppression layer is formed in the region where the first dislocation suppression layer is not formed.

2. The semiconductor device according to claim 1, further comprising: A strip patterned trench gate is formed on the first main surface such that the strip patterns face each other; An n-type hole barrier layer is formed on the first main surface below the p-type base layer; A strip patterned trench emitter is formed on the first main surface and arranged at a predetermined distance from the strip patterned trench gate, such that the strip patterns face each other. A p-type floating layer is disposed between the trench gate and the trench emitter. The p-type floating layer has one end in contact with the side surface of the trench gate and another end in contact with the side surface of the trench emitter. An n-type field cutoff layer is formed on the second main surface as being located on the side of the p-type collector layer closer to the substrate; as well as An n-type drift layer is disposed between the n-type field cutoff layer and the n-type hole barrier layer. The p-type base layer is formed in the region surrounded by the strip patterned trench gate.

3. The semiconductor device according to claim 1, In the plan view, the silicon-germanium layer is formed on the entire silicon substrate.

4. The semiconductor device according to claim 1, In the plan view, the silicon-germanium layer is selectively formed on the silicon substrate.

5. The semiconductor device according to claim 4, The silicon-germanium layer has a striped pattern in the plan view.

6. The semiconductor device according to claim 1, The silicon-germanium layer includes an upper surface on the first main surface side and a lower surface on the second main surface side. Each of the upper and lower surfaces has a heterojunction.

7. The semiconductor device according to claim 1, The silicon-germanium layer includes an upper surface on the first main surface side and a lower surface on the second main surface side. The upper surface has the heterojunction, while the lower surface does not have the heterojunction.

8. The semiconductor device according to claim 1, In the plan view, the silicon substrate includes a cell formation region and a peripheral region surrounding the cell formation region. In the plan view, the dislocation suppression layer is formed below the peripheral region.

9. The semiconductor device according to claim 8, The dislocation suppression layer includes a lattice spacing strain layer containing any one of carbon, silicon, argon, fluorine, and nitrogen.

10. The semiconductor device according to claim 8, The dislocation suppression layer includes a first dislocation suppression layer and a second dislocation suppression layer. In the cross-sectional view, the first dislocation suppression layer is closer to the first main surface than the second dislocation suppression layer. In the plan view, the first dislocation suppression layer is arranged below the peripheral region, and In the plan view, the second dislocation suppression layer is arranged below the cell formation region.

11. The semiconductor device according to claim 10, Each of the first dislocation suppression layer and the second dislocation suppression layer comprises a silicon-germanium layer.

12. The semiconductor device according to claim 10, The first fault suppression layer comprises a lattice spacing strain layer containing any one of carbon, silicon, argon, fluorine, and nitrogen, and The second dislocation suppression layer includes a silicon-germanium layer.

13. A method for manufacturing a semiconductor device, comprising: The step of preparing a silicon substrate, wherein the silicon substrate comprises the following items formed in a region of its first main surface: an n-type emitter layer, a p-type base layer, a trench gate, a trench emitter, a p-type floating layer, an n-type hole barrier layer, a gate electrode, and an emitter electrode; The first step is to form a p-type collector layer on the second main surface, with the second main surface facing the first main surface of the silicon substrate; The second step is to form a first dislocation suppression layer inside the p-type collector layer, and the first dislocation suppression layer forms a heterojunction with the silicon substrate. The third step is to form an n-type field cutoff layer on the first main surface side of the p-type collector layer; as well as The fourth step is to form a collector electrode connected to the p-type collector layer. In the planar view, the silicon substrate includes a cell formation region and a peripheral region surrounding the cell formation region. The cell formation region includes: an n-type emitter layer, a p-type base layer, a trench gate, a trench emitter, a p-type floating layer, and an n-type hole barrier layer. In the plan view, the first dislocation suppression layer is formed below the peripheral region. The first dislocation suppression layer includes an upper surface on the first main surface side and a lower surface on the second main surface side. Each of the upper and lower surfaces has the heterojunction.

14. The method for manufacturing a semiconductor device according to claim 13, The first step and the second step include: The step of forming the first implantation layer is used to form the P-type impurity implantation layer by ion implantation, which involves doping the second main surface of the silicon substrate with P-type impurities. The step of forming the second implantation layer involves forming the first germanium implantation layer by ion implantation, which involves doping the second main surface of the silicon substrate with germanium; then, The annealing step activates the P-type impurity implantation layer and the first germanium implantation layer by annealing the second main surface of the silicon substrate, thereby forming the p-type collector layer and the first dislocation suppression layer.

15. The method for manufacturing a semiconductor device according to claim 14, In the planar view, the first dislocation suppression layer is formed on the entire silicon substrate. The first dislocation suppression layer includes an upper surface on the first main surface side and a lower surface on the second main surface side. Each of the upper and lower surfaces has the heterojunction, or the upper surface has the heterojunction while the lower surface does not.

16. The method of manufacturing a semiconductor device according to claim 14, further comprising: The step of forming the third implantation layer involves forming a second germanium implantation layer in a portion closer to the second main surface than the first germanium implantation layer by ion implantation using germanium to dope the second main surface of the silicon substrate. In the step of forming the second implanted layer, one or more first germanium implanted layers are formed. In the step of forming the third implanted layer, in the plan view, in the region where one or more of the first germanium implanted layers have not been formed, one or more of the second germanium implanted layers are formed, and One or more of the second germanium implantation layers are activated by an annealing step, thereby forming one or more second dislocation suppression layers.

17. The method of manufacturing a semiconductor device according to claim 16, Multiple first dislocation suppression layers are arranged to form a strip pattern in a planar view, and Multiple second dislocation suppression layers are arranged to form a strip pattern in a planar view.

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